[Bug target/94317] gcc/config/arm/arm_mve.h:13907: strange assignment ?
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94317 --- Comment #8 from SRINATH PARVATHANENI --- Hi David, >>Can the author please indicate where the test cases for this code >>are in the gcc trunk testsuite. I'll give them some exercise. Christophe wrote: > There are lots of tests under gcc.target/arm/mve, but I think all them just > check that the generated code contains the instruction we expect to generate > from the intrinsic. (All of them have dg-do compile). Everything Christophe mentioned above is correct, expect for all them having "dg-do compile", Monday a patch was posted by Andre to changes tests to assemble. ``` commit 962406639c0ca9f0d948c843ad2a1ca5b17806da Author: Andre Vieira Date: Mon Mar 23 12:07:28 2020 + testsuite, arm: Change tests to assemble ``` >In the past I contributed Neon intrinsics executable tests (see >gcc.target/aarch64/advsimd-intrinsics) which caught several corner-case bugs. >It would probably be good to have similar things for MVE, but that's a huge >task. Thanks Christophe, I will check that. Regards, SRI.
[Bug target/94317] gcc/config/arm/arm_mve.h:13907: strange assignment ?
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94317 SRINATH PARVATHANENI changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|--- |FIXED --- Comment #10 from SRINATH PARVATHANENI --- Committed to trunk.
[Bug other/89863] [meta-bug] Issues that static analyzers (cppcheck, clang-static-analyzer) find that gcc misses
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89863 Bug 89863 depends on bug 94317, which changed state. Bug 94317 Summary: gcc/config/arm/arm_mve.h:13907: strange assignment ? https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94317 What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|--- |FIXED
[Bug target/94341] mve_mov can produce ICE on latest trunk
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94341 --- Comment #2 from SRINATH PARVATHANENI --- Patch committed by Andre: commit b094133c1c5bf21ccd60c344de6f4a798140e61b Author: Andre Simoes Dias Vieira Date: Tue Apr 7 13:36:43 2020 +0100 arm: MVE: Fix constant load pattern This patch fixes the constant load pattern for MVE, this was not accounting correctly for label + offset cases. Added test that ICE'd before and removed the scan assemblers for the mve_vector* tests as they were too fragile.
[Bug target/94341] mve_mov can produce ICE on latest trunk
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94341 SRINATH PARVATHANENI changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED|RESOLVED --- Comment #3 from SRINATH PARVATHANENI --- Fixed
[Bug c/94735] New: MVE vector load/store pair getting removed with -O2.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94735 Bug ID: 94735 Summary: MVE vector load/store pair getting removed with -O2. Product: gcc Version: 10.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: c Assignee: unassigned at gcc dot gnu.org Reporter: sripar01 at gcc dot gnu.org Target Milestone: --- Created attachment 48362 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=48362&action=edit test case $ arm-none-eabi-gcc -v Using built-in specs. COLLECT_GCC=arm-none-eabi-gcc COLLECT_LTO_WRAPPER=/media/sripar01/2tb_work/Release/build-arm-none-eabi/install/libexec/gcc/arm-none-eabi/10.0.1/lto-wrapper Target: arm-none-eabi Configured with: /media/sripar01/2tb_work/Release/src/gcc/configure --target=arm-none-eabi --prefix=/media/sripar01/2tb_work/Release/build-arm-none-eabi/install// --with-gmp=/media/sripar01/2tb_work/Release/build-arm-none-eabi/host-tools --with-mpfr=/media/sripar01/2tb_work/Release/build-arm-none-eabi/host-tools --with-mpc=/media/sripar01/2tb_work/Release/build-arm-none-eabi/host-tools --with-isl=/media/sripar01/2tb_work/Release/build-arm-none-eabi/host-tools --disable-shared --disable-nls --disable-threads --disable-tls --enable-checking=yes --enable-languages=c --without-cloog --without-isl --with-newlib --without-headers --with-multilib-list=rmprofile --with-pkgversion=unknown Thread model: single Supported LTO compression algorithms: zlib gcc version 10.0.1 20200423 (experimental) (unknown) $ arm-none-eabi-gcc mve_vstore.i -S -O2 -march=armv8.1-m.main+mve -mfloat-abi=hard On compiling attached test case (mve_vstore.i) with -02 optimizes out a pair of vector load/store statements.
[Bug c/94735] MVE vector load/store pair getting removed with -O2.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94735 SRINATH PARVATHANENI changed: What|Removed |Added Status|UNCONFIRMED |NEW Assignee|unassigned at gcc dot gnu.org |sripar01 at gcc dot gnu.org Target||arm-none-eabi Ever confirmed|0 |1 Last reconfirmed||2020-04-23
[Bug target/94959] New: Wrong code gen for MVE intrinsics vldrbq_s32 which fails with assembler `Error: lo register required`
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94959
Bug ID: 94959
Summary: Wrong code gen for MVE intrinsics vldrbq_s32 which
fails with assembler `Error: lo register required`
Product: gcc
Version: 10.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: sripar01 at gcc dot gnu.org
Target Milestone: ---
Created attachment 48457
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=48457&action=edit
test case
$ arm-none-eabi-gcc -v
Using built-in specs.
COLLECT_GCC=arm-none-eabi-gcc
COLLECT_LTO_WRAPPER=/media/sripar01/2tb_work/Release/build-arm-none-eabi/install/libexec/gcc/arm-none-eabi/10.0.1/lto-wrapper
Target: arm-none-eabi
Configured with: /media/sripar01/2tb_work/Release/src/gcc/configure
--target=arm-none-eabi
--prefix=/media/sripar01/2tb_work/Release/build-arm-none-eabi/install//
--with-gmp=/media/sripar01/2tb_work/Release/build-arm-none-eabi/host-tools
--with-mpfr=/media/sripar01/2tb_work/Release/build-arm-none-eabi/host-tools
--with-mpc=/media/sripar01/2tb_work/Release/build-arm-none-eabi/host-tools
--with-isl=/media/sripar01/2tb_work/Release/build-arm-none-eabi/host-tools
--disable-shared --disable-nls --disable-threads --disable-tls
--enable-checking=yes --enable-languages=c,c++,fortran --with-newlib
--with-multilib-list=rmprofile --with-pkgversion=unknown
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 10.0.1 20200427 (experimental) (unknown)
$arm-none-eabi-gcc new.c -c -Ofast -march=armv8.1-m.main+mve -mfloat-abi=hard
new.c: In function 'foo':
new.c:12351:27: warning: passing argument 1 of '__arm_vldrbq_s32' makes pointer
from integer without a cast [-Wint-conversion]
12351 | b += __arm_vldrbq_s32(c1);
| ^~
| |
| char
new.c:8600:34: note: expected 'const int8_t *' {aka 'const signed char *'} but
argument is of type 'char'
8600 | __arm_vldrbq_s32 (int8_t const * __base)
| ~~~^~
/tmp/cc3Q97vs.s: Assembler messages:
/tmp/cc3Q97vs.s:47: Error: lo register required -- `vldrb.s32 q2,[ip]'
`vldrb.s32 q2,[ip]' --> For vldrbq_s32 MVE intrinsic, only low registers are
allowed as second argument and but current compiler is generating wrong code,
which is failing with assembler as shown above.
The test case added is not a properly written one (char variable c passed to
vldrbq_s32 where as expected is const int8_t *) but this is done to reproduce
the above failure.
[Bug target/94959] Wrong code gen for MVE intrinsics vldrbq_s32 which fails with assembler `Error: lo register required`
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94959 SRINATH PARVATHANENI changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |sripar01 at gcc dot gnu.org Target||arm Last reconfirmed||2020-05-05 Ever confirmed|0 |1 Status|UNCONFIRMED |NEW
[Bug target/94959] Wrong code gen for MVE intrinsics vldrbq_s32 which fails with assembler `Error: lo register required`
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94959 SRINATH PARVATHANENI changed: What|Removed |Added Resolution|--- |FIXED Status|NEW |RESOLVED --- Comment #3 from SRINATH PARVATHANENI --- Committed patch to trunk and backported to GCC-10.
[Bug target/94735] MVE vector load/store pair getting removed with -O2.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94735 SRINATH PARVATHANENI changed: What|Removed |Added Resolution|--- |FIXED Status|NEW |RESOLVED --- Comment #3 from SRINATH PARVATHANENI --- Committed patch to trunk and gcc-10.
[Bug c/96682] Arm: Wrong code generated for MVE with -O1 and above optimization options.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96682 SRINATH PARVATHANENI changed: What|Removed |Added Status|UNCONFIRMED |NEW Ever confirmed|0 |1 Last reconfirmed||2020-08-18
[Bug c/96682] New: Arm: Wrong code generated for MVE with -O1 and above optimization options.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96682
Bug ID: 96682
Summary: Arm: Wrong code generated for MVE with -O1 and above
optimization options.
Product: gcc
Version: 10.2.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: sripar01 at gcc dot gnu.org
Target Milestone: ---
Target: arm
Created attachment 49074
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=49074&action=edit
test case
$ arm-none-eabi -v
Using built-in specs.
COLLECT_GCC=../MVE_PUBLIC/gcc-arm-none-eabi-10-2020-q2-preview/bin/arm-none-eabi-gcc
COLLECT_LTO_WRAPPER=/media/sripar01/2tb_work/MVE_PUBLIC/gcc-arm-none-eabi-10-2020-q2-preview/bin/../lib/gcc/arm-none-eabi/10.1.1/lto-wrapper
Target: arm-none-eabi
Configured with:
/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-13_20200625_1593044217/src/gcc/configure
--target=arm-none-eabi
--prefix=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-13_20200625_1593044217/install-native
--libexecdir=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-13_20200625_1593044217/install-native/lib
--infodir=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-13_20200625_1593044217/install-native/share/doc/gcc-arm-none-eabi/info
--mandir=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-13_20200625_1593044217/install-native/share/doc/gcc-arm-none-eabi/man
--htmldir=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-13_20200625_1593044217/install-native/share/doc/gcc-arm-none-eabi/html
--pdfdir=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-13_20200625_1593044217/install-native/share/doc/gcc-arm-none-eabi/pdf
--enable-languages=c,c++ --enable-plugins --disable-decimal-float
--disable-libffi --disable-libgomp --disable-libmudflap --disable-libquadmath
--disable-libssp --disable-libstdcxx-pch --disable-nls --disable-shared
--disable-threads --disable-tls --with-gnu-as --with-gnu-ld --with-newlib
--with-headers=yes --with-python-dir=share/gcc-arm-none-eabi
--with-sysroot=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-13_20200625_1593044217/install-native/arm-none-eabi
--build=x86_64-linux-gnu --host=x86_64-linux-gnu
--with-gmp=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-13_20200625_1593044217/build-native/host-libs/usr
--with-mpfr=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-13_20200625_1593044217/build-native/host-libs/usr
--with-mpc=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-13_20200625_1593044217/build-native/host-libs/usr
--with-isl=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-13_20200625_1593044217/build-native/host-libs/usr
--with-libelf=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-13_20200625_1593044217/build-native/host-libs/usr
--with-host-libstdcxx='-static-libgcc -Wl,-Bstatic,-lstdc++,-Bdynamic -lm'
--with-pkgversion='GNU Arm Embedded Toolchain 10-2020-q2-preview'
--with-multilib-list=rmprofile,aprofile
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 10.1.1 20200529 (release) (GNU Arm Embedded Toolchain
10-2020-q2-preview)
$ arm-none-eabi-gcc bug.c -mfloat-abi=hard -march=armv8.1-m.main+mve.fp -O3 -c
x.i:65:1: warning: return type defaults to 'int' [-Wimplicit-int]
65 | fn1(__fp16 *pSrc) {
| ^~~
/tmp/ccOTL3zZ.s: Assembler messages:
/tmp/ccOTL3zZ.s:40: Error: instruction does not support writeback -- `vldr.16
s15,[r0]!'
vldr.16 and vstr.16 does not support write back for MVE, wrong code-gen for the
attached test case bug.c.
[Bug c/96683] New: Arm: MVE ACLE intrinsics vst1q_{s8|u8|s16|u16} is not supported by GCC.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96683
Bug ID: 96683
Summary: Arm: MVE ACLE intrinsics vst1q_{s8|u8|s16|u16} is not
supported by GCC.
Product: gcc
Version: 11.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: sripar01 at gcc dot gnu.org
Target Milestone: ---
Target: arm
Created attachment 49076
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=49076&action=edit
test case
$ arm-none-eabi-gcc -v
Using built-in specs.
COLLECT_GCC=arm-none-eabi-gcc
COLLECT_LTO_WRAPPER=/work/gnu-work/Release/build-arm-none-eabi/install/libexec/gcc/arm-none-eabi/10.2.1/lto-wrapper
Target: arm-none-eabi
Configured with: /work/gnu-work/Release/src/gcc/configure
--target=arm-none-eabi
--prefix=/work/gnu-work/Release/build-arm-none-eabi/install//
--with-gmp=/work/gnu-work/Release/build-arm-none-eabi/host-tools
--with-mpfr=/work/gnu-work/Release/build-arm-none-eabi/host-tools
--with-mpc=/work/gnu-work/Release/build-arm-none-eabi/host-tools
--with-isl=/work/gnu-work/Release/build-arm-none-eabi/host-tools
--disable-shared --disable-nls --disable-threads --disable-tls
--enable-checking=yes --enable-languages=c,c++,fortran --with-newlib
--with-multilib-list=rmprofile --with-pkgversion=unknown : (reconfigured)
/work/gnu-work/Release/src/gcc/configure --target=arm-none-eabi
--prefix=/work/gnu-work/Release/build-arm-none-eabi/install//
--with-gmp=/work/gnu-work/Release/build-arm-none-eabi/host-tools
--with-mpfr=/work/gnu-work/Release/build-arm-none-eabi/host-tools
--with-mpc=/work/gnu-work/Release/build-arm-none-eabi/host-tools
--with-isl=/work/gnu-work/Release/build-arm-none-eabi/host-tools
--disable-shared --disable-nls --disable-threads --disable-tls
--enable-checking=yes --with-newlib --with-multilib-list=rmprofile
--with-pkgversion=unknown target_alias=arm-none-eabi CFLAGS='-O0 -g3'
CXXFLAGS='-O0 -g3' --enable-languages=c,c++,fortran,lto --no-create
--no-recursion
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 10.2.1 20200803 (unknown)
$ arm-none-eabi-gcc bug.c -mfloat-abi=hard -march=armv8.1-m.main+mve.fp -O3
bug.c: In function 'foo':
bug.c:9358:3: error: this builtin is not supported for this target
9358 | __builtin_mve_vst1q_sv8hi ((__builtin_neon_hi *) __addr, __value);
| ^
gcc for arm-none-eabi target fails to compile MVE ACLE intrinsics
vst1q(_s8|_s16|_u8|_u16).
[Bug c/96684] New: arm: MVE intrinsics / __ARM_undef presence in f16 vector max routine
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96684 Bug ID: 96684 Summary: arm: MVE intrinsics / __ARM_undef presence in f16 vector max routine Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: c Assignee: unassigned at gcc dot gnu.org Reporter: sripar01 at gcc dot gnu.org Target Milestone: --- Target: arm Created attachment 49077 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=49077&action=edit test case $ arm-none-eabi-gcc -v Using built-in specs. COLLECT_GCC=arm-none-eabi-gcc COLLECT_LTO_WRAPPER=/work/gnu-work/Release/build-arm-none-eabi/install/libexec/gcc/arm-none-eabi/10.2.1/lto-wrapper Target: arm-none-eabi Configured with: /work/gnu-work/Release/src/gcc/configure --target=arm-none-eabi --prefix=/work/gnu-work/Release/build-arm-none-eabi/install// --with-gmp=/work/gnu-work/Release/build-arm-none-eabi/host-tools --with-mpfr=/work/gnu-work/Release/build-arm-none-eabi/host-tools --with-mpc=/work/gnu-work/Release/build-arm-none-eabi/host-tools --with-isl=/work/gnu-work/Release/build-arm-none-eabi/host-tools --disable-shared --disable-nls --disable-threads --disable-tls --enable-checking=yes --enable-languages=c,c++,fortran --with-newlib --with-multilib-list=rmprofile --with-pkgversion=unknown : (reconfigured) /work/gnu-work/Release/src/gcc/configure --target=arm-none-eabi --prefix=/work/gnu-work/Release/build-arm-none-eabi/install// --with-gmp=/work/gnu-work/Release/build-arm-none-eabi/host-tools --with-mpfr=/work/gnu-work/Release/build-arm-none-eabi/host-tools --with-mpc=/work/gnu-work/Release/build-arm-none-eabi/host-tools --with-isl=/work/gnu-work/Release/build-arm-none-eabi/host-tools --disable-shared --disable-nls --disable-threads --disable-tls --enable-checking=yes --with-newlib --with-multilib-list=rmprofile --with-pkgversion=unknown target_alias=arm-none-eabi CFLAGS='-O0 -g3' CXXFLAGS='-O0 -g3' --enable-languages=c,c++,fortran,lto --no-create --no-recursion Thread model: single Supported LTO compression algorithms: zlib gcc version 10.2.1 20200803 (unknown) $ arm-none-eabi-gcc bug.c -mfloat-abi=hard -march=armv8.1-m.main+mve.fp -O3 --specs=rdimon.specs /work/gnu-work/Release/build-arm-none-eabi/install/lib/gcc/arm-none-eabi/10.2.1/../../../../arm-none-eabi/bin/ld: /tmp/ccQXZj1p.o: in function `main': bug.c:(.text.startup+0x30): undefined reference to `__ARM_undef' collect2: error: ld returned 1 exit status
[Bug c/96684] arm: MVE intrinsics / __ARM_undef presence in f16 vector max routine
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96684 SRINATH PARVATHANENI changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed||2020-08-18 Ever confirmed|0 |1 --- Comment #1 from SRINATH PARVATHANENI --- __ARM_undef undefined reference generated from the test cases for the compiler. Need to fix this.
[Bug c/96683] Arm: MVE ACLE intrinsics vst1q_{s8|u8|s16|u16} is not supported by GCC.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96683 SRINATH PARVATHANENI changed: What|Removed |Added Last reconfirmed||2020-08-18 Ever confirmed|0 |1 Status|UNCONFIRMED |NEW
[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233 SRINATH PARVATHANENI changed: What|Removed |Added CC||sripar01 at gcc dot gnu.org --- Comment #28 from SRINATH PARVATHANENI --- (In reply to Christophe Lyon from comment #24) > Created attachment 49169 [details] > a32/a64 intrinsics not supported by the aarch64 target The __crc* intrinsic are already supported (but defined in arm_acle.h instead). arm_acle.h:__crc32b (uint32_t __a, uint8_t __b) arm_acle.h:__crc32cb (uint32_t __a, uint8_t __b) arm_acle.h:__crc32cd (uint32_t __a, uint64_t __b) arm_acle.h:__crc32ch (uint32_t __a, uint16_t __b) arm_acle.h:__crc32cw (uint32_t __a, uint32_t __b) arm_acle.h:__crc32d (uint32_t __a, uint64_t __b) arm_acle.h:__crc32h (uint32_t __a, uint16_t __b) arm_acle.h:__crc32w (uint32_t __a, uint32_t __b)
[Bug target/95421] [AArch64] Missing NEON functions documented on ARM's web site
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95421
SRINATH PARVATHANENI changed:
What|Removed |Added
CC||sripar01 at gcc dot gnu.org
--- Comment #3 from SRINATH PARVATHANENI ---
I see following intrinsics for AArch64 already implemented.
vst3q_lane_p8
vst3q_lane_s8
vst3q_lane_u8
__extension__ extern __inline void __attribute__ ((__always_inline__,
__gnu_inline__, __artificial__)) vst3q_lane_p8 (poly8_t *__ptr, poly8x16x3_t
__b, const int __c) { union { poly8x16x3_t __i; __builtin_aarch64_simd_ci __o;
} __temp = { __b }; __builtin_aarch64_st3_lanev16qi ((__builtin_aarch64_simd_qi
*) __ptr, __temp.__o, __c); }
__extension__ extern __inline void __attribute__ ((__always_inline__,
__gnu_inline__, __artificial__)) vst3q_lane_s8 (int8_t *__ptr, int8x16x3_t __b,
const int __c) { union { int8x16x3_t __i; __builtin_aarch64_simd_ci __o; }
__temp = { __b }; __builtin_aarch64_st3_lanev16qi ((__builtin_aarch64_simd_qi
*) __ptr, __temp.__o, __c); }
__extension__ extern __inline void __attribute__ ((__always_inline__,
__gnu_inline__, __artificial__)) vst3q_lane_u8 (uint8_t *__ptr, uint8x16x3_t
__b, const int __c) { union { uint8x16x3_t __i; __builtin_aarch64_simd_ci __o;
} __temp = { __b }; __builtin_aarch64_st3_lanev16qi ((__builtin_aarch64_simd_qi
*) __ptr, __temp.__o, __c); }
[Bug c/99939] New: CMSE: -march=armv8.1-m.main+mve does not support correctly.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99939 Bug ID: 99939 Summary: CMSE: -march=armv8.1-m.main+mve does not support correctly. Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: c Assignee: unassigned at gcc dot gnu.org Reporter: sripar01 at gcc dot gnu.org Target Milestone: --- Host: x86_64 Target: arm Created attachment 50515 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=50515&action=edit Pre-processor output file The current arm-none-eabi-gcc does not support CMSE correctly on passing command line option "-march=armv8.1-m.main+mve -mfloat-abi=hard -mfpu=auto -mcmse". On compiling the attached testcase test.c with mentioned command line I see following error message: $ arm-none-eabi-gcc -march=armv8.1-m.main+mve -mcmse -mfpu=auto -mfloat-abi=hard -Wl,-section-start=.gnu.sgstubs=0x19 --specs=rdimon.specs test.i /media/sripar01/2tb_work/embedded_toolchain/gcc-arm-none-eabi-10-2020-q4-major/bin/../lib/gcc/arm-none-eabi/10.2.1/../../../../arm-none-eabi/bin/ld: /tmp/cc8Jg0A2.o: in function `secure_fun': test.i:(.text+0x16): undefined reference to `cmse_check_address_range' collect2: error: ld returned 1 exit status I see "undefined reference to `cmse_check_address_range'" in the error message but this function is present in the file gcc/libgcc/config/arm/cmse.c and is available for multilib build with `-mcmse` option. $ arm-none-eabi-gcc -v Using built-in specs. COLLECT_GCC=arm-none-eabi-gcc COLLECT_LTO_WRAPPER=/media/sripar01/2tb_work/embedded_toolchain/gcc-arm-none-eabi-10-2020-q4-major/bin/../lib/gcc/arm-none-eabi/10.2.1/lto-wrapper Target: arm-none-eabi Configured with: /mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-48_20201124_1606180641/src/gcc/configure --target=arm-none-eabi --prefix=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-48_20201124_1606180641/install-native --libexecdir=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-48_20201124_1606180641/install-native/lib --infodir=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-48_20201124_1606180641/install-native/share/doc/gcc-arm-none-eabi/info --mandir=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-48_20201124_1606180641/install-native/share/doc/gcc-arm-none-eabi/man --htmldir=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-48_20201124_1606180641/install-native/share/doc/gcc-arm-none-eabi/html --pdfdir=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-48_20201124_1606180641/install-native/share/doc/gcc-arm-none-eabi/pdf --enable-languages=c,c++ --enable-plugins --disable-decimal-float --disable-libffi --disable-libgomp --disable-libmudflap --disable-libquadmath --disable-libssp --disable-libstdcxx-pch --disable-nls --disable-shared --disable-threads --disable-tls --with-gnu-as --with-gnu-ld --with-newlib --with-headers=yes --with-python-dir=share/gcc-arm-none-eabi --with-sysroot=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-48_20201124_1606180641/install-native/arm-none-eabi --build=x86_64-linux-gnu --host=x86_64-linux-gnu --with-gmp=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-48_20201124_1606180641/build-native/host-libs/usr --with-mpfr=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-48_20201124_1606180641/build-native/host-libs/usr --with-mpc=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-48_20201124_1606180641/build-native/host-libs/usr --with-isl=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-48_20201124_1606180641/build-native/host-libs/usr --with-libelf=/mnt/workspace/workspace/GCC-10-pipeline/jenkins-GCC-10-pipeline-48_20201124_1606180641/build-native/host-libs/usr --with-host-libstdcxx='-static-libgcc -Wl,-Bstatic,-lstdc++,-Bdynamic -lm' --with-pkgversion='GNU Arm Embedded Toolchain 10-2020-q4-major' --with-multilib-list=rmprofile,aprofile Thread model: single Supported LTO compression algorithms: zlib gcc version 10.2.1 20201103 (release) (GNU Arm Embedded Toolchain 10-2020-q4-major)
[Bug target/97205] arm: Compiler fails with an ICE for -O0 on Trunk and GCC-10 for _Generic feature.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97205 SRINATH PARVATHANENI changed: What|Removed |Added CC||bernd.edlinger at hotmail dot de, ||rguenth at gcc dot gnu.org --- Comment #1 from SRINATH PARVATHANENI --- On bisecting I found the following patch is causing the ICE. 70cdb21e579191fe9f0f1d45e328908e59c0179e is the first bad commit commit 70cdb21e579191fe9f0f1d45e328908e59c0179e Author: Bernd Edlinger Date: Wed Aug 28 10:18:23 2019 + expr.c (expand_assignment): Handle misaligned DECLs. 2019-09-28 Bernd Edlinger Richard Biener * expr.c (expand_assignment): Handle misaligned DECLs. (expand_expr_real_1): Handle FUNCTION_DECL as unaligned. * function.c (assign_parm_adjust_stack_rtl): Check movmisalign optab too. (assign_parm_setup_stack): Allocate properly aligned stack slots. * varasm.c (build_constant_desc): Align constants of misaligned types. * config/arm/predicates.md (aligned_operand): New predicate. * config/arm/arm.md (movdi, movsi, movhi, movhf, movsf, movdf): Use aligned_operand to check restrictions on memory addresses. * config/arm/neon.md (movti, mov, mov): Likewise. * config/arm/vec-common.md (mov): Likewise. Co-Authored-By: Richard Biener
[Bug libgomp/97291] [SIMT] Move SIMT_XCHG_* out of non-uniform execution region
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97291 SRINATH PARVATHANENI changed: What|Removed |Added CC||sripar01 at gcc dot gnu.org --- Comment #4 from SRINATH PARVATHANENI --- Sorry those are wrong commits, their are meant for PR97271.
[Bug target/97271] [ARM MVE]: Wrong code generated for scatter store with writeback intrinsics with -O2.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97271
SRINATH PARVATHANENI changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|--- |FIXED
--- Comment #1 from SRINATH PARVATHANENI ---
Committed to trunk:
commit 377535881166969dba43794f298170978d797ef6
Author: Srinath Parvathaneni
Date: Fri Oct 16 11:40:25 2020 +0100
arm: Fix wrong code generated for mve scatter store with writeback
intrinsics with -O2 (PR97271).
This patch fixes (PR97271) the wrong code-gen for mve scatter store with
writeback intrinsics with -O2.
$cat bug.c
void
foo (uint32x4_t * addr, const int offset, int32x4_t value)
{
vstrwq_scatter_base_wb_s32 (addr, 8, value);
}
$ arm-none-eabi-gcc bug.c -S -O2 -march=armv8.1-m.main+mve
-mfloat-abi=hard -o -
Without this patch:
...
foo:
vldrw.32q3, [r0]
vstrw.u32 q0, [q3, #8]! ---> (A)
vldr.64 d4, .L3
vldr.64 d5, .L3+8
vldrw.32q3, [r0]
vstrw.u32 q2, [q3, #8]! ---> (B)
bx lr
...
With this patch:
...
foo:
vldrw.32q3, [r0]
vstrw.u32 q0, [q3, #8]! --> (C)
vstrw.32q3, [r0]
bx lr
...
Without this patch 2 vstrw assembly instructions (A and B) are generated
for vstrwq_scatter_base_wb_s32
intrinsic where as fix generates only one vstrw assembly instruction (C).
Committed to GCC-10:
commit 4199cfa3d18eb99893456bd461061daa75115711
Author: Srinath Parvathaneni
Date: Fri Oct 16 11:40:25 2020 +0100
arm: Fix wrong code generated for mve scatter store with writeback
intrinsics with -O2 (PR97271).
This patch fixes (PR97271) the wrong code-gen for mve scatter store with
writeback intrinsics with -O2.
$cat bug.c
void
foo (uint32x4_t * addr, const int offset, int32x4_t value)
{
vstrwq_scatter_base_wb_s32 (addr, 8, value);
}
$ arm-none-eabi-gcc bug.c -S -O2 -march=armv8.1-m.main+mve
-mfloat-abi=hard -o -
Without this patch:
...
foo:
vldrw.32q3, [r0]
vstrw.u32 q0, [q3, #8]! ---> (A)
vldr.64 d4, .L3
vldr.64 d5, .L3+8
vldrw.32q3, [r0]
vstrw.u32 q2, [q3, #8]! ---> (B)
bx lr
...
With this patch:
...
foo:
vldrw.32q3, [r0]
vstrw.u32 q0, [q3, #8]! --> (C)
vstrw.32q3, [r0]
bx lr
...
Without this patch 2 vstrw assembly instructions (A and B) are generated
for vstrwq_scatter_base_wb_s32
intrinsic where as fix generates only one vstrw assembly instruction (C).
[Bug target/97327] -mcpu=cortex-m55 warns without -mfloat-abi=hard or -march=armv8.1-m.main
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97327 SRINATH PARVATHANENI changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|--- |FIXED --- Comment #8 from SRINATH PARVATHANENI --- Committed patches to trunk and GCC-10 branches.
[Bug target/96682] Arm: Wrong code generated for MVE with -O1 and above optimization options.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96682 SRINATH PARVATHANENI changed: What|Removed |Added Resolution|--- |FIXED Status|NEW |RESOLVED --- Comment #2 from SRINATH PARVATHANENI --- Pushed fix to trunk and gcc-10 branches.
[Bug target/96683] Arm: MVE ACLE intrinsics vst1q_{s8|u8|s16|u16} is not supported by GCC.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96683 SRINATH PARVATHANENI changed: What|Removed |Added Resolution|--- |FIXED Status|NEW |RESOLVED --- Comment #3 from SRINATH PARVATHANENI --- Pushed patch to trunk and gcc-10 branch.
[Bug target/96684] arm: MVE intrinsics / __ARM_undef presence in f16 vector max routine
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96684 SRINATH PARVATHANENI changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #2 from SRINATH PARVATHANENI --- Committed patch to trunk and gcc-10 branch as below. commit 251950d899bc3c18b5775fe9fe20bebbdc8d15cb Author: Joe Ramsay Date: Fri Oct 2 15:28:29 2020 +0100 commit e68d5be766d7b94f2cddb42cc0d62be9039f34e0 Author: Joe Ramsay Date: Fri Oct 2 15:28:29 2020 +0100 arm: Remove coercion from scalar argument to vmin & vmax intrinsics
[Bug target/97205] arm: Compiler fails with an ICE for -O0 on Trunk and GCC-10 for _Generic feature.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97205
--- Comment #4 from SRINATH PARVATHANENI ---
(In reply to Bernd Edlinger from comment #2)
> Thanks for reporting this.
>
> The expansion of assignments to misaligned ssa names
> does not handle the case of misaligned stores, which
> would result in incorrect code without the assertion.
>
> I have an untested patch below:
>
> diff --git a/gcc/emit-rtl.c b/gcc/emit-rtl.c
> index 3706f0a..12b81cd 100644
> --- a/gcc/emit-rtl.c
> +++ b/gcc/emit-rtl.c
> @@ -2089,7 +2089,8 @@ set_mem_attributes_minus_bitpos (rtx ref, tree t, int
> objectp,
> {
> gcc_assert (handled_component_p (t)
> || TREE_CODE (t) == MEM_REF
> - || TREE_CODE (t) == TARGET_MEM_REF);
> + || TREE_CODE (t) == TARGET_MEM_REF
> + || TREE_CODE (t) == SSA_NAME);
> attrs.expr = t;
> attrs.offset_known_p = true;
> attrs.offset = 0;
> diff --git a/gcc/expr.c b/gcc/expr.c
> index 9d951e8..49f2699 100644
> --- a/gcc/expr.c
> +++ b/gcc/expr.c
> @@ -5200,6 +5200,9 @@ expand_assignment (tree to, tree from, bool
> nontemporal)
>|| (TREE_CODE (to) == MEM_REF
> && (REF_REVERSE_STORAGE_ORDER (to)
> || mem_ref_refers_to_non_mem_p (to)))
> + || (TREE_CODE (to) == SSA_NAME
> + && mode != BLKmode
> + && TYPE_ALIGN (TREE_TYPE (to)) < GET_MODE_ALIGNMENT (mode))
>|| TREE_CODE (TREE_TYPE (to)) == ARRAY_TYPE)
> {
>machine_mode mode1;
> diff --git a/gcc/testsuite/gcc.c-torture/compile/pr97205.c
> b/gcc/testsuite/gcc.c-torture/compile/pr97205.c
> new file mode 100644
> index 000..6600011
> --- /dev/null
> +++ b/gcc/testsuite/gcc.c-torture/compile/pr97205.c
> @@ -0,0 +1,7 @@
> +int a;
> +typedef __attribute__((aligned(2))) int x;
> +int f ()
> +{
> + x b = a;
> + return b;
> +}
With the above patch I'm getting ICE as below while building arm-none-eabi
target:
checking for scalbnl... during RTL pass: expand
generice_bug/src/gcc/libstdc++-v3/src/c++98/locale_init.cc: In constructor
'std::locale::_Impl::_Impl(std::size_t)':
generice_bug/src/gcc/libstdc++-v3/src/c++98/locale_init.cc:471:3: internal
compiler error: tree check: expected bit_field_ref or mem_ref, have ssa_name in
expand_assignment, at expr.c:5203
471 | locale::_Impl::
| ^~
[Bug target/97205] arm: Compiler fails with an ICE for -O0 on Trunk and GCC-10 for _Generic feature.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97205 --- Comment #8 from SRINATH PARVATHANENI --- (In reply to Bernd Edlinger from comment #5) > (In reply to SRINATH PARVATHANENI from comment #4) > > With the above patch I'm getting ICE as below while building arm-none-eabi > > target: > > > > checking for scalbnl... during RTL pass: expand > > > > generice_bug/src/gcc/libstdc++-v3/src/c++98/locale_init.cc: In constructor > > 'std::locale::_Impl::_Impl(std::size_t)': > > > > generice_bug/src/gcc/libstdc++-v3/src/c++98/locale_init.cc:471:3: internal > > compiler error: tree check: expected bit_field_ref or mem_ref, have ssa_name > > in expand_assignment, at expr.c:5203 > > 471 | locale::_Impl:: > > | ^~ > > Hmm, it looks like I cannot reproduce this, > which version did you use for that ? > what is in line 5203 of expr.c ? Sorry for confusing you by mentioned ICE, that was because of merge conflict. I have resolved the conflict and applied the patch correctly. The build is successful and I have tested the test reported in this Bugzilla and it is fixed. Thanks.
[Bug target/97205] arm: Compiler fails with an ICE for -O0 on Trunk and GCC-10 for _Generic feature.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97205 --- Comment #15 from SRINATH PARVATHANENI --- (In reply to Bernd Edlinger from comment #14) > fixed on trunk. Thanks Bernd for fixing this on trunk, would you mind backporting this to GCC-10 as well? Thanks you. Regards, Srinath.
[Bug c/97205] New: arm: Compiler fails with an ICE for -O0 on Trunk and GCC-10 for _Generic feature.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97205
Bug ID: 97205
Summary: arm: Compiler fails with an ICE for -O0 on Trunk and
GCC-10 for _Generic feature.
Product: gcc
Version: 11.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: sripar01 at gcc dot gnu.org
Target Milestone: ---
Target: arm
Created attachment 49270
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=49270&action=edit
testcase
Nested _Generic feature generating ICE with -O0 on GCC Trunk and GCC-10.
$arm-none-eabi-gcc -v
Using built-in specs.
COLLECT_GCC=/arm/pdtl/builds/fsf-trunk.2226/installed/rhe6x86_64/arm-none-eabi/bin/arm-none-eabi-gcc
COLLECT_LTO_WRAPPER=/arm/pdtl/builds/fsf-trunk.2226/installed/rhe6x86_64/arm-none-eabi/bin/../libexec/gcc/arm-none-eabi/11.0.0/lto-wrapper
Target: arm-none-eabi
Configured with:
/tmp/dgboter/bbs/rhev-vm5--rhe6x86_64/buildbot/rhe6x86_64--arm-none-eabi/build/src/gcc/configure
--target=arm-none-eabi
--prefix=/tmp/dgboter/bbs/rhev-vm5--rhe6x86_64/buildbot/rhe6x86_64--arm-none-eabi/build/build-arm-none-eabi/install//
--with-gmp=/tmp/dgboter/bbs/rhev-vm5--rhe6x86_64/buildbot/rhe6x86_64--arm-none-eabi/build/build-arm-none-eabi/host-tools
--with-mpfr=/tmp/dgboter/bbs/rhev-vm5--rhe6x86_64/buildbot/rhe6x86_64--arm-none-eabi/build/build-arm-none-eabi/host-tools
--with-mpc=/tmp/dgboter/bbs/rhev-vm5--rhe6x86_64/buildbot/rhe6x86_64--arm-none-eabi/build/build-arm-none-eabi/host-tools
--with-isl=/tmp/dgboter/bbs/rhev-vm5--rhe6x86_64/buildbot/rhe6x86_64--arm-none-eabi/build/build-arm-none-eabi/host-tools
--disable-shared --disable-nls --disable-threads --disable-tls
--enable-checking=yes --enable-languages=c,c++,fortran --with-newlib
--with-multilib-list=aprofile --with-pkgversion=fsf-trunk.2226
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 11.0.0 20200609 (experimental) (fsf-trunk.2226)
$ cat x.c
int a;
typedef __attribute__((aligned(2))) int x;
int fn1() {
x b = ({
_Generic(_Generic(fn1, default : a), int : _Generic(fn1, default : a));
});
return b;
}
$ arm-none-eabi-gcc x.c -O0 -c -Wall -Werror
during RTL pass: expand
x.c: In function 'fn1':
x.c:4:5: internal compiler error: in gen_movsi, at config/arm/arm.md:6364
4 | x b = ({
| ^
0x1516e1d gen_movsi(rtx_def*, rtx_def*)
/tmp/dgboter/bbs/rhev-vm5--rhe6x86_64/buildbot/rhe6x86_64--arm-none-eabi/build/src/gcc/gcc/config/arm/arm.md:6364
0x925ddf insn_gen_fn::operator()(rtx_def*, rtx_def*) const
/tmp/dgboter/bbs/rhev-vm5--rhe6x86_64/buildbot/rhe6x86_64--arm-none-eabi/build/src/gcc/gcc/recog.h:317
0x925ddf emit_move_insn_1(rtx_def*, rtx_def*)
/tmp/dgboter/bbs/rhev-vm5--rhe6x86_64/buildbot/rhe6x86_64--arm-none-eabi/build/src/gcc/gcc/expr.c:3759
0x926872 emit_move_insn(rtx_def*, rtx_def*)
/tmp/dgboter/bbs/rhev-vm5--rhe6x86_64/buildbot/rhe6x86_64--arm-none-eabi/build/src/gcc/gcc/expr.c:3929
0x92ef96 store_expr(tree_node*, rtx_def*, int, bool, bool)
/tmp/dgboter/bbs/rhev-vm5--rhe6x86_64/buildbot/rhe6x86_64--arm-none-eabi/build/src/gcc/gcc/expr.c:6038
0x93172e expand_assignment(tree_node*, tree_node*, bool)
/tmp/dgboter/bbs/rhev-vm5--rhe6x86_64/buildbot/rhe6x86_64--arm-none-eabi/build/src/gcc/gcc/expr.c:5588
0x7dd4bc expand_gimple_stmt_1
/tmp/dgboter/bbs/rhev-vm5--rhe6x86_64/buildbot/rhe6x86_64--arm-none-eabi/build/src/gcc/gcc/cfgexpand.c:3751
0x7dd4bc expand_gimple_stmt
/tmp/dgboter/bbs/rhev-vm5--rhe6x86_64/buildbot/rhe6x86_64--arm-none-eabi/build/src/gcc/gcc/cfgexpand.c:3847
0x7dfd75 expand_gimple_basic_block
/tmp/dgboter/bbs/rhev-vm5--rhe6x86_64/buildbot/rhe6x86_64--arm-none-eabi/build/src/gcc/gcc/cfgexpand.c:5888
0x7e0c7e execute
/tmp/dgboter/bbs/rhev-vm5--rhe6x86_64/buildbot/rhe6x86_64--arm-none-eabi/build/src/gcc/gcc/cfgexpand.c:6572
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
[Bug target/96795] MVE: issue with polymorphism and integer promotion
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96795 SRINATH PARVATHANENI changed: What|Removed |Added Last reconfirmed||2020-10-01 Status|UNCONFIRMED |ASSIGNED Assignee|unassigned at gcc dot gnu.org |sripar01 at gcc dot gnu.org CC||sripar01 at gcc dot gnu.org Ever confirmed|0 |1
[Bug target/96795] MVE: issue with polymorphism and integer promotion
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96795 SRINATH PARVATHANENI changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|--- |FIXED --- Comment #3 from SRINATH PARVATHANENI --- Fixed in trunk and gcc-10.
[Bug target/97271] New: [ARM MVE]: Wrong code generated for scatter store with writeback intrinsics with -O2.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97271
Bug ID: 97271
Summary: [ARM MVE]: Wrong code generated for scatter store with
writeback intrinsics with -O2.
Product: gcc
Version: 11.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: sripar01 at gcc dot gnu.org
Target Milestone: ---
Created attachment 49300
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=49300&action=edit
test case
$ arm-none-eabi-gcc -v
Using built-in specs.
COLLECT_GCC=/work/gnu-work/Release/build-arm-none-eabi/install/bin/arm-none-eabi-gcc
COLLECT_LTO_WRAPPER=/work/gnu-work/Release/build-arm-none-eabi/install/libexec/gcc/arm-none-eabi/11.0.0/lto-wrapper
Target: arm-none-eabi
Configured with: /work/gnu-work/Release/src/gcc/configure
--target=arm-none-eabi
--prefix=/work/gnu-work/Release/build-arm-none-eabi/install//
--with-gmp=/work/gnu-work/Release/build-arm-none-eabi/host-tools
--with-mpfr=/work/gnu-work/Release/build-arm-none-eabi/host-tools
--with-mpc=/work/gnu-work/Release/build-arm-none-eabi/host-tools
--with-isl=/work/gnu-work/Release/build-arm-none-eabi/host-tools
--disable-shared --disable-nls --disable-threads --disable-tls
--enable-checking=yes --enable-languages=c,c++,fortran --with-newlib
--with-multilib-list=rmprofile --with-pkgversion=unknown
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 11.0.0 20200930 (experimental) (unknown)
$ cat bug.c
#include "arm_mve.h"
void
foo (uint32x4_t * addr, const int offset, int32x4_t value)
{
vstrwq_scatter_base_wb_s32 (addr, 8, value);
}
$ arm-none-eabi-gcc bug.c -S -O2 -march=armv8.1-m.main+mve -mfloat-abi=hard -o
-
...
foo:
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
vldrw.32q3, [r0]
vstrw.u32 q0, [q3, #8]! ---> (A)
vldr.64 d4, .L3
vldr.64 d5, .L3+8
vldrw.32q3, [r0]
vstrw.u32 q2, [q3, #8]! ---> (B)
bx lr
...
Current compiler wrongly generates 2 vstrw assembly instructions, where are
only one is expected.
[Bug target/97271] [ARM MVE]: Wrong code generated for scatter store with writeback intrinsics with -O2.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97271 SRINATH PARVATHANENI changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Ever confirmed|0 |1 Assignee|unassigned at gcc dot gnu.org |sripar01 at gcc dot gnu.org Last reconfirmed||2020-10-02
[Bug target/97327] -mcpu=cortex-m55 warns without -mfloat-abi=hard or -march=armv8.1-m.main
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97327 SRINATH PARVATHANENI changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassigned at gcc dot gnu.org |sripar01 at gcc dot gnu.org
[Bug c/100419] New: Arm: arm_mve.h generates warning when compiled with -Wsystem-headers.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100419
Bug ID: 100419
Summary: Arm: arm_mve.h generates warning when compiled with
-Wsystem-headers.
Product: gcc
Version: 12.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: sripar01 at gcc dot gnu.org
Target Milestone: ---
Host: x86_64
Target: arm
On compiling following testcase using -Wsystem-headers options, generates lot
of warnings related to redefined macros in header file "arm_mve.h"
$ cat bug.c
#include "arm_mve.h"
$arm-none-eabi-gcc -mcpu=cortex-m55+nofp -mfloat-abi=hard bug.c
-Wsystem-headers -c
In file included from bug.c:1:
/media/sripar01/2tb_work/embedded_toolchain/gcc-arm-none-eabi-10-2020-q4-major/lib/gcc/arm-none-eabi/10.2.1/include/arm_mve.h:38868:
warning: "__arm_vcmpneq" redefined
38868 | #define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
|
/media/sripar01/2tb_work/embedded_toolchain/gcc-arm-none-eabi-10-2020-q4-major/lib/gcc/arm-none-eabi/10.2.1/include/arm_mve.h:38416:
note: this is the location of the previous definition
38416 | #define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
|
/media/sripar01/2tb_work/embedded_toolchain/gcc-arm-none-eabi-10-2020-q4-major/lib/gcc/arm-none-eabi/10.2.1/include/arm_mve.h:39990:
warning: "__arm_vstrwq_scatter_offset_p" redefined
39990 | #define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1
= (p1); \
|
/media/sripar01/2tb_work/embedded_toolchain/gcc-arm-none-eabi-10-2020-q4-major/lib/gcc/arm-none-eabi/10.2.1/include/arm_mve.h:39984:
note: this is the location of the previous definition
39984 | #define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1
= (p1); \
|
/media/sripar01/2tb_work/embedded_toolchain/gcc-arm-none-eabi-10-2020-q4-major/lib/gcc/arm-none-eabi/10.2.1/include/arm_mve.h:41625:
warning: "__arm_vmaxq_x" redefined
41625 | #define __arm_vmaxq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
|
/media/sripar01/2tb_work/embedded_toolchain/gcc-arm-none-eabi-10-2020-q4-major/lib/gcc/arm-none-eabi/10.2.1/include/arm_mve.h:40157:
note: this is the location of the previous definition
40157 | #define __arm_vmaxq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
|
/media/sripar01/2tb_work/embedded_toolchain/gcc-arm-none-eabi-10-2020-q4-major/lib/gcc/arm-none-eabi/10.2.1/include/arm_mve.h:41807:
warning: "__arm_vmlsdavaq" redefined
41807 | #define __arm_vmlsdavaq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
|
/media/sripar01/2tb_work/embedded_toolchain/gcc-arm-none-eabi-10-2020-q4-major/lib/gcc/arm-none-eabi/10.2.1/include/arm_mve.h:39402:
note: this is the location of the previous definition
39402 | #define __arm_vmlsdavaq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
|
/media/sripar01/2tb_work/embedded_toolchain/gcc-arm-none-eabi-10-2020-q4-major/lib/gcc/arm-none-eabi/10.2.1/include/arm_mve.h:41815:
warning: "__arm_vmlsdavaxq" redefined
41815 | #define __arm_vmlsdavaxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
|
/media/sripar01/2tb_work/embedded_toolchain/gcc-arm-none-eabi-10-2020-q4-major/lib/gcc/arm-none-eabi/10.2.1/include/arm_mve.h:39394:
note: this is the location of the previous definition
39394 | #define __arm_vmlsdavaxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
/media/sripar01/2tb_work/embedded_toolchain/gcc-arm-none-eabi-10-2020-q4-major/lib/gcc/arm-none-eabi/10.2.1/include/arm_mve.h:41830:
warning: "__arm_vmlsdavq_p" redefined
41830 | #define __arm_vmlsdavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
|
/media/sripar01/2tb_work/embedded_toolchain/gcc-arm-none-eabi-10-2020-q4-major/lib/gcc/arm-none-eabi/10.2.1/include/arm_mve.h:39384:
note: this is the location of the previous definition
39384 | #define __arm_vmlsdavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
|
/media/sripar01/2tb_work/embedded_toolchain/gcc-arm-none-eabi-10-2020-q4-major/lib/gcc/arm-none-eabi/10.2.1/include/arm_mve.h:41844:
warning: "__arm_vmlsdavxq_p" redefined
41844 | #define __arm_vmlsdavxq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
|
/media/sripar01/2tb_work/embedded_toolchain/gcc-arm-none-eabi-10-2020-q4-major/lib/gcc/arm-none-eabi/10.2.1/include/arm_mve.h:39374:
note: this is the location of the previous definition
39374 | #define __arm_vmlsdavxq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
|
/media/sripar01/2tb_work/embedded_toolchain/gcc-arm-none-eabi-10-2020-q4-major/lib/gcc/arm-none-eabi/10.2.1/include/arm_mve.h:41945:
warning: "__arm_vrmlaldavhaq" redefined
41945 | #define __arm_vrmlaldavhaq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
|
/media/sripar01/2tb_work/embedded_toolchain/gcc-arm-none-eabi-10-2020-q4-major/lib/gcc/arm-none-eabi/10.2.1/include/arm_mve.h:39364:
note: this is the locatio
[Bug target/100419] Arm: arm_mve.h generates warning when compiled with -Wsystem-headers.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100419 SRINATH PARVATHANENI changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Ever confirmed|0 |1 Last reconfirmed||2021-05-05
[Bug target/100419] Arm: arm_mve.h generates warning when compiled with -Wsystem-headers.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100419 SRINATH PARVATHANENI changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|--- |FIXED --- Comment #4 from SRINATH PARVATHANENI --- Committed to Trunk, gcc-11 and gcc-10.
[Bug target/97205] arm: Compiler fails with an ICE for -O0 on Trunk and GCC-10 for _Generic feature.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97205
--- Comment #20 from SRINATH PARVATHANENI ---
(In reply to rguent...@suse.de from comment #17)
> On Mon, 23 Nov 2020, bernd.edlinger at hotmail dot de wrote:
>
> > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97205
> >
> > --- Comment #16 from Bernd Edlinger ---
> > (In reply to SRINATH PARVATHANENI from comment #15)
> > > (In reply to Bernd Edlinger from comment #14)
> > > > fixed on trunk.
> > >
> > > Thanks Bernd for fixing this on trunk, would you mind backporting this to
> > > GCC-10 as well?
> > >
> > > Thanks you.
> > >
> > > Regards,
> > > Srinath.
> >
> > Since it is a gcc_checking_assert that triggers the ICE,
> > I assumed that does not affect a release build,
> > is that correct?
>
> That is correct.
I did not understand what you meant above, please correct me if I'm wrong.
My observation:
$ arm-none-eabi-gcc bugx.c -O0 -c
during RTL pass: expand
bugx.c: In function 'fn1':
bugx.c:4:5: internal compiler error: in gen_movsi, at config/arm/arm.md:6364
4 | x b = ({
| ^
0x14ede14 gen_movsi(rtx_def*, rtx_def*)
/data/dgboter/bbs/build22--cen7x86_64/buildbot/cen7x86_64--arm-none-eabi--all-profiles/build/src/gcc/gcc/config/arm/arm.md:6364
0x92153f insn_gen_fn::operator()(rtx_def*, rtx_def*) const
/data/dgboter/bbs/build22--cen7x86_64/buildbot/cen7x86_64--arm-none-eabi--all-profiles/build/src/gcc/gcc/recog.h:317
0x92153f emit_move_insn_1(rtx_def*, rtx_def*)
/data/dgboter/bbs/build22--cen7x86_64/buildbot/cen7x86_64--arm-none-eabi--all-profiles/build/src/gcc/gcc/expr.c:3759
0x921cf4 emit_move_insn(rtx_def*, rtx_def*)
/data/dgboter/bbs/build22--cen7x86_64/buildbot/cen7x86_64--arm-none-eabi--all-profiles/build/src/gcc/gcc/expr.c:3855
0x92a6f0 store_expr(tree_node*, rtx_def*, int, bool, bool)
/data/dgboter/bbs/build22--cen7x86_64/buildbot/cen7x86_64--arm-none-eabi--all-profiles/build/src/gcc/gcc/expr.c:5931
0x92c973 expand_assignment(tree_node*, tree_node*, bool)
/data/dgboter/bbs/build22--cen7x86_64/buildbot/cen7x86_64--arm-none-eabi--all-profiles/build/src/gcc/gcc/expr.c:5516
0x7d965c expand_gimple_stmt_1
/data/dgboter/bbs/build22--cen7x86_64/buildbot/cen7x86_64--arm-none-eabi--all-profiles/build/src/gcc/gcc/cfgexpand.c:3755
0x7d965c expand_gimple_stmt
/data/dgboter/bbs/build22--cen7x86_64/buildbot/cen7x86_64--arm-none-eabi--all-profiles/build/src/gcc/gcc/cfgexpand.c:3851
0x7dbf65 expand_gimple_basic_block
/data/dgboter/bbs/build22--cen7x86_64/buildbot/cen7x86_64--arm-none-eabi--all-profiles/build/src/gcc/gcc/cfgexpand.c:5895
0x7dce7b execute
/data/dgboter/bbs/build22--cen7x86_64/buildbot/cen7x86_64--arm-none-eabi--all-profiles/build/src/gcc/gcc/cfgexpand.c:6550
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See
[Bug target/97205] arm: Compiler fails with an ICE for -O0 on Trunk and GCC-10 for _Generic feature.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97205 --- Comment #23 from SRINATH PARVATHANENI --- (In reply to rguent...@suse.de from comment #22) > On Wed, 19 May 2021, bernd.edlinger at hotmail dot de wrote: > > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97205 > > > > --- Comment #21 from Bernd Edlinger --- > > Hi Srinath, > > > > when we add new assertions to gcc we use always a gcc_checking_assert > > nowadays, that is also the case here. > > > > The assertion is only firing in your compiler because it is a development > > snapshot 10.3.1. So that is an experimemtal version. > > 10.3.1 is not an experimental version, so the assert should not fire > there unless you configure with --enable-checking (which you might > have done). Thanks rguent...@suse.de and Bernd Edlinger. My I'm again having confusion with the wording development/release/experiment versions. All development versions checks for gcc_checking_assert whether --enable-checking=yes or --enable-checking=no (eg: 10.3.1), but release versions only check for gcc_checking_assert when --enable-checking=yes (eg:10.3.0). If I wanted to build a toolchain using development version (eg:10.3.1) and for this test to not to fail , I should either pass --enable-checking=no or apply this patch (which was committed to trunk) on the top of gcc-10.3.1 source code. Is my understanding correct?
[Bug target/97205] arm: Compiler fails with an ICE for -O0 on Trunk and GCC-10 for _Generic feature.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97205 --- Comment #25 from SRINATH PARVATHANENI --- (In reply to rguent...@suse.de from comment #24) > On Thu, 20 May 2021, sripar01 at gcc dot gnu.org wrote: > > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97205 > > > > --- Comment #23 from SRINATH PARVATHANENI --- > > (In reply to rguent...@suse.de from comment #22) > > > On Wed, 19 May 2021, bernd.edlinger at hotmail dot de wrote: > > > > > > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97205 > > > > > > > > --- Comment #21 from Bernd Edlinger > > > > --- > > > > Hi Srinath, > > > > > > > > when we add new assertions to gcc we use always a gcc_checking_assert > > > > nowadays, that is also the case here. > > > > > > > > The assertion is only firing in your compiler because it is a > > > > development > > > > snapshot 10.3.1. So that is an experimemtal version. > > > > > > 10.3.1 is not an experimental version, so the assert should not fire > > > there unless you configure with --enable-checking (which you might > > > have done). > > > > Thanks rguent...@suse.de and Bernd Edlinger. > > > > My I'm again having confusion with the wording > > development/release/experiment > > versions. > > > > All development versions checks for gcc_checking_assert whether > > --enable-checking=yes or --enable-checking=no (eg: 10.3.1), but release > > versions only check for gcc_checking_assert when --enable-checking=yes > > (eg:10.3.0). > > No. gcc_checking_assert is enabled when --enable-checking=yes > --enable-checking defaults to =yes on the master branch. On release > branches it defaults to =release, that includes snapshots and thus > 10.3.1. > > > If I wanted to build a toolchain using development version (eg:10.3.1) and > > for > > this test to not to fail , I should either pass --enable-checking=no or > > apply > > this patch (which was committed to trunk) on the top of gcc-10.3.1 source > > code. > > > > Is my understanding correct? > > You don't need anything special for 10.3.1, that is not a development > version. If you do not specify any --enable-checking at configure > time the default is that the assert does not trigger and thus > the ICE should not happen. Thanks for the clarification.
[Bug target/100856] New: Arm: Multilib mapping is missing for CDE arguments.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100856
Bug ID: 100856
Summary: Arm: Multilib mapping is missing for CDE arguments.
Product: gcc
Version: 12.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: sripar01 at gcc dot gnu.org
Target Milestone: ---
For the +cdecp extensions, properly multilib linking is missing in
arm-none-eabi.
$ arm-none-eabi-gcc -march=armv8.1-m.main+mve.fp+cdecp0+cdecp1+cdecp2
-mfloat-abi=hard -fomit-frame-pointer -mfpu=auto --print-multi-dir
.
$ cat xx.c
#include "arm_cde.h"
int main()
{
return 0;
}
$ arm-none-eabi-gcc -march=armv8.1-m.main+mve.fp+cdecp0+cdecp1+cdecp2
-mfloat-abi=hard
/media/sripar01/2tb_work/CDE/src/gcc/gcc/testsuite/gcc.target/arm/acle/xx.c
--specs=rdimon.specs
/media/sripar01/2tb_work/Bug_fixing/build-arm-none-eabi/install/lib/gcc/arm-none-eabi/12.0.0/../../../../arm-none-eabi/bin/ld:
error: /tmp/ccUBPNX2.o uses VFP register arguments, a.out does not
/media/sripar01/2tb_work/Bug_fixing/build-arm-none-eabi/install/lib/gcc/arm-none-eabi/12.0.0/../../../../arm-none-eabi/bin/ld:
error: /tmp/ccUBPNX2.o: conflicting CPU architectures 2/21
/media/sripar01/2tb_work/Bug_fixing/build-arm-none-eabi/install/lib/gcc/arm-none-eabi/12.0.0/../../../../arm-none-eabi/bin/ld:
failed to merge target specific data of file /tmp/ccUBPNX2.o
collect2: error: ld returned 1 exit status
$ arm-none-eabi-gcc -v
Using built-in specs.
COLLECT_GCC=arm-none-eabi-gcc
COLLECT_LTO_WRAPPER=/media/sripar01/2tb_work/Bug_fixing/build-arm-none-eabi/install/libexec/gcc/arm-none-eabi/12.0.0/lto-wrapper
Target: arm-none-eabi
Configured with: /media/sripar01/2tb_work/Bug_fixing/src/gcc/configure
--target=arm-none-eabi
--prefix=/media/sripar01/2tb_work/Bug_fixing/build-arm-none-eabi/install//
--with-gmp=/media/sripar01/2tb_work/Bug_fixing/build-arm-none-eabi/host-tools
--with-mpfr=/media/sripar01/2tb_work/Bug_fixing/build-arm-none-eabi/host-tools
--with-mpc=/media/sripar01/2tb_work/Bug_fixing/build-arm-none-eabi/host-tools
--with-isl=/media/sripar01/2tb_work/Bug_fixing/build-arm-none-eabi/host-tools
--disable-shared --disable-nls --disable-threads --disable-tls
--enable-checking=yes --enable-languages=c,c++,fortran --with-newlib
--with-multilib-list=rmprofile --with-pkgversion=unknown
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 12.0.0 20210520 (experimental) (unknown)
[Bug target/100856] Arm: Multilib mapping is missing for CDE arguments.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100856 SRINATH PARVATHANENI changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Last reconfirmed||2021-06-01 Ever confirmed|0 |1 Target||arm-none-eabi
[Bug target/101016] New: Arm: vld1q polymorphic variants failing with __ARM_undef undefined reference error during linking.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101016
Bug ID: 101016
Summary: Arm: vld1q polymorphic variants failing with
__ARM_undef undefined reference error during linking.
Product: gcc
Version: 12.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: sripar01 at gcc dot gnu.org
Target Milestone: ---
The following testcase test.c is failing with undefined reference to
`__ARM_undef' at linking.
$cat test.c
#include "arm_mve.h"
void fn1() {
uint32_t orgOffsetArray[1];
vld1q(orgOffsetArray);
}
$arm-none-eabi-gcc test.c -mcpu=cortex-m55 -mfloat-abi=hard
--specs=rdimon.specs
/media/sripar01/2tb_work/CDE/build-arm-none-eabi/install/lib/gcc/arm-none-eabi/12.0.0/../../../../arm-none-eabi/bin/ld:
/media/sripar01/2tb_work/CDE/build-arm-none-eabi/install/lib/gcc/arm-none-eabi/12.0.0/../../../../arm-none-eabi/lib/thumb/v8-m.main+dp/hard/rdimon-crt0.o:
in function `_mainCRTStartup':
/media/sripar01/2tb_work/CDE/src/newlib-cygwin/libgloss/arm/crt0.S:545:
undefined reference to `main'
/media/sripar01/2tb_work/CDE/build-arm-none-eabi/install/lib/gcc/arm-none-eabi/12.0.0/../../../../arm-none-eabi/bin/ld:
/tmp/ccqfgEBM.o: in function `fn1':
test.c:(.text+0x1c): undefined reference to `__ARM_undef'
collect2: error: ld returned 1 exit status
$arm-none-eabi-gcc -v
Using built-in specs.
COLLECT_GCC=/media/sripar01/2tb_work/CDE/build-arm-none-eabi/install/bin/arm-none-eabi-gcc
COLLECT_LTO_WRAPPER=/media/sripar01/2tb_work/CDE/build-arm-none-eabi/install/libexec/gcc/arm-none-eabi/12.0.0/lto-wrapper
Target: arm-none-eabi
Configured with: /media/sripar01/2tb_work/CDE/src/gcc/configure
--target=arm-none-eabi
--prefix=/media/sripar01/2tb_work/CDE/build-arm-none-eabi/install//
--with-gmp=/media/sripar01/2tb_work/CDE/build-arm-none-eabi/host-tools
--with-mpfr=/media/sripar01/2tb_work/CDE/build-arm-none-eabi/host-tools
--with-mpc=/media/sripar01/2tb_work/CDE/build-arm-none-eabi/host-tools
--with-isl=/media/sripar01/2tb_work/CDE/build-arm-none-eabi/host-tools
--disable-shared --disable-nls --disable-threads --disable-tls
--enable-checking=yes --enable-languages=c,c++,fortran --with-newlib
--with-multilib-list=rmprofile --with-pkgversion=unknown
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 12.0.0 20210608 (experimental) (unknown)
[Bug target/101016] Arm: vld1q polymorphic variants failing with __ARM_undef undefined reference error during linking.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101016 SRINATH PARVATHANENI changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |sripar01 at gcc dot gnu.org Status|UNCONFIRMED |ASSIGNED Known to fail||10.3.0, 11.1.0 Last reconfirmed||2021-06-10 Ever confirmed|0 |1
[Bug target/101016] Arm: vld1q polymorphic variants failing with undefined reference to `__ARM_undef` error.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101016 SRINATH PARVATHANENI changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED|RESOLVED --- Comment #4 from SRINATH PARVATHANENI --- Fixed
[Bug target/100856] Arm: Multilib mapping is missing for CDE arguments.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100856 SRINATH PARVATHANENI changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|--- |FIXED --- Comment #4 from SRINATH PARVATHANENI --- Fixed.
[Bug target/99939] CMSE: -march=armv8.1-m.main+mve does not support CMSE correctly.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99939 SRINATH PARVATHANENI changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|--- |FIXED --- Comment #4 from SRINATH PARVATHANENI --- Fixed
