[Bug target/90363] or1k: Extra mask insn after load from memory
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90363 --- Comment #3 from Stafford Horne --- Author: shorne Date: Sun Jul 21 20:58:54 2019 New Revision: 273647 URL: https://gcc.gnu.org/viewcvs?rev=273647&root=gcc&view=rev Log: or1k: Fix code quality for volatile memory loads Volatile memory does not match the memory_operand predicate. This causes extra extend/mask instructions instructions when reading from volatile memory. On OpenRISC loading volatile memory can be treated the same as regular memory loads which supports combined sign/zero extends. Fixing this eliminates the need for extra extend/mask instructions. This also adds a test provided by Richard Selvaggi which uncovered the issue while we were looking into another issue. gcc/ChangeLog: PR target/90363 * config/or1k/or1k.md (zero_extendsi2): Update predicate. (extendsi2): Update predicate. * gcc/config/or1k/predicates.md (volatile_mem_operand): New. (reg_or_mem_operand): New. gcc/testsuite/ChangeLog: PR target/90363 * gcc.target/or1k/swap-1.c: New test. * gcc.target/or1k/swap-2.c: New test. Modified: trunk/gcc/ChangeLog trunk/gcc/config/or1k/or1k.md trunk/gcc/config/or1k/predicates.md trunk/gcc/testsuite/ChangeLog
[Bug target/90362] or1k: Soft divide does not work correctly
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90362 --- Comment #3 from Stafford Horne --- Author: shorne Date: Sun Jul 21 20:59:50 2019 New Revision: 273648 URL: https://gcc.gnu.org/viewcvs?rev=273648&root=gcc&view=rev Log: or1k: Fix issues with msoft-div Fixes bad assembly logic with software divide as reported by Richard Selvaggi. Also, add a basic test to verify the soft math works when enabled. gcc/testsuite/ChangeLog: PR target/90362 * gcc.target/or1k/div-mul-3.c: New test. libgcc/ChangeLog: PR target/90362 * config/or1k/lib1funcs.S (__udivsi3): Change l.sfeqi to l.sfeq and l.sfltsi to l.sflts equivalents as the immediate instructions are not available on every processor. Change a l.bnf to l.bf to fix logic issue. Modified: trunk/gcc/testsuite/ChangeLog trunk/libgcc/ChangeLog trunk/libgcc/config/or1k/lib1funcs.S
[Bug target/90363] or1k: Extra mask insn after load from memory
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90363 Stafford Horne changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|--- |FIXED --- Comment #4 from Stafford Horne --- The fix for this has been committed to SVN.
[Bug target/90362] or1k: Soft divide does not work correctly
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90362 Stafford Horne changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|--- |FIXED --- Comment #4 from Stafford Horne --- The fix for this has been committed to SVN.
[Bug target/90362] New: or1k: Soft divide does not work correctly
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90362
Bug ID: 90362
Summary: or1k: Soft divide does not work correctly
Product: gcc
Version: 9.1.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: shorne at gcc dot gnu.org
Target Milestone: ---
Example:
#include
int main() {
printf ("400/3 = %d", 400/3);
}
When running:
$ or1k-elf-gcc -msoft-div simplediv.c
$ or1k-elf-run ./a.out
400/3 = 3�
Expected
400/3 = 133
[Bug target/90362] or1k: Soft divide does not work correctly
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90362 Stafford Horne changed: What|Removed |Added Target||or1k Status|UNCONFIRMED |NEW URL||https://github.com/stffrdhr ||n/gcc/issues/6 Last reconfirmed||2019-05-06 CC||shorne at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Stafford Horne --- Proposed patch: diff --git a/libgcc/config/or1k/lib1funcs.S b/libgcc/config/or1k/lib1funcs.S index d2103923486..6d058977229 100644 --- a/libgcc/config/or1k/lib1funcs.S +++ b/libgcc/config/or1k/lib1funcs.S @@ -68,18 +68,18 @@ __udivmodsi3_internal: is not clobbered by this routine, and use that as to save a return address without creating a stack frame. */ - l.sfeqi r4, 0 /* division by zero; return 0. */ + l.sfeq r4, r0 /* division by zero; return 0. */ l.ori r11, r0, 0 /* initial quotient */ l.bf9f l.ori r12, r3, 0 /* initial remainder */ /* Given X/Y, shift Y left until Y >= X. */ l.ori r6, r0, 1 /* mask = 1 */ -1: l.sfltsir4, 0 /* y has msb set */ +1: l.sflts r4, r0 /* y has msb set */ l.bf2f l.sfltur4, r12 /* y < x */ l.add r4, r4, r4 /* y <<= 1 */ - l.bnf 1b + l.bf1b
[Bug target/90362] or1k: Soft divide does not work correctly
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90362 Stafford Horne changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassigned at gcc dot gnu.org |shorne at gcc dot gnu.org
[Bug target/90363] New: or1k: Extra mask insn after load from memory
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90363
Bug ID: 90363
Summary: or1k: Extra mask insn after load from memory
Product: gcc
Version: 9.1.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: shorne at gcc dot gnu.org
Target Milestone: ---
When compiling the below code we see and extra "l.andi r17, r17, 0xff" mask
instruction when reading a byte from memory. This is not needed as loads
already zero extend.
Example:
#include
volatile uint8_t g_doswap = 1;
uint64_t swap_1(uint64_t u64)
{
uint32_t u64_lo, u64_hi, u64_tmp;
u64_lo = u64 & 0x;
u64_hi = u64 >> 32;
if (g_doswap) {
u64_tmp = u64_lo;
u64_lo = u64_hi;
u64_hi = u64_tmp;
}
u64 = u64_lo;
u64 += ((uint64_t) u64_hi << 32);
return u64;
} // swap_1
Output: or1k-elf-gcc -O2 -S doswap_1.c
.file "doswap_1.c"
.section.text
.align 4
.global swap_1
.type swap_1, @function
swap_1:
l.movhi r17, ha(.LANCHOR0)
l.lbz r17, lo(.LANCHOR0)(r17)
l.andi r17, r17, 0xff// < Where is this
coming from
l.movhi r19, hi(0)
l.sfeq r17, r19
l.orr12, r4, r4
l.bf.L6
l.orr11, r3, r3
l.bf.L6
l.orr11, r4, r4
l.orr12, r3, r3
.L6:
l.jrr9
l.nop
.size swap_1, .-swap_1
.global g_doswap
.section.data
.set.LANCHOR0,. + 0
.type g_doswap, @object
.size g_doswap, 1
g_doswap:
.byte 1
.ident "GCC: (GNU) 9.0.1 20190326 (experimental)"
[Bug target/90363] or1k: Extra mask insn after load from memory
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90363 Stafford Horne changed: What|Removed |Added Target||or1k Status|UNCONFIRMED |ASSIGNED URL||https://github.com/stffrdhr ||n/gcc/issues/4 Last reconfirmed||2019-05-06 Assignee|unassigned at gcc dot gnu.org |shorne at gcc dot gnu.org Ever confirmed|0 |1
[Bug target/90362] or1k: Soft divide does not work correctly
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90362 --- Comment #2 from Stafford Horne --- Originally reported by Richard Selvaggi.
[Bug target/90363] or1k: Extra mask insn after load from memory
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90363
--- Comment #2 from Stafford Horne ---
(In reply to Segher Boessenkool from comment #1)
> Trying 13 -> 14:
>13: r51:QI=[r50:SI+low(`*.LANCHOR0')]
> REG_DEAD r50:SI
>14: r43:SI=zero_extend(r51:QI)
> REG_DEAD r51:QI
> Failed to match this instruction:
> (set (reg:SI 43 [ g_doswap.0_2+-3 ])
> (zero_extend:SI (mem/v/c:QI (lo_sum:SI (reg/f:SI 50)
> (symbol_ref:SI ("*.LANCHOR0") [flags 0x182])) [0 g_doswap+0
> S1 A8])))
>
> The mem arg in that does not match nonimmediate_operand, since it is const.
> You want something like reg_or_mem_operand.
Yes, thanks sorry, I did investigation a while ago. I forgot to add when I was
creating this bug.
The issue is that the volatile does not match non immediate_operand.
The following patch fixes that:
iff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md
index 2dad51cd46b..757d899c442 100644
--- a/gcc/config/or1k/or1k.md
+++ b/gcc/config/or1k/or1k.md
@@ -328,11 +328,11 @@
;; Sign Extending
;; -
-;; Zero extension can always be done with AND and an extending load.
+;; Zero extension can always be done with AND or an extending load.
(define_insn "zero_extendsi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
- (zero_extend:SI (match_operand:I12 1 "nonimmediate_operand" "r,m")))]
+ (zero_extend:SI (match_operand:I12 1 "reg_or_mem_operand" "r,m")))]
""
"@
l.andi\t%0, %1,
@@ -344,7 +344,7 @@
(define_insn "extendsi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
- (sign_extend:SI (match_operand:I12 1 "nonimmediate_operand" "r,m")))]
+ (sign_extend:SI (match_operand:I12 1 "reg_or_mem_operand" "r,m")))]
"TARGET_SEXT"
"@
l.exts\t%0, %1
diff --git a/gcc/config/or1k/predicates.md b/gcc/config/or1k/predicates.md
index 879236bca49..b895f1b4228 100644
--- a/gcc/config/or1k/predicates.md
+++ b/gcc/config/or1k/predicates.md
@@ -82,3 +82,21 @@
(define_predicate "equality_comparison_operator"
(match_code "ne,eq"))
+
+;; Borrowed from rs6000
+; Return true if the operand is in volatile memory. Note that during the
+;; RTL generation phase, memory_operand does not return TRUE for volatile
+;; memory references. So this function allows us to recognize volatile
+;; references where it's safe.
+(define_predicate "volatile_mem_operand"
+ (and (match_code "mem")
+ (match_test "MEM_VOLATILE_P (op)")
+ (if_then_else (match_test "reload_completed")
+(match_operand 0 "memory_operand")
+(match_test "memory_address_p (mode, XEXP (op, 0))"
+
+;; Return true if the operand is a register or memory; including volatile
+;; memory.
+(define_predicate "reg_or_mem_operand"
+ (ior (match_operand 0 "nonimmediate_operand")
+ (match_operand 0 "volatile_mem_operand")))
[Bug target/99783] New: relocation truncated to fit: R_OR1K_GOT16 on OpenRISC, building libgeos
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99783 Bug ID: 99783 Summary: relocation truncated to fit: R_OR1K_GOT16 on OpenRISC, building libgeos Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: shorne at gcc dot gnu.org Target Milestone: --- I confirm, when building with libgeos as described by Giulio ''' # git clone git://git.busybox.net/buildroot # wget https://git.busybox.net/buildroot-test/tree/utils/br-reproduce-build - modify BASE_GIT=... with your buildroot path in br-reproduce-build then: # chmod a+x br-reproduce-build # ./br-reproduce-build 3eb9f9d0f6d8274b2d19753c006bd83f7d536e3c ''' - This issue is an overflow in the 16-bit immediate in the l.lwz load instruction generated for R_OR1K_GOT16 by GCC. So the fix has to start with GCC. I will need to have a bit further look on how to handle this. Some of the errors: linux-uclibc/9.3.0/crtbeginS.o: in function `__do_global_dtors_aux': crtstuff.c:(.text+0x118): relocation truncated to fit: R_OR1K_GOT16 against symbol `__cxa_finalize' defined in .text section in /home/shorne/work/openrisc/3eb9f9d0f6d8274b2d19753c006bd83f7d536e3c/output/host/or1k-buildroot-linux-uclibc/sysroot/lib/libc.so. 1 crtstuff.c:(.text+0x140): relocation truncated to fit: R_OR1K_GOT16 against symbol `__deregister_frame_info@@GLIBC_2.0' defined in .text section in /home/shorne/work/openrisc/3eb9f9d0f6d8274b2d19753c006bd83f7d536e3c/output/host/opt/ext-toolchain/bin/../lib /gcc/or1k-buildroot-linux-uclibc/9.3.0/../../../../or1k-buildroot-linux-uclibc/lib/libgcc_s.so /home/shorne/work/openrisc/3eb9f9d0f6d8274b2d19753c006bd83f7d536e3c/output/host/opt/ext-toolchain/bin/../lib/gcc/or1k-buildroot- linux-uclibc/9.3.0/crtbeginS.o: in function `frame_dummy': crtstuff.c:(.text+0x1a0): relocation truncated to fit: R_OR1K_GOT16 against symbol `__register_frame_info@@GLIBC_2.0' defined in .text section in /home/shorne/work/openrisc/3eb9f9d0f6d8274b2d19753c006bd83f7d536e3c/output/host/opt/ext-toolchain/bin/../lib/g cc/or1k-buildroot-linux-uclibc/9.3.0/../../../../or1k-buildroot-linux-uclibc/lib/libgcc_s.so CMakeFiles/geos.dir/src/algorithm/BoundaryNodeRule.cpp.o: in function `geos::algorithm::BoundaryNodeRule::~BoundaryNodeRule()': BoundaryNodeRule.cpp:(.text._ZN4geos9algorithm16BoundaryNodeRuleD2Ev[_ZN4geos9algorithm16BoundaryNodeRuleD5Ev]+0x24): relocation truncated to fit: R_OR1K_GOT16 against symbol `vtable for geos::algorithm::BoundaryNodeRule' defined in .data.rel.ro._ZTVN4geos 9algorithm16BoundaryNodeRuleE[_ZTVN4geos9algorithm16BoundaryNodeRuleE] section in CMakeFiles/geos.dir/src/algorithm/BoundaryNode Rule.cpp.o CMakeFiles/geos.dir/src/algorithm/CGAlgorithmsDD.cpp.o: in function `geos::algorithm::CGAlgorithmsDD::orientationIndex(double, d ouble, double, double, double, double)': CGAlgorithmsDD.cpp:(.text+0x308): relocation truncated to fit: R_OR1K_GOT16 against symbol `geos::util::IllegalArgumentException ::~IllegalArgumentException()' defined in .text._ZN4geos4util24IllegalArgumentExceptionD2Ev[_ZN4geos4util24IllegalArgumentExcept ionD5Ev] section in CMakeFiles/geos.dir/src/algorithm/CGAlgorithmsDD.cpp.o CGAlgorithmsDD.cpp:(.text+0x310): relocation truncated to fit: R_OR1K_GOT16 against symbol `typeinfo for geos::util::IllegalArgu mentException' defined in .data.rel.ro._ZTIN4geos4util24IllegalArgumentExceptionE[_ZTIN4geos4util24IllegalArgumentExceptionE] se ction in CMakeFiles/geos.dir/src/algorithm/CGAlgorithmsDD.cpp.o CMakeFiles/geos.dir/src/algorithm/CGAlgorithmsDD.cpp.o: in function `geos::algorithm::CGAlgorithmsDD::signOfDet2x2(double, doubl e, double, double)': CGAlgorithmsDD.cpp:(.text+0xa34): relocation truncated to fit: R_OR1K_GOT16 against symbol `geos::util::IllegalArgumentException ::~IllegalArgumentException()' defined in .text._ZN4geos4util24IllegalArgumentExceptionD2Ev[_ZN4geos4util24IllegalArgumentExcept ionD5Ev] section in CMakeFiles/geos.dir/src/algorithm/CGAlgorithmsDD.cpp.o CGAlgorithmsDD.cpp:(.text+0xa3c): relocation truncated to fit: R_OR1K_GOT16 against symbol `typeinfo for geos::util::IllegalArgu mentException' defined in .data.rel.ro._ZTIN4geos4util24IllegalArgumentExceptionE[_ZTIN4geos4util24IllegalArgumentExceptionE] se ction in CMakeFiles/geos.dir/src/algorithm/CGAlgorithmsDD.cpp.o CMakeFiles/geos.dir/src/algorithm/CGAlgorithmsDD.cpp.o: in function `geos::util::GEOSException::GEOSException(std::__cxx11::basi c_string, std::allocator > const&, std::__cxx11::basic_string, s td::allocator > const&)': CGAlgorithmsDD.cpp:(.text._ZN4geos4util13GEOSExceptionC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES9_[_ZN4geos4util 13GEOSExceptionC5ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES9_]
[Bug target/99783] relocation truncated to fit: R_OR1K_GOT16 on OpenRISC, building libgeos
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99783 Stafford Horne changed: What|Removed |Added Target||or1k-*-* Assignee|unassigned at gcc dot gnu.org |shorne at gcc dot gnu.org Status|UNCONFIRMED |ASSIGNED CC||giulio.benetti@micronovasrl ||.com, shorne at gcc dot gnu.org Ever confirmed|0 |1 Last reconfirmed||2021-03-26 --- Comment #1 from Stafford Horne --- Reported originally in binutils. https://sourceware.org/bugzilla/show_bug.cgi?id=21464
[Bug rtl-optimization/12754] Faulty register allocation under certain circumstances
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=12754 Stafford Horne changed: What|Removed |Added CC||shorne at gcc dot gnu.org --- Comment #5 from Stafford Horne --- There has been a complete rewrite of the or1k compiler now. Should this be closed?
[Bug rtl-optimization/12754] Faulty register allocation under certain circumstances
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=12754 Stafford Horne changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |shorne at gcc dot gnu.org Status|NEW |SUSPENDED --- Comment #6 from Stafford Horne --- Suspending as this is on the old re-written port.
[Bug rtl-optimization/12754] Faulty register allocation under certain circumstances
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=12754 Stafford Horne changed: What|Removed |Added Status|SUSPENDED |RESOLVED Resolution|--- |FIXED
[Bug rtl-optimization/12754] Faulty register allocation under certain circumstances
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=12754 Stafford Horne changed: What|Removed |Added Resolution|FIXED |WONTFIX
[Bug target/99783] relocation truncated to fit: R_OR1K_GOT16 on OpenRISC, building libgeos
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99783 Stafford Horne changed: What|Removed |Added Resolution|--- |MOVED Status|ASSIGNED|RESOLVED --- Comment #10 from Stafford Horne --- Closing this as its a binutils issue. I have opened: https://sourceware.org/bugzilla/show_bug.cgi?id=28735
[Bug target/94372] pthread doesn't define _REENTRANT in preprocessor on OpenRISC
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94372 Stafford Horne changed: What|Removed |Added Status|WAITING |ASSIGNED --- Comment #2 from Stafford Horne --- The patch looks fine, I missed it as it seems the patch was only posted in bugzilla. Usually sending a patch to gcc-patches will get more attention.
[Bug target/94372] pthread doesn't define _REENTRANT in preprocessor on OpenRISC
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94372 Stafford Horne changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|--- |FIXED --- Comment #4 from Stafford Horne --- Patch applied. Thank you
[Bug target/102584] [OpenRISC] backend generates wrong halfword constant
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102584
Stafford Horne changed:
What|Removed |Added
CC||shorne at gcc dot gnu.org
Last reconfirmed||2022-02-02
Assignee|unassigned at gcc dot gnu.org |shorne at gcc dot
gnu.org
Status|UNCONFIRMED |ASSIGNED
Ever confirmed|0 |1
--- Comment #2 from Stafford Horne ---
I confirm this looks strange. It seems to be due to not handling some case for
HImode in or1k_expand_move, see below.
Is this causing any actual issue? As I see it the result is that the registers
will be loaded with f123 instead of f123, but if using HImode only the
lower 16-bits will be used. I confirmed with some simple tests.
void
or1k_expand_move (machine_mode mode, rtx op0, rtx op1)
{
if (MEM_P (op0))
{
if (!const0_operand (op1, mode))
op1 = force_reg (mode, op1);
}
else if (mode == QImode || mode == HImode)
{
/* ??? Maybe promote MEMs and CONST_INT to SImode,
and then squish back with gen_lowpart. */
}
else
{
...
}
// NOTE at this point op0 and op1 are, checked using print_rtl()
// (reg:HI 3 r3)
// (const_int -3805 [0xf123])
emit_insn (gen_rtx_SET (op0, op1));
}
[Bug rtl-optimization/104153] [12 Regression] ICE due to recent ifcvt changes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104153 Stafford Horne changed: What|Removed |Added CC||shorne at gcc dot gnu.org --- Comment #8 from Stafford Horne --- I am seeing a similar ICE when building glibc. /home/shorne/work/gnu-toolchain/gcc/libstdc++-v3/src/c++98/localename.cc: In constructor 'std::locale::_Impl::_Impl(const char*, std::size_t)': /home/shorne/work/gnu-toolchain/gcc/libstdc++-v3/src/c++98/localename.cc:315:3: internal compiler error: in df_refs_verify, at df-scan.cc:4003 315 | } | ^ 0x6ad94e df_refs_verify /home/shorne/work/gnu-toolchain/gcc/gcc/df-scan.cc:4003 0xc2d286 df_insn_refs_verify /home/shorne/work/gnu-toolchain/gcc/gcc/df-scan.cc:4086 0xc2eefb df_bb_verify /home/shorne/work/gnu-toolchain/gcc/gcc/df-scan.cc:4119 0xc2f28f df_scan_verify() /home/shorne/work/gnu-toolchain/gcc/gcc/df-scan.cc:4240 0xc1bc14 df_verify() /home/shorne/work/gnu-toolchain/gcc/gcc/df-core.cc:1818 0xc1bc14 df_analyze_1 /home/shorne/work/gnu-toolchain/gcc/gcc/df-core.cc:1214 0x177e1e1 execute_rtl_cprop /home/shorne/work/gnu-toolchain/gcc/gcc/cprop.cc:1925 0x177e1e1 execute /home/shorne/work/gnu-toolchain/gcc/gcc/cprop.cc:1964 Please submit a full bug report, with preprocessed source (by using -freport-bug). Please include the complete backtrace with any bug report. See <https://gcc.gnu.org/bugs/> for instructions. I confirm the patch also fixes things for me.
[Bug rtl-optimization/104153] [12 Regression] ICE due to recent ifcvt changes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104153 --- Comment #9 from Stafford Horne --- Note, I said glibc but of course error I listed was when compiling gcc during glibc toolchain building.
[Bug target/120587] New: [OpenRISC] ICE in ce1 due to emit_move_multi_word assert failure
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120587 Bug ID: 120587 Summary: [OpenRISC] ICE in ce1 due to emit_move_multi_word assert failure Product: gcc Version: 16.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: shorne at gcc dot gnu.org Target Milestone: --- Created attachment 61599 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=61599&action=edit libgcc file used to reproduce We are getting the following ERROR when building the current master of GCC. Version git@: 02a6f9a0df1 Stafford Horne or1k: Fix struct return test Fails on __muldi3 in libgcc. See attached __muldi3.i Run with: cc1 -O2 __muldi3.i Error: during RTL pass: ce1 dump file: libgcc2.c.286r.ce1 /home/shorne/work/gnu-toolchain/gcc/libgcc/libgcc2.c: In function '__muldi3': /home/shorne/work/gnu-toolchain/gcc/libgcc/libgcc2.c:538:1: internal compiler error: in emit_move_multi_word, at expr.cc:4492 538 | } | ^ 0x1b094df internal_error(char const*, ...) /home/shorne/work/gnu-toolchain/gcc/gcc/diagnostic-global-context.cc:517 0x6459c1 fancy_abort(char const*, int, char const*) /home/shorne/work/gnu-toolchain/gcc/gcc/diagnostic.cc:1815 0x473a2e emit_move_multi_word /home/shorne/work/gnu-toolchain/gcc/gcc/expr.cc:4492 0x93fd7d emit_move_insn(rtx_def*, rtx_def*) /home/shorne/work/gnu-toolchain/gcc/gcc/expr.cc:4746 0x9175f1 copy_to_reg(rtx_def*) /home/shorne/work/gnu-toolchain/gcc/gcc/explow.cc:630 0xd18977 gen_lowpart_general(machine_mode, rtx_def*) /home/shorne/work/gnu-toolchain/gcc/gcc/rtlhooks.cc:56 0x9414c7 convert_mode_scalar /home/shorne/work/gnu-toolchain/gcc/gcc/expr.cc:818 0x9421a1 convert_modes(machine_mode, machine_mode, rtx_def*, int) /home/shorne/work/gnu-toolchain/gcc/gcc/expr.cc:961 0xc0afa0 prepare_operand(insn_code, rtx_def*, int, machine_mode, machine_mode, int) /home/shorne/work/gnu-toolchain/gcc/gcc/optabs.cc:4637 0xc0b33a prepare_cmp_insn /home/shorne/work/gnu-toolchain/gcc/gcc/optabs.cc:4538 0xc0f0dd emit_conditional_move(rtx_def*, rtx_comparison, rtx_def*, rtx_def*, machine_mode, int) /home/shorne/work/gnu-toolchain/gcc/gcc/optabs.cc:5098 0x192cc7b noce_emit_cmove /home/shorne/work/gnu-toolchain/gcc/gcc/ifcvt.cc:1777 0x193365b try_emit_cmove_seq /home/shorne/work/gnu-toolchain/gcc/gcc/ifcvt.cc:3410 0x193365b noce_convert_multiple_sets_1 /home/shorne/work/gnu-toolchain/gcc/gcc/ifcvt.cc:3705 0x1933c71 noce_convert_multiple_sets /home/shorne/work/gnu-toolchain/gcc/gcc/ifcvt.cc:3496 0x1938687 noce_process_if_block /home/shorne/work/gnu-toolchain/gcc/gcc/ifcvt.cc:4045 0x1938687 noce_find_if_block /home/shorne/work/gnu-toolchain/gcc/gcc/ifcvt.cc:4726 0x1938687 find_if_header /home/shorne/work/gnu-toolchain/gcc/gcc/ifcvt.cc:4931 0x1938687 if_convert /home/shorne/work/gnu-toolchain/gcc/gcc/ifcvt.cc:6078 0x1938d01 rest_of_handle_if_conversion /home/shorne/work/gnu-toolchain/gcc/gcc/ifcvt.cc:6143
[Bug target/120587] [OpenRISC] ICE in ce1 due to emit_move_multi_word assert failure
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120587
Stafford Horne changed:
What|Removed |Added
Target||or1k
Last reconfirmed||2025-06-08
Status|UNCONFIRMED |ASSIGNED
Ever confirmed|0 |1
--- Comment #1 from Stafford Horne ---
Discussed on the mailing list.
https://gcc.gnu.org/pipermail/gcc-patches/2025-June/685962.html
In summary validate_subregs was modified in the patch:
2025-05-18 eb2ea476db2 Dimitar Dimitrov emit-rtl: Allow extra checks for
paradoxical subregs [PR119966]
After this the oepnrisc port no longer generates subregs when converting
special register SR_F from BI to SI.
A patch in the works is:
--- a/gcc/config/or1k/or1k.cc
+++ b/gcc/config/or1k/or1k.cc
@@ -1408,8 +1408,9 @@ static bool
or1k_can_change_mode_class (machine_mode from, machine_mode to,
reg_class_t rclass)
{
+ /* Allow cnoverting special flags to SI mode subregs. */
if (rclass == FLAG_REGS)
-return from == to;
+return from == to || (from == BImode && to == SImode);
return true;
}
