Re: Register Allocation Bug?

[Segher Boessenkool]

#define ESP 
(rel,value,addr) \
asm volatile ("mov (%%esp, %2, 4), %0\n 
\t"  \
  "lea (%%esp, %2, 4), %1\n 
\t"  \
  : "=r" (value),  
"=r" (addr)   \
  :  
"r" (rel)); \


It didn't work as expected so I looked at the assembler code generated
for the above:

 1:   b8 00 00 00 00  mov$0x0,%eax
 2:   8b 04 84mov(%esp,%eax,4),%eax
 3:   8d 14 84lea(%esp,%eax,4),%edx
 4:   89 45 f8mov%eax,0xfff8(%ebp)
 5:   89 55 fcmov%edx,0xfffc(%ebp)


As it turns out, %eax is being used for both input and output in line
2, clobbering %eax, so of course line 3 does not give the expected
result... Is this a compiler error?


It's not a compiler bug: you need to use an "early clobber", namely
"=&r"(value) .  See the Fine Manual.


Segher

Re: [Bug target/90513] asm thunks do not work on PowerPC64/VxWorks (kernel mode)

[Segher Boessenkool]

On Tue, Jun 11, 2019 at 10:25:58PM +0530, Umesh Kalappa wrote:
> We would like to know comments on the  below  proposed change ?

As I said in the PR, this is not a proper patch.  Also, like Eric says
there, it does not do the right thing for many configurations.

Fix the loader, instead?


Segher