Supporting subreg style patterns

[shmuel gutl]

My hardware directly supports instructions of the form

subreg:SI(reg:VEC v1,3) = SI:a1

That is, a particular field of a vector register can be used as the 
target of a move from a general register. Reginfo refuses to recognize 
that any registers can satisfy this subreg expression and therefore 
ira/reload/lra uses memory to make the transfer. If I allow vector 
registers to support SImode, I can get subreg 0 working, but no others 
since the various fields do not have a register equivalent. Are there 
any hooks or data structures to support this feature? Are there any 
examples in supported architectures?


Thanks

Shmeel

assigning hard regs to pseudo regs

[shmuel gutl]

For certain instructions, I am trying to do my own register assignments 
before IRA runs. I call df_analyze to find all register references and 
after my manipulations I call df_scan_blocks to reparse the insns.


A typical replacement that I want to handle is a register reference of 
the form

(subreg:REGQ (reg/v: TI 195 [x2] 4)

If I replace the entire subreg expression by genRTX the compilation 
works but I lose the reference to X2 (plus I have to update every 
reference to reg expressions referencing reg 195).
If I call SET_REGNO on the inner expression, it automatically updates 
all of the comparable expressions, and register 195 only appears as 
original reg in any insn. The insn dumps look correct to me. But reload 
will complain that register 195 didn't get a hard register assignment.

What do I need to do to make reload happy?

Thanks shmeel