How to activate instruction scheduling in GCC?
Hi ALL I'm a pure beginner in GCC, and currently working on a project to implement instruction scheduling for a new DSP processor. This processor doesn't have pipeline interlock, so the compiler HAVE to schedule the instruction without relying on hardware help anymore The problem is, I'm a very beginner in GCC. I think the scheduling in GCC is activated by INSN_SCHEDULING variable (in automatically generated file: insn-attr.h), but I don't even know how to activate this variable. Any help would be appreciated -- View this message in context: http://www.nabble.com/How-to-activate-instruction-scheduling-in-GCC--tf4167590.html#a11857079 Sent from the gcc - Dev mailing list archive at Nabble.com.
Re: How to activate instruction scheduling in GCC?
Thanks .. your reply is really helpful ... Btw, I checked the MIPS backend at MIPS.c, but I can't find the definition of some functions such as: get_attr_hazard(), gen_hazard_nop (), etc. Anyone know where those functions defined? Ian Lance Taylor-3 wrote: > > petruk_gile <[EMAIL PROTECTED]> writes: > >> I'm a pure beginner in GCC, and currently working on a project to >> implement >> instruction scheduling for a new DSP processor. This processor doesn't >> have >> pipeline interlock, so the compiler HAVE to schedule the instruction >> without >> relying on hardware help anymore >> >> The problem is, I'm a very beginner in GCC. I think the scheduling in GCC >> is >> activated by INSN_SCHEDULING variable (in automatically generated file: >> insn-attr.h), but I don't even know how to activate this variable. > > INSN_SCHEDULING will automatically be turned on if you have any > define_insn_reservation clauses in your CPU.md file. See the > "Processor pipeline description" documentation in the gcc internals > manual. > > That said, the gcc scheduler unfortunately does not work very well for > processors which do not have hardware interlocks. The scheduler will > lay out the instructions more or less optimally. But the scheduler > has no ability to insert nops when they are required to satisfy > interlock constraints. > > I know of two workable approachs. You can either insert the required > nops in the TARGET_MACHINE_DEPENDENT_REORG pass or in the > TARGET_ASM_FUNCTION_PROLOGUE hook. I personally prefer the latter > approach, as it takes effect after all other instruction rearrangement > is complete, but there are existing backends which use the former. > > For an example of inserting nops in TARGET_MACHINE_DEPENDENT_REORG, > see the MIPS backend, specifically mips_avoid_hazards. For an example > of inserting nops in TARGET_ASM_FUNCTION_PROLOGUE, see the FRV > backend, specifically frv_pack_insns. > > Ian > > -- View this message in context: http://www.nabble.com/How-to-activate-instruction-scheduling-in-GCC--tf4167590.html#a11940780 Sent from the gcc - Dev mailing list archive at Nabble.com.
Re: How to activate instruction scheduling in GCC?
Sorry, no need already to bother with the last question, already knew that it is (again) generated automatically from the Machine description file petruk_gile wrote: > > Thanks .. your reply is really helpful ... > > Btw, I checked the MIPS backend at MIPS.c, but I can't find the definition > of some functions such as: > > get_attr_hazard(), gen_hazard_nop (), etc. > > Anyone know where those functions defined? > > > > > Ian Lance Taylor-3 wrote: >> >> petruk_gile <[EMAIL PROTECTED]> writes: >> >>> I'm a pure beginner in GCC, and currently working on a project to >>> implement >>> instruction scheduling for a new DSP processor. This processor doesn't >>> have >>> pipeline interlock, so the compiler HAVE to schedule the instruction >>> without >>> relying on hardware help anymore >>> >>> The problem is, I'm a very beginner in GCC. I think the scheduling in >>> GCC is >>> activated by INSN_SCHEDULING variable (in automatically generated file: >>> insn-attr.h), but I don't even know how to activate this variable. >> >> INSN_SCHEDULING will automatically be turned on if you have any >> define_insn_reservation clauses in your CPU.md file. See the >> "Processor pipeline description" documentation in the gcc internals >> manual. >> >> That said, the gcc scheduler unfortunately does not work very well for >> processors which do not have hardware interlocks. The scheduler will >> lay out the instructions more or less optimally. But the scheduler >> has no ability to insert nops when they are required to satisfy >> interlock constraints. >> >> I know of two workable approachs. You can either insert the required >> nops in the TARGET_MACHINE_DEPENDENT_REORG pass or in the >> TARGET_ASM_FUNCTION_PROLOGUE hook. I personally prefer the latter >> approach, as it takes effect after all other instruction rearrangement >> is complete, but there are existing backends which use the former. >> >> For an example of inserting nops in TARGET_MACHINE_DEPENDENT_REORG, >> see the MIPS backend, specifically mips_avoid_hazards. For an example >> of inserting nops in TARGET_ASM_FUNCTION_PROLOGUE, see the FRV >> backend, specifically frv_pack_insns. >> >> Ian >> >> > > -- View this message in context: http://www.nabble.com/How-to-activate-instruction-scheduling-in-GCC--tf4167590.html#a11941887 Sent from the gcc - Dev mailing list archive at Nabble.com.
How to add target specific dependency?
Hi all .. I'm currently porting GCC into a new processor, and I have a problem in instruction scheduling ... The case is like this: In the machine description (*.md) file, sometimes I emit a single RTL instruction into multiple ASM instruction. The problem is, in some case I need to emit an operand that actually doesn't exist in its RTL representation. For example : "movpqi_insn x,y" instruction will be translated as ==> "sar x, *ar15" and "lar y, *ar15" Where "sar" means "Store register" and "lar" means "load register" ... Since GCC performs instruction scheduling in RTL form, it doesn't know that instruction "movpqi_insn" actually reads AR15 Hence, sometimes GCC moves an instruction that actually SHOULD NOT be moved, due to data dependence in AR15, and it causes incorrect scheduling (This is my analysis, please tell me if you guys think I'm wrong)... So, I need to: (1) whether disable the scheduling for that particular dependency, or (2) Inform GCC that "movpqi_insn" has an additional dependency in AR15 The problem is, I still don't know how can i do those 2 things ... So if any of you have any advice, I'd be really grateful :D Thx .. Any info will be appreciated ... -- View this message in context: http://www.nabble.com/How-to-add-target-specific-dependency--tf4316367.html#a12290297 Sent from the gcc - Dev mailing list archive at Nabble.com.
