Re: Transitioning to a new Xtensa Port Maintainer

2020-05-28 Thread Max Filippov via Gcc
Hi Alan,

On Thu, May 28, 2020 at 7:53 PM Alan Modra via Gcc  wrote:
>
> On Thu, May 28, 2020 at 10:12:04AM -0700, augustine.sterling--- via Gcc wrote:
> > After a long run as the Xtensa port maintainer, it is time for me to move
> > on.
> >
> > I nominate Max Filippov [cc'd] as the new maintainer. He has contributed
> > numerous patches over the years which have required minimal comments from
> > me.
>
> Sign him up by adding his name in binutils/MAINTAINERS.
>
> > If there is anything I need to do to facilitate this, let me know. I'm
> > happy to still review patches when needed.
>
> That sounds like you're not abandoning binutils entirely, so you could
> simply leave your name in binutils/MAINTAINERS where it is but put Max
> on the line before your entry.

I've committed this change to binutils/MAINTAINERS.

-- 
Thanks.
-- Max


Re: Max Filippov appointed Xtensa maintainer

2020-06-06 Thread Max Filippov via Gcc
On Fri, Jun 5, 2020 at 5:50 PM David Edelsohn  wrote:
> I am pleased to announce that the GCC Steering Committee has
> appointed Max Filippov as Xtensa maintainer.

Thank you for your trust.

> Please join me in congratulating Max on his new role.
> Max, please update your listing in the MAINTAINERS file.

Updated as follows:

2020-06-06  Max Filippov  

* MAINTAINERS: Add myself as xtensa port maintainer.
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 5528aad5e232..d1343d33f1ab 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -118,6 +118,7 @@ visium portEric Botcazou

 x86-64 portJan Hubicka
 xstormy16 portNick Clifton
 xtensa portSterling Augustine
+xtensa portMax Filippov

 OS Port Maintainers(OS alphabetical order)

@@ -383,7 +384,6 @@ Chris Fairles
 Alessandro Fanfarillo
 Changpeng Fang
 Li Feng
-Max Filippov
 Thomas Fitzsimmons
 Alexander Fomin
 Brian Ford
-- 
Thanks.
-- Max


Re: out-of-bounds heap access in IRA

2022-10-31 Thread Max Filippov via Gcc
On Mon, Oct 31, 2022 at 1:23 PM Max Filippov  wrote:
> I've been playing with a cross-compiler built with ASAN for
> target=xtensa-linux-uclibc and I was consistently getting a
> report for out-of-bound heap access inside IRA.

I'll file a bug report.

-- 
Thanks.
-- Max


unneeded spills of SF values on xtensa with FPU

2024-03-25 Thread Max Filippov via Gcc
Hi Suwa-san,

I've noticed that in xtensa configurations with hardware FPU
function arguments of type float are spilled on the stack although
there's no need for that. E.g. the following function:

int f(float a, float b)
{
return a < b;
}

translates to the following with -O2:

f:
   entry   sp, 48
   wfr f0, a2
   wfr f1, a3
   s32i.n  a2, sp, 0
   olt.s   b0, f0, f1
   movi.n  a8, 0
   movi.n  a2, 1
   s32i.n  a3, sp, 4
   movfa2, a8, b0
   retw.n

The relevant RTL looks like this at the end of IRA:

(insn 18 4 19 2 (set (reg:SF 51)
   (reg:SF 2 a2 [ a ])) "test2.c":2:1 61 {movsf_internal}
(expr_list:REG_DEAD (reg:SF 2 a2 [ a ])
   (nil)))
(insn 19 18 7 2 (set (reg:SF 52)
   (reg:SF 3 a3 [ b ])) "test2.c":2:1 61 {movsf_internal}
(expr_list:REG_DEAD (reg:SF 3 a3 [ b ])
   (nil)))
(insn 7 19 21 2 (set (reg:CC 18 b0)
   (lt:CC (reg:SF 51)
   (reg:SF 52))) "test2.c":3:11 100 {slt_sf}
(expr_list:REG_DEAD (reg:SF 52)
   (expr_list:REG_DEAD (reg:SF 51)
   (nil

and it is transformed to the following by the end of LRA:

(insn 18 4 19 2 (set (mem/c:SF (reg/f:SI 1 sp) [1 %sfp+0 S4 A32])
   (reg:SF 2 a2 [ a ])) "test2.c":2:1 61 {movsf_internal}
(nil))
(insn 19 18 24 2 (set (mem/c:SF (plus:SI (reg/f:SI 1 sp)
   (const_int 4 [0x4])) [1 %sfp+4 S4 A32])
   (reg:SF 3 a3 [ b ])) "test2.c":2:1 61 {movsf_internal}
(nil))
(insn 24 19 25 2 (set (reg:SF 19 f0 [51])
   (mem/c:SF (reg/f:SI 1 sp) [1 %sfp+0 S4 A32])) "test2.c":3:11 61
{movsf_internal}
(nil))
(insn 25 24 7 2 (set (reg:SF 20 f1 [52])
   (mem/c:SF (plus:SI (reg/f:SI 1 sp)
   (const_int 4 [0x4])) [1 %sfp+4 S4 A32])) "test2.c":3:11
61 {movsf_internal}
(nil))
(insn 7 25 21 2 (set (reg:CC 18 b0)
   (lt:CC (reg:SF 19 f0 [51])
   (reg:SF 20 f1 [52]))) "test2.c":3:11 100 {slt_sf}
(nil))

LRA stops checking alternatives for insns 18 and 19 at s32i.n,
but even if I move wfr at the head of the movsf_internal list it
still loses to s32i.n.
Postreload pass replaces the lsi instructions 24 and 25 with
wfr from a2 and a3, but doesn't remove the spills.
I wonder what can be done with that?

--
Thanks.
-- Max


[RFC] Draft Xtensa FDPIC ABI

2024-05-13 Thread Max Filippov via Gcc
Hello.

This is a draft FDPIC ABI specification for the Xtensa architecture.
Please send comments. I will be implementing the final ABI version in
gcc and binutils.

 The Xtensa FDPIC ABI

April 8, 2024
  Version 1

Based on SH FDPIC ABI Version 1.0 by Joseph Myers.
Based on FR-V FDPIC ABI Version 1.0a by Kevin Buettner, Alexandre
Oliva and Richard Henderson.

Introduction


This document describes extensions to the existing Xtensa ELF ABI (as
used on GNU/Linux) required to support the implementation of shared
libraries on a system whose OS (and hardware) require that processes
share a common address space.  This document will also attempt to
explore the motivations behind and the implications of these extensions.

One of the primary goals in using shared libraries is to reduce the
memory requirements of the overall system.  Thus, if two processes use
the same library, the hope is that at least some of the memory pages
will be shared between the two processes resulting in an overall
savings.  To realize these savings, tools used to build a program and
library must identify which sections may be shared and which must not
be shared.  The shared sections, when grouped together, are commonly
referred to as the "text segment" whereas the non-shared (grouped)
sections are commonly referred to as the "data segment".  The text
segment is read-only and is usually comprised of executable code and
read-only data.  The data segment must be writable and it is this fact
which makes it non-sharable.

Systems which utilize disjoint address spaces for its processes are
free to group the text and data segments in such a way that they
may always be loaded with fixed relative positions of the text
and data segments.  I.e, for a given load object, the offset from
the start of the text segment to the start of the data segment is
constant.  This property greatly simplifies the design of the
shared library machinery.

The design of the shared library mechanism described in this document
does not (and cannot) have this property.  Due to the fact that all
processes share a common address space, the text and data segments
will be placed at arbitrary locations relative to each other and will
therefore need a mechanism whereby executable code will always be able
to find its corresponding data.  One of the CPU's registers is
typically dedicated to hold the base address of the data segment.
This register will be called the "FDPIC register" in this document.
Such a register is sometimes used in systems with disjoint address
spaces too, but this is for efficiency rather than necessity.

The fact that the locations of the text and data segments are at
non-constant offsets with respect to each other also complicates
function pointer representation.  As noted above, executable code
must be able to find its corresponding data segment.  When making an
indirect function call, it is therefore important that both the
address of the function and the base address of the data segment are
available.  This means that a function pointer needs to represented as
the address of a "function descriptor" which contains the address of
the actual code to execute as well as the corresponding data (FDPIC
register) address.


FDPIC Register
--

The FDPIC register is used as a base register for accessing the global
offset table (GOT) and function descriptors.  Since both code and data
are relocatable, executable code may not contain any instruction
sequences which directly encode a pointer's value.  Instead, pointers
to global data are indirectly referenced via the global offset table.
At load time, pointers contained in the global offset table are
relocated by the dynamic linker to point at the correct locations.

This FDPIC ABI is defined as extension of the base call0 Xtensa ABI.
Register a11 is used as the FDPIC register.  Version of the FDPIC ABI
based on windowed Xtensa ABI is not defined in this document revision.

Upon entry to a function, the caller saved register a11 is the FDPIC
register.  As described above, it contains the GOT address for that
function.  a11 obtains its value in one of the following ways:

1) By being inherited from the calling function in the case
   of a direct call to a function within the same load module.

2) By being set from a function descriptor as part of a direct
   or an indirect call.

The specifics associated with each of these cases are covered in
greater detail in "Function Calls", below.

A non-leaf function should save a11 either on the stack or in one of
the callee-saved registers if it needs to use it later.  After that
there's no requirement to preserve the original a11 value, that
register does not have any special meaning inside the function.

Note that once a function has moved a11 to one of its callee saved
registers, the function is then free to use that register as the FDPIC
register for acc