[Question, C6X] Under what situations should we disable DCE in sched2?

[Felix Yang]

Hello,

I find DCE in sched2 is disabled for C6X backend. Is this a
performance consideration? Or a GCC BUG?
And under what situations should we disable DCE in sched2?
Can anyone explain this? Many thanks.

The code snippet:

static void
c6x_reorg (void)
{
  basic_block bb;
  rtx *call_labels;
  bool do_selsched = (c6x_flag_schedule_insns2 && flag_selective_scheduling2
 && !maybe_skip_selective_scheduling ());

  

  /* Make sure the real-jump insns we create are not deleted.  When modulo-
 scheduling, situations where a reg is only stored in a loop can also
 cause dead code when doing the initial unrolling.  */
  sched_no_dce = true;
  


Cheers,
Felix

[Question, IRA] Different IRA behaviour with the same RTL input but trivially different CFG

[Felix Yang]

Hi Vladmir,

I think that IRA should give the same result with the same RTL
input. But I find that this is not always true.
I test IRA with two inputs, say X and Y. The RTL insns are the
same (ignore the UIDs). And the only difference between the two is the
CFG.
There are two blocks in X which is merged into one block in Y.
Only one edge exists between the two blocks in X.
After IRA processing, I find the move insns emitted by ira-emit.c
is different. And this brings performance issues with the target code.
What are the possible reasons for this? Since IRA is somewhat
complex, can you give me some suggestions please?
Many thanks.

Cheers,
Felix