Porting new target architecture to GCC
Hello, In a course at my university (Universität Würzburg, Germany) we have created a 32-bit RISC CPU architecture -- the HaDesXI-CPU -- (in VHDL) which we then play onto a FPGA (the Xilinx Spartan-3AN) to use. So far if we want to do anything with it, we have to write the assembly code ourselves. How much work would it be to write a HadesXI backend for GCC? (The idea is to use this as a possible bachelor thesis.) Where would be a good place to start; what are the prerequisites for undertaking a project like this other than knowing the CPU architecture inside out? Thanks for your advice, Ben Morgan
Re: Porting new target architecture to GCC
Thank you all very much for your comments and advice! It certainly has helped me to gain a better perspective on porting GCC to a new architecture. It's not directly a suggestion from my "Betreuer"; a few suggested it as a Praktikum or as a masters thesis, and I wanted to look into it and see what was possible. Ben
Re: Porting new target architecture to GCC
On 02/05/12 16:36, Ian Lance Taylor wrote: I don't know what a bachelor thesis is, so I don't know if this would be suitable. A GCC port by itself would be too simple for a masters thesis in the U.S. Yes, on second thought, the Betreuer I mentioned did not say anything about a masters thesis; I just recall seeing that someone at some university had done a port for his masters thesis (albeit with GCC 2.9).
