[stm32f4] status of the bsp
Hello I am interested in development of the stm32f4 bsp. We have small project based on the STM32F429 MCPU which we would like to run RTEMS on. >From the current code one could say there is not much. Only UART in polling, started I2C, some defines and few registers descriptions, interrupts just touched. Is anyone working on this so I would not double the work? What is current status of the work? Who can I contact for some initial information about bsps? Still a lot of reading to do... Best regards Tomasz ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [stm32f4] status of the bsp
Hi Chris Yes, I am very interested. I guess you have interrupts working there? Do you mind your code or work based on it to end up under RTEMS licence on the git repository? Thanks 2014-09-19 6:00 GMT+02:00 Chris Nott : > Hi, I was fiddling with this platform and got as far as a project > implementing a USB device. If you are interested I could send you the code. > It hasn't been touched for a while, it may or may not have bit rot. > > Sent with AquaMail for Android > http://www.aqua-mail.com > > On 18 September 2014 12:12:21 Tomasz Gregorek > wrote: > >> Hello >> >> I am interested in development of the stm32f4 bsp. >> We have small project based on the STM32F429 MCPU which we would like to >> run RTEMS on. >> >> From the current code one could say there is not much. Only UART in >> polling, started I2C, some defines and few registers descriptions, >> interrupts just touched. >> >> Is anyone working on this so I would not double the work? >> What is current status of the work? >> >> Who can I contact for some initial information about bsps? >> >> Still a lot of reading to do... >> >> Best regards >> Tomasz >> ___ >> devel mailing list >> devel@rtems.org >> http://lists.rtems.org/mailman/listinfo/devel >> > ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [stm32f4] status of the bsp
2014-09-19 18:26 GMT+02:00 Chris Nott : > Interrupts working yes. > > No I don't mind. It's a bit of a mess though, I was in the process of > doing another cleaner USB device implementation for BeagleBone Black, which > I was then going to backport to STM32F4 and eventually maybe work towards > some sort of general RTEMS USB device framework. > > Actually I got the BB black code enumerating as well, I just ran out of > time to work on it. > > I'll send the STM32 project to you soon, I will be travelling for the next > week so if I don't get a chance tonight it will probably be in a week or so. > > Regards, > Chris. > > Sent with AquaMail for Android > http://www.aqua-mail.com > > On 19 September 2014 00:43:59 Tomasz Gregorek > wrote: > >> Hi Chris >> >> Yes, I am very interested. >> I guess you have interrupts working there? >> >> Do you mind your code or work based on it to end up under RTEMS licence >> on the git repository? >> Thanks >> >> 2014-09-19 6:00 GMT+02:00 Chris Nott : >> >>> Hi, I was fiddling with this platform and got as far as a project >>> implementing a USB device. If you are interested I could send you the code. >>> It hasn't been touched for a while, it may or may not have bit rot. >>> >>> Sent with AquaMail for Android >>> http://www.aqua-mail.com >>> >>> On 18 September 2014 12:12:21 Tomasz Gregorek >>> wrote: >>> >>>> Hello >>>> >>>> I am interested in development of the stm32f4 bsp. >>>> We have small project based on the STM32F429 MCPU which we would like >>>> to run RTEMS on. >>>> >>>> From the current code one could say there is not much. Only UART in >>>> polling, started I2C, some defines and few registers descriptions, >>>> interrupts just touched. >>>> >>>> Is anyone working on this so I would not double the work? >>>> What is current status of the work? >>>> >>>> Who can I contact for some initial information about bsps? >>>> >>>> Still a lot of reading to do... >>>> >>>> Best regards >>>> Tomasz >>>> ___ >>>> devel mailing list >>>> devel@rtems.org >>>> http://lists.rtems.org/mailman/listinfo/devel >>>> >>> >> No worries, we have some work to do. We have clocks settings and UART interrupt driven implementations almost ready and will be sending those for the review in a day or two. I2C and SPI drivers are the next targets. Thanks ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [stm32f4] status of the bsp
2014-09-19 18:37 GMT+02:00 Gedare Bloom : > On Fri, Sep 19, 2014 at 12:26 PM, Chris Nott wrote: > > Interrupts working yes. > > > > No I don't mind. It's a bit of a mess though, I was in the process of > doing > > another cleaner USB device implementation for BeagleBone Black, which I > was > > then going to backport to STM32F4 and eventually maybe work towards some > > sort of general RTEMS USB device framework. > > > There is some support for USB in the BSD stack which is probably the > best place to put efforts toward improving. I don't personally know > the state of USB there. > > That's a good idea. Thanks Gedare (PS. sending with rtems-devel) > > Actually I got the BB black code enumerating as well, I just ran out of > time > > to work on it. > > > > I'll send the STM32 project to you soon, I will be travelling for the > next > > week so if I don't get a chance tonight it will probably be in a week or > so. > > > > Regards, > > Chris. > > > > Sent with AquaMail for Android > > http://www.aqua-mail.com > > > > On 19 September 2014 00:43:59 Tomasz Gregorek > > > wrote: > >> > >> Hi Chris > >> > >> Yes, I am very interested. > >> I guess you have interrupts working there? > >> > >> Do you mind your code or work based on it to end up under RTEMS licence > on > >> the git repository? > >> Thanks > >> > >> 2014-09-19 6:00 GMT+02:00 Chris Nott : > >>> > >>> Hi, I was fiddling with this platform and got as far as a project > >>> implementing a USB device. If you are interested I could send you the > code. > >>> It hasn't been touched for a while, it may or may not have bit rot. > >>> > >>> Sent with AquaMail for Android > >>> http://www.aqua-mail.com > >>> > >>> On 18 September 2014 12:12:21 Tomasz Gregorek < > tomasz.grego...@gmail.com> > >>> wrote: > >>>> > >>>> Hello > >>>> > >>>> I am interested in development of the stm32f4 bsp. > >>>> We have small project based on the STM32F429 MCPU which we would like > to > >>>> run RTEMS on. > >>>> > >>>> From the current code one could say there is not much. Only UART in > >>>> polling, started I2C, some defines and few registers descriptions, > >>>> interrupts just touched. > >>>> > >>>> Is anyone working on this so I would not double the work? > >>>> What is current status of the work? > >>>> > >>>> Who can I contact for some initial information about bsps? > >>>> > >>>> Still a lot of reading to do... > >>>> > >>>> Best regards > >>>> Tomasz > >>>> ___ > >>>> devel mailing list > >>>> devel@rtems.org > >>>> http://lists.rtems.org/mailman/listinfo/devel > >> > >> > > > > ___ > > devel mailing list > > devel@rtems.org > > http://lists.rtems.org/mailman/listinfo/devel > ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH] bsp:stm32f4XXXX system clock configuration
From: Tomasz Gregorek
Added simple math to caclulate register values for the PLL
and for the prescalers. It will try to keep 48MHz for the USB OTG FS.
Also it will slow down Flash memory for the high speeds.
---
c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h | 10 +
.../libbsp/arm/stm32f4/include/stm32f4_flash.h | 45 +
.../libbsp/arm/stm32f4/include/stm32f4_rcc.h | 94 +
c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c| 211 +
4 files changed, 360 insertions(+)
create mode 100644 c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
index 59d13ef..d26f914 100644
--- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
@@ -55,6 +55,16 @@
/** @} */
+/**
+ * @name STM32F4 FLASH
+ * @{
+ */
+
+#include
+#define STM32F4_FLASH ((volatile stm32f4_flash *) (STM32F4_BASE + 0x40023C00))
+
+/** @} */
+
#include
/**
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
new file mode 100644
index 000..ed08d76
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
@@ -0,0 +1,45 @@
+/**
+ * @file
+ * @ingroup stm32f4_flash
+ * @brief STM32F4 FLASH support.
+ */
+
+/*
+ * Copyright (c) 2012 Sebastian Huber. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ *
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_STM32F4_FLASH_H
+#define LIBBSP_ARM_STM32F4_STM32F4_FLASH_H
+
+#include
+
+/**
+ * @defgroup stm32f10xxx_flash STM32F4 FLASH Support
+ * @ingroup stm32f4_flash
+ * @brief STM32F4FXXX FLASH Support
+ * @{
+ */
+
+typedef struct {
+ uint32_t acr;
+ uint32_t keyr;
+ uint32_t optkeyr;
+ uint32_t sr;
+ uint32_t cr;
+ uint32_t optcr;
+ uint32_t optcr1;
+} stm32f4_flash;
+
+/** @} */
+
+#endif /* LIBBSP_ARM_STM32F4_STM32F4_FLASH_H */
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
index 8126340..ce85b8e 100644
--- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
@@ -56,4 +56,98 @@ typedef struct {
/** @} */
+#define RCC_CR_HSION BSP_BIT32(0)
+#define RCC_CR_HSIRDY BSP_BIT32(1)
+#define RCC_CR_HSITRIM3
+#define RCC_CR_HSICAL 8
+#define RCC_CR_HSEON BSP_BIT32(16)
+#define RCC_CR_HSERDY BSP_BIT32(17)
+#define RCC_CR_HSEBYP BSP_BIT32(18)
+#define RCC_CR_CSSON BSP_BIT32(19)
+#define RCC_CR_PLLON BSP_BIT32(24)
+#define RCC_CR_PLLRDY BSP_BIT32(25)
+#define RCC_CR_PLLI2SON BSP_BIT32(26)
+#define RCC_CR_PLLI2SRDY BSP_BIT32(27)
+
+
+#define RCC_PLLCFGR_PLLM0
+#define RCC_PLLCFGR_PLLN6
+#define RCC_PLLCFGR_PLLP16
+
+#define RCC_PLLCFGR_PLLSRC_HSE BSP_BIT32(22)
+#define RCC_PLLCFGR_PLLSRC_HSI 0
+
+#define RCC_PLLCFGR_PLLQ 24
+
+
+#define RCC_CFGR_SW 0
+#define RCC_CFGR_SW_MASK 3
+#define RCC_CFGR_SW_HSI 0
+#define RCC_CFGR_SW_HSE 1
+#define RCC_CFGR_SW_PLL 2
+
+#define RCC_CFGR_SWS 2
+#define RCC_CFGR_SWS_MASK(3 << RCC_CFGR_SWS)
+
+#define RCC_CFGR_SWS_HSI 0
+#define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS)
+#define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS)
+
+#define RCC_CFGR_HPRE4
+#define RCC_CFGR_HPRE_BY_1 0
+#define RCC_CFGR_HPRE_BY_2 ( 8 << RCC_CFGR_HPRE)
+#define RCC_CFGR_HPRE_BY_4 ( 9 << RCC_CFGR_HPRE)
+#define RCC_CFGR_HPRE_BY_8 (10 << RCC_CFGR_HPRE)
+#define RCC_CFGR_HPRE_BY_16 (11 << RCC_CFGR_HPRE)
+#define RCC_CFGR_HPRE_BY_64 (12 << RCC_CFGR_HPRE)
+#define RCC_CFGR_HPRE_BY_128 (13 << RCC_CFGR_HPRE)
+#define RCC_CFGR_HPRE_BY_256 (14 << RCC_CFGR_HPRE)
+#define RCC_CFGR_HPRE_BY_512 (15 << RCC_CFGR_HPRE)
+
+#define RCC_CFGR_PPRE110
+#define RCC_CFGR_PPRE1_BY_1 0
+#define RCC_CFGR_PPRE1_BY_2 (4 << RCC_CFGR_PPRE1)
+#define RCC_CFGR_PPRE1_BY_4 (5 << RCC_CFGR_PPRE1)
+#define RCC_CFGR_PPRE1_BY_8 (6 << RCC_CFGR_PPRE1)
+#define RCC_CFGR_PPRE1_BY_16 (7 << RCC_CFGR_PPRE1)
+
+#define RCC_CFGR_PPRE213
+#define RCC_CFGR_PPRE2_BY_1 0
+#define RCC_CFGR_PPRE2_BY_2 (4 << RCC_CFGR_PPRE2)
+#define RCC_CFGR_PPRE2_BY_4 (5 << RCC_CFGR_PPRE2)
+#define RCC_CFGR_PPRE2_BY_8 (6 << RCC_CFGR_PPRE2)
+#define RCC_CFGR_PPRE2_BY_16 (7 << RCC_CFGR_PPRE2)
+
+#define RCC_CFGR_RTCPRE 16
+#define RCC_CFGR_RTCPRE_SET(a) (a << RCC_CFGR_RTCPRE)
+
+#define RCC_CFGR_MCO1 21
+#define RCC_CFGR_MCO1_HSI 0
+#define RCC_CFGR_MC
Re: [PATCH] bsp:stm32f4XXXX system clock configuration
sorry, ignore this one.
2014-09-20 20:15 GMT+02:00 :
> From: Tomasz Gregorek
>
> Added simple math to caclulate register values for the PLL
> and for the prescalers. It will try to keep 48MHz for the USB OTG FS.
> Also it will slow down Flash memory for the high speeds.
> ---
> c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h | 10 +
> .../libbsp/arm/stm32f4/include/stm32f4_flash.h | 45 +
> .../libbsp/arm/stm32f4/include/stm32f4_rcc.h | 94 +
> c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c| 211
> +
> 4 files changed, 360 insertions(+)
> create mode 100644
> c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
>
> diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
> b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
> index 59d13ef..d26f914 100644
> --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
> +++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
> @@ -55,6 +55,16 @@
>
> /** @} */
>
> +/**
> + * @name STM32F4 FLASH
> + * @{
> + */
> +
> +#include
> +#define STM32F4_FLASH ((volatile stm32f4_flash *) (STM32F4_BASE +
> 0x40023C00))
> +
> +/** @} */
> +
> #include
>
> /**
> diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
> b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
> new file mode 100644
> index 000..ed08d76
> --- /dev/null
> +++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
> @@ -0,0 +1,45 @@
> +/**
> + * @file
> + * @ingroup stm32f4_flash
> + * @brief STM32F4 FLASH support.
> + */
> +
> +/*
> + * Copyright (c) 2012 Sebastian Huber. All rights reserved.
> + *
> + * embedded brains GmbH
> + * Obere Lagerstr. 30
> + * 82178 Puchheim
> + * Germany
> + *
> + *
> + * The license and distribution terms for this file may be
> + * found in the file LICENSE in this distribution or at
> + * http://www.rtems.org/license/LICENSE.
> + */
> +
> +#ifndef LIBBSP_ARM_STM32F4_STM32F4_FLASH_H
> +#define LIBBSP_ARM_STM32F4_STM32F4_FLASH_H
> +
> +#include
> +
> +/**
> + * @defgroup stm32f10xxx_flash STM32F4 FLASH Support
> + * @ingroup stm32f4_flash
> + * @brief STM32F4FXXX FLASH Support
> + * @{
> + */
> +
> +typedef struct {
> + uint32_t acr;
> + uint32_t keyr;
> + uint32_t optkeyr;
> + uint32_t sr;
> + uint32_t cr;
> + uint32_t optcr;
> + uint32_t optcr1;
> +} stm32f4_flash;
> +
> +/** @} */
> +
> +#endif /* LIBBSP_ARM_STM32F4_STM32F4_FLASH_H */
> diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
> b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
> index 8126340..ce85b8e 100644
> --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
> +++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
> @@ -56,4 +56,98 @@ typedef struct {
>
> /** @} */
>
> +#define RCC_CR_HSION BSP_BIT32(0)
> +#define RCC_CR_HSIRDY BSP_BIT32(1)
> +#define RCC_CR_HSITRIM3
> +#define RCC_CR_HSICAL 8
> +#define RCC_CR_HSEON BSP_BIT32(16)
> +#define RCC_CR_HSERDY BSP_BIT32(17)
> +#define RCC_CR_HSEBYP BSP_BIT32(18)
> +#define RCC_CR_CSSON BSP_BIT32(19)
> +#define RCC_CR_PLLON BSP_BIT32(24)
> +#define RCC_CR_PLLRDY BSP_BIT32(25)
> +#define RCC_CR_PLLI2SON BSP_BIT32(26)
> +#define RCC_CR_PLLI2SRDY BSP_BIT32(27)
> +
> +
> +#define RCC_PLLCFGR_PLLM0
> +#define RCC_PLLCFGR_PLLN6
> +#define RCC_PLLCFGR_PLLP16
> +
> +#define RCC_PLLCFGR_PLLSRC_HSE BSP_BIT32(22)
> +#define RCC_PLLCFGR_PLLSRC_HSI 0
> +
> +#define RCC_PLLCFGR_PLLQ 24
> +
> +
> +#define RCC_CFGR_SW 0
> +#define RCC_CFGR_SW_MASK 3
> +#define RCC_CFGR_SW_HSI 0
> +#define RCC_CFGR_SW_HSE 1
> +#define RCC_CFGR_SW_PLL 2
> +
> +#define RCC_CFGR_SWS 2
> +#define RCC_CFGR_SWS_MASK(3 << RCC_CFGR_SWS)
> +
> +#define RCC_CFGR_SWS_HSI 0
> +#define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS)
> +#define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS)
> +
> +#define RCC_CFGR_HPRE4
> +#define RCC_CFGR_HPRE_BY_1 0
> +#define RCC_CFGR_HPRE_BY_2 ( 8 << RCC_CFGR_HPRE)
> +#define RCC_CFGR_HPRE_BY_4 ( 9 << RCC_CFGR_HPRE)
> +#define RCC_CFGR_HPRE_BY_8 (10 << RCC_CFGR_HPRE)
> +#define RCC_CFGR_HPRE_BY_16 (11 << RCC_CFGR_HPRE)
> +#define RCC_CFGR_HPRE_BY_64 (12 << RCC_CFGR_HPRE)
> +#define RCC_CFGR_HPRE_BY_128 (13 << RCC_CFGR_HPRE)
> +#define RCC_CFGR_HPRE_BY_256 (14 << RCC_CFGR_HPRE)
> +#define RCC_CFGR_HPRE_BY_512 (15 << RCC_CFGR_HPRE)
> +
> +#define RCC_CFGR
[PATCH] bsp:stm32f4XXXX system clock configuration
From: Tomasz Gregorek
Added simple math to caclulate register values for the PLL
and for the prescalers. It will try to keep 48MHz for the USB OTG FS.
Also it will slow down Flash memory for the high speeds.
---
c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h | 10 +
.../libbsp/arm/stm32f4/include/stm32f4_flash.h | 41
.../libbsp/arm/stm32f4/include/stm32f4_rcc.h | 94 +
c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c| 211 +
4 files changed, 356 insertions(+)
create mode 100644 c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
index 59d13ef..d26f914 100644
--- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
@@ -55,6 +55,16 @@
/** @} */
+/**
+ * @name STM32F4 FLASH
+ * @{
+ */
+
+#include
+#define STM32F4_FLASH ((volatile stm32f4_flash *) (STM32F4_BASE + 0x40023C00))
+
+/** @} */
+
#include
/**
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
new file mode 100644
index 000..31b3992
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
@@ -0,0 +1,41 @@
+/**
+ * @file
+ * @ingroup stm32f4_flash
+ * @brief STM32F4 FLASH support.
+ */
+
+/*
+ * Copyright (c) 2014 Tomasz Gregorek. All rights reserved.
+ *
+ *
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_STM32F4_FLASH_H
+#define LIBBSP_ARM_STM32F4_STM32F4_FLASH_H
+
+#include
+
+/**
+ * @defgroup stm32f10xxx_flash STM32F4 FLASH Support
+ * @ingroup stm32f4_flash
+ * @brief STM32F4FXXX FLASH Support
+ * @{
+ */
+
+typedef struct {
+ uint32_t acr;
+ uint32_t keyr;
+ uint32_t optkeyr;
+ uint32_t sr;
+ uint32_t cr;
+ uint32_t optcr;
+ uint32_t optcr1;
+} stm32f4_flash;
+
+/** @} */
+
+#endif /* LIBBSP_ARM_STM32F4_STM32F4_FLASH_H */
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
index 8126340..ce85b8e 100644
--- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
@@ -56,4 +56,98 @@ typedef struct {
/** @} */
+#define RCC_CR_HSION BSP_BIT32(0)
+#define RCC_CR_HSIRDY BSP_BIT32(1)
+#define RCC_CR_HSITRIM3
+#define RCC_CR_HSICAL 8
+#define RCC_CR_HSEON BSP_BIT32(16)
+#define RCC_CR_HSERDY BSP_BIT32(17)
+#define RCC_CR_HSEBYP BSP_BIT32(18)
+#define RCC_CR_CSSON BSP_BIT32(19)
+#define RCC_CR_PLLON BSP_BIT32(24)
+#define RCC_CR_PLLRDY BSP_BIT32(25)
+#define RCC_CR_PLLI2SON BSP_BIT32(26)
+#define RCC_CR_PLLI2SRDY BSP_BIT32(27)
+
+
+#define RCC_PLLCFGR_PLLM0
+#define RCC_PLLCFGR_PLLN6
+#define RCC_PLLCFGR_PLLP16
+
+#define RCC_PLLCFGR_PLLSRC_HSE BSP_BIT32(22)
+#define RCC_PLLCFGR_PLLSRC_HSI 0
+
+#define RCC_PLLCFGR_PLLQ 24
+
+
+#define RCC_CFGR_SW 0
+#define RCC_CFGR_SW_MASK 3
+#define RCC_CFGR_SW_HSI 0
+#define RCC_CFGR_SW_HSE 1
+#define RCC_CFGR_SW_PLL 2
+
+#define RCC_CFGR_SWS 2
+#define RCC_CFGR_SWS_MASK(3 << RCC_CFGR_SWS)
+
+#define RCC_CFGR_SWS_HSI 0
+#define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS)
+#define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS)
+
+#define RCC_CFGR_HPRE4
+#define RCC_CFGR_HPRE_BY_1 0
+#define RCC_CFGR_HPRE_BY_2 ( 8 << RCC_CFGR_HPRE)
+#define RCC_CFGR_HPRE_BY_4 ( 9 << RCC_CFGR_HPRE)
+#define RCC_CFGR_HPRE_BY_8 (10 << RCC_CFGR_HPRE)
+#define RCC_CFGR_HPRE_BY_16 (11 << RCC_CFGR_HPRE)
+#define RCC_CFGR_HPRE_BY_64 (12 << RCC_CFGR_HPRE)
+#define RCC_CFGR_HPRE_BY_128 (13 << RCC_CFGR_HPRE)
+#define RCC_CFGR_HPRE_BY_256 (14 << RCC_CFGR_HPRE)
+#define RCC_CFGR_HPRE_BY_512 (15 << RCC_CFGR_HPRE)
+
+#define RCC_CFGR_PPRE110
+#define RCC_CFGR_PPRE1_BY_1 0
+#define RCC_CFGR_PPRE1_BY_2 (4 << RCC_CFGR_PPRE1)
+#define RCC_CFGR_PPRE1_BY_4 (5 << RCC_CFGR_PPRE1)
+#define RCC_CFGR_PPRE1_BY_8 (6 << RCC_CFGR_PPRE1)
+#define RCC_CFGR_PPRE1_BY_16 (7 << RCC_CFGR_PPRE1)
+
+#define RCC_CFGR_PPRE213
+#define RCC_CFGR_PPRE2_BY_1 0
+#define RCC_CFGR_PPRE2_BY_2 (4 << RCC_CFGR_PPRE2)
+#define RCC_CFGR_PPRE2_BY_4 (5 << RCC_CFGR_PPRE2)
+#define RCC_CFGR_PPRE2_BY_8 (6 << RCC_CFGR_PPRE2)
+#define RCC_CFGR_PPRE2_BY_16 (7 << RCC_CFGR_PPRE2)
+
+#define RCC_CFGR_RTCPRE 16
+#define RCC_CFGR_RTCPRE_SET(a) (a << RCC_CFGR_RTCPRE)
+
+#define RCC_CFGR_MCO1 21
+#define RCC_CFGR_MCO1_HSI 0
+#define RCC_CFGR_MCO1_LSE (1 << RCC_CFGR_MCO1)
+#define RCC_CFGR_MCO1_HSE (2 <
Re: [PATCH] bsp:stm32f4XXXX system clock configuration
There are not only styles to be corrected. I will send a new version soon.
2014-09-20 20:41 GMT+02:00 Joel Sherrill :
> Style comments from me. I will let those who know who the HW comment on
> that.
>
> On September 20, 2014 1:23:26 PM CDT, "tomasz.grego...@gmail.com" <
> tomasz.grego...@gmail.com> wrote:
> >From: Tomasz Gregorek
> >
> >Added simple math to caclulate register values for the PLL
> >and for the prescalers. It will try to keep 48MHz for the USB OTG FS.
> >Also it will slow down Flash memory for the high speeds.
> >---
> > c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h | 10 +
> > .../libbsp/arm/stm32f4/include/stm32f4_flash.h | 41
> > .../libbsp/arm/stm32f4/include/stm32f4_rcc.h | 94 +
> >c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c| 211
> >+
> > 4 files changed, 356 insertions(+)
> >create mode 100644
> >c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
> >
> >diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
> >b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
> >index 59d13ef..d26f914 100644
> >--- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
> >+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
> >@@ -55,6 +55,16 @@
> >
> > /** @} */
> >
> >+/**
> >+ * @name STM32F4 FLASH
> >+ * @{
> >+ */
> >+
> >+#include
> >+#define STM32F4_FLASH ((volatile stm32f4_flash *) (STM32F4_BASE +
> >0x40023C00))
> >+
> >+/** @} */
> >+
> > #include
> >
> > /**
> >diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
> >b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
> >new file mode 100644
> >index 000..31b3992
> >--- /dev/null
> >+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
> >@@ -0,0 +1,41 @@
> >+/**
> >+ * @file
> >+ * @ingroup stm32f4_flash
> >+ * @brief STM32F4 FLASH support.
> >+ */
> >+
> >+/*
> >+ * Copyright (c) 2014 Tomasz Gregorek. All rights reserved.
> >+ *
> >+ *
> >+ *
> >+ * The license and distribution terms for this file may be
> >+ * found in the file LICENSE in this distribution or at
> >+ * http://www.rtems.org/license/LICENSE.
> >+ */
> >+
> >+#ifndef LIBBSP_ARM_STM32F4_STM32F4_FLASH_H
> >+#define LIBBSP_ARM_STM32F4_STM32F4_FLASH_H
> >+
> >+#include
> >+
> >+/**
> >+ * @defgroup stm32f10xxx_flash STM32F4 FLASH Support
> >+ * @ingroup stm32f4_flash
> >+ * @brief STM32F4FXXX FLASH Support
> >+ * @{
> >+ */
> >+
> >+typedef struct {
> >+ uint32_t acr;
> >+ uint32_t keyr;
> >+ uint32_t optkeyr;
> >+ uint32_t sr;
> >+ uint32_t cr;
> >+ uint32_t optcr;
> >+ uint32_t optcr1;
> >+} stm32f4_flash;
> >+
> >+/** @} */
> >+
> >+#endif /* LIBBSP_ARM_STM32F4_STM32F4_FLASH_H */
> >diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
> >b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
> >index 8126340..ce85b8e 100644
> >--- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
> >+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
> >@@ -56,4 +56,98 @@ typedef struct {
> >
> > /** @} */
> >
> >+#define RCC_CR_HSION BSP_BIT32(0)
> >+#define RCC_CR_HSIRDY BSP_BIT32(1)
> >+#define RCC_CR_HSITRIM3
> >+#define RCC_CR_HSICAL 8
> >+#define RCC_CR_HSEON BSP_BIT32(16)
> >+#define RCC_CR_HSERDY BSP_BIT32(17)
> >+#define RCC_CR_HSEBYP BSP_BIT32(18)
> >+#define RCC_CR_CSSON BSP_BIT32(19)
> >+#define RCC_CR_PLLON BSP_BIT32(24)
> >+#define RCC_CR_PLLRDY BSP_BIT32(25)
> >+#define RCC_CR_PLLI2SON BSP_BIT32(26)
> >+#define RCC_CR_PLLI2SRDY BSP_BIT32(27)
> >+
> >+
> >+#define RCC_PLLCFGR_PLLM0
> >+#define RCC_PLLCFGR_PLLN6
> >+#define RCC_PLLCFGR_PLLP16
> >+
> >+#define RCC_PLLCFGR_PLLSRC_HSE BSP_BIT32(22)
> >+#define RCC_PLLCFGR_PLLSRC_HSI 0
> >+
> >+#define RCC_PLLCFGR_PLLQ 24
> >+
> >+
> >+#define RCC_CFGR_SW 0
> >+#define RCC_CFGR_SW_MASK 3
> >+#define RCC_CFGR_SW_HSI 0
> >+#define RCC_CFGR_SW_HSE 1
> >+#define RCC_CFGR_SW_PLL 2
> >+
> >+#define RCC_CFGR_SWS 2
> >+#define RCC_CFGR_SWS_MASK(3 << RCC_CFGR_SWS)
> >+
> >+#define RCC_CFGR_SWS_HSI 0
> >+#define RCC_CFGR_SWS_HSE
[PATCH] bsp/stm32f4XXXX: System clock configuration
From: Tomasz Gregorek
Added simple math to caclulate register values for the PLL
and for the prescalers. It will try to keep 48MHz for the USB OTG FS.
Also it will set latency on the Flash memory for the high speeds.
Limitations:
It is assumed that 1MHz resolution is enough.
Best fits for the clocks are achieved with multiplies of 42MHz.
Even though APB1, APB2 and AHB are calculated user is still required
to provide correct values for the bsp configuration for the:
STM32F4_PCLK1
STM32F4_PCLK2
STM32F4_HCLK (= system clock)
as those are used for the peripheral clocking calculations.
---
c/src/lib/libbsp/arm/stm32f4/Makefile.am | 1 +
c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h | 10 +
.../libbsp/arm/stm32f4/include/stm32f4_flash.h | 54
.../libbsp/arm/stm32f4/include/stm32f4_rcc.h | 150 +--
c/src/lib/libbsp/arm/stm32f4/preinstall.am | 4 +
c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c| 280 -
6 files changed, 475 insertions(+), 24 deletions(-)
create mode 100644 c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
diff --git a/c/src/lib/libbsp/arm/stm32f4/Makefile.am
b/c/src/lib/libbsp/arm/stm32f4/Makefile.am
index 027fcad..055a0b1 100644
--- a/c/src/lib/libbsp/arm/stm32f4/Makefile.am
+++ b/c/src/lib/libbsp/arm/stm32f4/Makefile.am
@@ -51,6 +51,7 @@ include_bsp_HEADERS += include/stm32f10xxx_rcc.h
include_bsp_HEADERS += include/stm32f10xxx_exti.h
include_bsp_HEADERS += include/stm32f4_gpio.h
include_bsp_HEADERS += include/stm32f4_rcc.h
+include_bsp_HEADERS += include/stm32f4_flash.h
include_bsp_HEADERS += include/stm32_i2c.h
include_bsp_HEADERS += include/i2c.h
include_bsp_HEADERS += include/stm32_usart.h
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
index 59d13ef..d26f914 100644
--- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
@@ -55,6 +55,16 @@
/** @} */
+/**
+ * @name STM32F4 FLASH
+ * @{
+ */
+
+#include
+#define STM32F4_FLASH ((volatile stm32f4_flash *) (STM32F4_BASE + 0x40023C00))
+
+/** @} */
+
#include
/**
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
new file mode 100644
index 000..55d9dc6
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
@@ -0,0 +1,54 @@
+/**
+ * @file
+ *
+ * @ingroup stm32f4_flash
+ *
+ * @brief STM32F4 FLASH support.
+ *
+ * Contains structure desribing registers responsible for the flash memory
+ * configuration.
+ */
+
+/*
+ * Copyright (c) 2014 Tomasz Gregorek. All rights reserved.
+ *
+ *
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_STM32F4_FLASH_H
+#define LIBBSP_ARM_STM32F4_STM32F4_FLASH_H
+
+#include
+
+/**
+ * @defgroup stm32f10xxx_flash STM32F4 FLASH Support
+ * @ingroup stm32f4_flash
+ * @brief STM32F4FXXX FLASH Support
+ * @{
+ */
+
+typedef struct {
+ uint32_t acr;
+ uint32_t keyr;
+ uint32_t optkeyr;
+ uint32_t sr;
+ uint32_t cr;
+ uint32_t optcr;
+ uint32_t optcr1;
+} stm32f4_flash;
+
+/** @} */
+
+#define FLASH_ACR_LATENCY( val ) BSP_FLD32( val, 0, 3 )
+#define FLASH_ACR_LATENCY_MSK BSP_MSK32( 0, 3 )
+#define FLASH_ACR_PRFTEN BSP_BIT32( 8 )
+#define FLASH_ACR_ICEN BSP_BIT32( 9 )
+#define FLASH_ACR_DCEN BSP_BIT32( 10 )
+#define FLASH_ACR_ICRST BSP_BIT32( 11 )
+#define FLASH_ACR_DCRST BSP_BIT32( 12 )
+
+#endif /* LIBBSP_ARM_STM32F4_STM32F4_FLASH_H */
\ No newline at end of file
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
index 8126340..311e484 100644
--- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
@@ -31,29 +31,135 @@
*/
typedef struct {
- uint32_t cr;
- uint32_t pllcfgr;
- uint32_t cfgr;
- uint32_t cir;
- uint32_t ahbrstr [3];
- uint32_t reserved_1c;
- uint32_t apbrstr [2];
- uint32_t reserved_28 [2];
- uint32_t ahbenr [3];
- uint32_t reserved_3c;
- uint32_t apbenr [2];
- uint32_t reserved_48 [2];
- uint32_t ahblpenr [3];
- uint32_t reserved_5c;
- uint32_t apblpenr [2];
- uint32_t reserved_68 [2];
- uint32_t bdcr;
- uint32_t csr;
- uint32_t reserved_78 [2];
- uint32_t sscgr;
- uint32_t plli2scfgr;
+ uint32_t cr;
+ uint32_t pllcfgr;
+ uint32_t cfgr;
+ uint32_t cir;
+ uint32_t ahbrstr[ 3 ];
+ uint32_t reserved_1c;
+ uint32_t apbrstr[ 2 ];
+ uint32_t reserved_28[ 2 ];
+ uint32_t ahbenr[ 3 ];
+ uint32_t reserved_3c;
+ uint32_t apbenr[ 2 ];
+ uint32_t reserved_48[ 2 ];
+ uint32_t ahblpenr[ 3 ];
+ uint32_t reserved_5c;
+ uint32_t apblpenr
Re: [PATCH] bsp/stm32f4XXXX: System clock configuration
2014-09-21 20:07 GMT+02:00 :
> From: Tomasz Gregorek
>
> Added simple math to caclulate register values for the PLL
> and for the prescalers. It will try to keep 48MHz for the USB OTG FS.
> Also it will set latency on the Flash memory for the high speeds.
>
> Limitations:
> It is assumed that 1MHz resolution is enough.
> Best fits for the clocks are achieved with multiplies of 42MHz.
> Even though APB1, APB2 and AHB are calculated user is still required
> to provide correct values for the bsp configuration for the:
> STM32F4_PCLK1
> STM32F4_PCLK2
> STM32F4_HCLK (= system clock)
> as those are used for the peripheral clocking calculations.
> ---
> c/src/lib/libbsp/arm/stm32f4/Makefile.am | 1 +
> c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h | 10 +
> .../libbsp/arm/stm32f4/include/stm32f4_flash.h | 54
> .../libbsp/arm/stm32f4/include/stm32f4_rcc.h | 150 +--
> c/src/lib/libbsp/arm/stm32f4/preinstall.am | 4 +
> c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c| 280
> -
> 6 files changed, 475 insertions(+), 24 deletions(-)
> create mode 100644
> c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
>
> diff --git a/c/src/lib/libbsp/arm/stm32f4/Makefile.am
> b/c/src/lib/libbsp/arm/stm32f4/Makefile.am
> index 027fcad..055a0b1 100644
> --- a/c/src/lib/libbsp/arm/stm32f4/Makefile.am
> +++ b/c/src/lib/libbsp/arm/stm32f4/Makefile.am
> @@ -51,6 +51,7 @@ include_bsp_HEADERS += include/stm32f10xxx_rcc.h
> include_bsp_HEADERS += include/stm32f10xxx_exti.h
> include_bsp_HEADERS += include/stm32f4_gpio.h
> include_bsp_HEADERS += include/stm32f4_rcc.h
> +include_bsp_HEADERS += include/stm32f4_flash.h
> include_bsp_HEADERS += include/stm32_i2c.h
> include_bsp_HEADERS += include/i2c.h
> include_bsp_HEADERS += include/stm32_usart.h
> diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
> b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
> index 59d13ef..d26f914 100644
> --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
> +++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
> @@ -55,6 +55,16 @@
>
> /** @} */
>
> +/**
> + * @name STM32F4 FLASH
> + * @{
> + */
> +
> +#include
> +#define STM32F4_FLASH ((volatile stm32f4_flash *) (STM32F4_BASE +
> 0x40023C00))
> +
> +/** @} */
> +
> #include
>
> /**
> diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
> b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
> new file mode 100644
> index 000..55d9dc6
> --- /dev/null
> +++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_flash.h
> @@ -0,0 +1,54 @@
> +/**
> + * @file
> + *
> + * @ingroup stm32f4_flash
> + *
> + * @brief STM32F4 FLASH support.
> + *
> + * Contains structure desribing registers responsible for the flash memory
> + * configuration.
> + */
> +
> +/*
> + * Copyright (c) 2014 Tomasz Gregorek. All rights reserved.
> + *
> + *
> + *
> + * The license and distribution terms for this file may be
> + * found in the file LICENSE in this distribution or at
> + * http://www.rtems.org/license/LICENSE.
> + */
> +
> +#ifndef LIBBSP_ARM_STM32F4_STM32F4_FLASH_H
> +#define LIBBSP_ARM_STM32F4_STM32F4_FLASH_H
> +
> +#include
> +
> +/**
> + * @defgroup stm32f10xxx_flash STM32F4 FLASH Support
> + * @ingroup stm32f4_flash
> + * @brief STM32F4FXXX FLASH Support
> + * @{
> + */
> +
> +typedef struct {
> + uint32_t acr;
> + uint32_t keyr;
> + uint32_t optkeyr;
> + uint32_t sr;
> + uint32_t cr;
> + uint32_t optcr;
> + uint32_t optcr1;
> +} stm32f4_flash;
> +
> +/** @} */
> +
> +#define FLASH_ACR_LATENCY( val ) BSP_FLD32( val, 0, 3 )
> +#define FLASH_ACR_LATENCY_MSK BSP_MSK32( 0, 3 )
> +#define FLASH_ACR_PRFTEN BSP_BIT32( 8 )
> +#define FLASH_ACR_ICEN BSP_BIT32( 9 )
> +#define FLASH_ACR_DCEN BSP_BIT32( 10 )
> +#define FLASH_ACR_ICRST BSP_BIT32( 11 )
> +#define FLASH_ACR_DCRST BSP_BIT32( 12 )
> +
> +#endif /* LIBBSP_ARM_STM32F4_STM32F4_FLASH_H */
> \ No newline at end of file
> diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
> b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
> index 8126340..311e484 100644
> --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
> +++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4_rcc.h
> @@ -31,29 +31,135 @@
> */
>
> typedef struct {
> - uint32_t cr;
> - uint32_t pllcfgr;
> - uint32_t cfgr;
> - uint32_t cir;
> - uint32_t ahbrstr [3];
> - uint32_t reserved_1c;
> - uint32_t apbrstr [2];
> - uint32_t reserved_28 [2];
> -
Re: STM32F4 register definitions and PLL settings patch
Hi Chris - pll_q = ( (long) ( src_clk * pll_n + src_clk * pll_n / 2 ) ) / pll_m / 48; + pll_q = ( (long) ( src_clk * pll_n ) ) / pll_m / 48; Your fix for the PLL_Q calculation is correct. It supposed to be rounding from <=X.5 to X and from >X.5 to (X+1) but first I messed up the equation second this clock should not exceed 48MHz so rounding up is not necessarily the best idea. -#define FLASH_ACR_LATENCY( val ) BSP_FLD32( val, 0, 3 ) -#define FLASH_ACR_LATENCY_MSK BSP_MSK32( 0, 3 ) +#define STM32F4_FLASH_ACR_LATENCY(val) BSP_FLD32(val, 0, 2) // Flash access latency +#define STM32F4_FLASH_ACR_LATENCY_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define STM32F4_FLASH_ACR_LATENCY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) I would argue about the STM32F4_FLASH_ACR_LATENCY where you use 3LSB of ACR (up to 7 wait states) which is correct for the STM32F405xx/07xx and STM32F415xx/17xx while for the STM32F42xxx and STM32F43xxx there are 4LSBs in use (up to 15 wait states). I am not sure how to deal with it. Do we need to distinguish for which chip we are compiling? Thanks and regards Tomasz 2014-10-18 11:06 GMT+02:00 Chris Nott : > Hi, > > I sent these header file changes previously, they didn't get picked up. > > I re-merged with the head, cleaned up formatting and fixed a bug with > PLL_Q setting not generating the right auxiliary clock frequency for USB > peripheral - Tomasz this was your change, could you please review my fix. > > Regards, > Chris. > > ___ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel > ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: STM32F4 register definitions and PLL settings patch
Hi Chris 2014-10-19 8:36 GMT+02:00 Chris Nott : > Hi, > > On 18/10/2014 3:45 AM, Tomasz Gregorek wrote: > > Hi Chris > > - pll_q = ( (long) ( src_clk * pll_n + src_clk * pll_n / 2 ) ) / pll_m / > 48; + pll_q = ( (long) ( src_clk * pll_n ) ) / pll_m / 48; > > Your fix for the PLL_Q calculation is correct. > It supposed to be rounding from <=X.5 to X and from >X.5 to (X+1) but > first I messed up the equation second this clock should not exceed 48MHz so > rounding up is not necessarily the best idea. > > A check for clock <= 48MHz would be good. Even better if we can check if > USB is used and warn if it is not exactly 48MHz.. > > > > -#define FLASH_ACR_LATENCY( val ) BSP_FLD32( val, 0, 3 ) -#define > FLASH_ACR_LATENCY_MSK BSP_MSK32( 0, 3 ) > > +#define STM32F4_FLASH_ACR_LATENCY(val) BSP_FLD32(val, 0, 2) // Flash > access latency +#define STM32F4_FLASH_ACR_LATENCY_GET(reg) > BSP_FLD32GET(reg, 0, 2) +#define STM32F4_FLASH_ACR_LATENCY_SET(reg, val) > BSP_FLD32SET(reg, val, 0, 2) > > I would argue about the STM32F4_FLASH_ACR_LATENCY where you use 3LSB of > ACR (up to 7 wait states) which is correct for the STM32F405xx/07xx and > STM32F415xx/17xx while for the STM32F42xxx and STM32F43xxx there are 4LSBs > in use (up to 15 wait states). > I am not sure how to deal with it. Do we need to distinguish for which > chip we are compiling? > > I think it should be safe to use 3 bits as it was. It's a pretty low risk > that someone will accidentally set a flash latency > 7 and it is pretty > likely a write to that bit would be ignored in the hardware anyway. > > Ideally yes when we support STM42xxx etc. as well we should add a build > option, but there may be more we need to add, like the operating chip > voltage. Honesty my priority so far is first adding register maps and > example projects to make RTEMS more useful out of the box for standard > boards like STM32F4Discovery. > I vote to keep simplified pll_q calculation, maybe add more comment in the configuration header for it. If we add a check, than also a switch to turn on/off USB would be needed so the warning will not print out if USB is not used. Of course it will be very good to have these but I agree with your priority of making RTEMS more useful on Discovery like boards first and we can keep upgrading the bsp with time. Yes, there are more registers specific to specific CPU versions, different number of UARTs and other peripherals. As above, lets keep it simple for the start. Myself I have working UART driver with interrupt driven data receiver (currently it is polled UART). I should be able to push it in few days. I2C is half working but will take more time due to work overload. Cheers Tomasz > > > > Thanks and regards > Tomasz > > > 2014-10-18 11:06 GMT+02:00 Chris Nott : > >> Hi, >> >> I sent these header file changes previously, they didn't get picked up. >> >> I re-merged with the head, cleaned up formatting and fixed a bug with >> PLL_Q setting not generating the right auxiliary clock frequency for USB >> peripheral - Tomasz this was your change, could you please review my fix. >> >> Regards, >> Chris. >> >> ___ >> devel mailing list >> devel@rtems.org >> http://lists.rtems.org/mailman/listinfo/devel >> > > > > ___ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel > ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
