Re: [PATCH 1/2] dev/clock: Move bcm2835-system-timer driver to shared space
Hi Mr. Kinsey Moore,
Thank you very much for your help.
I just sent patch 1. And about patch2, I have a question:
In shared/dev/clock/bcm2835-system-timer.c:
#if RTEMS_BSP == raspberrypi4b
#include
#else
#include
#endif /* RTEMS_BSP */
Do I need to rename bcm2711.h in rpi4 BSP to raspberrypi.h, this will modify
many files in rpi4 BSP.
Best regards,
Ning
From: Kinsey Moore
Sent: Tuesday, April 9, 2024 11:10
To: Ning Yang
Cc: devel@rtems.org
Subject: Re: [PATCH 1/2] dev/clock: Move bcm2835-system-timer driver to shared
space
One comment inline below.
On Tue, Apr 9, 2024 at 10:02 AM Ning Yang mailto:yan...@qq.com>>
wrote:
This patch moves the bcm2835 system timer driver in the arm/raspberrypi
directory to the shared directory.
Made some changes in the include section to adapt to rpi4 BSP.
---
.../clockdrv.c => shared/dev/clock/bcm2835-system-timer.c} | 7 +++
spec/build/bsps/arm/raspberrypi/obj.yml| 2 +-
2 files changed, 8 insertions(+), 1 deletion(-)
rename bsps/{arm/raspberrypi/clock/clockdrv.c =>
shared/dev/clock/bcm2835-system-timer.c} (95%)
diff --git a/bsps/arm/raspberrypi/clock/clockdrv.c
b/bsps/shared/dev/clock/bcm2835-system-timer.c
similarity index 95%
rename from bsps/arm/raspberrypi/clock/clockdrv.c
rename to bsps/shared/dev/clock/bcm2835-system-timer.c
index 8d220d51ba..2725735860 100644
--- a/bsps/arm/raspberrypi/clock/clockdrv.c
+++ b/bsps/shared/dev/clock/bcm2835-system-timer.c
@@ -22,7 +22,14 @@
#include
#include
#include
+
+#if RTEMS_BSP == raspberrypi4b
+#include
+#define BCM2835_REG(addr) *(volatile uint32_t*)(addr)
+#else
#include
+#endif /* RTEMS_BSP */
+
This change should really be in patch 2, but there is another issue with this
change. This pattern is not used in existing code that I could find because
it's fragile and introduces BSP-specific code into a shared driver that will
need to be updated for every single BSP that eventually wants to use it. Either
the RPi4 BSP should define BCM2835_REG as a 32bit register access for
compatibility or this driver should have its register accesses renamed to
something more generic such as PI32_REG which the RPi3 and RPi4 BSPs can
provide for usage with this driver.
#include
/* This is defined in ../../../shared/dev/clock/clockimpl.h */
diff --git a/spec/build/bsps/arm/raspberrypi/obj.yml
b/spec/build/bsps/arm/raspberrypi/obj.yml
index ec5c82a8fb..ea370829df 100644
--- a/spec/build/bsps/arm/raspberrypi/obj.yml
+++ b/spec/build/bsps/arm/raspberrypi/obj.yml
@@ -26,7 +26,6 @@ install:
- bsps/arm/raspberrypi/include/bsp/vc.h
links: []
source:
-- bsps/arm/raspberrypi/clock/clockdrv.c
- bsps/arm/raspberrypi/console/console-config.c
- bsps/arm/raspberrypi/console/fb.c
- bsps/arm/raspberrypi/console/fbcons.c
@@ -47,6 +46,7 @@ source:
- bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c
- bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
- bsps/arm/shared/start/bsp-start-memcpy.S
+- bsps/shared/dev/clock/bcm2835-system-timer.c
- bsps/shared/dev/cpucounter/cpucounterfrequency.c
- bsps/shared/dev/cpucounter/cpucounterread.c
- bsps/shared/dev/getentropy/getentropy-cpucounter.c
--
2.34.1
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[PATCH 3/3] bsps/xil-ttc: Improve clock driver
Make the clock driver parameters configurable. Use the maximum counter
frequency to get the best time resolution. Decouple the CPU counter from the
timecounter. Make the tick catch up handling more robust. Add a validation
test for the tick catch up.
---
bsps/arm/xilinx-zynqmp-rpu/include/bsp.h | 3 -
bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h | 1 -
bsps/shared/dev/clock/xil-ttc.c | 255 +-
spec/build/bsps/arm/xilinx-zynqmp-rpu/grp.yml | 6 +
spec/build/bsps/optxilclockttcbaseaddr.yml| 18 ++
spec/build/bsps/optxilclockttcirq.yml | 18 ++
spec/build/bsps/optxilclockttcrefclk.yml | 18 ++
.../validation/bsps/objclockxilttc.yml| 14 +
.../validation/bsps/validation-bsp-0.yml | 6 +-
testsuites/validation/tc-dev-clock-xil-ttc.c | 136 ++
10 files changed, 337 insertions(+), 138 deletions(-)
create mode 100644 spec/build/bsps/optxilclockttcbaseaddr.yml
create mode 100644 spec/build/bsps/optxilclockttcirq.yml
create mode 100644 spec/build/bsps/optxilclockttcrefclk.yml
create mode 100644 spec/build/testsuites/validation/bsps/objclockxilttc.yml
create mode 100644 testsuites/validation/tc-dev-clock-xil-ttc.c
diff --git a/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
b/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
index d80cedbd0d..70ad4f3c57 100644
--- a/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
+++ b/bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
@@ -59,7 +59,6 @@
#include
#include
-#include
#include
@@ -76,8 +75,6 @@ extern "C" {
#define BSP_ARM_A9MPCORE_GT_BASE 0
-#define BSP_SELECTED_TTC_ADDR ZYNQMP_TTC0
-
/**
* @brief Zynq UltraScale+ MPSoC specific set up of the MMU.
*
diff --git a/bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h
b/bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h
index a65e5404f0..51aa613cdd 100644
--- a/bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h
+++ b/bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h
@@ -51,7 +51,6 @@
extern "C" {
#endif /* __cplusplus */
-#define BSP_SELECTED_TTC_IRQ ZYNQMP_IRQ_TTC_0_0
#define BSP_INTERRUPT_VECTOR_COUNT 188
/** @} */
diff --git a/bsps/shared/dev/clock/xil-ttc.c b/bsps/shared/dev/clock/xil-ttc.c
index 0140bb7445..624845d71c 100644
--- a/bsps/shared/dev/clock/xil-ttc.c
+++ b/bsps/shared/dev/clock/xil-ttc.c
@@ -1,14 +1,16 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
/**
* @file
*
- * @ingroup RTEMSBSPsARMZynqMP
+ * @ingroup RTEMSDriverClockXilTTC
*
- * @brief Triple Timer Counter clock functions definitions.
+ * @brief This source file contains a Clock Driver implementation using the
+ * Xilinx Triple Timer Counter (TTC).
*/
/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
+ * Copyright (C) 2024 embedded brains GmbH & Co. KG
* Copyright (C) 2023 Reflex Aerospace GmbH
*
* Written by Philip Kirkpatrick
@@ -38,175 +40,160 @@
#include
#include
#include
-#include
#include
+#include
#include
-typedef struct {
- struct timecounter ttc_tc;
- uint32_t irq_match_interval;
- uint32_t tick_miss;
-} ttc_clock_context;
-
-static ttc_clock_context ttc_clock_instance = {0, };
+#if XTTCPS_COUNT_VALUE_MASK != UINT32_MAX
+#error "unexpected XTTCPS_COUNT_VALUE_MASK value"
+#endif
-#define TTC_REFERENCE_CLOCK 1
+/**
+ * @defgroup RTEMSDriverClockXilTTC \
+ * Xilinx Triple Timer Counter (TTC) Clock Driver
+ *
+ * @ingroup RTEMSDriverClockImpl
+ *
+ * @brief This group contains the Xilinx Triple Timer Counter (TTC) Clock
+ * Driver implementation.
+ *
+ * @{
+ */
uint32_t _CPU_Counter_frequency( void )
{
- return ttc_clock_instance.ttc_tc.tc_frequency;
+ return XIL_CLOCK_TTC_REFERENCE_CLOCK;
}
-static uint32_t zynqmp_ttc_get_timecount(struct timecounter *tc)
+CPU_Counter_ticks _CPU_Counter_read(void)
{
- uint32_t time;
- time = XTtcPs_ReadReg(BSP_SELECTED_TTC_ADDR, XTTCPS_COUNT_VALUE_OFFSET);
- return time;
+ return XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET);
}
-CPU_Counter_ticks _CPU_Counter_read(void)
+static void xil_ttc_initialize(void)
{
- return zynqmp_ttc_get_timecount(&ttc_clock_instance.ttc_tc);
+ /* Do not use a prescaler to get a high resolution time source */
+ XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_CLK_CNTRL_OFFSET, 0);
+
+ /* Disable interupts */
+ XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_IER_OFFSET, 0);
+
+ /*
+ * Enable the timer, do not enable waveform output, increment up, use
+ * overflow mode, enable match mode.
+ */
+ XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_CNT_CNTRL_OFFSET,
+ XTTCPS_CNT_CNTRL_EN_WAVE_MASK | XTTCPS_CNT_CNTRL_MATCH_MASK);
}
-/**
- * @brief Initialize the HW peripheral for clock driver
- *
- * Clock driver is implemented by RTI module
- *
- * @retval Void
- */
-static void zynqmp_ttc_clock_driver_support_initialize_hardware(void)
-{
+RTEMS_SYSINIT_ITEM(
+ xil_ttc_initialize,
+ RTEMS_SYSINIT_CPU_COUNTER,
+ RTEMS_SYSINIT_ORDER_MIDDLE
+);
+
+typedef struct {
+ struct timecounter base;
+
[PATCH 1/3] bsps/xil-ttc: Use interrupt entry
---
bsps/shared/dev/clock/xil-ttc.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/bsps/shared/dev/clock/xil-ttc.c b/bsps/shared/dev/clock/xil-ttc.c
index 340c428a48..384f23663b 100644
--- a/bsps/shared/dev/clock/xil-ttc.c
+++ b/bsps/shared/dev/clock/xil-ttc.c
@@ -191,18 +191,24 @@ static void
zynqmp_ttc_clock_driver_support_at_tick(ttc_clock_context *tc)
/* Else, something is set up wrong, only match should be enabled */
}
+static rtems_interrupt_entry zynqmp_ttc_interrupt_entry;
+
static void zynqmp_ttc_clock_driver_support_install_isr(
rtems_interrupt_handler handler
)
{
rtems_status_code sc;
- sc = rtems_interrupt_handler_install(
-BSP_SELECTED_TTC_IRQ,
-"Clock",
-RTEMS_INTERRUPT_UNIQUE,
+ rtems_interrupt_entry_initialize(
+&zynqmp_ttc_interrupt_entry,
handler,
&ttc_clock_instance
+"Clock"
+ );
+ sc = rtems_interrupt_entry_install(
+BSP_SELECTED_TTC_IRQ,
+RTEMS_INTERRUPT_UNIQUE,
+&zynqmp_ttc_interrupt_entry
);
if ( sc != RTEMS_SUCCESSFUL ) {
rtems_fatal_error_occurred(0xdeadbeef);
--
2.35.3
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[PATCH 0/3] Improve Xilinx TTC clock driver
Sebastian Huber (3): bsps/xil-ttc: Use interrupt entry bsps/xil-ttc: Add XIL_FATAL_TTC_IRQ_INSTALL bsps/xil-ttc: Improve clock driver bsps/arm/xilinx-zynqmp-rpu/include/bsp.h | 3 - bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h | 1 - bsps/include/bsp/fatal.h | 3 + bsps/shared/dev/clock/xil-ttc.c | 267 +- spec/build/bsps/arm/xilinx-zynqmp-rpu/grp.yml | 6 + spec/build/bsps/optxilclockttcbaseaddr.yml| 18 ++ spec/build/bsps/optxilclockttcirq.yml | 18 ++ spec/build/bsps/optxilclockttcrefclk.yml | 18 ++ .../bsps/fatal-clock-xil-ttc-irq-install.yml | 21 ++ .../validation/bsps/objclockxilttc.yml| 14 + .../validation/bsps/validation-bsp-0.yml | 6 +- spec/build/testsuites/validation/grp.yml | 2 + .../bsps/tr-fatal-clock-xil-ttc-irq-install.c | 187 .../bsps/tr-fatal-clock-xil-ttc-irq-install.h | 84 ++ .../bsps/ts-fatal-clock-xil-ttc-irq-install.c | 79 ++ testsuites/validation/tc-dev-clock-xil-ttc.c | 136 + 16 files changed, 721 insertions(+), 142 deletions(-) create mode 100644 spec/build/bsps/optxilclockttcbaseaddr.yml create mode 100644 spec/build/bsps/optxilclockttcirq.yml create mode 100644 spec/build/bsps/optxilclockttcrefclk.yml create mode 100644 spec/build/testsuites/validation/bsps/fatal-clock-xil-ttc-irq-install.yml create mode 100644 spec/build/testsuites/validation/bsps/objclockxilttc.yml create mode 100644 testsuites/validation/bsps/tr-fatal-clock-xil-ttc-irq-install.c create mode 100644 testsuites/validation/bsps/tr-fatal-clock-xil-ttc-irq-install.h create mode 100644 testsuites/validation/bsps/ts-fatal-clock-xil-ttc-irq-install.c create mode 100644 testsuites/validation/tc-dev-clock-xil-ttc.c -- 2.35.3 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 2/3] bsps/xil-ttc: Add XIL_FATAL_TTC_IRQ_INSTALL
---
bsps/include/bsp/fatal.h | 3 +
bsps/shared/dev/clock/xil-ttc.c | 6 +-
.../bsps/fatal-clock-xil-ttc-irq-install.yml | 21 ++
spec/build/testsuites/validation/grp.yml | 2 +
.../bsps/tr-fatal-clock-xil-ttc-irq-install.c | 187 ++
.../bsps/tr-fatal-clock-xil-ttc-irq-install.h | 84
.../bsps/ts-fatal-clock-xil-ttc-irq-install.c | 79
7 files changed, 378 insertions(+), 4 deletions(-)
create mode 100644
spec/build/testsuites/validation/bsps/fatal-clock-xil-ttc-irq-install.yml
create mode 100644
testsuites/validation/bsps/tr-fatal-clock-xil-ttc-irq-install.c
create mode 100644
testsuites/validation/bsps/tr-fatal-clock-xil-ttc-irq-install.h
create mode 100644
testsuites/validation/bsps/ts-fatal-clock-xil-ttc-irq-install.c
diff --git a/bsps/include/bsp/fatal.h b/bsps/include/bsp/fatal.h
index ffdb4bc8e1..87fc481ead 100644
--- a/bsps/include/bsp/fatal.h
+++ b/bsps/include/bsp/fatal.h
@@ -214,6 +214,9 @@ typedef enum {
/* MicroBlaze fatal codes */
MICROBLAZE_FATAL_CLOCK_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(16),
+
+ /* Xilinx fatal codes */
+ XIL_FATAL_TTC_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(17),
} bsp_fatal_code;
RTEMS_NO_RETURN static inline void
diff --git a/bsps/shared/dev/clock/xil-ttc.c b/bsps/shared/dev/clock/xil-ttc.c
index 384f23663b..0140bb7445 100644
--- a/bsps/shared/dev/clock/xil-ttc.c
+++ b/bsps/shared/dev/clock/xil-ttc.c
@@ -35,11 +35,9 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include
-
-#include
#include
#include
+#include
#include
#include
#include
@@ -211,7 +209,7 @@ static void zynqmp_ttc_clock_driver_support_install_isr(
&zynqmp_ttc_interrupt_entry
);
if ( sc != RTEMS_SUCCESSFUL ) {
-rtems_fatal_error_occurred(0xdeadbeef);
+bsp_fatal(XIL_FATAL_TTC_IRQ_INSTALL);
}
}
diff --git
a/spec/build/testsuites/validation/bsps/fatal-clock-xil-ttc-irq-install.yml
b/spec/build/testsuites/validation/bsps/fatal-clock-xil-ttc-irq-install.yml
new file mode 100644
index 00..253131551d
--- /dev/null
+++ b/spec/build/testsuites/validation/bsps/fatal-clock-xil-ttc-irq-install.yml
@@ -0,0 +1,21 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: test-program
+cflags: []
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+cppflags: []
+cxxflags: []
+enabled-by: bsps/arm/xilinx-zynqmp-rpu
+features: c cprogram
+includes: []
+ldflags: []
+links: []
+source:
+- testsuites/validation/bsps/tr-fatal-clock-xil-ttc-irq-install.c
+- testsuites/validation/bsps/ts-fatal-clock-xil-ttc-irq-install.c
+stlib: []
+target: testsuites/validation/bsps/ts-fatal-clock-xil-ttc-irq-install.exe
+type: build
+use-after:
+- validation
+use-before: []
diff --git a/spec/build/testsuites/validation/grp.yml
b/spec/build/testsuites/validation/grp.yml
index 726cf732dd..f10c6a9823 100644
--- a/spec/build/testsuites/validation/grp.yml
+++ b/spec/build/testsuites/validation/grp.yml
@@ -78,6 +78,8 @@ links:
uid: validation-tls-0
- role: build-dependency
uid: validation-tls-1
+- role: build-dependency
+ uid: bsps/fatal-clock-xil-ttc-irq-install
- role: build-dependency
uid: bsps/fatal-sparc-leon3-cache-snooping-disabled-boot
- role: build-dependency
diff --git a/testsuites/validation/bsps/tr-fatal-clock-xil-ttc-irq-install.c
b/testsuites/validation/bsps/tr-fatal-clock-xil-ttc-irq-install.c
new file mode 100644
index 00..731b454ee4
--- /dev/null
+++ b/testsuites/validation/bsps/tr-fatal-clock-xil-ttc-irq-install.c
@@ -0,0 +1,187 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup DevClockXilTtcValFatalIrqInstall
+ */
+
+/*
+ * Copyright (C) 2024 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFT
Re: [PATCH 1/2] dev/clock: Move bcm2835-system-timer driver to shared space
Hi Ning,
Patch 1 looks good. Instead of renaming it, you can include bcm2711.h in
the RPi4's raspberrypi.h or in bsp.h so that the RPi4 BSP remains largely
unchanged.
Kinsey
On Wed, Apr 10, 2024 at 2:14 AM yan...@qq.com wrote:
> Hi Mr. Kinsey Moore,
>
> Thank you very much for your help.
>
> I just sent patch 1. And about patch2, I have a question:
>
> In shared/dev/clock/bcm2835-system-timer.c:
>
> #if RTEMS_BSP == raspberrypi4b
> #include
> #else
> #include
> #endif /* RTEMS_BSP */
>
> Do I need to rename bcm2711.h in rpi4 BSP to raspberrypi.h, this will
> modify many files in rpi4 BSP.
>
> Best regards,
>
> Ning
> --
> *From:* Kinsey Moore
> *Sent:* Tuesday, April 9, 2024 11:10
> *To:* Ning Yang
> *Cc:* devel@rtems.org
> *Subject:* Re: [PATCH 1/2] dev/clock: Move bcm2835-system-timer driver to
> shared space
>
> One comment inline below.
>
> On Tue, Apr 9, 2024 at 10:02 AM Ning Yang wrote:
>
> This patch moves the bcm2835 system timer driver in the arm/raspberrypi
> directory to the shared directory.
>
> Made some changes in the include section to adapt to rpi4 BSP.
> ---
> .../clockdrv.c => shared/dev/clock/bcm2835-system-timer.c} | 7 +++
> spec/build/bsps/arm/raspberrypi/obj.yml| 2 +-
> 2 files changed, 8 insertions(+), 1 deletion(-)
> rename bsps/{arm/raspberrypi/clock/clockdrv.c =>
> shared/dev/clock/bcm2835-system-timer.c} (95%)
>
> diff --git a/bsps/arm/raspberrypi/clock/clockdrv.c
> b/bsps/shared/dev/clock/bcm2835-system-timer.c
> similarity index 95%
> rename from bsps/arm/raspberrypi/clock/clockdrv.c
> rename to bsps/shared/dev/clock/bcm2835-system-timer.c
> index 8d220d51ba..2725735860 100644
> --- a/bsps/arm/raspberrypi/clock/clockdrv.c
> +++ b/bsps/shared/dev/clock/bcm2835-system-timer.c
> @@ -22,7 +22,14 @@
> #include
> #include
> #include
> +
> +#if RTEMS_BSP == raspberrypi4b
> +#include
> +#define BCM2835_REG(addr) *(volatile uint32_t*)(addr)
> +#else
> #include
> +#endif /* RTEMS_BSP */
> +
>
>
> This change should really be in patch 2, but there is another issue with
> this change. This pattern is not used in existing code that I could find
> because it's fragile and introduces BSP-specific code into a shared driver
> that will need to be updated for every single BSP that eventually wants to
> use it. Either the RPi4 BSP should define BCM2835_REG as a 32bit register
> access for compatibility or this driver should have its register accesses
> renamed to something more generic such as PI32_REG which the RPi3 and RPi4
> BSPs can provide for usage with this driver.
>
> #include
>
> /* This is defined in ../../../shared/dev/clock/clockimpl.h */
> diff --git a/spec/build/bsps/arm/raspberrypi/obj.yml
> b/spec/build/bsps/arm/raspberrypi/obj.yml
> index ec5c82a8fb..ea370829df 100644
> --- a/spec/build/bsps/arm/raspberrypi/obj.yml
> +++ b/spec/build/bsps/arm/raspberrypi/obj.yml
> @@ -26,7 +26,6 @@ install:
>- bsps/arm/raspberrypi/include/bsp/vc.h
> links: []
> source:
> -- bsps/arm/raspberrypi/clock/clockdrv.c
> - bsps/arm/raspberrypi/console/console-config.c
> - bsps/arm/raspberrypi/console/fb.c
> - bsps/arm/raspberrypi/console/fbcons.c
> @@ -47,6 +46,7 @@ source:
> - bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c
> - bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
> - bsps/arm/shared/start/bsp-start-memcpy.S
> +- bsps/shared/dev/clock/bcm2835-system-timer.c
> - bsps/shared/dev/cpucounter/cpucounterfrequency.c
> - bsps/shared/dev/cpucounter/cpucounterread.c
> - bsps/shared/dev/getentropy/getentropy-cpucounter.c
> --
> 2.34.1
>
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>
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[PATCH] bsps/aarch64/raspberrypi: Add system timer support
The clock from the ARM timer is derived from the system clock. This clock can change dynamically e.g. if the system goes into reduced power or in low power mode. Thus the clock speed adapts to the overall system performance capabilities. For accurate timing it is recommended to use the system timers. if BSP_CLOCK_USE_SYSTEMTIMER = 1, use the System Timer, otherwise use the ARM Timer. --- .../aarch64/raspberrypi/include/bsp/bcm2711.h | 28 .../raspberrypi/include/bsp/raspberrypi.h | 43 +++ bsps/aarch64/raspberrypi/start/bspstartmmu.c | 8 spec/build/bsps/aarch64/raspberrypi/bsp4b.yml | 1 + spec/build/bsps/aarch64/raspberrypi/obj.yml | 3 ++ .../bsps/aarch64/raspberrypi/objclock.yml | 4 +- .../aarch64/raspberrypi/objsystemtimer.yml| 22 ++ .../aarch64/raspberrypi/optsystemtimer.yml| 24 +++ 8 files changed, 132 insertions(+), 1 deletion(-) create mode 100644 bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h create mode 100644 spec/build/bsps/aarch64/raspberrypi/objsystemtimer.yml create mode 100644 spec/build/bsps/aarch64/raspberrypi/optsystemtimer.yml diff --git a/bsps/aarch64/raspberrypi/include/bsp/bcm2711.h b/bsps/aarch64/raspberrypi/include/bsp/bcm2711.h index e6c77fa025..8707582ebb 100644 --- a/bsps/aarch64/raspberrypi/include/bsp/bcm2711.h +++ b/bsps/aarch64/raspberrypi/include/bsp/bcm2711.h @@ -11,6 +11,7 @@ /* * Copyright (C) 2022 Mohd Noor Aman * Copyright (C) 2023 Utkarsh Verma + * Copyright (C) 2024 Ning Yang * * * Redistribution and use in source and binary forms, with or without @@ -91,6 +92,27 @@ #define BCM2711_UART5_BASE (BCM2711_PL011_BASE + 0xa00) #define BCM2711_UART5_SIZE BCM2711_PL011_DEVICE_SIZE +/* System Timer */ +/** + * NOTE: The GPU uses Compare registers 0 and 2 for + * it's own RTOS. 1 and 3 are available for use in + * RTEMS. + */ +#define BCM2835_GPU_TIMER_BASE(BCM2711_PERIPHERAL_BASE + 0x200+ 0x3000) +#define BCM2835_GPU_TIMER_SIZE0x1C + +#define BCM2835_GPU_TIMER_CS (BCM2835_GPU_TIMER_BASE + 0x00) +#define BCM2835_GPU_TIMER_CS_M0 0x0001 +#define BCM2835_GPU_TIMER_CS_M1 0x0002 +#define BCM2835_GPU_TIMER_CS_M2 0x0004 +#define BCM2835_GPU_TIMER_CS_M3 0x0008 +#define BCM2835_GPU_TIMER_CLO (BCM2835_GPU_TIMER_BASE + 0x04) +#define BCM2835_GPU_TIMER_CHI (BCM2835_GPU_TIMER_BASE + 0x08) +#define BCM2835_GPU_TIMER_C0 (BCM2835_GPU_TIMER_BASE + 0x0C) +#define BCM2835_GPU_TIMER_C1 (BCM2835_GPU_TIMER_BASE + 0x10) +#define BCM2835_GPU_TIMER_C2 (BCM2835_GPU_TIMER_BASE + 0x14) +#define BCM2835_GPU_TIMER_C3 (BCM2835_GPU_TIMER_BASE + 0x18) + /* ARM Local */ #define BCM2711_ARM_LOCAL_BASE 0xff80LL #define BCM2711_ARM_LOCAL_SIZE 0x80 @@ -114,4 +136,10 @@ #define BCM2711_IRQ_AUX(BCM2711_IRQ_VC_PERIPHERAL_BASE + 29) #define BCM2711_IRQ_PL011_UART (BCM2711_IRQ_VC_PERIPHERAL_BASE + 57) +/* Interrupt Vectors: System Timer */ +#define BCM2835_IRQ_ID_GPU_TIMER_M0(BCM2711_IRQ_VC_PERIPHERAL_BASE + 0) +#define BCM2835_IRQ_ID_GPU_TIMER_M1(BCM2711_IRQ_VC_PERIPHERAL_BASE + 1) +#define BCM2835_IRQ_ID_GPU_TIMER_M2(BCM2711_IRQ_VC_PERIPHERAL_BASE + 2) +#define BCM2835_IRQ_ID_GPU_TIMER_M3(BCM2711_IRQ_VC_PERIPHERAL_BASE + 3) + #endif /* LIBBSP_AARCH64_RASPBERRYPI_BSP_BCM2711_H */ diff --git a/bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h b/bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h new file mode 100644 index 00..2e1c673bfb --- /dev/null +++ b/bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsAArch64RaspberryPi + * + * @brief RaspberryPi shared Register Definitions + */ + +/* + * Copyright (C) 2024 Ning Yang + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABI
[PATCH] dev/irq: Improve Doxgyen group assignments
Make the GIC interrupt controller support a subgroup of the generic interrupt
controller support.
---
bsps/aarch64/include/dev/irq/arm-gic-arch.h| 13 +++--
bsps/arm/include/dev/irq/arm-gic-arch.h| 13 +++--
bsps/include/dev/irq/arm-gic-irq.h | 15 ---
bsps/include/dev/irq/arm-gic-regs.h| 15 ---
bsps/include/dev/irq/arm-gic-tm27.h| 7 ---
bsps/include/dev/irq/arm-gic.h | 18 --
bsps/include/dev/irq/arm-gicv3.h | 13 +++--
bsps/shared/dev/irq/arm-gicv2-get-attributes.c | 5 +++--
bsps/shared/dev/irq/arm-gicv2-zynqmp.c | 6 --
bsps/shared/dev/irq/arm-gicv2.c| 5 +++--
bsps/shared/dev/irq/arm-gicv3.c| 13 +++--
11 files changed, 94 insertions(+), 29 deletions(-)
diff --git a/bsps/aarch64/include/dev/irq/arm-gic-arch.h
b/bsps/aarch64/include/dev/irq/arm-gic-arch.h
index 94b832c2c5..5ca2c7314e 100644
--- a/bsps/aarch64/include/dev/irq/arm-gic-arch.h
+++ b/bsps/aarch64/include/dev/irq/arm-gic-arch.h
@@ -3,9 +3,10 @@
/**
* @file
*
- * @ingroup RTEMSBSPsAArch64Shared
+ * @ingroup DevIRQGIC
*
- * @brief AArch64-specific ARM GICv3 handlers.
+ * @brief This header file provides interfaces of the ARM Generic Interrupt
+ * Controller (GIC) support specific to the AArch64 architecture.
*/
/*
@@ -46,6 +47,12 @@
extern "C" {
#endif
+/**
+ * @addtogroup DevIRQGIC
+ *
+ * @{
+ */
+
static inline uint32_t arm_interrupt_enable_interrupts(void)
{
uint32_t status = _CPU_ISR_Get_level();
@@ -72,6 +79,8 @@ static inline void
arm_interrupt_facility_set_exception_handler(void)
);
}
+/** @} */
+
#ifdef __cplusplus
}
#endif
diff --git a/bsps/arm/include/dev/irq/arm-gic-arch.h
b/bsps/arm/include/dev/irq/arm-gic-arch.h
index f2ea76f22f..f6c8b5d426 100644
--- a/bsps/arm/include/dev/irq/arm-gic-arch.h
+++ b/bsps/arm/include/dev/irq/arm-gic-arch.h
@@ -3,9 +3,10 @@
/**
* @file
*
- * @ingroup RTEMSBSPsARMShared
+ * @ingroup DevIRQGIC
*
- * @brief ARM-specific IRQ handlers.
+ * @brief This header file provides interfaces of the ARM Generic Interrupt
+ * Controller (GIC) support specific to the Arm architecture.
*/
/*
@@ -44,6 +45,12 @@
extern "C" {
#endif
+/**
+ * @addtogroup DevIRQGIC
+ *
+ * @{
+ */
+
static inline uint32_t arm_interrupt_enable_interrupts(void)
{
return _ARMV4_Status_irq_enable();
@@ -62,6 +69,8 @@ static inline void
arm_interrupt_facility_set_exception_handler(void)
*/
}
+/** @} */
+
#ifdef __cplusplus
}
#endif
diff --git a/bsps/include/dev/irq/arm-gic-irq.h
b/bsps/include/dev/irq/arm-gic-irq.h
index 518256ad2b..25870fec07 100644
--- a/bsps/include/dev/irq/arm-gic-irq.h
+++ b/bsps/include/dev/irq/arm-gic-irq.h
@@ -1,11 +1,12 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
- * @file
+ * @file
*
- * @ingroup arm_gic
+ * @ingroup DevIRQGIC
*
- * @brief ARM GIC IRQ
+ * @brief This header file provides interfaces of the ARM Generic Interrupt
+ * Controller (GIC) support.
*/
/*
@@ -43,6 +44,12 @@
extern "C" {
#endif /* __cplusplus */
+/**
+ * @addtogroup DevIRQGIC
+ *
+ * @{
+ */
+
#define ARM_GIC_IRQ_SGI_0 0
#define ARM_GIC_IRQ_SGI_1 1
#define ARM_GIC_IRQ_SGI_2 2
@@ -98,6 +105,8 @@ uint32_t arm_gic_irq_processor_count(void);
void arm_gic_irq_initialize_secondary_cpu(void);
#endif
+/** @} */
+
#ifdef __cplusplus
}
#endif /* __cplusplus */
diff --git a/bsps/include/dev/irq/arm-gic-regs.h
b/bsps/include/dev/irq/arm-gic-regs.h
index 097ff67c13..c03a7a7a07 100644
--- a/bsps/include/dev/irq/arm-gic-regs.h
+++ b/bsps/include/dev/irq/arm-gic-regs.h
@@ -1,11 +1,12 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
- * @file
+ * @file
*
- * @ingroup arm_gic
+ * @ingroup DevIRQGIC
*
- * @brief ARM GIC Register definitions
+ * @brief This header file provides interfaces of the ARM Generic Interrupt
+ * Controller (GIC) memory-mapped registers.
*/
/*
@@ -38,6 +39,12 @@
#include
+/**
+ * @addtogroup DevIRQGIC
+ *
+ * @{
+ */
+
typedef struct {
uint32_t iccicr;
#define GIC_CPUIF_ICCICR_CBPR BSP_BIT32(4)
@@ -225,4 +232,6 @@ typedef struct {
uint32_t icspigrpmodr[64];
} gic_sgi_ppi;
+/** @} */
+
#endif /* LIBBSP_ARM_SHARED_ARM_GIC_REGS_H */
diff --git a/bsps/include/dev/irq/arm-gic-tm27.h
b/bsps/include/dev/irq/arm-gic-tm27.h
index 6baab7a45c..38e3ecf938 100644
--- a/bsps/include/dev/irq/arm-gic-tm27.h
+++ b/bsps/include/dev/irq/arm-gic-tm27.h
@@ -1,11 +1,12 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
- * @file
+ * @file
*
- * @ingroup arm_gic
+ * @ingroup DevIRQGIC
*
- * @brief ARM GIC TM27 Support
+ * @brief This header file provides the TM27 support for the ARM Generic
+ * Interrupt Controller (GIC).
*/
/*
diff --git a/bsps/include/dev/irq/arm-gic.h b/bsps/include/dev/irq/arm-gic.h
index 73c9a688d5..4e418de68f 100644
--- a/bsps/include/dev/irq/arm-gic.h
+++ b/bsps/include/de
