date:20231012

Re: [PATCH] sparc: Fix stack corruption

2023-10-12 Thread Martin Åberg


Hello Sebastian,

I have reviewed the ticket and the patch. The fix is OK.

--
Best regards,

Martin Åberg
Software Engineer
Frontgrade Gaisler
martin.ab...@gaisler.com

Frontgrade Gaisler AB, Kungsgatan 12, SE-411 19 GÖTEBORG, Sweden.
+46 (0) 31 775 8650, www.gaisler.com



On 2023-09-20 09:38, Sebastian Huber wrote:

Fix a potential stack corruption in uniprocessor configurations during
start multitasking .

The system initialization uses the interrupt stack.  A first level
interrupt shall never interrupt a context which uses the interrupt
stack.  Such a use would lead to stack corruption and undefined system
behaviour.  Unfortunately, in uniprocessor configurations this was the
case.  Multiprocessing is started using _CPU_Context_restore().  The
caller of this function (_Thread_Start_multitasking()) uses the
interrupt stack.  Later we have in cpukit/score/cpu/sparc/cpu_asm.S:

 mov %g1, %psr ! restore status register and
   !  ENABLE TRAPS 

 ld  [%o1 + G5_OFFSET], %g5! restore the global registers
 ld  [%o1 + G7_OFFSET], %g7

 ! Load thread specific ISR dispatch prevention flag
 ld  [%o1 + ISR_DISPATCH_DISABLE_STACK_OFFSET], %o2
 ! Store it to memory later to use the cycles

 ldd [%o1 + L0_OFFSET], %l0! restore the local registers
 ldd [%o1 + L2_OFFSET], %l2
 ldd [%o1 + L4_OFFSET], %l4
 ldd [%o1 + L6_OFFSET], %l6

 ! Now restore thread specific ISR dispatch prevention flag
 st  %o2, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]

 ldd [%o1 + I0_OFFSET], %i0! restore the input registers
 ldd [%o1 + I2_OFFSET], %i2
 ldd [%o1 + I4_OFFSET], %i4
 ldd [%o1 + I6_FP_OFFSET], %i6

 ldd [%o1 + O6_SP_OFFSET], %o6 ! restore the output registers

Between the ENABLE TRAPS and the restore of the output registers, we
still use the stack of the caller and interrupts may be enabled.  If an
interrupt happens in this code block, the interrupt stack is
concurrently used which may lead to a crash.

Fix this by adding a new function _SPARC_Start_multiprocessing() for
uniprocessor configurations.  This function first sets the stack pointer
to use the stack of the heir thread.

Close #4955.
---
  cpukit/score/cpu/sparc/cpu_asm.S  | 29 ++-
  .../score/cpu/sparc/include/rtems/score/cpu.h | 19 
  2 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/cpukit/score/cpu/sparc/cpu_asm.S b/cpukit/score/cpu/sparc/cpu_asm.S
index 287c2c4cd9..fd7186b499 100644
--- a/cpukit/score/cpu/sparc/cpu_asm.S
+++ b/cpukit/score/cpu/sparc/cpu_asm.S
@@ -246,6 +246,14 @@ done_flushing:
  mov %g1, %psr ! restore status register and
!  ENABLE TRAPS 
  
+/*

+ * WARNING: This code does not run with the restored stack pointer.  In
+ * SMP configurations, it uses a processor-specific stack.  In
+ * uniprocessor configurations, it uses the stack of the caller.  In
+ * this case, the caller shall ensure that it is not the interrupt
+ * stack (which is also the system initialization stack).
+ */
+
  ld  [%o1 + G5_OFFSET], %g5! restore the global registers
  ld  [%o1 + G7_OFFSET], %g7
  
@@ -266,7 +274,9 @@ done_flushing:

  ldd [%o1 + I4_OFFSET], %i4
  ldd [%o1 + I6_FP_OFFSET], %i6
  
-ldd [%o1 + O6_SP_OFFSET], %o6 ! restore the output registers

+ldd [%o1 + O6_SP_OFFSET], %o6 ! restore the non-volatile output
+  ! registers (stack pointer,
+  ! link register)
  
  jmp %o7 + 8   ! return

  nop   ! delay slot
@@ -325,6 +335,23 @@ SYM(_CPU_Context_restore):
  ba  SYM(_CPU_Context_restore_heir)
  mov %i0, %o1  ! in the delay slot
  
+#if !defined(RTEMS_SMP)

+.align 4
+PUBLIC(_SPARC_Start_multitasking)
+SYM(_SPARC_Start_multitasking):
+/*
+ * Restore the stack pointer right now, so that the window flushing and
+ * interrupts during _CPU_Context_restore_heir() use the stack of the
+ * heir thread.  This is crucial for the interrupt handling to prevent
+ * a concurrent use of the interrupt stack (which is also the system
+ * initialization stack).
+ */
+ld  [%o0 + O6_SP_OFFSET], %o6
+
+ba  SYM(_CPU_Context_restore)
+ nop
+#endif
+
  /*
   *  void _SPARC_Interrupt_trap()
   *
diff --git a/cpukit/score/cpu/sparc/include/rtems/score/cpu.h 
b/cpukit/score/cpu/sparc/include/rtems/score/cpu.h
index 2021b108db..a21c

Re: [PATCH] doxygen: Replace and move main page

2023-10-12 Thread Sebastian Huber


Hello Joel,

thanks for having a look at it. I used the features list here as a 
template for the mainpage:


https://docs.rtems.org/branches/master/user/overview/index.html#features

Maybe it needs to be updated as well.

On 10.10.23 20:43, Joel Sherrill wrote:
Sorry. Not sure how this kept slipping through the cracks.  The 13 
September ping did coincide with me being on a trip and then sick.


This is the only revision I see in my inbox. There is an email which 
says "how about this version?" but I don't see anything on it.


A few comments inline.

On Fri, Jul 28, 2023 at 9:37 AM Sebastian Huber 
> wrote:


Replace the main page with a high level description of the RTEMS feature
set similar to:

https://docs.rtems.org/branches/master/user/overview/index.html#features 


The replaced content can be found in the RTEMS Classic API Guide:

https://docs.rtems.org/branches/master/c-user/overview.html


https://docs.rtems.org/branches/master/c-user/key_concepts.html


Update #3705.
---
v2:

* Add OAR copyright.

* Move to cpukit/doxygen/mainpage.h

* Not not install

  cpukit/doxygen/mainpage.h             | 204 ++
  cpukit/include/rtems/rtems/mainpage.h | 951 --
  spec/build/cpukit/librtemscpu.yml     |   1 -
  3 files changed, 204 insertions(+), 952 deletions(-)
  create mode 100644 cpukit/doxygen/mainpage.h
  delete mode 100644 cpukit/include/rtems/rtems/mainpage.h

diff --git a/cpukit/doxygen/mainpage.h b/cpukit/doxygen/mainpage.h
new file mode 100644
index 00..ce341e0ffd
--- /dev/null
+++ b/cpukit/doxygen/mainpage.h
@@ -0,0 +1,204 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSImplDoxygen
+ *
+ * @brief This file exists to provide a top level description of
RTEMS for
+ *   Doxygen.
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH & Co. KG
+ * Copyright (C) 1989, 2014 On-Line Applications Research
Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer
in the
+ *    documentation and/or other materials provided with the
distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @mainpage
+ *
+ * The Real-Time Executive for Multiprocessor Systems (RTEMS) is a
+ * multi-threaded, single address-space, real-time operating system
with no
+ * kernel-space/user-space separation.  It is capable to operate in
an SMP
+ * configuration providing a state of the art feature set.
+ *
+ * RTEMS and all third-party software distributed with RTEMS which
may be
+ * linked to the application is licensed under permissive open
source licenses.
+ * This means that the licenses do not properagate to the
application software.


properagate -> propagate

+ * Most of the original RTEMS code is now under the [BSD 2-Clause
+ * license](https://git.rtems.org/rtems/tree/LICENSE.BSD-2-Clause
).  Legacy


GPLv2 does not imply legacy. Some code in RTEMS is under a legacy license.


Which alternative wording would you use?



+ * code of RTEMS is under a [modified GPL 2.0 or later license with an
+ * exception for static
linking](https://git.rtems.org/rtems/tree/LICENSE
>).
+ * It e

Re: [PATCH] sparc: Fix stack corruption

2023-10-12 Thread Sebastian Huber


On 12.10.23 11:59, Martin Åberg wrote:

I have reviewed the ticket and the patch. The fix is OK.


Thanks for the review, I checked it in.

--
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Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
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[PATCH v2 1/4] bsps/clock: Import Xilinx TTC hardware definitions

2023-10-12 Thread Kinsey Moore

This imports the TTC hardware definitions for the triple timer counters
on various Xilinx platforms. This was imported as specified in the
VERSION file in this commit.
---
 bsps/include/dev/clock/VERSION |  24 
 bsps/include/dev/clock/xttcps_hw.h | 207 +
 2 files changed, 231 insertions(+)
 create mode 100644 bsps/include/dev/clock/VERSION
 create mode 100644 bsps/include/dev/clock/xttcps_hw.h

diff --git a/bsps/include/dev/clock/VERSION b/bsps/include/dev/clock/VERSION
new file mode 100644
index 00..1ccbe7c216
--- /dev/null
+++ b/bsps/include/dev/clock/VERSION
@@ -0,0 +1,24 @@
+The information in this file describes the source of
+bsps/include/dev/clock/xttcps_hw.h.
+
+Import from:
+
+https://github.com/Xilinx/embeddedsw.git
+
+commit 5330a64c8efd14f0eef09befdbb8d3d738c33ec2
+Refs: 
+Author: Nicole Baze 
+AuthorDate: Mon Oct 3 13:27:19 2022 -0700
+Commit: Siva Addepalli 
+CommitDate: Fri Oct 7 10:26:16 2022 +0530
+
+xilpm: versal: server: Fix bug in AIE2 zeroization
+
+There is a bug in AIE2 zeriozation function when polling for memory
+zeroization complete. Currently the entire memory register is being
+checked against zero but instead we need to check the bits specific
+to the memory tiles. This patch updates the zeroization check by
+adding a mask so that only the desired bits are checked for zero.
+
+Signed-off-by: Nicole Baze 
+Acked-by: Jesus De Haro 
diff --git a/bsps/include/dev/clock/xttcps_hw.h 
b/bsps/include/dev/clock/xttcps_hw.h
new file mode 100644
index 00..0559c4a00c
--- /dev/null
+++ b/bsps/include/dev/clock/xttcps_hw.h
@@ -0,0 +1,207 @@
+/**
+* Copyright (C) 2010 - 2021 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+**/
+
+/*/
+/**
+*
+* @file xttcps_hw.h
+* @addtogroup ttcps_v3_15
+* @{
+*
+* This file defines the hardware interface to one of the three timer counters
+* in the Ps block.
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   WhoDate Changes
+* - --  -
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.5   srm10/06/17 Updated XTTCPS_COUNT_VALUE_MASK,
+*   XTTCPS_INTERVAL_VAL_MASK, XTTCPS_MATCH_MASK macros to
+*   mask 16 bit values for zynq and 32 bit values for
+*   zynq ultrascale+mpsoc "
+* 
+*
+**/
+
+#ifndef XTTCPS_HW_H/* prevent circular inclusions */
+#define XTTCPS_HW_H/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Include Files */
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/** Constant Definitions */
+/*
+ * Flag for a9 processor
+ */
+ #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+ #define ARMA9
+ #endif
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of the device.
+ *
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_OFFSET0xU  /**< Clock Control 
Register */
+#define XTTCPS_CNT_CNTRL_OFFSET0x000CU  /**< Counter 
Control Register*/
+#define XTTCPS_COUNT_VALUE_OFFSET  0x0018U  /**< Current Counter Value 
*/
+#define XTTCPS_INTERVAL_VAL_OFFSET 0x0024U  /**< Interval Count Value 
*/
+#define XTTCPS_MATCH_0_OFFSET  0x0030U  /**< Match 1 value */
+#define XTTCPS_MATCH_1_OFFSET  0x003CU  /**< Match 2 value */
+#define XTTCPS_MATCH_2_OFFSET  0x0048U  /**< Match 3 value */
+#define XTTCPS_ISR_OFFSET  0x0054U  /**< Interrupt 
Status Register */
+#define XTTCPS_IER_OFFSET  0x0060U  /**< Interrupt 
Enable Register */
+/* @} */
+
+/** @name Clock Control Register
+ * Clock Control Register definitions
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_PS_EN_MASK0x0001U  /**< Prescale 
enable */
+#define XTTCPS_CLK_CNTRL_PS_VAL_MASK   0x001EU  /**< Prescale value */
+#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT   1U  /**< Prescale 
shift */
+#define XTTCPS_CLK_CNTRL_PS_DISABLE16U  /**< 
Prescale disable */
+#define XTTCPS_CLK_CNTRL_SRC_MASK  0x0020U  /**< Clock source 
*/
+#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x0040U  /**< External Clock edge */
+/* @} */
+
+/** @name Counter Control Register
+ * Counter Control Register definitions
+ * @{
+ */
+#define XTTCPS_CNT_CNTRL_DIS_MASK  0x0001U /**< Disable the 
counter */
+#

[PATCH v2 0/4] Add ZynqMP Cortex-R5 BSP

2023-10-12 Thread Kinsey Moore

Changes from v1 (originally submitted by Philip Kirkpatrick):
Refactoring:
* import Xilinx code before modification
* better use the existing Xilinx support code
Other:
* An additional patch to add cache support (also from Philip) has been
  integrated and refactored

This has been tested on Xilinx's QEMU with Xilinx's device tree
definitions using the following command line options to QEMU:
-no-reboot -nographic -M arm-generic-fdt -serial null -serial mon:stdio \
-device loader,file=,cpu-num=4 \
-device loader,addr=0xff5e023c,data=0x80088fde,data-len=4 \
-device loader,addr=0xff9a,data=0x8218,data-len=4 \
-hw-dtb /LATEST/SINGLE_ARCH/board-zynqmp-zcu102.dtb \
-m 4096 -display none

hello.exe and ts-validation-cache.exe operated as expected. Ticker
produced output, but the timing and content was incorrect on QEMU.


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[PATCH v2 3/4] bsps/xil: Adjust Xilinx support code for Cortex-R5

2023-10-12 Thread Kinsey Moore

This fixes some issues in the Xilinx support code that are critical to
support the Cortex-R5F cores present in my Xilinx SoCs. The imported
Cortex-R5 xil_cache.c matches the existing information in
bsps/shared/xil/VERSION.
---
 bsps/include/xil/arm/ARMv8/32bit/xil_system.h | 37 ++
 bsps/include/xil/arm/ARMv8/64bit/xil_system.h | 37 ++
 bsps/include/xil/arm/cortexa9/xil_system.h| 38 +++
 bsps/include/xil/arm/cortexr5/xil_system.h| 38 +++
 bsps/include/xil/microblaze/xil_system.h  | 37 ++
 bsps/include/xil/xdebug.h |  2 +
 bsps/shared/xil/{ => arm/ARMv8}/xil_cache.c   |  0
 bsps/shared/xil/arm/cortexr5/xil_mpu.c|  4 ++
 spec/build/bsps/objxilinxsupport.yml  |  1 -
 spec/build/bsps/objxilinxsupportilp32.yml |  3 +-
 spec/build/bsps/objxilinxsupportlp64.yml  |  3 +-
 spec/build/bsps/objxilinxsupportr5.yml|  5 ++-
 12 files changed, 201 insertions(+), 4 deletions(-)
 create mode 100644 bsps/include/xil/arm/ARMv8/32bit/xil_system.h
 create mode 100644 bsps/include/xil/arm/ARMv8/64bit/xil_system.h
 create mode 100644 bsps/include/xil/arm/cortexa9/xil_system.h
 create mode 100644 bsps/include/xil/arm/cortexr5/xil_system.h
 create mode 100644 bsps/include/xil/microblaze/xil_system.h
 create mode 100644 bsps/include/xil/xdebug.h
 rename bsps/shared/xil/{ => arm/ARMv8}/xil_cache.c (100%)

diff --git a/bsps/include/xil/arm/ARMv8/32bit/xil_system.h 
b/bsps/include/xil/arm/ARMv8/32bit/xil_system.h
new file mode 100644
index 00..7269e5c8d9
--- /dev/null
+++ b/bsps/include/xil/arm/ARMv8/32bit/xil_system.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ *  COPYRIGHT (c) 2023.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_SHARED_XIL_SYSTEM_H
+#define LIBBSP_SHARED_XIL_SYSTEM_H
+
+/*
+ * This file defines anything necessary for the Xilinx support infrastructure 
to
+ * function properly on a particular platform.
+ */
+
+#endif
diff --git a/bsps/include/xil/arm/ARMv8/64bit/xil_system.h 
b/bsps/include/xil/arm/ARMv8/64bit/xil_system.h
new file mode 100644
index 00..7269e5c8d9
--- /dev/null
+++ b/bsps/include/xil/arm/ARMv8/64bit/xil_system.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ *  COPYRIGHT (c) 2023.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THI

[PATCH v2 2/4] bsps/xil: Import Xilinx Cortex-R5 support

2023-10-12 Thread Kinsey Moore

This imports Xilinx support code for the MPU and cache on Cortex-R5
cores. This was imported as specified in bsps/shared/xil/VERSION.
---
 bsps/include/xil/arm/cortexr5/xil_mpu.h  | 117 +
 bsps/shared/xil/arm/cortexr5/xil_cache.c | 561 
 bsps/shared/xil/arm/cortexr5/xil_mpu.c   | 641 +++
 3 files changed, 1319 insertions(+)
 create mode 100644 bsps/include/xil/arm/cortexr5/xil_mpu.h
 create mode 100644 bsps/shared/xil/arm/cortexr5/xil_cache.c
 create mode 100644 bsps/shared/xil/arm/cortexr5/xil_mpu.c

diff --git a/bsps/include/xil/arm/cortexr5/xil_mpu.h 
b/bsps/include/xil/arm/cortexr5/xil_mpu.h
new file mode 100644
index 00..af3d52d795
--- /dev/null
+++ b/bsps/include/xil/arm/cortexr5/xil_mpu.h
@@ -0,0 +1,117 @@
+/**
+* Copyright (c) 2014 - 2022 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+**/
+
+/*/
+/**
+* @file xil_mmu.h
+*
+* @addtogroup r5_mpu_apis Cortex R5 Processor MPU specific APIs
+*
+* MPU functions provides access to MPU operations such as enable MPU, disable
+* MPU and set attribute for section of memory.
+* Boot code invokes Init_MPU function to configure the MPU. A total of 10 MPU
+* regions are allocated with another 6 being free for users. Overview of the
+* memory attributes for different MPU regions is as given below,
+*
+*|   | Memory Range| Attributes of MPURegion   
  |
+*|---|-|-|
+*| DDR   | 0x - 0x7FFF | Normal write-back 
Cacheable |
+*| PL| 0x8000 - 0xBFFF | Strongly Ordered  
  |
+*| QSPI  | 0xC000 - 0xDFFF | Device Memory 
  |
+*| PCIe  | 0xE000 - 0xEFFF | Device Memory 
  |
+*| STM_CORESIGHT | 0xF800 - 0xF8FF | Device Memory 
  |
+*| RPU_R5_GIC| 0xF900 - 0xF90F | Device memory 
  |
+*| FPS   | 0xFD00 - 0xFDFF | Device Memory 
  |
+*| LPS   | 0xFE00 - 0x | Device Memory 
  |
+*| OCM   | 0xFFFC - 0x | Normal write-back 
Cacheable |
+*
+*
+* @note
+* For a system where DDR is less than 2GB, region after DDR and before PL is
+* marked as undefined in translation table. Memory range 0xFE00-0xFEFF 
is
+* allocated for upper LPS slaves, where as memory region 0xFF00-0x 
is
+* allocated for lower LPS slaves.
+*
+* @{
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date Changes
+* -   ---
+* 5.00  pkp  02/10/14 Initial version
+* 6.4   asa  08/16/17 Added many APIs for MPU access to make MPU usage
+*user-friendly. The APIs added are: 
Xil_UpdateMPUConfig,
+*Xil_GetMPUConfig, 
Xil_GetNumOfFreeRegions,
+*Xil_GetNextMPURegion, 
Xil_DisableMPURegionByRegNum,
+*Xil_GetMPUFreeRegMask, 
Xil_SetMPURegionByRegNum, and
+*Xil_InitializeExistingMPURegConfig.
+*Added a new array of structure of 
type XMpuConfig to
+*represent the MPU configuration table.
+* 7.7  sk   01/10/22 Modify Xil_SetTlbAttributes function argument name to fix
+*misra_c_2012_rule_8_3 violation.
+* 
+*
+
+*
+*
+**/
+/**
+ *@cond nocomments
+ */
+
+#ifndef XIL_MPU_H
+#define XIL_MPU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#include "xil_types.h"
+/* Include Files */
+
+/* Macros (Inline Functions) Definitions */
+#define MPU_REG_DISABLED   0U
+#define MPU_REG_ENABLED1U
+#define MAX_POSSIBLE_MPU_REGS  16U
+/ Type Definitions ***/
+struct XMpuConfig{
+   u32 RegionStatus; /* Enabled or disabled */
+   INTPTR BaseAddress;/* MPU region base address */
+   u64 Size; /* MPU region size address */
+   u32 Attribute; /* MPU region size attribute */
+};
+
+typedef struct XMpuConfig XMpu_Config[MAX_POSSIBLE_MPU_REGS];
+
+extern XMpu_Config Mpu_Config;
+/** Constant Definitions */
+
+/** Variable Definitions */
+
+/** Function Prototypes

[PATCH v2 4/4] bsps/arm: Add BSP for ZynqMP RPU

2023-10-12 Thread Kinsey Moore

From: Philip Kirkpatrick 

---
 .../console/console-config.c  | 129 ++
 bsps/arm/xilinx-zynqmp-rpu/include/bsp.h  |  96 
 bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h  |  65 +
 bsps/arm/xilinx-zynqmp-rpu/include/tm27.h |  54 +
 bsps/arm/xilinx-zynqmp-rpu/start/bspreset.c   |  43 
 bsps/arm/xilinx-zynqmp-rpu/start/bspstart.c   |  48 
 .../xilinx-zynqmp-rpu/start/bspstarthooks.c   |  66 +
 .../arm/xilinx-zynqmp-rpu/start/bspstartmpu.c | 142 +++
 bsps/include/dev/clock/xttcps_hw.h|   3 +
 bsps/include/peripheral_maps/xilinx_zynqmp.h  | 118 +
 bsps/shared/dev/clock/xil-ttc.c   | 229 ++
 spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml |  21 ++
 .../arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml   |  95 
 .../bsps/arm/xilinx-zynqmp-rpu/linkcmds.yml   |  46 
 .../arm/xilinx-zynqmp-rpu/optclkfastidle.yml  |  21 ++
 .../bsps/arm/xilinx-zynqmp-rpu/optclkuart.yml |  17 ++
 .../bsps/arm/xilinx-zynqmp-rpu/optconirq.yml  |  16 ++
 .../bsps/arm/xilinx-zynqmp-rpu/optint0len.yml |  18 ++
 .../bsps/arm/xilinx-zynqmp-rpu/optint0ori.yml |  18 ++
 .../bsps/arm/xilinx-zynqmp-rpu/optint1len.yml |  18 ++
 .../bsps/arm/xilinx-zynqmp-rpu/optint1ori.yml |  18 ++
 .../arm/xilinx-zynqmp-rpu/optnocachelen.yml   |  19 ++
 .../arm/xilinx-zynqmp-rpu/optprocunitrpu.yml  |  17 ++
 .../bsps/arm/xilinx-zynqmp-rpu/optramlen.yml  |  21 ++
 .../bsps/arm/xilinx-zynqmp-rpu/optramori.yml  |  19 ++
 .../arm/xilinx-zynqmp-rpu/optresetvec.yml |  16 ++
 spec/build/bsps/objxilinxsupportr5.yml|   3 +-
 spec/build/bsps/optxilsupportpath.yml |   3 +-
 28 files changed, 1377 insertions(+), 2 deletions(-)
 create mode 100644 bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
 create mode 100644 bsps/arm/xilinx-zynqmp-rpu/include/bsp.h
 create mode 100644 bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h
 create mode 100644 bsps/arm/xilinx-zynqmp-rpu/include/tm27.h
 create mode 100644 bsps/arm/xilinx-zynqmp-rpu/start/bspreset.c
 create mode 100644 bsps/arm/xilinx-zynqmp-rpu/start/bspstart.c
 create mode 100644 bsps/arm/xilinx-zynqmp-rpu/start/bspstarthooks.c
 create mode 100644 bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c
 create mode 100644 bsps/include/peripheral_maps/xilinx_zynqmp.h
 create mode 100644 bsps/shared/dev/clock/xil-ttc.c
 create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/abi.yml
 create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/bspmercuryxu5.yml
 create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/linkcmds.yml
 create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkfastidle.yml
 create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optclkuart.yml
 create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optconirq.yml
 create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0len.yml
 create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optint0ori.yml
 create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1len.yml
 create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optint1ori.yml
 create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optnocachelen.yml
 create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optprocunitrpu.yml
 create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optramlen.yml
 create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optramori.yml
 create mode 100644 spec/build/bsps/arm/xilinx-zynqmp-rpu/optresetvec.yml

diff --git a/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c 
b/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
new file mode 100644
index 00..f52e008f2b
--- /dev/null
+++ b/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
@@ -0,0 +1,129 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2013, 2017 embedded brains GmbH
+ *
+ * Copyright (C) 2019 DornerWorks
+ *
+ * Written by Jeff Kubascik 
+ *and Josh Whitehead 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTI

[RSB PATCH 2/5] rtems/kernel: Update to latest

2023-10-12 Thread chrisj

From: Chris Johns 

- libdl: fix TLS in base image
- bsps/xnandpsu: fixes
- cpukit/jffs2: avoid dead lock
- bsps/imxrt: enable USB and fix PHY clock enable
- bsps/stm32h7: update STM32 H7 HAL
---
 rtems/config/tools/rtems-kernel-6.cfg | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/rtems/config/tools/rtems-kernel-6.cfg 
b/rtems/config/tools/rtems-kernel-6.cfg
index c9c884f..02b66b6 100644
--- a/rtems/config/tools/rtems-kernel-6.cfg
+++ b/rtems/config/tools/rtems-kernel-6.cfg
@@ -2,10 +2,10 @@
 # RTEMS 6
 #
 
-%define rtems_kernel_version c1d9dcbbb2a436256b49d9a0c322c78261509264
+%define rtems_kernel_version 25a4dff56ef48dd9eb646558404b55a0555a87f4
 
 %hash sha512 rtems-kernel-%{rtems_kernel_version}.tar.bz2 \
-   
dH0PgnSQ1k6pTCP/NhIgWzhDjHqFuLI03RBhbjaRFvRs5CUbZIG+x8opTb13czga/cUhOBd9JC7x557FkX0seA==
+   
CKj52ct4Bz3XrktSajwH1NsNrFX06VCEpmMHmeNwsseR+TWan9Pxsr8s/n2u8CdhjKfxztbrVB34NN8TCq8lkQ==
 #
 # The RTEMS build instructions.
 #
-- 
2.31.1

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[RSB PATCH 1/5] rtems/tools: Update to latest

2023-10-12 Thread chrisj

From: Chris Johns 

Minor fix in rtems-test
---
 rtems/config/tools/rtems-tools-6.cfg | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/rtems/config/tools/rtems-tools-6.cfg 
b/rtems/config/tools/rtems-tools-6.cfg
index 9632d5b..859c297 100644
--- a/rtems/config/tools/rtems-tools-6.cfg
+++ b/rtems/config/tools/rtems-tools-6.cfg
@@ -10,14 +10,14 @@
  %define rtems_tools_source rtems-tools-%{rtems_tools_version}
  %define rtems_tools_ext xz
 %else
- %define rtems_tools_version eda9325e583f761c53ee3db83124cc77cb4fefb5
+ %define rtems_tools_version 7dc34d2cabf5e9f77b6a9d035b01a75a6f593044
  %define rtems_tools_ext bz2
 %endif
 
 %define rtems_tools_source rtems-tools-%{rtems_tools_version}
 %source set rtems-tools 
https://git.rtems.org/rtems-tools/snapshot/%{rtems_tools_source}.tar.%{rtems_tools_ext}
 %hash   sha512 rtems-tools-%{rtems_tools_version}.tar.bz2 \
-   
kdrwOv0iUKYjWud2g/9aSnduIniNWnQKry04zwKEiwlKdg1KnMhGu4b0mpQD2PnsYxGha/ksPEnHLPnahQTarg==
+   
I8F4RkorMvfM9OUuS6hRfAEjxMydtE6sHTjnTzpek854caQAC2eHN2Hqi6HIN/9zXEWA7YeFgNsYdJsBsA5Hcg==
 
 #
 # Optionally enable/disable building the RTEMS Tools via the command line.
-- 
2.31.1

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[RSB PATCH 4/5] rtems/net-services: Update to latest

2023-10-12 Thread chrisj

From: Chris Johns 

- Updates for the RTEMS test changes
---
 rtems/config/net/net-services-1.cfg | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/rtems/config/net/net-services-1.cfg 
b/rtems/config/net/net-services-1.cfg
index bf1bdc8..cf17227 100644
--- a/rtems/config/net/net-services-1.cfg
+++ b/rtems/config/net/net-services-1.cfg
@@ -9,9 +9,9 @@
 #
 # Net Services Version
 #
-%define rtems_net_services_version fe0706060e5687a99c01d155e05d25bc34915ae1
+%define rtems_net_services_version 1651ac768f744725708c4328745665e1e7fa3c26
 %hash sha512 rtems-net-services-%{rtems_net_services_version}.tar.bz2 \
-   
5R/rhW3Supzw7KvDdkVYrWt3y3mxZ8hubwA8HpWtAZosWVlEauGvUpCfh1CthrHKHJ6uW1NpmewoAaZ9T25jsA==
+   
+czrODTpJF+nvMF4TFQFi3qn3k+X/N4JnxHFChrWGXAnaBQayjEkSNObhmETG3qe/ET8dhXHwJs/1A3A7e3uLA==
 
 %define rtems_waf_version 68654b4f995382765605dc16917baad4bdbf7f7c
 %hash sha512 rtems-waf-%{rtems_waf_version}.tar.bz2 \
-- 
2.31.1

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[RSB PATCH 3/5] rtems/libbsd: Update to latest

2023-10-12 Thread chrisj

From: Chris Johns 

- Pick up fixes to x86 (i368) bus space usage in kernel DMA
---
 rtems/config/tools/rtems-libbsd-6.cfg | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/rtems/config/tools/rtems-libbsd-6.cfg 
b/rtems/config/tools/rtems-libbsd-6.cfg
index c89b5eb..3bb1db7 100644
--- a/rtems/config/tools/rtems-libbsd-6.cfg
+++ b/rtems/config/tools/rtems-libbsd-6.cfg
@@ -3,9 +3,9 @@
 #
 
 #  branch: 6-freebsd-12
-%define rtems_libbsd_version a0d36f58fd7587c14b82044f49735ee5aca152f2
+%define rtems_libbsd_version 1524f95e93a0e0ff85d676d214e0e57cac44e4f5
 %hash sha512 rtems-libbsd-%{rtems_libbsd_version}.tar.bz2 \
-  
E17YUAzCenQVp2t9IeGp0rRBjSr8/O8PCkF50T5gQ5vfyKttlrayqIbbOatcoVrqAN7IY4qpfazRYS4UF+jEKg==
+  
QiNVx1kFPcX9tmkY2mdWO2gb/t32J+AJkXOBAkyjfsaUuvBz43oMeOrpBFJuuix6eTmmukSzAulUCLdqBJlAWQ==
 %define rtems_waf_version ad08908c452c6a9bbb3bf7bbbcc9fc03fe46cc7f
 %hash sha512 rtems-waf-%{rtems_waf_version}.tar.bz2 \
   
EyuEit0DsAR1gK9Ki1sjl416PFgFe7dcggH3H/hmdAPmMjEIIdX7TVOTDgOIK1Pt0DW6lZ9NcW7O87GZFyy8hg==
-- 
2.31.1

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[RSB PATCH 5/5] rtems/net-legacy: Update to latest

2023-10-12 Thread chrisj

From: Chris Johns 

Pick up the test printer header change
---
 rtems/config/tools/rtems-net-legacy-6.cfg | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/rtems/config/tools/rtems-net-legacy-6.cfg 
b/rtems/config/tools/rtems-net-legacy-6.cfg
index 559ec01..d5ac842 100644
--- a/rtems/config/tools/rtems-net-legacy-6.cfg
+++ b/rtems/config/tools/rtems-net-legacy-6.cfg
@@ -3,9 +3,9 @@
 #
 
 #  branch: main
-%define rtems_net_version 3a83bcef4bd62fda5c0f9c94dd649fc32d962ab2
+%define rtems_net_version a1e5d91c818d0881293c3c9e7d549816d34f6c77
 %hash sha512 rtems-net-legacy-%{rtems_net_version}.tar.bz2 \
-   
ANUrgSU3YRAnbEM/9wL5R4LrRCcyDYZz9KbRhTxnNYvUPjrfNgO+bM1qEYtJI6qUxvlKZYkVIkeOKxsAtjj1/A==
+   
wM9thMsQQdhtNVBV+FnnE/YS+2r+N7rYLsmCUMs4zQIgQ/bqhg4Sk2nkgse9NBs/gXTeCzzwG3/BTH6eQIYjBg==
 %define rtems_waf_version 68654b4f995382765605dc16917baad4bdbf7f7c
 %hash sha512 rtems-waf-%{rtems_waf_version}.tar.bz2 \

NAuyFxjfSiQd6VfYZl4fJClywPrLF2fN+GjXHjq3ddceqaBrSeHZ+XpYpU3XTnk2qKICsUSTLV+CskDuWdwqvQ==
-- 
2.31.1

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[PATCH 2/2] cpukit: Remove unused includes

2023-10-12 Thread Kinsey Moore

---
 cpukit/libblock/src/bdbuf.c| 1 -
 cpukit/libcsupport/src/getpid.c| 1 -
 cpukit/libcsupport/src/getppid.c   | 2 --
 cpukit/libcsupport/src/isatty_r.c  | 1 -
 cpukit/libcsupport/src/sup_fs_location.c   | 1 -
 cpukit/posix/src/condtimedwait.c   | 1 -
 cpukit/posix/src/killinfo.c| 1 -
 cpukit/posix/src/mutexattrsetprotocol.c| 1 -
 cpukit/posix/src/mutexunlock.c | 2 --
 cpukit/posix/src/psignal.c | 1 -
 cpukit/posix/src/psignalclearsignals.c | 1 -
 cpukit/posix/src/psignalsetprocesssignals.c| 1 -
 cpukit/posix/src/psignalunblockthread.c| 1 -
 cpukit/posix/src/pthreadgetschedparam.c| 1 -
 cpukit/posix/src/pthreadsetschedparam.c| 1 -
 cpukit/sapi/src/sapirbtreeinsert.c | 1 -
 cpukit/score/src/heap.c| 2 --
 cpukit/score/src/objectinitializeinformation.c | 1 -
 cpukit/score/src/threadrestart.c   | 2 --
 cpukit/score/src/userextiterate.c  | 2 --
 20 files changed, 25 deletions(-)

diff --git a/cpukit/libblock/src/bdbuf.c b/cpukit/libblock/src/bdbuf.c
index 06b756272f..ee98ada85f 100644
--- a/cpukit/libblock/src/bdbuf.c
+++ b/cpukit/libblock/src/bdbuf.c
@@ -39,7 +39,6 @@
 #include 
 
 #include 
-#include 
 #include 
 #include 
 
diff --git a/cpukit/libcsupport/src/getpid.c b/cpukit/libcsupport/src/getpid.c
index 84cab91a39..464504de7e 100644
--- a/cpukit/libcsupport/src/getpid.c
+++ b/cpukit/libcsupport/src/getpid.c
@@ -40,7 +40,6 @@
 #include 
 
 #include 
-#include 
 
 /**
  *  4.1.1 Get Process and Parent Process IDs, P1003.1b-1993, p. 83
diff --git a/cpukit/libcsupport/src/getppid.c b/cpukit/libcsupport/src/getppid.c
index 46d1cc8e08..2ca7a8f900 100644
--- a/cpukit/libcsupport/src/getppid.c
+++ b/cpukit/libcsupport/src/getppid.c
@@ -46,8 +46,6 @@
 
 #include 
 
-#include 
-
 pid_t _POSIX_types_Ppid = 0;
 
 /**
diff --git a/cpukit/libcsupport/src/isatty_r.c 
b/cpukit/libcsupport/src/isatty_r.c
index 7a758c54a8..3ae285fb26 100644
--- a/cpukit/libcsupport/src/isatty_r.c
+++ b/cpukit/libcsupport/src/isatty_r.c
@@ -44,7 +44,6 @@
  */
 #include 
 #include 
-#include 
 
 int _isatty_r(
   struct _reent *ptr,
diff --git a/cpukit/libcsupport/src/sup_fs_location.c 
b/cpukit/libcsupport/src/sup_fs_location.c
index 1f533f37f4..a121b252fb 100644
--- a/cpukit/libcsupport/src/sup_fs_location.c
+++ b/cpukit/libcsupport/src/sup_fs_location.c
@@ -39,7 +39,6 @@
 #include 
 
 #include 
-#include 
 
 rtems_interrupt_lock rtems_filesystem_mt_entry_lock_control =
   RTEMS_INTERRUPT_LOCK_INITIALIZER("mount table entry");
diff --git a/cpukit/posix/src/condtimedwait.c b/cpukit/posix/src/condtimedwait.c
index b063aac9b1..258e38a357 100644
--- a/cpukit/posix/src/condtimedwait.c
+++ b/cpukit/posix/src/condtimedwait.c
@@ -39,7 +39,6 @@
 #endif
 
 #include 
-#include 
 
 /*
  *  11.4.4 Waiting on a Condition, P1003.1c/Draft 10, p. 105
diff --git a/cpukit/posix/src/killinfo.c b/cpukit/posix/src/killinfo.c
index 2765ab30ca..f56c5b3174 100644
--- a/cpukit/posix/src/killinfo.c
+++ b/cpukit/posix/src/killinfo.c
@@ -47,7 +47,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 
diff --git a/cpukit/posix/src/mutexattrsetprotocol.c 
b/cpukit/posix/src/mutexattrsetprotocol.c
index 5a6c44cf52..c3205c9a75 100644
--- a/cpukit/posix/src/mutexattrsetprotocol.c
+++ b/cpukit/posix/src/mutexattrsetprotocol.c
@@ -44,7 +44,6 @@
 #include 
 #include 
 #include 
-#include 
 
 /*
  *  13.6.1 Mutex Initialization Scheduling Attributes, P1003.1c/Draft 10, p. 
128
diff --git a/cpukit/posix/src/mutexunlock.c b/cpukit/posix/src/mutexunlock.c
index 681aa8fd1b..0644cec188 100644
--- a/cpukit/posix/src/mutexunlock.c
+++ b/cpukit/posix/src/mutexunlock.c
@@ -41,8 +41,6 @@
 #include 
 #include 
 
-#include 
-
 bool _POSIX_Mutex_Auto_initialization( POSIX_Mutex_Control *the_mutex )
 {
   unsigned long zero;
diff --git a/cpukit/posix/src/psignal.c b/cpukit/posix/src/psignal.c
index a829c60ee1..3bfd779630 100644
--- a/cpukit/posix/src/psignal.c
+++ b/cpukit/posix/src/psignal.c
@@ -50,7 +50,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 
 /*
diff --git a/cpukit/posix/src/psignalclearsignals.c 
b/cpukit/posix/src/psignalclearsignals.c
index f31cbf0d27..0c8ae8e1a6 100644
--- a/cpukit/posix/src/psignalclearsignals.c
+++ b/cpukit/posix/src/psignalclearsignals.c
@@ -44,7 +44,6 @@
 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
diff --git a/cpukit/posix/src/psignalsetprocesssignals.c 
b/cpukit/posix/src/psignalsetprocesssignals.c
index 213de57406..9af03943f4 100644
--- a/cpukit/posix/src/psignalsetprocesssignals.c
+++ b/cpukit/posix/src/psignalsetprocesssignals.c
@@ -43,7 +43,6 @@
 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
diff --git a/cpukit/posix/src/psignalunblockthread.c 
b/cpukit/posix/src/psignalunblockthread.c
index 5b0168c22d..61c2602b96 100644
--- a/cpukit/posix/s

[PATCH 1/2] bsps: Remove unused includes

2023-10-12 Thread Kinsey Moore

---
 bsps/aarch64/shared/cache/cache.c  | 1 -
 bsps/shared/dev/i2c/cadence-i2c.c  | 1 -
 bsps/shared/irq/irq-generic.c  | 3 ---
 bsps/shared/start/bspgetworkarea-default.c | 1 -
 4 files changed, 6 deletions(-)

diff --git a/bsps/aarch64/shared/cache/cache.c 
b/bsps/aarch64/shared/cache/cache.c
index 4d299bf665..d6e0930038 100644
--- a/bsps/aarch64/shared/cache/cache.c
+++ b/bsps/aarch64/shared/cache/cache.c
@@ -36,7 +36,6 @@
 
 #include 
 #include 
-#include 
 #include 
 
 #define CPU_DATA_CACHE_ALIGNMENT 64
diff --git a/bsps/shared/dev/i2c/cadence-i2c.c 
b/bsps/shared/dev/i2c/cadence-i2c.c
index 6704288a79..67dec0da46 100644
--- a/bsps/shared/dev/i2c/cadence-i2c.c
+++ b/bsps/shared/dev/i2c/cadence-i2c.c
@@ -28,7 +28,6 @@
 #include 
 #include 
 
-#include 
 #include 
 
 #include 
diff --git a/bsps/shared/irq/irq-generic.c b/bsps/shared/irq/irq-generic.c
index e2997da623..b6238025b7 100644
--- a/bsps/shared/irq/irq-generic.c
+++ b/bsps/shared/irq/irq-generic.c
@@ -35,9 +35,6 @@
  */
 
 #include 
-#include 
-
-#include 
 
 #include 
 
diff --git a/bsps/shared/start/bspgetworkarea-default.c 
b/bsps/shared/start/bspgetworkarea-default.c
index 7080aa6053..5f956b124f 100644
--- a/bsps/shared/start/bspgetworkarea-default.c
+++ b/bsps/shared/start/bspgetworkarea-default.c
@@ -39,7 +39,6 @@
  */
 
 #include 
-#include 
 
 #if defined(HAS_UBOOT) && !defined(BSP_DISABLE_UBOOT_WORK_AREA_CONFIG)
   #define USE_UBOOT
-- 
2.39.2

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Re: [PATCH 2/2] cpukit: Remove unused includes

2023-10-12 Thread Sebastian Huber


Looks good, a nice cleanup.

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Re: [RSB 1/3] 6/7: Update Newlib

2023-10-12 Thread Sebastian Huber


On 10.10.23 07:57, Sebastian Huber wrote:

On 09.10.23 23:52, Chris Johns wrote:
Ok to all patches in the series. Thanks for newlib changes for ARM, 
they will be nice to use.


I have to fix the riscv issue before we can update Newlib.


I fixed the riscv issue and checked in an updated version of the patches.

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Re: [PATCH] sparc: Fix stack corruption

Re: [PATCH] doxygen: Replace and move main page

Re: [PATCH] sparc: Fix stack corruption

[PATCH v2 1/4] bsps/clock: Import Xilinx TTC hardware definitions

[PATCH v2 0/4] Add ZynqMP Cortex-R5 BSP

[PATCH v2 3/4] bsps/xil: Adjust Xilinx support code for Cortex-R5

[PATCH v2 2/4] bsps/xil: Import Xilinx Cortex-R5 support

[PATCH v2 4/4] bsps/arm: Add BSP for ZynqMP RPU

[RSB PATCH 2/5] rtems/kernel: Update to latest

[RSB PATCH 1/5] rtems/tools: Update to latest

[RSB PATCH 4/5] rtems/net-services: Update to latest

[RSB PATCH 3/5] rtems/libbsd: Update to latest

[RSB PATCH 5/5] rtems/net-legacy: Update to latest

[PATCH 2/2] cpukit: Remove unused includes

[PATCH 1/2] bsps: Remove unused includes

Re: [PATCH 2/2] cpukit: Remove unused includes

Re: [RSB 1/3] 6/7: Update Newlib

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