[PATCH rtems-source-builder v2] bare/config: add renode rsb installation config

[Muhammad Sulthan Mazaya]

Use the design of how qemu handle config files + add version number to
the config file name.

---
 bare/config/devel/renode-1.13.3-1.cfg | 11 ++
 bare/config/devel/renode.bset |  7 
 source-builder/config/renode-1.13.3.cfg   |  7 
 source-builder/config/renode-common-1.cfg | 45 +++
 4 files changed, 70 insertions(+)
 create mode 100644 bare/config/devel/renode-1.13.3-1.cfg
 create mode 100644 bare/config/devel/renode.bset
 create mode 100644 source-builder/config/renode-1.13.3.cfg
 create mode 100644 source-builder/config/renode-common-1.cfg

diff --git a/bare/config/devel/renode-1.13.3-1.cfg 
b/bare/config/devel/renode-1.13.3-1.cfg
new file mode 100644
index 000..ad9b0ad
--- /dev/null
+++ b/bare/config/devel/renode-1.13.3-1.cfg
@@ -0,0 +1,11 @@
+#
+# Renode from git
+#
+
+%if %{release} == %{nil}
+ %define release 1
+%endif
+
+%define renode_version 1.13.3
+
+%include %{_configdir}/renode-1.13.3.cfg
diff --git a/bare/config/devel/renode.bset b/bare/config/devel/renode.bset
new file mode 100644
index 000..f89168d
--- /dev/null
+++ b/bare/config/devel/renode.bset
@@ -0,0 +1,7 @@
+#
+# Build set for Renode
+#
+
+%define release 1
+
+devel/renode-1.13.3-1
diff --git a/source-builder/config/renode-1.13.3.cfg 
b/source-builder/config/renode-1.13.3.cfg
new file mode 100644
index 000..5aff341
--- /dev/null
+++ b/source-builder/config/renode-1.13.3.cfg
@@ -0,0 +1,7 @@
+#
+# Renode 1.13.3 Version 1.
+#
+# This configuration file configure's, make's and install's Renode.
+#
+
+%include %{_configdir}/renode-common-1.cfg
diff --git a/source-builder/config/renode-common-1.cfg 
b/source-builder/config/renode-common-1.cfg
new file mode 100644
index 000..65be946
--- /dev/null
+++ b/source-builder/config/renode-common-1.cfg
@@ -0,0 +1,45 @@
+#
+# Renode from git
+#
+
+%if %{release} == %{nil}
+ %define release 1
+%endif
+
+Name:  renode-%{renode_version}-%{_host}-%{release}
+Summary:   Renode v%{renode_version}
+Version:   %{renode_version}
+Release:   %{release}
+URL:  http://www.renode.io
+
+#
+# Renode source
+#
+%source set renode 
https://github.com/renode/renode/releases/download/v%{renode_version}/renode_%{renode_version}_source.tar.xz
+
+#
+# Prepare the source code.
+#
+%prep
+  build_top=$(pwd)
+
+  source_dir_renode="renode_%{renode_version}_source"
+  %source setup renode -q -n renode_%{renode_version}_source
+
+  cd ${build_top}
+
+%build
+  build_top=$(pwd)
+
+  cd ${source_dir_renode}
+  ./build.sh
+
+  cd ${build_top}
+
+%install
+  build_top=$(pwd)
+
+  mkdir -p %{_bindir}
+  cp -r ./${source_dir_renode}/* %{_bindir}
+
+  cd ${build_top}
-- 
2.34.1

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Re: Need community suggestions for a new generic GPIO API

[Joel Sherrill]

On Tue, Jul 11, 2023 at 12:50 PM Gedare Bloom  wrote:

> On Tue, Jul 11, 2023 at 7:05 AM Christian MAUDERER
>  wrote:
> >
> > Hello Utkarsh,
> >
> > please be a bit careful with GPIO and pin functions. That's a quite
> > difficult topic.
> >
> > Some controller manufacturers mix these functions. One such example is
> > the STM32 family. I'll take the STM32F410 as an example. That chip has a
> > GPIO register block with one GPIOx_MODER where you can select whether a
> > pin is a Input, GPIO, alternate function or analog mode. There is also a
> > GPIOx_OSPEEDR that defines speed and some others that define pull ups /
> > downs and so on.
> >
> > Other controllers - like a lot of the NXP ones - have two completely
> > independent modules for that. I'll take the i.MXRT1050 series as an
> > example: That chip has an IOMUXC where you can set a pin function for a
> > pad. For example, there is a register IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26.
> > In that register, you can set a pin function of GPIO4_IO26. There is a
> > related PAD_CTL register in the IOMUXC where you can set up pull ups /
> > downs, drive strength and so on. The GPIO controller where you set up
> > levels and interrupts for that pin is a completely unrelated module. On
> > the i.MXRT1166 you can even assign some pins to two different GPIO
> > controllers. So it's not possible to have a 1:1 mapping between pin and
> > GPIO.
> >
> > If you ask me GPIO and pin function are two separate things and need two
> > APIs. That should make it possible to support controllers like the STM32
> > (where some of the GPIO registers would be controlled by the GPIO API
> > and some by the pin function API) and for controllers like the i.MXRT
> > where the two APIs would handle different hardware modules.
> >
> > If you take a look at Linux or FreeBSD, they usually split that up just
> > like that. If you want to dig deeper into that, maybe it would be worth
> > to take a look at some other embedded operating systems. For example
> > Zephyr or Contiki or any of the ones in Wikipedia "Comparison of
> > real-time operating systems". It can even be a good idea to create a
> > compatible interface.
> >
> This reminds me that I think the pinmux was lifted out of libbsd and
> put into RTEMS for the BBB.
> * shared/freebsd/sys/arm/ti/ti_pinmux.c
>
> This may be the right direction to go for other targets, where they
> have support in FreeBSD. And where they don't, compliance to that
> pinmux API may be preferable.
>

Not directly an API but the Virtio standard includes a GPIO device.
Assuming it was well thought out (I would assume it is), that is probably
the easiest device you want this API to interface with.

https://docs.oasis-open.org/virtio/virtio/v1.2/csd01/virtio-v1.2-csd01.html

FWIW I would like to see RTEMS support the full complement of virtio
device drivers.This should make it easiest to have RTEMS as a guest
under a variety of hypervisors, etc. including Xen.

--joel

>
> > Best regards
> >
> > Christian
> >
> > On 2023-07-07 21:48, Utkarsh Verma wrote:
> > > Dear all,
> > >
> > > While working on the Raspberry Pi 4 BSP, I realized that the GPIO API
> > > could be improved. It seems that last year, a GSoC student worked on
> > > introducing a new GPIO API, called GPIO2 to RTEMS. However, it did not
> > > get merged. Discussing this topic with my mentor and on RTEMS Discord
> > > revealed that it would be a good idea to get it merged. For that, I
> > > would like to ask the community the following:
> > >
> > > - Moving forward, will GPIO2 API be the community-preferred GPIO API?
> > > - What would be the recommended way in this new API to select
> > > alternate pin functions? Will that be left for the BSP to decide?
> > >
> > > Here are the links associated with GPIO2:
> > > Git Repo: https://github.com/dtbpkmte/GSoC-2022-RTEMS
> > > GPIO2 commit:
> https://github.com/dtbpkmte/GSoC-2022-RTEMS/commit/0aec268f1209c
> > > Blog post about the API:
> > >
> https://medium.com/@dtbpkmte/gsoc-2022-rtems-coding-period-week-4-gpio-wiki-1f10e5c4458
> > > ___
> > > devel mailing list
> > > devel@rtems.org
> > > http://lists.rtems.org/mailman/listinfo/devel
> >
> > --
> > 
> > embedded brains GmbH & Co. KG
> > Herr Christian MAUDERER
> > Dornierstr. 4
> > 82178 Puchheim
> > Germany
> > email:  christian.maude...@embedded-brains.de
> > phone:  +49-89-18 94 741 - 18
> > mobile: +49-176-152 206 08
> >
> > Registergericht: Amtsgericht München
> > Registernummer: HRA 117265
> > Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
> > Unsere Datenschutzerklärung finden Sie hier:
> > https://embedded-brains.de/datenschutzerklaerung/
> > ___
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> > devel@rtems.org
> > http://lists.rtems.org/mailman/listinfo/devel
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Re: [PATCH rtems-source-builder] bare/config: add renode rsb installation config

[Joel Sherrill]

On Tue, Jul 11, 2023 at 1:01 PM Gedare Bloom  wrote:

> This probably requires some documentation, as it requires several
> packages that are not going to be typically installed already by RTEMS
> users/developers. Chris, is there any place to document required
> dependencies/packages for a build set?
>

The Users Guide obviously does the base set required commonly
but a section on Requirements for Renode.io would probably be the
right way to go.

Also sb-check checks for program executables being present. I don't know
if we have any way to say program X is used by Y. For example, the newer
qemu versions use some other build program that I didn't have installed and
can't remember right now.

--joel


>
> The patch has a whitespace problem
>
> +# Renode source
> +#
>  It might be a non-ASCII character, as it gets eaten by email but is
> in the patch file.
>
> Gedare
>
> On Mon, Jul 10, 2023 at 5:13 AM Muhammad Sulthan Mazaya
>  wrote:
> >
> > An implementation of renode rsb installation config. It uses renode's
> > github release as source and build the package using their build script.
> >
> > ---
> >  bare/config/devel/renode-git-1.cfg | 47 ++
> >  bare/config/devel/renode.bset  |  9 ++
> >  2 files changed, 56 insertions(+)
> >  create mode 100644 bare/config/devel/renode-git-1.cfg
> >  create mode 100644 bare/config/devel/renode.bset
> >
> > diff --git a/bare/config/devel/renode-git-1.cfg
> b/bare/config/devel/renode-git-1.cfg
> > new file mode 100644
> > index 000..df424a6
> > --- /dev/null
> > +++ b/bare/config/devel/renode-git-1.cfg
> > @@ -0,0 +1,47 @@
> > +#
> > +# Renode from github
> > +#
> > +
> > +%if %{release} == %{nil}
> > + %define release 1
> > +%endif
> > +
> > +%define renode_version 1.13.3
> > +
> > +Name:  renode-%{renode_version}-%{_host}-%{release}
> > +Summary:   Renode v%{renode_version}
> > +Version:   %{renode_version}
> > +Release:   %{release}
> > +URL:  http://www.renode.io
> > +
> > +#
> > +# Renode source
> > +#
> > +%source set renode
> https://github.com/renode/renode/releases/download/v%{renode_version}/renode_%{renode_version}_source.tar.xz
> > +
> > +#
> > +# Prepare the source code.
> > +#
> > +%prep
> > +  build_top=$(pwd)
> > +
> > +  source_dir_renode="renode_%{renode_version}_source"
> > +  %source setup renode -q -n renode_%{renode_version}_source
> > +
> > +  cd ${build_top}
> > +
> > +%build
> > +  build_top=$(pwd)
> > +
> > +  cd ${source_dir_renode}
> > +  ./build.sh
> > +
> > +  cd ${build_top}
> > +
> > +%install
> > +  build_top=$(pwd)
> > +
> > +  mkdir -p %{_bindir}
> > +  cp -r ./${source_dir_renode}/* %{_bindir}
> > +
> > +  cd ${build_top}
> > diff --git a/bare/config/devel/renode.bset
> b/bare/config/devel/renode.bset
> > new file mode 100644
> > index 000..d64a2a2
> > --- /dev/null
> > +++ b/bare/config/devel/renode.bset
> > @@ -0,0 +1,9 @@
> > +#
> > +# Build set for Renode
> > +#
> > +
> > +%if %{release} == %{nil}
> > +%define release 1
> > +%endif
> > +
> > +devel/renode-git-1
> > --
> > 2.34.1
> >
> > ___
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> > devel@rtems.org
> > http://lists.rtems.org/mailman/listinfo/devel
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Re: [PATCH] TMS570 console driver, SCI frame error (baudrate calculation error)

[Pavel Pisa]

Hello Zack and Gedare,

On Tuesday 11 of July 2023 19:52:27 Gedare Bloom wrote:
> Thanks for the patch. Someone should probably test it, or identify in
> the documentation why this calculation was off-by-1. Pavel, any clues?
> On Sun, Jul 9, 2023 at 10:09 PM zack  wrote:
> > Fixes #4903
> > diff --git a/bsps/arm/tms570/console/tms570-sci.c
> > b/bsps/arm/tms570/console/tms570-sci.c index 768770a4c8..59a0b7e6f1
> > 100644
> > --- a/bsps/arm/tms570/console/tms570-sci.c
> > +++ b/bsps/arm/tms570/console/tms570-sci.c
> > @@ -311,7 +311,7 @@ bool tms570_sci_set_attributes(
> >/* Apply baudrate to the hardware */
> >baudrate *= 2 * 16;
> >bauddiv = (BSP_PLL_OUT_CLOCK + baudrate / 2) / baudrate;
> > -  ctx->regs->BRS = bauddiv? bauddiv - 1: 0;
> > +  ctx->regs->BRS = bauddiv? bauddiv - 2: 0;

I think that change is not correct. The actual used values
for BSP_PLL_OUT_CLOCK and baudrate should be provided to analyze
the case. The code can result in some rounding error and can
be enhanced if fractional divider is used or even super finegrained
fractional divider. But these options are available only for
for SCI/LIN peripheral case.

According to

TMS570LS31x/21x 16/32-Bit RISC Flash Microcontroller
Technical Reference Manual
Literature Number: SPNU499B

26.2.3 SCI Baud Rate

  SCICLK Frequency = VCLK Frequency / (P + 1 + M / 16)

  Asynchronous baud value = SCICLK Frequency / 16

So the substraction of one corresponds to the manual.

Actual code does not use M part. It would be problem if it is
leftover from some boot/monitor but it is part of BRS 32-bit
register which is overwritten in the whole, so such problem
should not appear either.

So I vote against the proposed change for now and suggest
to do analysis what happens in the computation and what
are input values and output. Change would/could affect
negatively large number of combinations of the baudrate
and clocks.

I would consider to discuss if the rounding formula
could/should be updated, but I think that it is the best
which cane be achieved for rations which do not result
in exact ratio.

  (BSP_PLL_OUT_CLOCK + baudrate / 2) / baudrate;

If there is interrest then code can be enhanced by fraction
dividers for SCI/LIN peripheral case. The field with variant
should be added into tms570_sci_context and in this case
the alternative formula can be used

  long long bauddiv;
  bauddiv = (BSP_PLL_OUT_CLOCK * 16ll + baudrate / 2) / baudrate;
  ctx->regs->BRS = ((bauddiv >> 4) & 0xff) | ((bauddiv & 0xf) << 24);

which should be rewritten after header for SCI/LIN update to

  ctx->regs->BRS = TMS570_LIN_BRS_P(bauddiv >> 4) | TMS570_LIN_BRS_M(bauddiv & 
0xf);

Best wishes,


Pavel
--
Pavel Pisa
phone:  +420 603531357
e-mail: p...@cmp.felk.cvut.cz
Department of Control Engineering FEE CVUT
Karlovo namesti 13, 121 35, Prague 2
university: http://control.fel.cvut.cz/
personal:   http://cmp.felk.cvut.cz/~pisa
projects:   https://www.openhub.net/accounts/ppisa
CAN related:http://canbus.pages.fel.cvut.cz/
RISC-V education: https://comparch.edu.cvut.cz/
Open Technologies Research Education and Exchange Services
https://gitlab.fel.cvut.cz/otrees/org/-/wikis/home

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[PATCH v3 03/38] bsps/grlib: Fix GRGPIO - IRQMAP bit fields

[Sebastian Huber]

Update #4842.
---
 bsps/include/grlib/grgpio-regs.h | 37 +---
 1 file changed, 24 insertions(+), 13 deletions(-)

diff --git a/bsps/include/grlib/grgpio-regs.h b/bsps/include/grlib/grgpio-regs.h
index b1768ff92e..8c3c7ffb16 100644
--- a/bsps/include/grlib/grgpio-regs.h
+++ b/bsps/include/grlib/grgpio-regs.h
@@ -285,18 +285,18 @@ extern "C" {
  * @{
  */
 
-#define GRGPIO_IRQMAPR_IRQMAP_I_SHIFT 24
-#define GRGPIO_IRQMAPR_IRQMAP_I_MASK 0x7f00U
-#define GRGPIO_IRQMAPR_IRQMAP_I_GET( _reg ) \
-  ( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_MASK ) >> \
-GRGPIO_IRQMAPR_IRQMAP_I_SHIFT )
-#define GRGPIO_IRQMAPR_IRQMAP_I_SET( _reg, _val ) \
-  ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_MASK ) | \
-( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_SHIFT ) & \
-  GRGPIO_IRQMAPR_IRQMAP_I_MASK ) )
-#define GRGPIO_IRQMAPR_IRQMAP_I( _val ) \
-  ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_SHIFT ) & \
-GRGPIO_IRQMAPR_IRQMAP_I_MASK )
+#define GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT 24
+#define GRGPIO_IRQMAPR_IRQMAP_I_0_MASK 0x1f00U
+#define GRGPIO_IRQMAPR_IRQMAP_I_0_GET( _reg ) \
+  ( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) >> \
+GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT )
+#define GRGPIO_IRQMAPR_IRQMAP_I_0_SET( _reg, _val ) \
+  ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) | \
+( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT ) & \
+  GRGPIO_IRQMAPR_IRQMAP_I_0_MASK ) )
+#define GRGPIO_IRQMAPR_IRQMAP_I_0( _val ) \
+  ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_0_SHIFT ) & \
+GRGPIO_IRQMAPR_IRQMAP_I_0_MASK )
 
 #define GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT 16
 #define GRGPIO_IRQMAPR_IRQMAP_I_1_MASK 0x1fU
@@ -324,7 +324,18 @@ extern "C" {
   ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT ) & \
 GRGPIO_IRQMAPR_IRQMAP_I_2_MASK )
 
-#define GRGPIO_IRQMAPR_IRQMAP_I_3 0x10U
+#define GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT 0
+#define GRGPIO_IRQMAPR_IRQMAP_I_3_MASK 0x1fU
+#define GRGPIO_IRQMAPR_IRQMAP_I_3_GET( _reg ) \
+  ( ( ( _reg ) & GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) >> \
+GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT )
+#define GRGPIO_IRQMAPR_IRQMAP_I_3_SET( _reg, _val ) \
+  ( ( ( _reg ) & ~GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) | \
+( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT ) & \
+  GRGPIO_IRQMAPR_IRQMAP_I_3_MASK ) )
+#define GRGPIO_IRQMAPR_IRQMAP_I_3( _val ) \
+  ( ( ( _val ) << GRGPIO_IRQMAPR_IRQMAP_I_3_SHIFT ) & \
+GRGPIO_IRQMAPR_IRQMAP_I_3_MASK )
 
 /** @} */
 
-- 
2.35.3

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[PATCH v3 06/38] bsps/grlib: Fix SPWTDP register name

[Sebastian Huber]

Update #4842.
---
 bsps/include/grlib/spwtdp-regs.h | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/bsps/include/grlib/spwtdp-regs.h b/bsps/include/grlib/spwtdp-regs.h
index b69fb5b0a5..2e951e4544 100644
--- a/bsps/include/grlib/spwtdp-regs.h
+++ b/bsps/include/grlib/spwtdp-regs.h
@@ -304,25 +304,25 @@ extern "C" {
 /** @} */
 
 /**
- * @defgroup RTEMSDeviceGRLIBSPWTDPCET0 Command Elapsed Time 3 (CET0)
+ * @defgroup RTEMSDeviceGRLIBSPWTDPCET3 Command Elapsed Time 3 (CET3)
  *
  * @brief This group contains register bit definitions.
  *
  * @{
  */
 
-#define SPWTDP_CET0_CET3_SHIFT 0
-#define SPWTDP_CET0_CET3_MASK 0xU
-#define SPWTDP_CET0_CET3_GET( _reg ) \
-  ( ( ( _reg ) & SPWTDP_CET0_CET3_MASK ) >> \
-SPWTDP_CET0_CET3_SHIFT )
-#define SPWTDP_CET0_CET3_SET( _reg, _val ) \
-  ( ( ( _reg ) & ~SPWTDP_CET0_CET3_MASK ) | \
-( ( ( _val ) << SPWTDP_CET0_CET3_SHIFT ) & \
-  SPWTDP_CET0_CET3_MASK ) )
-#define SPWTDP_CET0_CET3( _val ) \
-  ( ( ( _val ) << SPWTDP_CET0_CET3_SHIFT ) & \
-SPWTDP_CET0_CET3_MASK )
+#define SPWTDP_CET3_CET3_SHIFT 0
+#define SPWTDP_CET3_CET3_MASK 0xU
+#define SPWTDP_CET3_CET3_GET( _reg ) \
+  ( ( ( _reg ) & SPWTDP_CET3_CET3_MASK ) >> \
+SPWTDP_CET3_CET3_SHIFT )
+#define SPWTDP_CET3_CET3_SET( _reg, _val ) \
+  ( ( ( _reg ) & ~SPWTDP_CET3_CET3_MASK ) | \
+( ( ( _val ) << SPWTDP_CET3_CET3_SHIFT ) & \
+  SPWTDP_CET3_CET3_MASK ) )
+#define SPWTDP_CET3_CET3( _val ) \
+  ( ( ( _val ) << SPWTDP_CET3_CET3_SHIFT ) & \
+SPWTDP_CET3_CET3_MASK )
 
 /** @} */
 
@@ -1075,7 +1075,7 @@ typedef struct spwtdp {
   /**
* @brief See @ref RTEMSDeviceGRLIBSPWTDPCET0.
*/
-  uint32_t cet0_0;
+  uint32_t cet0;
 
   /**
* @brief See @ref RTEMSDeviceGRLIBSPWTDPCET1.
@@ -1088,9 +1088,9 @@ typedef struct spwtdp {
   uint32_t cet2;
 
   /**
-   * @brief See @ref RTEMSDeviceGRLIBSPWTDPCET0.
+   * @brief See @ref RTEMSDeviceGRLIBSPWTDPCET3.
*/
-  uint32_t cet0_1;
+  uint32_t cet3;
 
   /**
* @brief See @ref RTEMSDeviceGRLIBSPWTDPCET4.
-- 
2.35.3

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[PATCH v3 07/38] bsps/grlib: Add GRCAN - CanTxIRQ

[Sebastian Huber]

Update #4842.
---
 bsps/include/grlib/grcan-regs.h | 33 +
 1 file changed, 17 insertions(+), 16 deletions(-)

diff --git a/bsps/include/grlib/grcan-regs.h b/bsps/include/grlib/grcan-regs.h
index fc69f4519e..85a5e56367 100644
--- a/bsps/include/grlib/grcan-regs.h
+++ b/bsps/include/grlib/grcan-regs.h
@@ -404,25 +404,26 @@ extern "C" {
 /** @} */
 
 /**
- * @defgroup RTEMSDeviceGRCANCanTxRD Transmit Channel Read Register (CanTxRD)
+ * @defgroup RTEMSDeviceGRCANCanTxIRQ \
+ *   Transmit Channel Interrupt Register (CanTxIRQ)
  *
  * @brief This group contains register bit definitions.
  *
  * @{
  */
 
-#define GRCAN_CANTXRD_IRQ_SHIFT 4
-#define GRCAN_CANTXRD_IRQ_MASK 0x0U
-#define GRCAN_CANTXRD_IRQ_GET( _reg ) \
-  ( ( ( _reg ) & GRCAN_CANTXRD_IRQ_MASK ) >> \
-GRCAN_CANTXRD_IRQ_SHIFT )
-#define GRCAN_CANTXRD_IRQ_SET( _reg, _val ) \
-  ( ( ( _reg ) & ~GRCAN_CANTXRD_IRQ_MASK ) | \
-( ( ( _val ) << GRCAN_CANTXRD_IRQ_SHIFT ) & \
-  GRCAN_CANTXRD_IRQ_MASK ) )
-#define GRCAN_CANTXRD_IRQ( _val ) \
-  ( ( ( _val ) << GRCAN_CANTXRD_IRQ_SHIFT ) & \
-GRCAN_CANTXRD_IRQ_MASK )
+#define GRCAN_CANTXIRQ_IRQ_SHIFT 4
+#define GRCAN_CANTXIRQ_IRQ_MASK 0x0U
+#define GRCAN_CANTXIRQ_IRQ_GET( _reg ) \
+  ( ( ( _reg ) & GRCAN_CANTXIRQ_IRQ_MASK ) >> \
+GRCAN_CANTXIRQ_IRQ_SHIFT )
+#define GRCAN_CANTXIRQ_IRQ_SET( _reg, _val ) \
+  ( ( ( _reg ) & ~GRCAN_CANTXIRQ_IRQ_MASK ) | \
+( ( ( _val ) << GRCAN_CANTXIRQ_IRQ_SHIFT ) & \
+  GRCAN_CANTXIRQ_IRQ_MASK ) )
+#define GRCAN_CANTXIRQ_IRQ( _val ) \
+  ( ( ( _val ) << GRCAN_CANTXIRQ_IRQ_SHIFT ) & \
+GRCAN_CANTXIRQ_IRQ_MASK )
 
 /** @} */
 
@@ -663,12 +664,12 @@ typedef struct grcan {
   /**
* @brief See @ref RTEMSDeviceGRCANCanTxRD.
*/
-  uint32_t cantxrd_0;
+  uint32_t cantxrd;
 
   /**
-   * @brief See @ref RTEMSDeviceGRCANCanTxRD.
+   * @brief See @ref RTEMSDeviceGRCANCanTxIRQ.
*/
-  uint32_t cantxrd_1;
+  uint32_t cantxirq;
 
   uint32_t reserved_218_300[ 58 ];
 
-- 
2.35.3

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[PATCH v3 05/38] bsps/grlib: Expand SpaceWire port bit fields

[Sebastian Huber]

Use the maximum width supported by the SpaceWire standard even if this
exceeds the configuration limits of a particular IP instance.

Update #4842.
---
 bsps/include/grlib/spwpnp-regs.h  | 2 +-
 bsps/include/grlib/spwrmap-regs.h | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/bsps/include/grlib/spwpnp-regs.h b/bsps/include/grlib/spwpnp-regs.h
index 45550e3a79..00c688bc55 100644
--- a/bsps/include/grlib/spwpnp-regs.h
+++ b/bsps/include/grlib/spwpnp-regs.h
@@ -194,7 +194,7 @@ extern "C" {
  */
 
 #define SPWPNP_PNPACTLNK_ACTIVE_SHIFT 1
-#define SPWPNP_PNPACTLNK_ACTIVE_MASK 0x1ffeU
+#define SPWPNP_PNPACTLNK_ACTIVE_MASK 0xfffeU
 #define SPWPNP_PNPACTLNK_ACTIVE_GET( _reg ) \
   ( ( ( _reg ) & SPWPNP_PNPACTLNK_ACTIVE_MASK ) >> \
 SPWPNP_PNPACTLNK_ACTIVE_SHIFT )
diff --git a/bsps/include/grlib/spwrmap-regs.h 
b/bsps/include/grlib/spwrmap-regs.h
index 7a19f4a2d3..9a0ed203f3 100644
--- a/bsps/include/grlib/spwrmap-regs.h
+++ b/bsps/include/grlib/spwrmap-regs.h
@@ -751,7 +751,7 @@ extern "C" {
  */
 
 #define SPWRMAP_IPMASK_IE_SHIFT 0
-#define SPWRMAP_IPMASK_IE_MASK 0xfU
+#define SPWRMAP_IPMASK_IE_MASK 0xU
 #define SPWRMAP_IPMASK_IE_GET( _reg ) \
   ( ( ( _reg ) & SPWRMAP_IPMASK_IE_MASK ) >> \
 SPWRMAP_IPMASK_IE_SHIFT )
@@ -774,7 +774,7 @@ extern "C" {
  */
 
 #define SPWRMAP_PIP_IP_SHIFT 0
-#define SPWRMAP_PIP_IP_MASK 0xfU
+#define SPWRMAP_PIP_IP_MASK 0xU
 #define SPWRMAP_PIP_IP_GET( _reg ) \
   ( ( ( _reg ) & SPWRMAP_PIP_IP_MASK ) >> \
 SPWRMAP_PIP_IP_SHIFT )
@@ -953,7 +953,7 @@ extern "C" {
  */
 
 #define SPWRMAP_LRUNSTAT_LR_SHIFT 1
-#define SPWRMAP_LRUNSTAT_LR_MASK 0x7fffeU
+#define SPWRMAP_LRUNSTAT_LR_MASK 0xfffeU
 #define SPWRMAP_LRUNSTAT_LR_GET( _reg ) \
   ( ( ( _reg ) & SPWRMAP_LRUNSTAT_LR_MASK ) >> \
 SPWRMAP_LRUNSTAT_LR_SHIFT )
-- 
2.35.3

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[PATCH v3 00/38] Integrate pre-qualified LEON3 BSP

[Sebastian Huber]

The register block specification were recently integrated in the RTEMS
Software Engineering manual.  Now it is time to integrate the
pre-qualified LEON3 BSP which uses the generated GRLIB header files.

The existing tests in the RTEMS test suite are basically BSP
independent. This patch set introduces BSP-specific validation tests.
These tests are disabled for other BSPs through the build system, for
example:

spec/build/testsuites/validation/bsp-sparc-leon3-gr712rc.yml
[...]
cxxflags: []
enabled-by: sparc/gr712rc
features: c cprogram
[...]

The patch set introduces new header files for GRLIB in
"bsps/include/grlib".  These header files were generated from
specification items in:

https://github.com/RTEMS/rtems-central/tree/master/spec/dev/grlib/if

The specification was created using the GRIP reference manual
(https://www.gaisler.com/products/grlib/grip.pdf) and is quite complete.
The generated header files were reviewed by the ISVV activity which
resulted in two tickets:

https://devel.rtems.org/ticket/4828

https://devel.rtems.org/ticket/4842

In the long term, the existing GRLIB header files should be replaced by
the generated header files. Using specification items for the register
blocks has the potential benefit that, in addition to the C header
files, files for C++/Rust/Python could be generated.

The main change for the sparc/gr712rc and sparc/gr740 BSPs is the
removal of the dynamic device enumeration in favor of a static
initialization.  This greatly simplifies the specification and
validation of the BSP-specific parts. It also reduces the code and data
size for applications which do not need the dynamic device enumeration.

v2:

* Move BSP-specific tests to "testsuites/validation/bsps".

* Rearrange patches so that they build individually.

v3:

* Restore previous behaviour of gptimer_tlib_reset().

* Use new IRQ(A)MP register block API also for
  LEON_Enable_interrupt_broadcast() and
  LEON_Disable_interrupt_broadcast().

* Add GRCAN - CanTxIRQ.

* Expand GRCLKGATE register bit fields.

* Move GR740-specific register blocks.

* Use GRLIB definition of GRSPW2

* Remove obsolete register block.  This register block was an incomplete
  duplicate of spec:/dev/grlib/if/grspw2.

* Use GRLIB definition of GRSPWROUTER.  Rename item to match with GRLIB
  naming.

Sebastian Huber (38):
  bsps/grlib: Add generated headers
  bsps/grlib: Fix FTMCTRL - MCFG1 bit fields
  bsps/grlib: Fix GRGPIO - IRQMAP bit fields
  bsps/grlib: Fix SpaceWire RMAP - Product ID
  bsps/grlib: Expand SpaceWire port bit fields
  bsps/grlib: Fix SPWTDP register name
  bsps/grlib: Add GRCAN - CanTxIRQ
  bsps/grlib: Expand GRCLKGATE register bit fields
  bsps/grlib: Move GR740-specific registers
  bsps/grlib: Use GRLIB definition of GRSPW2
  bsps/grlib: Remove obsolete header file
  bsps/grlib: Use GRLIB definition of GRSPWROUTER
  bsps: Use new APBUART register block API
  bsp/leon3: Untangle interrupt controller support
  bsp/leon3: Move and simplify bsp_irq_fixup()
  bsp/leon3: Use new IRQ(A)MP register block API
  bsp/leon3: Move system control register support
  bsp/leon3: Use new GPTIMER register block API
  bsp/leon3: Use new L2CACHE register block API
  bsp/leon3: Add LEON3_APBUART_BASE
  bsp/leon3: LEON3_PLB_FREQUENCY_DEFINED_BY_GPTIMER
  bsp/leon3: Add LEON3_GPTIMER_BASE
  bsp/leon3: Add LEON3_IRQAMP_BASE
  bsp/leon3: Add LEON3_IRQAMP_PROBE_TIMESTAMP
  bsp/leon3: Add LEON3_HAS_ASR_22_23_UP_COUNTER
  bsp/leon3: Add LEON3_L2CACHE_BASE
  bsp/leon3: Move leon3_power_down_loop()
  bsp/leon3: Simplify fatal error handling
  bsp/leon3: Add LEON3_PROBE_ASR_22_23_UP_COUNTER
  bsp/leon3: Add LEON3_IRQAMP_EXTENDED_INTERRUPT
  bsp/leon3: Use LEON3_GPTIMER_BASE
  bsp/leon3: Enable up-counter conditionally
  bsps/sparc: Remove BSP_POWER_DOWN_AT_FATAL_HALT
  bsp/leon3: Fix group memberships
  bsp/leon3: Add specialized target hash
  validation: grlib
  validation: Test sparc/leon3 BSP family
  bsp/leon3: Simplify shutdown

 bsps/include/grlib/ahbstat-regs.h |  171 ++
 bsps/include/grlib/ahbtrace-regs.h|  313 +++
 bsps/include/grlib/apbuart-regs.h |  281 +++
 bsps/include/grlib/apbuart.h  |  108 +-
 bsps/include/grlib/apbuart_termios.h  |4 +-
 bsps/include/grlib/dsu4-regs.h|  788 +++
 bsps/include/grlib/ftmctrl-regs.h |  322 +++
 bsps/include/grlib/gptimer-regs.h |  379 
 bsps/include/grlib/gr1553b-regs.h | 1393 
 bsps/include/grlib/grcan-regs.h   |  723 +++
 bsps/include/grlib/grclkgate-regs.h   |  212 ++
 bsps/include/grlib/grethgbit-regs.h   |  446 
 bsps/include/grlib/grgpio-regs.h  |  630 ++
 bsps/include/grlib/griommu-regs.h |  878 
 bsps/include/grlib/grpci2-regs.h  |  875 
 bsps/include/grlib/grspw2-regs.h  | 1429 
 bsps/include/grlib/grspwrouter-regs.h | 1925 +++

[PATCH v3 04/38] bsps/grlib: Fix SpaceWire RMAP - Product ID

[Sebastian Huber]

Update #4842.
---
 bsps/include/grlib/spwrmap-regs.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/bsps/include/grlib/spwrmap-regs.h 
b/bsps/include/grlib/spwrmap-regs.h
index a75b02a39b..7a19f4a2d3 100644
--- a/bsps/include/grlib/spwrmap-regs.h
+++ b/bsps/include/grlib/spwrmap-regs.h
@@ -1075,7 +1075,7 @@ extern "C" {
 SPWRMAP_PNPVEND_VI_MASK )
 
 #define SPWRMAP_PNPVEND_PI_SHIFT 0
-#define SPWRMAP_PNPVEND_PI_MASK 0x3ffU
+#define SPWRMAP_PNPVEND_PI_MASK 0xU
 #define SPWRMAP_PNPVEND_PI_GET( _reg ) \
   ( ( ( _reg ) & SPWRMAP_PNPVEND_PI_MASK ) >> \
 SPWRMAP_PNPVEND_PI_SHIFT )
@@ -1112,7 +1112,7 @@ extern "C" {
 SPWRMAP_PNPUVEND_VI_MASK )
 
 #define SPWRMAP_PNPUVEND_PI_SHIFT 0
-#define SPWRMAP_PNPUVEND_PI_MASK 0x3ffU
+#define SPWRMAP_PNPUVEND_PI_MASK 0xU
 #define SPWRMAP_PNPUVEND_PI_GET( _reg ) \
   ( ( ( _reg ) & SPWRMAP_PNPUVEND_PI_MASK ) >> \
 SPWRMAP_PNPUVEND_PI_SHIFT )
-- 
2.35.3

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[PATCH v3 02/38] bsps/grlib: Fix FTMCTRL - MCFG1 bit fields

[Sebastian Huber]

There was an off by one error in all bit fields.  Add the R flag.

Update #4842.
---
 bsps/include/grlib/ftmctrl-regs.h | 127 --
 1 file changed, 70 insertions(+), 57 deletions(-)

diff --git a/bsps/include/grlib/ftmctrl-regs.h 
b/bsps/include/grlib/ftmctrl-regs.h
index 6de7d49fd6..fb4203270c 100644
--- a/bsps/include/grlib/ftmctrl-regs.h
+++ b/bsps/include/grlib/ftmctrl-regs.h
@@ -82,59 +82,61 @@ extern "C" {
  * @{
  */
 
-#define FTMCTRL_MCFG1_PBRDY 0x8000U
-
-#define FTMCTRL_MCFG1_ABRDY 0x4000U
-
-#define FTMCTRL_MCFG1_IOBUSW 0x2000U
-
-#define FTMCTRL_MCFG1_IBRDY_SHIFT 27
-#define FTMCTRL_MCFG1_IBRDY_MASK 0x1800U
-#define FTMCTRL_MCFG1_IBRDY_GET( _reg ) \
-  ( ( ( _reg ) & FTMCTRL_MCFG1_IBRDY_MASK ) >> \
-FTMCTRL_MCFG1_IBRDY_SHIFT )
-#define FTMCTRL_MCFG1_IBRDY_SET( _reg, _val ) \
-  ( ( ( _reg ) & ~FTMCTRL_MCFG1_IBRDY_MASK ) | \
-( ( ( _val ) << FTMCTRL_MCFG1_IBRDY_SHIFT ) & \
-  FTMCTRL_MCFG1_IBRDY_MASK ) )
-#define FTMCTRL_MCFG1_IBRDY( _val ) \
-  ( ( ( _val ) << FTMCTRL_MCFG1_IBRDY_SHIFT ) & \
-FTMCTRL_MCFG1_IBRDY_MASK )
-
-#define FTMCTRL_MCFG1_BEXCN 0x400U
-
-#define FTMCTRL_MCFG1_IO_WAITSTATES 0x100U
-
-#define FTMCTRL_MCFG1_IOEN_SHIFT 20
-#define FTMCTRL_MCFG1_IOEN_MASK 0xf0U
-#define FTMCTRL_MCFG1_IOEN_GET( _reg ) \
-  ( ( ( _reg ) & FTMCTRL_MCFG1_IOEN_MASK ) >> \
-FTMCTRL_MCFG1_IOEN_SHIFT )
-#define FTMCTRL_MCFG1_IOEN_SET( _reg, _val ) \
-  ( ( ( _reg ) & ~FTMCTRL_MCFG1_IOEN_MASK ) | \
-( ( ( _val ) << FTMCTRL_MCFG1_IOEN_SHIFT ) & \
-  FTMCTRL_MCFG1_IOEN_MASK ) )
-#define FTMCTRL_MCFG1_IOEN( _val ) \
-  ( ( ( _val ) << FTMCTRL_MCFG1_IOEN_SHIFT ) & \
-FTMCTRL_MCFG1_IOEN_MASK )
-
-#define FTMCTRL_MCFG1_ROMBANKSZ 0x8U
-
-#define FTMCTRL_MCFG1_PWEN_SHIFT 14
-#define FTMCTRL_MCFG1_PWEN_MASK 0x3c000U
-#define FTMCTRL_MCFG1_PWEN_GET( _reg ) \
-  ( ( ( _reg ) & FTMCTRL_MCFG1_PWEN_MASK ) >> \
-FTMCTRL_MCFG1_PWEN_SHIFT )
-#define FTMCTRL_MCFG1_PWEN_SET( _reg, _val ) \
-  ( ( ( _reg ) & ~FTMCTRL_MCFG1_PWEN_MASK ) | \
-( ( ( _val ) << FTMCTRL_MCFG1_PWEN_SHIFT ) & \
-  FTMCTRL_MCFG1_PWEN_MASK ) )
-#define FTMCTRL_MCFG1_PWEN( _val ) \
-  ( ( ( _val ) << FTMCTRL_MCFG1_PWEN_SHIFT ) & \
-FTMCTRL_MCFG1_PWEN_MASK )
-
-#define FTMCTRL_MCFG1_PROM_WIDTH_SHIFT 12
-#define FTMCTRL_MCFG1_PROM_WIDTH_MASK 0x3000U
+#define FTMCTRL_MCFG1_PBRDY 0x4000U
+
+#define FTMCTRL_MCFG1_ABRDY 0x2000U
+
+#define FTMCTRL_MCFG1_IOBUSW_SHIFT 27
+#define FTMCTRL_MCFG1_IOBUSW_MASK 0x1800U
+#define FTMCTRL_MCFG1_IOBUSW_GET( _reg ) \
+  ( ( ( _reg ) & FTMCTRL_MCFG1_IOBUSW_MASK ) >> \
+FTMCTRL_MCFG1_IOBUSW_SHIFT )
+#define FTMCTRL_MCFG1_IOBUSW_SET( _reg, _val ) \
+  ( ( ( _reg ) & ~FTMCTRL_MCFG1_IOBUSW_MASK ) | \
+( ( ( _val ) << FTMCTRL_MCFG1_IOBUSW_SHIFT ) & \
+  FTMCTRL_MCFG1_IOBUSW_MASK ) )
+#define FTMCTRL_MCFG1_IOBUSW( _val ) \
+  ( ( ( _val ) << FTMCTRL_MCFG1_IOBUSW_SHIFT ) & \
+FTMCTRL_MCFG1_IOBUSW_MASK )
+
+#define FTMCTRL_MCFG1_IBRDY 0x400U
+
+#define FTMCTRL_MCFG1_BEXCN 0x200U
+
+#define FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT 20
+#define FTMCTRL_MCFG1_IO_WAITSTATES_MASK 0xf0U
+#define FTMCTRL_MCFG1_IO_WAITSTATES_GET( _reg ) \
+  ( ( ( _reg ) & FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) >> \
+FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT )
+#define FTMCTRL_MCFG1_IO_WAITSTATES_SET( _reg, _val ) \
+  ( ( ( _reg ) & ~FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) | \
+( ( ( _val ) << FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT ) & \
+  FTMCTRL_MCFG1_IO_WAITSTATES_MASK ) )
+#define FTMCTRL_MCFG1_IO_WAITSTATES( _val ) \
+  ( ( ( _val ) << FTMCTRL_MCFG1_IO_WAITSTATES_SHIFT ) & \
+FTMCTRL_MCFG1_IO_WAITSTATES_MASK )
+
+#define FTMCTRL_MCFG1_IOEN 0x8U
+
+#define FTMCTRL_MCFG1_R 0x4U
+
+#define FTMCTRL_MCFG1_ROMBANKSZ_SHIFT 14
+#define FTMCTRL_MCFG1_ROMBANKSZ_MASK 0x3c000U
+#define FTMCTRL_MCFG1_ROMBANKSZ_GET( _reg ) \
+  ( ( ( _reg ) & FTMCTRL_MCFG1_ROMBANKSZ_MASK ) >> \
+FTMCTRL_MCFG1_ROMBANKSZ_SHIFT )
+#define FTMCTRL_MCFG1_ROMBANKSZ_SET( _reg, _val ) \
+  ( ( ( _reg ) & ~FTMCTRL_MCFG1_ROMBANKSZ_MASK ) | \
+( ( ( _val ) << FTMCTRL_MCFG1_ROMBANKSZ_SHIFT ) & \
+  FTMCTRL_MCFG1_ROMBANKSZ_MASK ) )
+#define FTMCTRL_MCFG1_ROMBANKSZ( _val ) \
+  ( ( ( _val ) << FTMCTRL_MCFG1_ROMBANKSZ_SHIFT ) & \
+FTMCTRL_MCFG1_ROMBANKSZ_MASK )
+
+#define FTMCTRL_MCFG1_PWEN 0x800U
+
+#define FTMCTRL_MCFG1_PROM_WIDTH_SHIFT 8
+#define FTMCTRL_MCFG1_PROM_WIDTH_MASK 0x300U
 #define FTMCTRL_MCFG1_PROM_WIDTH_GET( _reg ) \
   ( ( ( _reg ) & FTMCTRL_MCFG1_PROM_WIDTH_MASK ) >> \
 FTMCTRL_MCFG1_PROM_WIDTH_SHIFT )
@@ -146,10 +148,21 @@ extern "C" {
   ( ( ( _val ) << FTMCTRL_MCFG1_PROM_WIDTH_SHIFT ) & \
 FTMCTRL_MCFG1_PROM_WIDTH_MASK )
 
-#define FTMCTRL_MCFG1_PROM_WRITE_WS 0x800U
-
-#define FTMCTRL_MCFG1_PROM_READ_WS_SHIFT 8
-#define FTMCTRL_MCFG1_PROM_READ_WS_MASK 0x300U
+#define FTMCTRL_MCFG1_PROM_WRITE_WS_SHIFT 4
+#define FTMCTRL_MCFG1_PROM_WRITE_WS_MASK 0xf0U
+#define FTMCTRL_MCFG1_PROM_WRITE_WS_GET( _reg ) \
+  ( ( ( _

[PATCH v3 11/38] bsps/grlib: Remove obsolete header file

[Sebastian Huber]

This header file was an incomplete duplicate of .

Update #4842.
---
 bsps/include/grlib/grspwrouter-regs.h | 890 --
 1 file changed, 890 deletions(-)
 delete mode 100644 bsps/include/grlib/grspwrouter-regs.h

diff --git a/bsps/include/grlib/grspwrouter-regs.h 
b/bsps/include/grlib/grspwrouter-regs.h
deleted file mode 100644
index f91c40dfe5..00
--- a/bsps/include/grlib/grspwrouter-regs.h
+++ /dev/null
@@ -1,890 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/**
- * @file
- *
- * @ingroup RTEMSDeviceGRSPWROUTER
- *
- * @brief This header file defines the GRSPWROUTER register block interface.
- */
-
-/*
- * Copyright (C) 2021 embedded brains GmbH & Co. KG
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *notice, this list of conditions and the following disclaimer in the
- *documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * This file is part of the RTEMS quality process and was automatically
- * generated.  If you find something that needs to be fixed or
- * worded better please post a report or patch to an RTEMS mailing list
- * or raise a bug report:
- *
- * https://www.rtems.org/bugs.html
- *
- * For information on updating and regenerating please refer to the How-To
- * section in the Software Requirements Engineering chapter of the
- * RTEMS Software Engineering manual.  The manual is provided as a part of
- * a release.  For development sources please refer to the online
- * documentation at:
- *
- * https://docs.rtems.org
- */
-
-/* Generated from spec:/dev/grlib/if/grspwrouter-header */
-
-#ifndef _GRLIB_GRSPWROUTER_REGS_H
-#define _GRLIB_GRSPWROUTER_REGS_H
-
-#include 
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Generated from spec:/dev/grlib/if/grspwrouter */
-
-/**
- * @defgroup RTEMSDeviceGRSPWROUTER GRSPWROUTER
- *
- * @ingroup RTEMSDeviceGRLIB
- *
- * @brief This group contains the GRSPWROUTER interfaces.
- *
- * @{
- */
-
-/**
- * @defgroup RTEMSDeviceGRSPWROUTERAMBACTRL AMBA port Control (AMBACTRL)
- *
- * @brief This group contains register bit definitions.
- *
- * @{
- */
-
-#define GRSPWROUTER_AMBACTRL_RA 0x8000U
-
-#define GRSPWROUTER_AMBACTRL_RX 0x4000U
-
-#define GRSPWROUTER_AMBACTRL_RC 0x2000U
-
-#define GRSPWROUTER_AMBACTRL_NCH_SHIFT 27
-#define GRSPWROUTER_AMBACTRL_NCH_MASK 0x1800U
-#define GRSPWROUTER_AMBACTRL_NCH_GET( _reg ) \
-  ( ( ( _reg ) & GRSPWROUTER_AMBACTRL_NCH_MASK ) >> \
-GRSPWROUTER_AMBACTRL_NCH_SHIFT )
-#define GRSPWROUTER_AMBACTRL_NCH_SET( _reg, _val ) \
-  ( ( ( _reg ) & ~GRSPWROUTER_AMBACTRL_NCH_MASK ) | \
-( ( ( _val ) << GRSPWROUTER_AMBACTRL_NCH_SHIFT ) & \
-  GRSPWROUTER_AMBACTRL_NCH_MASK ) )
-#define GRSPWROUTER_AMBACTRL_NCH( _val ) \
-  ( ( ( _val ) << GRSPWROUTER_AMBACTRL_NCH_SHIFT ) & \
-GRSPWROUTER_AMBACTRL_NCH_MASK )
-
-#define GRSPWROUTER_AMBACTRL_DI 0x100U
-
-#define GRSPWROUTER_AMBACTRL_ME 0x80U
-
-#define GRSPWROUTER_AMBACTRL_RD 0x2U
-
-#define GRSPWROUTER_AMBACTRL_RE 0x1U
-
-#define GRSPWROUTER_AMBACTRL_TQ 0x100U
-
-#define GRSPWROUTER_AMBACTRL_RS 0x40U
-
-#define GRSPWROUTER_AMBACTRL_PM 0x20U
-
-#define GRSPWROUTER_AMBACTRL_TI 0x10U
-
-#define GRSPWROUTER_AMBACTRL_IE 0x8U
-
-/** @} */
-
-/**
- * @defgroup RTEMSDeviceGRSPWROUTERAMBASTS AMBA port Status (AMBASTS)
- *
- * @brief This group contains register bit definitions.
- *
- * @{
- */
-
-#define GRSPWROUTER_AMBASTS_NIRQ_SHIFT 28
-#define GRSPWROUTER_AMBASTS_NIRQ_MASK 0x7000U
-#define GRSPWROUTER_AMBASTS_NIRQ_GET( _reg ) \
-  ( ( ( _reg ) & GRSPWROUTER_AMBASTS_NIRQ_MASK ) >> \
-GRSPWROUTER_AMBASTS_NIRQ_SHIFT )
-#define GRSPWROUTER_AMBASTS_NIRQ_SET( _reg, _val ) \
-  ( ( ( _reg ) & ~GRSPWROUTER_AMBASTS_NIRQ_MASK ) | \
-( ( ( _val ) << GRSPWROUTER_AMBASTS_NIRQ_SHIFT ) & \
-  GRSPWROUTER_AMBASTS_NIRQ_MASK ) )
-#define GRSPWROUTER_AMBASTS_NIRQ( _val 

[PATCH v3 08/38] bsps/grlib: Expand GRCLKGATE register bit fields

[Sebastian Huber]

Use the maximum width supported by the GRLIB even if this exceeds the
configuration limits of a particular IP instance.

Update #4842.
---
 bsps/include/grlib/grclkgate-regs.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/bsps/include/grlib/grclkgate-regs.h 
b/bsps/include/grlib/grclkgate-regs.h
index cf0a136802..22dae51207 100644
--- a/bsps/include/grlib/grclkgate-regs.h
+++ b/bsps/include/grlib/grclkgate-regs.h
@@ -82,7 +82,7 @@ extern "C" {
  */
 
 #define GRCLKGATE_UNLOCK_UNLOCK_SHIFT 0
-#define GRCLKGATE_UNLOCK_UNLOCK_MASK 0x7ffU
+#define GRCLKGATE_UNLOCK_UNLOCK_MASK 0xU
 #define GRCLKGATE_UNLOCK_UNLOCK_GET( _reg ) \
   ( ( ( _reg ) & GRCLKGATE_UNLOCK_UNLOCK_MASK ) >> \
 GRCLKGATE_UNLOCK_UNLOCK_SHIFT )
@@ -105,7 +105,7 @@ extern "C" {
  */
 
 #define GRCLKGATE_CLKEN_ENABLE_SHIFT 0
-#define GRCLKGATE_CLKEN_ENABLE_MASK 0x7ffU
+#define GRCLKGATE_CLKEN_ENABLE_MASK 0xU
 #define GRCLKGATE_CLKEN_ENABLE_GET( _reg ) \
   ( ( ( _reg ) & GRCLKGATE_CLKEN_ENABLE_MASK ) >> \
 GRCLKGATE_CLKEN_ENABLE_SHIFT )
@@ -128,7 +128,7 @@ extern "C" {
  */
 
 #define GRCLKGATE_RESET_RESET_SHIFT 0
-#define GRCLKGATE_RESET_RESET_MASK 0x7ffU
+#define GRCLKGATE_RESET_RESET_MASK 0xU
 #define GRCLKGATE_RESET_RESET_GET( _reg ) \
   ( ( ( _reg ) & GRCLKGATE_RESET_RESET_MASK ) >> \
 GRCLKGATE_RESET_RESET_SHIFT )
-- 
2.35.3

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[PATCH v3 09/38] bsps/grlib: Move GR740-specific registers

[Sebastian Huber]

Update #4842.
---
 bsps/include/grlib/gr740thsens-regs.h | 226 --
 bsps/include/grlib/grgprbank-regs.h   | 677 -
 .../leon3/include/bsp/gr740-bootstrap-regs.h} |  78 +-
 .../leon3/include/bsp/gr740-iopll-regs.h  | 679 ++
 .../leon3/include/bsp/gr740-thsens-regs.h | 229 ++
 5 files changed, 948 insertions(+), 941 deletions(-)
 delete mode 100644 bsps/include/grlib/gr740thsens-regs.h
 delete mode 100644 bsps/include/grlib/grgprbank-regs.h
 rename bsps/{include/grlib/grgpreg-regs.h => 
sparc/leon3/include/bsp/gr740-bootstrap-regs.h} (53%)
 create mode 100644 bsps/sparc/leon3/include/bsp/gr740-iopll-regs.h
 create mode 100644 bsps/sparc/leon3/include/bsp/gr740-thsens-regs.h

diff --git a/bsps/include/grlib/gr740thsens-regs.h 
b/bsps/include/grlib/gr740thsens-regs.h
deleted file mode 100644
index f9ec8103b9..00
--- a/bsps/include/grlib/gr740thsens-regs.h
+++ /dev/null
@@ -1,226 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/**
- * @file
- *
- * @ingroup RTEMSDeviceGR740THSENS
- *
- * @brief This header file defines the GR740THSENS register block interface.
- */
-
-/*
- * Copyright (C) 2021 embedded brains GmbH & Co. KG
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *notice, this list of conditions and the following disclaimer in the
- *documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * This file is part of the RTEMS quality process and was automatically
- * generated.  If you find something that needs to be fixed or
- * worded better please post a report or patch to an RTEMS mailing list
- * or raise a bug report:
- *
- * https://www.rtems.org/bugs.html
- *
- * For information on updating and regenerating please refer to the How-To
- * section in the Software Requirements Engineering chapter of the
- * RTEMS Software Engineering manual.  The manual is provided as a part of
- * a release.  For development sources please refer to the online
- * documentation at:
- *
- * https://docs.rtems.org
- */
-
-/* Generated from spec:/dev/grlib/if/gr740thsens-header */
-
-#ifndef _GRLIB_GR740THSENS_REGS_H
-#define _GRLIB_GR740THSENS_REGS_H
-
-#include 
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Generated from spec:/dev/grlib/if/gr740thsens */
-
-/**
- * @defgroup RTEMSDeviceGR740THSENS GR740THSENS
- *
- * @ingroup RTEMSDeviceGRLIB
- *
- * @brief This group contains the GR740THSENS interfaces.
- *
- * @{
- */
-
-/**
- * @defgroup RTEMSDeviceGR740THSENSCTRL Control register (CTRL)
- *
- * @brief This group contains register bit definitions.
- *
- * @{
- */
-
-#define GR740THSENS_CTRL_DIV_SHIFT 16
-#define GR740THSENS_CTRL_DIV_MASK 0x3ffU
-#define GR740THSENS_CTRL_DIV_GET( _reg ) \
-  ( ( ( _reg ) & GR740THSENS_CTRL_DIV_MASK ) >> \
-GR740THSENS_CTRL_DIV_SHIFT )
-#define GR740THSENS_CTRL_DIV_SET( _reg, _val ) \
-  ( ( ( _reg ) & ~GR740THSENS_CTRL_DIV_MASK ) | \
-( ( ( _val ) << GR740THSENS_CTRL_DIV_SHIFT ) & \
-  GR740THSENS_CTRL_DIV_MASK ) )
-#define GR740THSENS_CTRL_DIV( _val ) \
-  ( ( ( _val ) << GR740THSENS_CTRL_DIV_SHIFT ) & \
-GR740THSENS_CTRL_DIV_MASK )
-
-#define GR740THSENS_CTRL_ALEN 0x100U
-
-#define GR740THSENS_CTRL_PDN 0x80U
-
-#define GR740THSENS_CTRL_DCORRECT_SHIFT 2
-#define GR740THSENS_CTRL_DCORRECT_MASK 0x7cU
-#define GR740THSENS_CTRL_DCORRECT_GET( _reg ) \
-  ( ( ( _reg ) & GR740THSENS_CTRL_DCORRECT_MASK ) >> \
-GR740THSENS_CTRL_DCORRECT_SHIFT )
-#define GR740THSENS_CTRL_DCORRECT_SET( _reg, _val ) \
-  ( ( ( _reg ) & ~GR740THSENS_CTRL_DCORRECT_MASK ) | \
-( ( ( _val ) << GR740THSENS_CTRL_DCORRECT_SHIFT ) & \
-  GR740THSENS_CTRL_DCORRECT_MASK ) )
-#define GR740THSENS_CTRL_DCORRECT( _val ) \
-  ( ( ( _val ) << GR740THSENS_CTRL_DCORRECT_SHIFT ) & \
-GR740THSENS_CTRL_DCORRECT_MASK )
-
-#define GR740THSENS_CTRL_SRSTN 0x2U
-
-#define GR740THSENS

[PATCH v3 10/38] bsps/grlib: Use GRLIB definition of GRSPW2

[Sebastian Huber]

Update #4842.
---
 bsps/include/grlib/grspw2-regs.h | 1122 ++
 1 file changed, 982 insertions(+), 140 deletions(-)

diff --git a/bsps/include/grlib/grspw2-regs.h b/bsps/include/grlib/grspw2-regs.h
index 8e9661edc2..6293230cfe 100644
--- a/bsps/include/grlib/grspw2-regs.h
+++ b/bsps/include/grlib/grspw2-regs.h
@@ -9,7 +9,7 @@
  */
 
 /*
- * Copyright (C) 2021 embedded brains GmbH & Co. KG
+ * Copyright (C) 2021, 2023 embedded brains GmbH & Co. KG
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -61,6 +61,282 @@
 extern "C" {
 #endif
 
+/* Generated from spec:/dev/grlib/if/grspw2-dma */
+
+/**
+ * @defgroup RTEMSDeviceGRSPW2DMA GRSPW2 DMA
+ *
+ * @ingroup RTEMSDeviceGRSPW2
+ *
+ * @brief This group contains the GRSPW2 DMA interfaces.
+ *
+ * @{
+ */
+
+/**
+ * @defgroup RTEMSDeviceGRSPW2DMADMACTRL DMA control/status (DMACTRL)
+ *
+ * @brief This group contains register bit definitions.
+ *
+ * @{
+ */
+
+#define GRSPW2_DMACTRL_INTNUM_SHIFT 26
+#define GRSPW2_DMACTRL_INTNUM_MASK 0xfc00U
+#define GRSPW2_DMACTRL_INTNUM_GET( _reg ) \
+  ( ( ( _reg ) & GRSPW2_DMACTRL_INTNUM_MASK ) >> \
+GRSPW2_DMACTRL_INTNUM_SHIFT )
+#define GRSPW2_DMACTRL_INTNUM_SET( _reg, _val ) \
+  ( ( ( _reg ) & ~GRSPW2_DMACTRL_INTNUM_MASK ) | \
+( ( ( _val ) << GRSPW2_DMACTRL_INTNUM_SHIFT ) & \
+  GRSPW2_DMACTRL_INTNUM_MASK ) )
+#define GRSPW2_DMACTRL_INTNUM( _val ) \
+  ( ( ( _val ) << GRSPW2_DMACTRL_INTNUM_SHIFT ) & \
+GRSPW2_DMACTRL_INTNUM_MASK )
+
+#define GRSPW2_DMACTRL_RES_SHIFT 24
+#define GRSPW2_DMACTRL_RES_MASK 0x300U
+#define GRSPW2_DMACTRL_RES_GET( _reg ) \
+  ( ( ( _reg ) & GRSPW2_DMACTRL_RES_MASK ) >> \
+GRSPW2_DMACTRL_RES_SHIFT )
+#define GRSPW2_DMACTRL_RES_SET( _reg, _val ) \
+  ( ( ( _reg ) & ~GRSPW2_DMACTRL_RES_MASK ) | \
+( ( ( _val ) << GRSPW2_DMACTRL_RES_SHIFT ) & \
+  GRSPW2_DMACTRL_RES_MASK ) )
+#define GRSPW2_DMACTRL_RES( _val ) \
+  ( ( ( _val ) << GRSPW2_DMACTRL_RES_SHIFT ) & \
+GRSPW2_DMACTRL_RES_MASK )
+
+#define GRSPW2_DMACTRL_EP 0x80U
+
+#define GRSPW2_DMACTRL_TR 0x40U
+
+#define GRSPW2_DMACTRL_IE 0x20U
+
+#define GRSPW2_DMACTRL_IT 0x10U
+
+#define GRSPW2_DMACTRL_RP 0x8U
+
+#define GRSPW2_DMACTRL_TP 0x4U
+
+#define GRSPW2_DMACTRL_TL 0x2U
+
+#define GRSPW2_DMACTRL_LE 0x1U
+
+#define GRSPW2_DMACTRL_SP 0x8000U
+
+#define GRSPW2_DMACTRL_SA 0x4000U
+
+#define GRSPW2_DMACTRL_EN 0x2000U
+
+#define GRSPW2_DMACTRL_NS 0x1000U
+
+#define GRSPW2_DMACTRL_RD 0x800U
+
+#define GRSPW2_DMACTRL_RX 0x400U
+
+#define GRSPW2_DMACTRL_AT 0x200U
+
+#define GRSPW2_DMACTRL_RA 0x100U
+
+#define GRSPW2_DMACTRL_TA 0x80U
+
+#define GRSPW2_DMACTRL_PR 0x40U
+
+#define GRSPW2_DMACTRL_PS 0x20U
+
+#define GRSPW2_DMACTRL_AI 0x10U
+
+#define GRSPW2_DMACTRL_RI 0x8U
+
+#define GRSPW2_DMACTRL_TI 0x4U
+
+#define GRSPW2_DMACTRL_RE 0x2U
+
+#define GRSPW2_DMACTRL_TE 0x1U
+
+/** @} */
+
+/**
+ * @defgroup RTEMSDeviceGRSPW2DMADMAMAXLEN DMA RX maximum length (DMAMAXLEN)
+ *
+ * @brief This group contains register bit definitions.
+ *
+ * @{
+ */
+
+#define GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT 2
+#define GRSPW2_DMAMAXLEN_RXMAXLEN_MASK 0x1fcU
+#define GRSPW2_DMAMAXLEN_RXMAXLEN_GET( _reg ) \
+  ( ( ( _reg ) & GRSPW2_DMAMAXLEN_RXMAXLEN_MASK ) >> \
+GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT )
+#define GRSPW2_DMAMAXLEN_RXMAXLEN_SET( _reg, _val ) \
+  ( ( ( _reg ) & ~GRSPW2_DMAMAXLEN_RXMAXLEN_MASK ) | \
+( ( ( _val ) << GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT ) & \
+  GRSPW2_DMAMAXLEN_RXMAXLEN_MASK ) )
+#define GRSPW2_DMAMAXLEN_RXMAXLEN( _val ) \
+  ( ( ( _val ) << GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT ) & \
+GRSPW2_DMAMAXLEN_RXMAXLEN_MASK )
+
+#define GRSPW2_DMAMAXLEN_RES_SHIFT 0
+#define GRSPW2_DMAMAXLEN_RES_MASK 0x3U
+#define GRSPW2_DMAMAXLEN_RES_GET( _reg ) \
+  ( ( ( _reg ) & GRSPW2_DMAMAXLEN_RES_MASK ) >> \
+GRSPW2_DMAMAXLEN_RES_SHIFT )
+#define GRSPW2_DMAMAXLEN_RES_SET( _reg, _val ) \
+  ( ( ( _reg ) & ~GRSPW2_DMAMAXLEN_RES_MASK ) | \
+( ( ( _val ) << GRSPW2_DMAMAXLEN_RES_SHIFT ) & \
+  GRSPW2_DMAMAXLEN_RES_MASK ) )
+#define GRSPW2_DMAMAXLEN_RES( _val ) \
+  ( ( ( _val ) << GRSPW2_DMAMAXLEN_RES_SHIFT ) & \
+GRSPW2_DMAMAXLEN_RES_MASK )
+
+/** @} */
+
+/**
+ * @defgroup RTEMSDeviceGRSPW2DMADMATXDESC \
+ *   DMA transmit descriptor table address (DMATXDESC)
+ *
+ * @brief This group contains register bit definitions.
+ *
+ * @{
+ */
+
+#define GRSPW2_DMATXDESC_DESCBASEADDR_SHIFT 0
+#define GRSPW2_DMATXDESC_DESCBASEADDR_MASK 0xU
+#define GRSPW2_DMATXDESC_DESCBASEADDR_GET( _reg ) \
+  ( ( ( _reg ) & GRSPW2_DMATXDESC_DESCBASEADDR_MASK ) >> \
+GRSPW2_DMATXDESC_DESCBASEADDR_SHIFT )
+#define GRSPW2_DMATXDESC_DESCBASEADDR_SET( _reg, _val ) \
+  ( ( ( _reg ) & ~GRSPW2_DMATXDESC_DESCBASEADDR_MASK ) | \
+( ( ( _val ) << GRSPW2_DMATXDESC_DESCBASEADDR_SHIFT ) & \
+  GRSPW2_DMATXDESC_DESCBASEADDR_MASK ) )
+#define GRSPW2_DMATXDESC_DESCBASEADDR( _val )

[PATCH v3 19/38] bsp/leon3: Use new L2CACHE register block API

[Sebastian Huber]

---
 bsps/sparc/leon3/start/cache.c | 38 --
 1 file changed, 23 insertions(+), 15 deletions(-)

diff --git a/bsps/sparc/leon3/start/cache.c b/bsps/sparc/leon3/start/cache.c
index 676f591857..ed6fb5733d 100644
--- a/bsps/sparc/leon3/start/cache.c
+++ b/bsps/sparc/leon3/start/cache.c
@@ -6,9 +6,13 @@
  * http://www.rtems.org/license/LICENSE.
  */
 
-#include 
+#include 
+#include 
+
 #include 
 
+#include 
+
 #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
 
 #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS
@@ -19,12 +23,11 @@
 
 #define CPU_DATA_CACHE_ALIGNMENT 64
 
-static inline volatile struct l2c_regs *get_l2c_regs(void)
+static inline l2cache *get_l2c_regs(void)
 {
-  volatile struct l2c_regs *l2c = NULL;
   struct ambapp_dev *adev;
 
-  adev = (void *) ambapp_for_each(
+  adev = (struct ambapp_dev *) ambapp_for_each(
 ambapp_plb(),
 OPTIONS_ALL | OPTIONS_AHB_SLVS,
 VENDOR_GAISLER,
@@ -32,27 +35,32 @@ static inline volatile struct l2c_regs *get_l2c_regs(void)
 ambapp_find_by_idx,
 NULL
   );
-  if (adev != NULL) {
-l2c = (volatile struct l2c_regs *) DEV_TO_AHB(adev)->start[1];
+
+  if (adev == NULL) {
+return NULL;
   }
 
-  return l2c;
+  return (l2cache *) DEV_TO_AHB(adev)->start[1];
 }
 
 static inline size_t get_l2_size(void)
 {
-  size_t size = 0;
-  volatile struct l2c_regs *l2c = get_l2c_regs();
+  l2cache *regs;
+  unsigned status;
+  unsigned ways;
+  unsigned set_size;
 
-  if (l2c != NULL) {
-unsigned status = l2c->status;
-unsigned ways = (status & 0x3) + 1;
-unsigned set_size = ((status & 0x7ff) >> 2) * 1024;
+  regs = get_l2c_regs();
 
-size = ways * set_size;
+  if (regs == NULL) {
+return 0;
   }
 
-  return size;
+  status = grlib_load_32(®s->l2cs);
+  ways = L2CACHE_L2CS_WAY_GET(status) + 1;
+  set_size = L2CACHE_L2CS_WAY_SIZE_GET(status) * 1024;
+
+  return ways * set_size;
 }
 
 static inline size_t get_l1_size(uint32_t l1_cfg)
-- 
2.35.3

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[PATCH v3 14/38] bsp/leon3: Untangle interrupt controller support

[Sebastian Huber]

Separate the probing of the interrupt controller from the
initialization.
---
 bsps/sparc/leon3/include/bsp/irqimpl.h | 83 ++
 bsps/sparc/leon3/include/leon.h| 10 +---
 bsps/sparc/leon3/start/amba.c  |  9 ---
 bsps/sparc/leon3/start/eirq.c  | 15 -
 spec/build/bsps/sparc/leon3/obj.yml|  1 +
 5 files changed, 97 insertions(+), 21 deletions(-)
 create mode 100644 bsps/sparc/leon3/include/bsp/irqimpl.h

diff --git a/bsps/sparc/leon3/include/bsp/irqimpl.h 
b/bsps/sparc/leon3/include/bsp/irqimpl.h
new file mode 100644
index 00..77619c99b9
--- /dev/null
+++ b/bsps/sparc/leon3/include/bsp/irqimpl.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsSPARCLEON3
+ *
+ * @brief This header file provides interfaces used by the interrupt support
+ *   implementation.
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_SPARC_LEON3_BSP_IRQIMPL_H
+#define LIBBSP_SPARC_LEON3_BSP_IRQIMPL_H
+
+#include 
+#include 
+
+struct ambapp_dev;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @addtogroup RTEMSBSPsSPARCLEON3
+ *
+ * @{
+ */
+
+/**
+ * @brief This lock serializes the interrupt controller access.
+ */
+extern rtems_interrupt_lock LEON3_IrqCtrl_Lock;
+
+/**
+ * @brief This pointer provides the IRQ(A)MP register block address.
+ */
+extern volatile struct irqmp_regs *LEON3_IrqCtrl_Regs;
+
+/**
+ * @brief This pointer provides the IRQ(A)MP device information block.
+ */
+extern struct ambapp_dev *LEON3_IrqCtrl_Adev;
+
+/**
+ * @brief Initializes the interrupt controller for the boot processor.
+ *
+ * @param[in, out] regs is the IRQ(A)MP register block address.
+ */
+void leon3_ext_irq_init( volatile struct irqmp_regs *regs );
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LIBBSP_SPARC_LEON3_BSP_IRQIMPL_H */
diff --git a/bsps/sparc/leon3/include/leon.h b/bsps/sparc/leon3/include/leon.h
index 6294feb8a7..0382e1b7e3 100644
--- a/bsps/sparc/leon3/include/leon.h
+++ b/bsps/sparc/leon3/include/leon.h
@@ -44,6 +44,7 @@
 
 #include 
 #include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
@@ -146,10 +147,6 @@ extern "C" {
 #define LEON3_REG_CACHE_CTRL_FI  0x0020 /* Flush instruction cache */
 #define LEON3_REG_CACHE_CTRL_DS  0x0080 /* Data cache snooping */
 
-/* LEON3 Interrupt Controller */
-extern volatile struct irqmp_regs *LEON3_IrqCtrl_Regs;
-extern struct ambapp_dev *LEON3_IrqCtrl_Adev;
-
 /* LEON3 GP Timer */
 extern volatile struct gptimer_regs *LEON3_Timer_Regs;
 extern struct ambapp_dev *LEON3_Timer_Adev;
@@ -193,8 +190,6 @@ static __inline__ int bsp_irq_fixup(int irq)
  *store the result back are vulnerable.
  */
 
-extern rtems_interrupt_lock LEON3_IrqCtrl_Lock;
-
 #define LEON3_IRQCTRL_ACQUIRE( _lock_context ) \
   rtems_interrupt_lock_acquire( &LEON3_IrqCtrl_Lock, _lock_context )
 
@@ -410,9 +405,6 @@ extern int leon3_timer_core_index;
  */
 extern unsigned int leon3_timer_prescaler;
 
-/* GRLIB extended IRQ controller register */
-void leon3_ext_irq_init(void);
-
 RTEMS_NO_RETURN void leon3_power_down_loop(void);
 
 static inline uint32_t leon3_get_cpu_count(
diff --git a/bsps/sparc/leon3/start/amba.c b/bsps/sparc/leon3/start/amba.c
index 15b72dcbe8..5ce3de6bdd 100644
--- a/bsps/sparc/leon3/start/amba.c
+++ b/bsps/sparc/leon3/start/amba.c
@@ -115,9 +115,6 @@ RTEMS_SYSINIT_ITEM(
 );
 #endif
 
-rtems_interrupt_lock LEON3_IrqCtrl_Lock =
-  RTEMS_INTERRUPT_LOCK_INITIALIZER("LEON3 IrqCtrl");
-
 /* Pointers to Interrupt Controller configuration registers */
 volatile struct irqmp_regs *LEON3_IrqCtrl_Regs;
 struct ambapp_dev *LEON

[PATCH v3 32/38] bsp/leon3: Enable up-counter conditionally

[Sebastian Huber]

---
 bsps/sparc/leon3/clock/ckinit.c | 5 +++--
 bsps/sparc/leon3/start/cpucounter.c | 5 +++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/bsps/sparc/leon3/clock/ckinit.c b/bsps/sparc/leon3/clock/ckinit.c
index 93826416c0..4767d57347 100644
--- a/bsps/sparc/leon3/clock/ckinit.c
+++ b/bsps/sparc/leon3/clock/ckinit.c
@@ -287,12 +287,13 @@ static void leon3_clock_initialize(void)
   tc->tc_counter_mask = 0x;
   tc->tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER;
 
-  leon3_up_counter_enable();
-
 #if defined(LEON3_HAS_ASR_22_23_UP_COUNTER)
+  leon3_up_counter_enable();
   leon3_clock_use_up_counter(tc);
 #else /* LEON3_HAS_ASR_22_23_UP_COUNTER */
 #if defined(LEON3_PROBE_ASR_22_23_UP_COUNTER)
+  leon3_up_counter_enable();
+
   if (leon3_up_counter_is_available()) {
 /* Use the LEON4 up-counter if available */
 leon3_clock_use_up_counter(tc);
diff --git a/bsps/sparc/leon3/start/cpucounter.c 
b/bsps/sparc/leon3/start/cpucounter.c
index 05ac62ace8..6af91f75e5 100644
--- a/bsps/sparc/leon3/start/cpucounter.c
+++ b/bsps/sparc/leon3/start/cpucounter.c
@@ -106,12 +106,13 @@ static void leon3_counter_initialize(void)
 
   counter = &_SPARC_Counter_mutable;
 
-  leon3_up_counter_enable();
-
 #if defined(LEON3_HAS_ASR_22_23_UP_COUNTER)
+  leon3_up_counter_enable();
   leon3_counter_use_up_counter(counter);
 #else /* LEON3_HAS_ASR_22_23_UP_COUNTER */
 #if defined(LEON3_PROBE_ASR_22_23_UP_COUNTER)
+  leon3_up_counter_enable();
+
   if (leon3_up_counter_is_available()) {
 /* Use the LEON4 up-counter if available */
 leon3_counter_use_up_counter(counter);
-- 
2.35.3

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[PATCH v3 27/38] bsp/leon3: Move leon3_power_down_loop()

[Sebastian Huber]

---
 bsps/sparc/leon3/include/bsp/leon3.h| 6 ++
 bsps/sparc/leon3/include/leon.h | 2 --
 bsps/sparc/leon3/start/bsp_fatal_halt.c | 2 +-
 bsps/sparc/leon3/start/bspclean.c   | 3 +--
 4 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/bsps/sparc/leon3/include/bsp/leon3.h 
b/bsps/sparc/leon3/include/bsp/leon3.h
index f9717c364c..1394dd1c1c 100644
--- a/bsps/sparc/leon3/include/bsp/leon3.h
+++ b/bsps/sparc/leon3/include/bsp/leon3.h
@@ -56,6 +56,12 @@ extern "C" {
  * @{
  */
 
+/**
+ * @brief Sets %asr19 to zero to enter the power-down mode of the processor in
+ *   an infinite loop.
+ */
+RTEMS_NO_RETURN void leon3_power_down_loop( void );
+
 /**
  * @brief This constant represents the flush instruction cache flag of the LEON
  *   cache control register.
diff --git a/bsps/sparc/leon3/include/leon.h b/bsps/sparc/leon3/include/leon.h
index fba64addfe..54d566799a 100644
--- a/bsps/sparc/leon3/include/leon.h
+++ b/bsps/sparc/leon3/include/leon.h
@@ -361,8 +361,6 @@ extern int leon3_timer_core_index;
  */
 extern unsigned int leon3_timer_prescaler;
 
-RTEMS_NO_RETURN void leon3_power_down_loop(void);
-
 #endif /* !ASM */
 
 #ifdef __cplusplus
diff --git a/bsps/sparc/leon3/start/bsp_fatal_halt.c 
b/bsps/sparc/leon3/start/bsp_fatal_halt.c
index 7462ab944c..ce628065b7 100644
--- a/bsps/sparc/leon3/start/bsp_fatal_halt.c
+++ b/bsps/sparc/leon3/start/bsp_fatal_halt.c
@@ -31,7 +31,7 @@
  */
 
 #include 
-#include 
+#include 
 #include 
 
 void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
diff --git a/bsps/sparc/leon3/start/bspclean.c 
b/bsps/sparc/leon3/start/bspclean.c
index 7414a61b83..acb2d6093c 100644
--- a/bsps/sparc/leon3/start/bspclean.c
+++ b/bsps/sparc/leon3/start/bspclean.c
@@ -34,10 +34,9 @@
 
 #include 
 #include 
+#include 
 #include 
 
-#include 
-
 void bsp_fatal_extension(
   rtems_fatal_source source,
   bool always_set_to_false,
-- 
2.35.3

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[PATCH v3 29/38] bsp/leon3: Add LEON3_PROBE_ASR_22_23_UP_COUNTER

[Sebastian Huber]

---
 bsps/sparc/leon3/clock/ckinit.c   |  5 +
 bsps/sparc/leon3/start/cpucounter.c   |  5 +
 spec/build/bsps/sparc/leon3/grp.yml   |  2 ++
 .../bsps/sparc/leon3/optasrupcntprobe.yml | 19 +++
 4 files changed, 31 insertions(+)
 create mode 100644 spec/build/bsps/sparc/leon3/optasrupcntprobe.yml

diff --git a/bsps/sparc/leon3/clock/ckinit.c b/bsps/sparc/leon3/clock/ckinit.c
index 0c8a0a8754..93826416c0 100644
--- a/bsps/sparc/leon3/clock/ckinit.c
+++ b/bsps/sparc/leon3/clock/ckinit.c
@@ -183,6 +183,8 @@ static void 
bsp_clock_handler_install(rtems_interrupt_handler isr)
 #define Clock_driver_support_set_interrupt_affinity(online_processors) \
   bsp_interrupt_set_affinity(clkirq, online_processors)
 
+#if defined(LEON3_HAS_ASR_22_23_UP_COUNTER) || \
+   defined(LEON3_PROBE_ASR_22_23_UP_COUNTER)
 static void leon3_clock_use_up_counter(struct timecounter *tc)
 {
   tc->tc_get_timecount = _SPARC_Get_timecount_asr23;
@@ -198,6 +200,7 @@ static void leon3_clock_use_up_counter(struct timecounter 
*tc)
 
   rtems_timecounter_install(tc);
 }
+#endif
 
 #if defined(LEON3_IRQAMP_PROBE_TIMESTAMP)
 static void leon3_clock_use_irqamp_timestamp(
@@ -289,11 +292,13 @@ static void leon3_clock_initialize(void)
 #if defined(LEON3_HAS_ASR_22_23_UP_COUNTER)
   leon3_clock_use_up_counter(tc);
 #else /* LEON3_HAS_ASR_22_23_UP_COUNTER */
+#if defined(LEON3_PROBE_ASR_22_23_UP_COUNTER)
   if (leon3_up_counter_is_available()) {
 /* Use the LEON4 up-counter if available */
 leon3_clock_use_up_counter(tc);
 return;
   }
+#endif
 
 #if defined(LEON3_IRQAMP_PROBE_TIMESTAMP)
   irqmp_ts = irqamp_get_timestamp_registers(LEON3_IrqCtrl_Regs);
diff --git a/bsps/sparc/leon3/start/cpucounter.c 
b/bsps/sparc/leon3/start/cpucounter.c
index d09dbe651b..46e0b304e5 100644
--- a/bsps/sparc/leon3/start/cpucounter.c
+++ b/bsps/sparc/leon3/start/cpucounter.c
@@ -39,6 +39,8 @@ uint32_t _CPU_Counter_frequency(void)
   return leon3_counter_frequency;
 }
 
+#if defined(LEON3_HAS_ASR_22_23_UP_COUNTER) || \
+   defined(LEON3_PROBE_ASR_22_23_UP_COUNTER)
 static void leon3_counter_use_up_counter(SPARC_Counter *counter)
 {
   counter->read_isr_disabled = _SPARC_Counter_read_asr23;
@@ -46,6 +48,7 @@ static void leon3_counter_use_up_counter(SPARC_Counter 
*counter)
 
   leon3_counter_frequency = leon3_up_counter_frequency();
 }
+#endif
 
 #if defined(LEON3_IRQAMP_PROBE_TIMESTAMP)
 static void leon3_counter_use_irqamp_timestamp(
@@ -108,11 +111,13 @@ static void leon3_counter_initialize(void)
 #if defined(LEON3_HAS_ASR_22_23_UP_COUNTER)
   leon3_counter_use_up_counter(counter);
 #else /* LEON3_HAS_ASR_22_23_UP_COUNTER */
+#if defined(LEON3_PROBE_ASR_22_23_UP_COUNTER)
   if (leon3_up_counter_is_available()) {
 /* Use the LEON4 up-counter if available */
 leon3_counter_use_up_counter(counter);
 return;
   }
+#endif
 
 #if defined(LEON3_IRQAMP_PROBE_TIMESTAMP)
   irqmp_ts = irqamp_get_timestamp_registers(LEON3_IrqCtrl_Regs);
diff --git a/spec/build/bsps/sparc/leon3/grp.yml 
b/spec/build/bsps/sparc/leon3/grp.yml
index 6d7a1b75c3..94d11bed55 100644
--- a/spec/build/bsps/sparc/leon3/grp.yml
+++ b/spec/build/bsps/sparc/leon3/grp.yml
@@ -36,6 +36,8 @@ links:
   uid: optapbuartbase
 - role: build-dependency
   uid: optasrupcnt
+- role: build-dependency
+  uid: optasrupcntprobe
 - role: build-dependency
   uid: optgptimerbase
 - role: build-dependency
diff --git a/spec/build/bsps/sparc/leon3/optasrupcntprobe.yml 
b/spec/build/bsps/sparc/leon3/optasrupcntprobe.yml
new file mode 100644
index 00..73c9cb6685
--- /dev/null
+++ b/spec/build/bsps/sparc/leon3/optasrupcntprobe.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+default:
+- enabled-by:
+  - sparc/gr712rc
+  - sparc/gr740
+  value: false
+enabled-by: true
+links: []
+name: LEON3_PROBE_ASR_22_23_UP_COUNTER
+description: |
+  If this option is set to true, then it will be probed if the %asr22 and
+  %asr23 up-counter is available.
+type: build
-- 
2.35.3

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[PATCH v3 36/38] validation: grlib

[Sebastian Huber]

---
 .../testsuites/validation/bsps/objgrlib.yml   |  16 +
 .../validation/bsps/validation-bsp-0.yml  |  23 ++
 spec/build/testsuites/validation/grp.yml  |   3 +
 .../validation/bsps/ts-validation-bsp-0.c |  73 
 .../tc-dev-grlib-apbuart-inbyte-nonblocking.c | 348 ++
 testsuites/validation/tc-dev-grlib-io.c   | 295 +++
 .../tc-dev-grlib-irqamp-get-timestamp.c   | 304 +++
 7 files changed, 1062 insertions(+)
 create mode 100644 spec/build/testsuites/validation/bsps/objgrlib.yml
 create mode 100644 spec/build/testsuites/validation/bsps/validation-bsp-0.yml
 create mode 100644 testsuites/validation/bsps/ts-validation-bsp-0.c
 create mode 100644 
testsuites/validation/tc-dev-grlib-apbuart-inbyte-nonblocking.c
 create mode 100644 testsuites/validation/tc-dev-grlib-io.c
 create mode 100644 testsuites/validation/tc-dev-grlib-irqamp-get-timestamp.c

diff --git a/spec/build/testsuites/validation/bsps/objgrlib.yml 
b/spec/build/testsuites/validation/bsps/objgrlib.yml
new file mode 100644
index 00..9a5df84195
--- /dev/null
+++ b/spec/build/testsuites/validation/bsps/objgrlib.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: objects
+cflags: []
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+cppflags: []
+cxxflags: []
+enabled-by: bsps/sparc/leon3
+includes: []
+install: []
+links: []
+source:
+- testsuites/validation/tc-dev-grlib-apbuart-inbyte-nonblocking.c
+- testsuites/validation/tc-dev-grlib-io.c
+- testsuites/validation/tc-dev-grlib-irqamp-get-timestamp.c
+type: build
diff --git a/spec/build/testsuites/validation/bsps/validation-bsp-0.yml 
b/spec/build/testsuites/validation/bsps/validation-bsp-0.yml
new file mode 100644
index 00..0ce137cce9
--- /dev/null
+++ b/spec/build/testsuites/validation/bsps/validation-bsp-0.yml
@@ -0,0 +1,23 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: test-program
+cflags: []
+copyrights:
+- Copyright (C) 2023 embedded brains GmbH & Co. KG
+cppflags: []
+cxxflags: []
+enabled-by: bsps/sparc/leon3
+features: c cprogram
+includes: []
+ldflags:
+- -Wl,--wrap=_IO_Relax
+links:
+- role: build-dependency
+  uid: objgrlib
+source:
+- testsuites/validation/bsps/ts-validation-bsp-0.c
+stlib: []
+target: testsuites/validation/bsps/ts-validation-bsp-0.exe
+type: build
+use-after:
+- validation
+use-before: []
diff --git a/spec/build/testsuites/validation/grp.yml 
b/spec/build/testsuites/validation/grp.yml
index 9aa9daff44..9000cf9624 100644
--- a/spec/build/testsuites/validation/grp.yml
+++ b/spec/build/testsuites/validation/grp.yml
@@ -10,6 +10,7 @@ enabled-by:
 - BUILD_VALIDATIONTESTS
 includes:
 - ${BSP_INCLUDES}
+- testsuites/validation
 install: []
 ldflags: []
 links:
@@ -79,6 +80,8 @@ links:
   uid: validation-tls-0
 - role: build-dependency
   uid: validation-tls-1
+- role: build-dependency
+  uid: bsps/validation-bsp-0
 type: build
 use-after:
 - validation
diff --git a/testsuites/validation/bsps/ts-validation-bsp-0.c 
b/testsuites/validation/bsps/ts-validation-bsp-0.c
new file mode 100644
index 00..c072c8fdf1
--- /dev/null
+++ b/testsuites/validation/bsps/ts-validation-bsp-0.c
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup TestsuitesBspsValidationBsp0
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated.  If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://

[PATCH v3 15/38] bsp/leon3: Move and simplify bsp_irq_fixup()

[Sebastian Huber]

---
 bsps/sparc/erc32/include/bsp/irqimpl.h   | 63 
 bsps/sparc/erc32/include/erc32.h |  5 --
 bsps/sparc/leon2/include/bsp/irqimpl.h   | 63 
 bsps/sparc/leon2/include/leon.h  |  5 --
 bsps/sparc/leon3/clock/ckinit.c  |  4 +-
 bsps/sparc/leon3/include/bsp/irq.h   |  1 -
 bsps/sparc/leon3/include/bsp/irqimpl.h   | 31 
 bsps/sparc/leon3/include/leon.h  | 18 ---
 bsps/sparc/leon3/start/eirq.c|  8 +--
 bsps/sparc/shared/irq/bsp_isr_handler.c  |  1 +
 spec/build/bsps/sparc/erc32/bsperc32.yml |  1 +
 spec/build/bsps/sparc/leon2/obj.yml  |  1 +
 12 files changed, 164 insertions(+), 37 deletions(-)
 create mode 100644 bsps/sparc/erc32/include/bsp/irqimpl.h
 create mode 100644 bsps/sparc/leon2/include/bsp/irqimpl.h

diff --git a/bsps/sparc/erc32/include/bsp/irqimpl.h 
b/bsps/sparc/erc32/include/bsp/irqimpl.h
new file mode 100644
index 00..6a8b17f188
--- /dev/null
+++ b/bsps/sparc/erc32/include/bsp/irqimpl.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsSPARCERC32
+ *
+ * @brief This header file provides interfaces used by the interrupt support
+ *   implementation.
+ */
+
+/*
+ * Copyright (C) 2023 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_SPARC_ERC32_BSP_IRQIMPL_H
+#define LIBBSP_SPARC_ERC32_BSP_IRQIMPL_H
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @addtogroup RTEMSBSPsSPARCERC32
+ *
+ * @{
+ */
+
+static inline uint32_t bsp_irq_fixup( uint32_t irq )
+{
+  return irq;
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LIBBSP_SPARC_ERC32_BSP_IRQIMPL_H */
diff --git a/bsps/sparc/erc32/include/erc32.h b/bsps/sparc/erc32/include/erc32.h
index f9cdbc960a..3967f4c918 100644
--- a/bsps/sparc/erc32/include/erc32.h
+++ b/bsps/sparc/erc32/include/erc32.h
@@ -326,11 +326,6 @@ typedef struct {
 
 extern ERC32_Register_Map ERC32_MEC;
 
-static __inline__ int bsp_irq_fixup(int irq)
-{
-   return irq;
-}
-
 /*
  *  Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask,
  *  and the Interrupt Pending Registers.
diff --git a/bsps/sparc/leon2/include/bsp/irqimpl.h 
b/bsps/sparc/leon2/include/bsp/irqimpl.h
new file mode 100644
index 00..868822f3aa
--- /dev/null
+++ b/bsps/sparc/leon2/include/bsp/irqimpl.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsSPARCLEON2
+ *
+ * @brief This header file provides interfaces used by the interrupt support
+ *   implementation.
+ */
+
+/*
+ * Copyright (C) 2023 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERV

[PATCH v3 35/38] bsp/leon3: Add specialized target hash

[Sebastian Huber]

---
 bsps/sparc/leon3/start/gettargethash.c | 71 ++
 spec/build/bsps/sparc/leon3/obj.yml|  2 +-
 2 files changed, 72 insertions(+), 1 deletion(-)
 create mode 100644 bsps/sparc/leon3/start/gettargethash.c

diff --git a/bsps/sparc/leon3/start/gettargethash.c 
b/bsps/sparc/leon3/start/gettargethash.c
new file mode 100644
index 00..c51031dc4f
--- /dev/null
+++ b/bsps/sparc/leon3/start/gettargethash.c
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsSPARCLEON3
+ *
+ * @brief This source file contains the sparc/leon3 implementation of
+ *   rtems_get_target_hash().
+ */
+
+/*
+ * Copyright (C) 2021, 2022 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+static Hash_Control bsp_target_hash;
+
+static void bsp_target_hash_initialize( void )
+{
+  Hash_Context context;
+  uint32_t frequency;
+
+  _Hash_Initialize( &context );
+
+  frequency = rtems_counter_frequency();
+  _Hash_Add_data( &context, &frequency, sizeof( frequency ) );
+
+  frequency = leon3_processor_local_bus_frequency();
+  _Hash_Add_data( &context, &frequency, sizeof( frequency ) );
+
+  _Hash_Finalize( &context, &bsp_target_hash );
+}
+
+const char *rtems_get_target_hash( void )
+{
+  return _Hash_Get_string( &bsp_target_hash );
+}
+
+RTEMS_SYSINIT_ITEM(
+  bsp_target_hash_initialize,
+  RTEMS_SYSINIT_TARGET_HASH,
+  RTEMS_SYSINIT_ORDER_SECOND
+);
diff --git a/spec/build/bsps/sparc/leon3/obj.yml 
b/spec/build/bsps/sparc/leon3/obj.yml
index fed50499b4..7a4ccaa0cb 100644
--- a/spec/build/bsps/sparc/leon3/obj.yml
+++ b/spec/build/bsps/sparc/leon3/obj.yml
@@ -32,7 +32,6 @@ source:
 - bsps/shared/dev/serial/console-termios.c
 - bsps/shared/irq/irq-default-handler.c
 - bsps/shared/start/bspreset-empty.c
-- bsps/shared/start/gettargethash-default.c
 - bsps/shared/start/sbrk.c
 - bsps/sparc/leon3/btimer/btimer.c
 - bsps/sparc/leon3/btimer/watchdog.c
@@ -49,6 +48,7 @@ source:
 - bsps/sparc/leon3/start/cpucounter.c
 - bsps/sparc/leon3/start/drvmgr_def_drivers.c
 - bsps/sparc/leon3/start/eirq.c
+- bsps/sparc/leon3/start/gettargethash.c
 - bsps/sparc/leon3/start/setvec.c
 - bsps/sparc/shared/gnatcommon.c
 - bsps/sparc/shared/irq/bsp_isr_handler.c
-- 
2.35.3

___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel

[PATCH v3 17/38] bsp/leon3: Move system control register support

[Sebastian Huber]

Move, document, and reformat support functions from  to
.
---
 bsps/sparc/leon3/include/bsp/leon3.h | 173 +++
 bsps/sparc/leon3/include/leon.h  | 100 +---
 bsps/sparc/leon3/start/bspsmp.c  |   1 -
 bsps/sparc/leon3/start/bspstart.c|   2 +-
 bsps/sparc/leon3/start/cache.c   |   2 +-
 5 files changed, 176 insertions(+), 102 deletions(-)

diff --git a/bsps/sparc/leon3/include/bsp/leon3.h 
b/bsps/sparc/leon3/include/bsp/leon3.h
index a5559bc7b9..75abc34fb7 100644
--- a/bsps/sparc/leon3/include/bsp/leon3.h
+++ b/bsps/sparc/leon3/include/bsp/leon3.h
@@ -38,6 +38,10 @@
 
 #include 
 
+#include 
+
+#include 
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -48,6 +52,175 @@ extern "C" {
  * @{
  */
 
+/**
+ * @brief This constant represents the flush instruction cache flag of the LEON
+ *   cache control register.
+ */
+#define LEON3_REG_CACHE_CTRL_FI 0x0020U
+
+/**
+ * @brief This constant represents the data cache snooping enable flag of the
+ *   LEON cache control register.
+ */
+#define LEON3_REG_CACHE_CTRL_DS 0x0080U
+
+/**
+ * @brief Sets the ASI 0x2 system register value.
+ *
+ * @param addr is the address of the ASI 0x2 system register.
+ *
+ * @param val is the value to set.
+ */
+static inline void leon3_set_system_register( uint32_t addr, uint32_t val )
+{
+  __asm__ volatile(
+"sta %1, [%0] 2"
+:
+: "r" ( addr ), "r" ( val )
+  );
+}
+
+/**
+ * @brief Gets the ASI 0x2 system register value.
+ *
+ * @param addr is the address of the ASI 0x2 system register.
+ *
+ * @return Returns the register value.
+ */
+static inline uint32_t leon3_get_system_register( uint32_t addr )
+{
+  uint32_t val;
+
+  __asm__ volatile(
+"lda [%1] 2, %0"
+: "=r" ( val )
+: "r" ( addr )
+  );
+
+  return val;
+}
+
+/**
+ * @brief Sets the LEON cache control register value.
+ *
+ * @param val is the value to set.
+ */
+static inline void leon3_set_cache_control_register( uint32_t val )
+{
+  leon3_set_system_register( 0x0, val );
+}
+
+/**
+ * @brief Gets the LEON cache control register value.
+ *
+ * @return Returns the register value.
+ */
+static inline uint32_t leon3_get_cache_control_register( void )
+{
+  return leon3_get_system_register( 0x0 );
+}
+
+/**
+ * @brief Checks if the data cache snooping is enabled.
+ *
+ * @return Returns true, if the data cache snooping is enabled, otherwise
+ *   false.
+ */
+static inline bool leon3_data_cache_snooping_enabled( void )
+{
+  return ( leon3_get_cache_control_register() & LEON3_REG_CACHE_CTRL_DS ) != 0;
+}
+
+/**
+ * @brief Gets the LEON instruction cache configuration register value.
+ *
+ * @return Returns the register value.
+ */
+static inline uint32_t leon3_get_inst_cache_config_register( void )
+{
+  return leon3_get_system_register( 0x8 );
+}
+
+/**
+ * @brief Gets the LEON data cache configuration register value.
+ *
+ * @return Returns the register value.
+ */
+static inline uint32_t leon3_get_data_cache_config_register( void )
+{
+  return leon3_get_system_register( 0xc );
+}
+
+/**
+ * @brief Gets the LEON up-counter low register (%ASR23) value.
+ *
+ * @return Returns the register value.
+ */
+static inline uint32_t leon3_up_counter_low( void )
+{
+  uint32_t asr23;
+
+  __asm__ volatile (
+"mov %%asr23, %0"
+: "=&r" (asr23)
+  );
+
+  return asr23;
+}
+
+/**
+ * @brief Gets the LEON up-counter high register (%ASR22) value.
+ *
+ * @return Returns the register value.
+ */
+static inline uint32_t leon3_up_counter_high(void)
+{
+  uint32_t asr22;
+
+  __asm__ volatile (
+"mov %%asr22, %0"
+: "=&r" (asr22)
+  );
+
+  return asr22;
+}
+
+/**
+ * @brief Enables the LEON up-counter.
+ */
+static inline void leon3_up_counter_enable( void )
+{
+  __asm__ volatile (
+"mov %g0, %asr22"
+  );
+}
+
+/**
+ * @brief Checks if the LEON up-counter is available.
+ *
+ * The LEON up-counter must have been enabled.
+ *
+ * @return Returns true, if the LEON up-counter is available, otherwise false.
+ */
+static inline bool leon3_up_counter_is_available( void )
+{
+  return leon3_up_counter_low() != leon3_up_counter_low();
+}
+
+/**
+ * @brief Gets the LEON up-counter frequency in Hz.
+ *
+ * @return Returns the frequency.
+ */
+static inline uint32_t leon3_up_counter_frequency( void )
+{
+  /*
+   * For simplicity, assume that the interrupt controller uses the processor
+   * clock.  This is at least true on the GR740.
+   */
+  return ambapp_freq_get( ambapp_plb(), LEON3_IrqCtrl_Adev );
+}
+
 /**
  * @brief This pointer provides the debug APBUART register block address.
  */
diff --git a/bsps/sparc/leon3/include/leon.h b/bsps/sparc/leon3/include/leon.h
index 618d71af9b..3d7ce03f2a 100644
--- a/bsps/sparc/leon3/include/leon.h
+++ b/bsps/sparc/leon3/include/leon.h
@@ -45,7 +45,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
@@ -142,12 +142,6 @@ extern "C" {
 #define LEON_REG_UART_CTRL_FA 0x8000 /* FIFO Available */
 #define LEON_R

[PATCH v3 37/38] validation: Test sparc/leon3 BSP family

[Sebastian Huber]

---
 ...arc-leon3-cache-snooping-disabled-boot.yml |  24 ++
 ...eon3-cache-snooping-disabled-secondary.yml |  25 +++
 ...fatal-sparc-leon3-clock-initialization.yml |  21 ++
 .../bsps/fatal-sparc-leon3-shutdown.yml   |  24 ++
 .../validation/bsps/objsparcgr712rc.yml   |  14 ++
 .../validation/bsps/validation-bsp-0.yml  |   2 +
 spec/build/testsuites/validation/grp.yml  |   8 +
 .../bsps/tc-fatal-sparc-leon3-shutdown.c  | 211 ++
 testsuites/validation/bsps/tc-sparc-gr712rc.c | 124 ++
 ...sparc-leon3-cache-snooping-disabled-boot.c | 175 +++
 ...sparc-leon3-cache-snooping-disabled-boot.h |  84 +++
 ...-leon3-cache-snooping-disabled-secondary.c | 176 +++
 ...-leon3-cache-snooping-disabled-secondary.h |  84 +++
 ...r-fatal-sparc-leon3-clock-initialization.c | 190 
 ...r-fatal-sparc-leon3-clock-initialization.h |  84 +++
 ...sparc-leon3-cache-snooping-disabled-boot.c |  79 +++
 ...-leon3-cache-snooping-disabled-secondary.c |  82 +++
 ...s-fatal-sparc-leon3-clock-initialization.c |  79 +++
 .../ts-fatal-sparc-leon3-shutdown-response.c  |  94 
 .../bsps/ts-fatal-sparc-leon3-shutdown.c  | 170 ++
 20 files changed, 1750 insertions(+)
 create mode 100644 
spec/build/testsuites/validation/bsps/fatal-sparc-leon3-cache-snooping-disabled-boot.yml
 create mode 100644 
spec/build/testsuites/validation/bsps/fatal-sparc-leon3-cache-snooping-disabled-secondary.yml
 create mode 100644 
spec/build/testsuites/validation/bsps/fatal-sparc-leon3-clock-initialization.yml
 create mode 100644 
spec/build/testsuites/validation/bsps/fatal-sparc-leon3-shutdown.yml
 create mode 100644 spec/build/testsuites/validation/bsps/objsparcgr712rc.yml
 create mode 100644 testsuites/validation/bsps/tc-fatal-sparc-leon3-shutdown.c
 create mode 100644 testsuites/validation/bsps/tc-sparc-gr712rc.c
 create mode 100644 
testsuites/validation/bsps/tr-fatal-sparc-leon3-cache-snooping-disabled-boot.c
 create mode 100644 
testsuites/validation/bsps/tr-fatal-sparc-leon3-cache-snooping-disabled-boot.h
 create mode 100644 
testsuites/validation/bsps/tr-fatal-sparc-leon3-cache-snooping-disabled-secondary.c
 create mode 100644 
testsuites/validation/bsps/tr-fatal-sparc-leon3-cache-snooping-disabled-secondary.h
 create mode 100644 
testsuites/validation/bsps/tr-fatal-sparc-leon3-clock-initialization.c
 create mode 100644 
testsuites/validation/bsps/tr-fatal-sparc-leon3-clock-initialization.h
 create mode 100644 
testsuites/validation/bsps/ts-fatal-sparc-leon3-cache-snooping-disabled-boot.c
 create mode 100644 
testsuites/validation/bsps/ts-fatal-sparc-leon3-cache-snooping-disabled-secondary.c
 create mode 100644 
testsuites/validation/bsps/ts-fatal-sparc-leon3-clock-initialization.c
 create mode 100644 
testsuites/validation/bsps/ts-fatal-sparc-leon3-shutdown-response.c
 create mode 100644 testsuites/validation/bsps/ts-fatal-sparc-leon3-shutdown.c

diff --git 
a/spec/build/testsuites/validation/bsps/fatal-sparc-leon3-cache-snooping-disabled-boot.yml
 
b/spec/build/testsuites/validation/bsps/fatal-sparc-leon3-cache-snooping-disabled-boot.yml
new file mode 100644
index 00..93afdb2c32
--- /dev/null
+++ 
b/spec/build/testsuites/validation/bsps/fatal-sparc-leon3-cache-snooping-disabled-boot.yml
@@ -0,0 +1,24 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: test-program
+cflags: []
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+cppflags: []
+cxxflags: []
+enabled-by:
+  and:
+  - RTEMS_SMP
+  - bsps/sparc/leon3
+features: c cprogram
+includes: []
+ldflags: []
+links: []
+source:
+- 
testsuites/validation/bsps/tr-fatal-sparc-leon3-cache-snooping-disabled-boot.c
+- 
testsuites/validation/bsps/ts-fatal-sparc-leon3-cache-snooping-disabled-boot.c
+stlib: []
+target: 
testsuites/validation/bsps/ts-fatal-sparc-leon3-cache-snooping-disabled-boot.exe
+type: build
+use-after:
+- validation
+use-before: []
diff --git 
a/spec/build/testsuites/validation/bsps/fatal-sparc-leon3-cache-snooping-disabled-secondary.yml
 
b/spec/build/testsuites/validation/bsps/fatal-sparc-leon3-cache-snooping-disabled-secondary.yml
new file mode 100644
index 00..20c4b43989
--- /dev/null
+++ 
b/spec/build/testsuites/validation/bsps/fatal-sparc-leon3-cache-snooping-disabled-secondary.yml
@@ -0,0 +1,25 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: test-program
+cflags: []
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+cppflags: []
+cxxflags: []
+enabled-by:
+  and:
+  - RTEMS_SMP
+  - bsps/sparc/leon3
+features: c cprogram
+includes: []
+ldflags:
+- -Wl,--wrap=bsp_start_on_secondary_processor
+links: []
+source:
+- 
testsuites/validation/bsps/tr-fatal-sparc-leon3-cache-snooping-disabled-secondary.c
+- 
testsuites/validation/bsps/ts-fatal-sparc-leon3-cache-snooping-disabled-secondary.c
+stlib: []
+target: 
testsuites/validation/bsps/ts-fatal-sparc-leon3-cache-snooping-disabled-sec

[PATCH v3 16/38] bsp/leon3: Use new IRQ(A)MP register block API

[Sebastian Huber]

---
 bsps/sparc/leon3/clock/ckinit.c|  11 ++-
 bsps/sparc/leon3/include/bsp/irq.h |   1 +
 bsps/sparc/leon3/include/bsp/irqimpl.h |  35 ++-
 bsps/sparc/leon3/include/leon.h|  63 ++---
 bsps/sparc/leon3/start/amba.c  |  11 ++-
 bsps/sparc/leon3/start/bspclean.c  |   9 +-
 bsps/sparc/leon3/start/bspsmp.c|  16 +++-
 bsps/sparc/leon3/start/cpucounter.c|  11 ++-
 bsps/sparc/leon3/start/eirq.c  | 124 ++---
 9 files changed, 187 insertions(+), 94 deletions(-)

diff --git a/bsps/sparc/leon3/clock/ckinit.c b/bsps/sparc/leon3/clock/ckinit.c
index 2ec701fe2a..b3761bed35 100644
--- a/bsps/sparc/leon3/clock/ckinit.c
+++ b/bsps/sparc/leon3/clock/ckinit.c
@@ -45,6 +45,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -179,11 +180,11 @@ static void 
bsp_clock_handler_install(rtems_interrupt_handler isr)
 
 static void leon3_clock_initialize(void)
 {
-  volatile struct irqmp_timestamp_regs *irqmp_ts;
+  irqamp_timestamp *irqmp_ts;
   volatile struct gptimer_regs *gpt;
   struct timecounter *tc;
 
-  irqmp_ts = &LEON3_IrqCtrl_Regs->timestamp[0];
+  irqmp_ts = irqamp_get_timestamp_registers(LEON3_IrqCtrl_Regs);
   gpt = LEON3_Timer_Regs;
   tc = &leon3_tc;
 
@@ -201,13 +202,13 @@ static void leon3_clock_initialize(void)
 tc->tc_frequency = leon3_up_counter_frequency();
 
 #ifdef RTEMS_PROFILING
-if (!irqmp_has_timestamp(irqmp_ts)) {
+if (irqmp_ts == NULL) {
   bsp_fatal(LEON3_FATAL_CLOCK_NO_IRQMP_TIMESTAMP_SUPPORT);
 }
 #endif
 
 leon3_tc_tick = leon3_tc_tick_irqmp_timestamp_init;
-  } else if (irqmp_has_timestamp(irqmp_ts)) {
+  } else if (irqmp_ts != NULL) {
 /* Use the interrupt controller timestamp counter if available */
 tc->tc_get_timecount = _SPARC_Get_timecount_up;
 tc->tc_frequency = ambapp_freq_get(ambapp_plb(), LEON3_Timer_Adev);
@@ -218,7 +219,7 @@ static void leon3_clock_initialize(void)
  * At least one TSISEL field must be non-zero to enable the timestamp
  * counter.  Use an arbitrary interrupt source.
  */
-irqmp_ts->control = 0x1;
+grlib_store_32(&irqmp_ts->itstmpc, IRQAMP_ITSTMPC_TSISEL(1));
   } else {
 #ifdef RTEMS_SMP
 /*
diff --git a/bsps/sparc/leon3/include/bsp/irq.h 
b/bsps/sparc/leon3/include/bsp/irq.h
index ef0f6245f9..38ea1de1f8 100644
--- a/bsps/sparc/leon3/include/bsp/irq.h
+++ b/bsps/sparc/leon3/include/bsp/irq.h
@@ -37,6 +37,7 @@
 #ifndef LIBBSP_LEON3_IRQ_CONFIG_H
 #define LIBBSP_LEON3_IRQ_CONFIG_H
 
+#include 
 #include 
 
 #define BSP_INTERRUPT_VECTOR_MAX_STD 15 /* Standard IRQ controller */
diff --git a/bsps/sparc/leon3/include/bsp/irqimpl.h 
b/bsps/sparc/leon3/include/bsp/irqimpl.h
index 60b198bd02..c957c7fbbc 100644
--- a/bsps/sparc/leon3/include/bsp/irqimpl.h
+++ b/bsps/sparc/leon3/include/bsp/irqimpl.h
@@ -38,7 +38,8 @@
 #define LIBBSP_SPARC_LEON3_BSP_IRQIMPL_H
 
 #include 
-#include 
+#include 
+#include 
 
 struct ambapp_dev;
 
@@ -52,15 +53,38 @@ extern "C" {
  * @{
  */
 
+/**
+ * @brief This object provides the index of the boot processor.
+ *
+ * This object should be read-only after initialization.
+ */
+extern uint32_t LEON3_Cpu_Index;
+
 /**
  * @brief This lock serializes the interrupt controller access.
  */
 extern rtems_interrupt_lock LEON3_IrqCtrl_Lock;
 
+/**
+ * @brief Acquires the interrupt controller lock.
+ *
+ * @param[out] _lock_context is the lock context.
+ */
+#define LEON3_IRQCTRL_ACQUIRE( _lock_context ) \
+  rtems_interrupt_lock_acquire( &LEON3_IrqCtrl_Lock, _lock_context )
+
+/**
+ * @brief Releases the interrupt controller lock.
+ *
+ * @param[in, out] _lock_context is the lock context.
+ */
+#define LEON3_IRQCTRL_RELEASE( _lock_context ) \
+  rtems_interrupt_lock_release( &LEON3_IrqCtrl_Lock, _lock_context )
+
 /**
  * @brief This pointer provides the IRQ(A)MP register block address.
  */
-extern volatile struct irqmp_regs *LEON3_IrqCtrl_Regs;
+extern irqamp *LEON3_IrqCtrl_Regs;
 
 /**
  * @brief This pointer provides the IRQ(A)MP device information block.
@@ -80,7 +104,7 @@ extern uint32_t LEON3_IrqCtrl_EIrq;
  *
  * @param[in, out] regs is the IRQ(A)MP register block address.
  */
-void leon3_ext_irq_init( volatile struct irqmp_regs *regs );
+void leon3_ext_irq_init( irqamp *regs );
 
 /**
  * @brief Acknowledges and maps extended interrupts if this feature is
@@ -91,12 +115,15 @@ void leon3_ext_irq_init( volatile struct irqmp_regs *regs 
);
 static inline uint32_t bsp_irq_fixup( uint32_t irq )
 {
   uint32_t eirq;
+  uint32_t cpu_self;
 
   if ( irq != LEON3_IrqCtrl_EIrq ) {
 return irq;
   }
 
-  eirq = LEON3_IrqCtrl_Regs->intid[ _LEON3_Get_current_processor() ] & 0x1f;
+  cpu_self = _LEON3_Get_current_processor();
+  eirq = grlib_load_32( &LEON3_IrqCtrl_Regs->pextack[ cpu_self ] );
+  eirq = IRQAMP_PEXTACK_EID_4_0_GET( eirq );
 
   if ( eirq < 16 ) {
 return irq;
diff --git a/bsps/sparc/leon3/include/leon.h b/bsps/sparc/leon3/include/leon.h
index 8a64285b3f..618d71af9

[PATCH v3 13/38] bsps: Use new APBUART register block API

[Sebastian Huber]

---
 bsps/include/grlib/apbuart_termios.h  |   4 +-
 bsps/shared/grlib/uart/apbuart_cons.c | 136 +-
 bsps/shared/grlib/uart/apbuart_polled.c   |  52 +
 bsps/shared/grlib/uart/apbuart_termios.c  |  49 +---
 bsps/sparc/leon3/console/console.c|   2 +-
 bsps/sparc/leon3/console/printk_support.c |  16 ++-
 bsps/sparc/leon3/include/bsp/leon3.h  |  62 ++
 7 files changed, 218 insertions(+), 103 deletions(-)
 create mode 100644 bsps/sparc/leon3/include/bsp/leon3.h

diff --git a/bsps/include/grlib/apbuart_termios.h 
b/bsps/include/grlib/apbuart_termios.h
index 82eb4b6de4..a19b99b609 100644
--- a/bsps/include/grlib/apbuart_termios.h
+++ b/bsps/include/grlib/apbuart_termios.h
@@ -34,7 +34,7 @@
 #define APBUART_TERMIOS_H
 
 #include 
-#include "grlib.h"
+#include "apbuart.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -42,7 +42,7 @@ extern "C" {
 
 struct apbuart_context {
   rtems_termios_device_context base;
-  struct apbuart_regs *regs;
+  apbuart *regs;
   unsigned int freq_hz;
   rtems_vector_number irq;
   volatile int sending;
diff --git a/bsps/shared/grlib/uart/apbuart_cons.c 
b/bsps/shared/grlib/uart/apbuart_cons.c
index 5d47b7f4a1..74f9bf3e0c 100644
--- a/bsps/shared/grlib/uart/apbuart_cons.c
+++ b/bsps/shared/grlib/uart/apbuart_cons.c
@@ -47,11 +47,15 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 #include 
 #include 
 
+#ifdef LEON3
+#include 
+#endif
+
 /*#define DEBUG 1  */
 
 #ifdef DEBUG
@@ -60,12 +64,6 @@
 #define DBG(x...)
 #endif
 
-/* LEON3 Low level transmit/receive functions provided by debug-uart code */
-#ifdef LEON3
-#include 
-extern struct apbuart_regs *leon3_debug_uart; /* The debug UART */
-#endif
-
 /* Probed hardware capabilities */
 enum {
CAP_FIFO = 0x01, /* FIFO available */
@@ -74,7 +72,7 @@ enum {
 struct apbuart_priv {
struct console_dev condev;
struct drvmgr_dev *dev;
-   struct apbuart_regs *regs;
+   apbuart *regs;
struct rtems_termios_tty *tty;
char devName[52];
volatile int sending;
@@ -213,18 +211,23 @@ static const rtems_termios_device_handler handler_polled 
= {
  * can select appropriate routines for the hardware. probecap() return value
  * is a CAP_ bitmask.
  */
-static int probecap(struct apbuart_regs *regs)
+static int probecap(apbuart *regs)
 {
int cap = 0;
+   uint32_t ctrl;
 
/* Probe FIFO */
-   if (regs->ctrl & APBUART_CTRL_FA) {
+   ctrl = grlib_load_32(®s->ctrl);
+   if (ctrl & APBUART_CTRL_FA) {
cap |= CAP_FIFO;
 
/* Probe RX delayed interrupt */
-   regs->ctrl |= APBUART_CTRL_DI;
-   if (regs->ctrl & APBUART_CTRL_DI) {
-   regs->ctrl &= ~APBUART_CTRL_DI;
+   ctrl |= APBUART_CTRL_DI;
+   grlib_store_32(®s->ctrl, ctrl);
+   ctrl = grlib_load_32(®s->ctrl);
+   if (ctrl & APBUART_CTRL_DI) {
+   ctrl &= ~APBUART_CTRL_DI;
+   grlib_store_32(®s->ctrl, ctrl);
cap |= CAP_DI;
}
}
@@ -241,6 +244,7 @@ int apbuart_init1(struct drvmgr_dev *dev)
char prefix[32];
unsigned int db;
static int first_uart = 1;
+   uint32_t ctrl;
 
/* The default operation in AMP is to use APBUART[0] for CPU[0],
 * APBUART[1] for CPU[1] and so on. The remaining UARTs is not used
@@ -269,10 +273,12 @@ int apbuart_init1(struct drvmgr_dev *dev)
if (ambadev == NULL)
return -1;
pnpinfo = &ambadev->info;
-   priv->regs = (struct apbuart_regs *)pnpinfo->apb_slv->start;
+   priv->regs = (apbuart *)pnpinfo->apb_slv->start;
 
/* Clear HW regs, leave baudrate register as it is */
-   priv->regs->status = 0;
+   grlib_store_32(&priv->regs->status, 0);
+
+   ctrl = grlib_load_32(&priv->regs->ctrl);
 
/* leave Transmitter/receiver if this is the RTEMS debug UART (assume
 * it has been setup by boot loader).
@@ -280,10 +286,10 @@ int apbuart_init1(struct drvmgr_dev *dev)
db = 0;
 #ifdef LEON3
if (priv->regs == leon3_debug_uart) {
-   db = priv->regs->ctrl & (APBUART_CTRL_RE |
-   APBUART_CTRL_TE |
-   APBUART_CTRL_PE |
-   APBUART_CTRL_PS);
+   db = ctrl & (APBUART_CTRL_RE |
+APBUART_CTRL_TE |
+APBUART_CTRL_PE |
+APBUART_CTRL_PS);
}
 #endif
/* Let UART debug tunnelling be untouched if Flow-control is set.
@@ -293,12 +299,12 @@ int apbuart_init1(struct drvmgr_dev *dev)
 * guess that we are debugging if FL is already set, the debugger set
 * either LB or DB depending on UART capabilities.
 */
-   if (priv->regs->ctrl & APBUART_CTRL_FL) {
-   

[PATCH v3 21/38] bsp/leon3: LEON3_PLB_FREQUENCY_DEFINED_BY_GPTIMER

[Sebastian Huber]

---
 bsps/sparc/leon3/clock/ckinit.c|  9 +++-
 bsps/sparc/leon3/include/bsp/leon3.h   | 27 ++
 bsps/sparc/leon3/start/cpucounter.c|  8 +++
 spec/build/bsps/sparc/leon3/grp.yml|  2 ++
 spec/build/bsps/sparc/leon3/optplbfreq.yml | 21 +
 5 files changed, 61 insertions(+), 6 deletions(-)
 create mode 100644 spec/build/bsps/sparc/leon3/optplbfreq.yml

diff --git a/bsps/sparc/leon3/clock/ckinit.c b/bsps/sparc/leon3/clock/ckinit.c
index eea598dd48..fc20577634 100644
--- a/bsps/sparc/leon3/clock/ckinit.c
+++ b/bsps/sparc/leon3/clock/ckinit.c
@@ -44,12 +44,15 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
 #include 
 
+#if !defined(LEON3_PLB_FREQUENCY_DEFINED_BY_GPTIMER)
+#include 
+#endif
+
 /* The LEON3 BSP Timer driver can rely on the Driver Manager if the
  * DrvMgr is initialized during startup. Otherwise the classic driver
  * must be used.
@@ -214,7 +217,11 @@ static void leon3_clock_initialize(void)
   } else if (irqmp_ts != NULL) {
 /* Use the interrupt controller timestamp counter if available */
 tc->tc_get_timecount = _SPARC_Get_timecount_up;
+#if defined(LEON3_PLB_FREQUENCY_DEFINED_BY_GPTIMER)
+tc->tc_frequency = leon3_processor_local_bus_frequency();
+#else
 tc->tc_frequency = ambapp_freq_get(ambapp_plb(), LEON3_Timer_Adev);
+#endif
 
 leon3_tc_tick = leon3_tc_tick_irqmp_timestamp_init;
 
diff --git a/bsps/sparc/leon3/include/bsp/leon3.h 
b/bsps/sparc/leon3/include/bsp/leon3.h
index 1402dfca1b..599d616aaf 100644
--- a/bsps/sparc/leon3/include/bsp/leon3.h
+++ b/bsps/sparc/leon3/include/bsp/leon3.h
@@ -42,7 +42,9 @@
 #include 
 #include 
 
+#if !defined(LEON3_PLB_FREQUENCY_DEFINED_BY_GPTIMER)
 #include 
+#endif
 
 #ifdef __cplusplus
 extern "C" {
@@ -194,6 +196,25 @@ extern gptimer *LEON3_Timer_Regs;
  */
 extern struct ambapp_dev *LEON3_Timer_Adev;
 
+/**
+ * @brief Gets the processor local bus frequency in Hz.
+ *
+ * @return Returns the frequency.
+ */
+static inline uint32_t leon3_processor_local_bus_frequency( void )
+{
+#if defined(LEON3_PLB_FREQUENCY_DEFINED_BY_GPTIMER)
+  return ( grlib_load_32( &LEON3_Timer_Regs->sreload ) + 1 ) *
+LEON3_GPTIMER_0_FREQUENCY_SET_BY_BOOT_LOADER;
+#else
+  /*
+   * For simplicity, assume that the interrupt controller uses the processor
+   * clock.  This is at least true on the GR740.
+   */
+  return ambapp_freq_get( ambapp_plb(), LEON3_IrqCtrl_Adev );
+#endif
+}
+
 /**
  * @brief Gets the LEON up-counter low register (%ASR23) value.
  *
@@ -257,11 +278,7 @@ static inline bool leon3_up_counter_is_available( void )
  */
 static inline uint32_t leon3_up_counter_frequency( void )
 {
-  /*
-   * For simplicity, assume that the interrupt controller uses the processor
-   * clock.  This is at least true on the GR740.
-   */
-  return ambapp_freq_get( ambapp_plb(), LEON3_IrqCtrl_Adev );
+  return leon3_processor_local_bus_frequency();
 }
 
 /**
diff --git a/bsps/sparc/leon3/start/cpucounter.c 
b/bsps/sparc/leon3/start/cpucounter.c
index 5672cbbd45..57fd487009 100644
--- a/bsps/sparc/leon3/start/cpucounter.c
+++ b/bsps/sparc/leon3/start/cpucounter.c
@@ -66,7 +66,11 @@ static void leon3_counter_initialize(void)
 /* Enable interrupt timestamping for an arbitrary interrupt line */
 grlib_store_32(&irqmp_ts->itstmpc, IRQAMP_ITSTMPC_TSISEL(1));
 
+#if defined(LEON3_PLB_FREQUENCY_DEFINED_BY_GPTIMER)
+leon3_counter_frequency = leon3_processor_local_bus_frequency();
+#else
 leon3_counter_frequency = ambapp_freq_get(ambapp_plb(), 
LEON3_IrqCtrl_Adev);
+#endif
   } else if (gpt != NULL) {
 gptimer_timer *timer;
 uint32_t   tctrl;
@@ -83,8 +87,12 @@ static void leon3_counter_initialize(void)
 tctrl |= GPTIMER_TCTRL_EN | GPTIMER_TCTRL_RS | GPTIMER_TCTRL_LD;
 grlib_store_32(&timer->tctrl, tctrl);
 
+#if defined(LEON3_PLB_FREQUENCY_DEFINED_BY_GPTIMER)
+leon3_counter_frequency = LEON3_GPTIMER_0_FREQUENCY_SET_BY_BOOT_LOADER;
+#else
 leon3_counter_frequency = ambapp_freq_get(ambapp_plb(), LEON3_Timer_Adev) /
   (grlib_load_32(&gpt->sreload) + 1);
+#endif
   }
 }
 
diff --git a/spec/build/bsps/sparc/leon3/grp.yml 
b/spec/build/bsps/sparc/leon3/grp.yml
index 48da9acba8..964682d0fe 100644
--- a/spec/build/bsps/sparc/leon3/grp.yml
+++ b/spec/build/bsps/sparc/leon3/grp.yml
@@ -38,6 +38,8 @@ links:
   uid: optconirq
 - role: build-dependency
   uid: optleon3smp
+- role: build-dependency
+  uid: optplbfreq
 - role: build-dependency
   uid: optpwrdwnhlt
 - role: build-dependency
diff --git a/spec/build/bsps/sparc/leon3/optplbfreq.yml 
b/spec/build/bsps/sparc/leon3/optplbfreq.yml
new file mode 100644
index 00..f542e322ac
--- /dev/null
+++ b/spec/build/bsps/sparc/leon3/optplbfreq.yml
@@ -0,0 +1,21 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+default:
+- enabl

[PATCH v3 12/38] bsps/grlib: Use GRLIB definition of GRSPWROUTER

[Sebastian Huber]

Rename parts to match with GRLIB naming.

Update #4842.
---
 bsps/include/grlib/grspwrouter-regs.h | 1925 +
 bsps/include/grlib/spwrmap-regs.h | 1443 --
 2 files changed, 1925 insertions(+), 1443 deletions(-)
 create mode 100644 bsps/include/grlib/grspwrouter-regs.h
 delete mode 100644 bsps/include/grlib/spwrmap-regs.h

diff --git a/bsps/include/grlib/grspwrouter-regs.h 
b/bsps/include/grlib/grspwrouter-regs.h
new file mode 100644
index 00..e688f34434
--- /dev/null
+++ b/bsps/include/grlib/grspwrouter-regs.h
@@ -0,0 +1,1925 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSDeviceGRSPWROUTER
+ *
+ * @brief This header file defines the GRSPWROUTER register block interface.
+ */
+
+/*
+ * Copyright (C) 2021, 2023 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated.  If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual.  The manual is provided as a part of
+ * a release.  For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+/* Generated from spec:/dev/grlib/if/grspwrouter-header */
+
+#ifndef _GRLIB_GRSPWROUTER_REGS_H
+#define _GRLIB_GRSPWROUTER_REGS_H
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Generated from spec:/dev/grlib/if/grspwrouter-portstats */
+
+/**
+ * @defgroup RTEMSDeviceGRSPWRouterPortStats SpaceWire Router Port Statistics
+ *
+ * @ingroup RTEMSDeviceGRSPWROUTER
+ *
+ * @brief This group contains the SpaceWire Router Port Statistics interfaces.
+ *
+ * @{
+ */
+
+/**
+ * @defgroup RTEMSDeviceGRSPWRouterPortStatsOCHARCNT \
+ *   Outgoing character counter, ports > 0 (OCHARCNT)
+ *
+ * @brief This group contains register bit definitions.
+ *
+ * @{
+ */
+
+#define GRSPWROUTER_OCHARCNT_OR 0x8000U
+
+#define GRSPWROUTER_OCHARCNT_CC_SHIFT 0
+#define GRSPWROUTER_OCHARCNT_CC_MASK 0x7fffU
+#define GRSPWROUTER_OCHARCNT_CC_GET( _reg ) \
+  ( ( ( _reg ) & GRSPWROUTER_OCHARCNT_CC_MASK ) >> \
+GRSPWROUTER_OCHARCNT_CC_SHIFT )
+#define GRSPWROUTER_OCHARCNT_CC_SET( _reg, _val ) \
+  ( ( ( _reg ) & ~GRSPWROUTER_OCHARCNT_CC_MASK ) | \
+( ( ( _val ) << GRSPWROUTER_OCHARCNT_CC_SHIFT ) & \
+  GRSPWROUTER_OCHARCNT_CC_MASK ) )
+#define GRSPWROUTER_OCHARCNT_CC( _val ) \
+  ( ( ( _val ) << GRSPWROUTER_OCHARCNT_CC_SHIFT ) & \
+GRSPWROUTER_OCHARCNT_CC_MASK )
+
+/** @} */
+
+/**
+ * @defgroup RTEMSDeviceGRSPWRouterPortStatsICHARCNT \
+ *   Incoming character counter, ports > 0 (ICHARCNT)
+ *
+ * @brief This group contains register bit definitions.
+ *
+ * @{
+ */
+
+#define GRSPWROUTER_ICHARCNT_OR 0x8000U
+
+#define GRSPWROUTER_ICHARCNT_CC_SHIFT 0
+#define GRSPWROUTER_ICHARCNT_CC_MASK 0x7fffU
+#define GRSPWROUTER_ICHARCNT_CC_GET( _reg ) \
+  ( ( ( _reg ) & GRSPWROUTER_ICHARCNT_CC_MASK ) >> \
+GRSPWROUTER_ICHARCNT_CC_SHIFT )
+#define GRSPWROUTER_ICHARCNT_CC_SET( _reg, _val ) \
+  ( ( ( _reg ) & ~GRSPWROUTER_ICHARCNT_CC_MASK ) | \
+( ( ( _val ) << GRSPWROUTER_ICHARCNT_CC_SHIFT ) & \
+  GRSPWROUTER_ICHARCNT_CC_MASK ) )
+#define GRSPWROUTER_ICHARCNT_CC( _val ) \
+  ( ( ( _val ) << GRSPWROUTER_ICHARCNT_CC_SHIFT ) & \
+GRSPWROUTER_ICHARCNT_CC_MASK )
+
+/** @} */
+
+/**
+ * @defgroup RTEMSDeviceGRSPWRouterPortStatsOPKTCNT \
+ *   

[PATCH v3 22/38] bsp/leon3: Add LEON3_GPTIMER_BASE

[Sebastian Huber]

---
 bsps/sparc/leon3/include/bsp/leon3.h  |  4 
 bsps/sparc/leon3/start/amba.c |  4 
 spec/build/bsps/sparc/leon3/grp.yml   |  2 ++
 .../build/bsps/sparc/leon3/optgptimerbase.yml | 20 +++
 4 files changed, 30 insertions(+)
 create mode 100644 spec/build/bsps/sparc/leon3/optgptimerbase.yml

diff --git a/bsps/sparc/leon3/include/bsp/leon3.h 
b/bsps/sparc/leon3/include/bsp/leon3.h
index 599d616aaf..18db7b8aea 100644
--- a/bsps/sparc/leon3/include/bsp/leon3.h
+++ b/bsps/sparc/leon3/include/bsp/leon3.h
@@ -189,7 +189,11 @@ static inline uint32_t 
leon3_get_data_cache_config_register( void )
 /**
  * @brief This pointer provides the GPTIMER register block address.
  */
+#if defined(LEON3_GPTIMER_BASE)
+#define LEON3_Timer_Regs ((gptimer *) LEON3_GPTIMER_BASE)
+#else
 extern gptimer *LEON3_Timer_Regs;
+#endif
 
 /**
  * @brief This pointer provides the GPTIMER device information block.
diff --git a/bsps/sparc/leon3/start/amba.c b/bsps/sparc/leon3/start/amba.c
index d4494224c4..36b988e90b 100644
--- a/bsps/sparc/leon3/start/amba.c
+++ b/bsps/sparc/leon3/start/amba.c
@@ -119,8 +119,10 @@ RTEMS_SYSINIT_ITEM(
 irqamp *LEON3_IrqCtrl_Regs;
 struct ambapp_dev *LEON3_IrqCtrl_Adev;
 
+#if !defined(LEON3_GPTIMER_BASE)
 gptimer *LEON3_Timer_Regs;
 struct ambapp_dev *LEON3_Timer_Adev;
+#endif
 
 /*
  *  amba_initialize
@@ -166,6 +168,7 @@ static void amba_initialize(void)
 LEON3_IrqCtrl_Regs += icsel;
   }
 
+#if !defined(LEON3_GPTIMER_BASE)
   /* find GP Timer */
   adev = (void *)ambapp_for_each(plb, (OPTIONS_ALL|OPTIONS_APB_SLVS),
  VENDOR_GAISLER, GAISLER_GPTIMER,
@@ -189,6 +192,7 @@ static void amba_initialize(void)
 if (leon3_timer_prescaler)
   grlib_store_32(&LEON3_Timer_Regs->sreload, leon3_timer_prescaler);
   }
+#endif
 }
 
 RTEMS_SYSINIT_ITEM(
diff --git a/spec/build/bsps/sparc/leon3/grp.yml 
b/spec/build/bsps/sparc/leon3/grp.yml
index 964682d0fe..cce4c1dc06 100644
--- a/spec/build/bsps/sparc/leon3/grp.yml
+++ b/spec/build/bsps/sparc/leon3/grp.yml
@@ -34,6 +34,8 @@ links:
   uid: objsmp
 - role: build-dependency
   uid: optapbuartbase
+- role: build-dependency
+  uid: optgptimerbase
 - role: build-dependency
   uid: optconirq
 - role: build-dependency
diff --git a/spec/build/bsps/sparc/leon3/optgptimerbase.yml 
b/spec/build/bsps/sparc/leon3/optgptimerbase.yml
new file mode 100644
index 00..b2158208a0
--- /dev/null
+++ b/spec/build/bsps/sparc/leon3/optgptimerbase.yml
@@ -0,0 +1,20 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+actions:
+- get-integer: null
+- format-and-define: null
+build-type: option
+default:
+- enabled-by: sparc/gr712rc
+  value: 0x8300
+- enabled-by: sparc/gr740
+  value: 0xff908000
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: LEON3_GPTIMER_BASE
+description: |
+  This option defines the base address of the GPTIMER register block used by
+  the clock driver.
+type: build
-- 
2.35.3

___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel

[PATCH v3 20/38] bsp/leon3: Add LEON3_APBUART_BASE

[Sebastian Huber]

---
 bsps/sparc/leon3/console/printk_support.c | 37 +++
 bsps/sparc/leon3/include/bsp/leon3.h  |  5 +++
 bsps/sparc/leon3/include/leon.h   |  2 +
 spec/build/bsps/sparc/leon3/grp.yml   |  2 +
 .../build/bsps/sparc/leon3/optapbuartbase.yml | 20 ++
 5 files changed, 58 insertions(+), 8 deletions(-)
 create mode 100644 spec/build/bsps/sparc/leon3/optapbuartbase.yml

diff --git a/bsps/sparc/leon3/console/printk_support.c 
b/bsps/sparc/leon3/console/printk_support.c
index cb77c66a96..9e260d2eac 100644
--- a/bsps/sparc/leon3/console/printk_support.c
+++ b/bsps/sparc/leon3/console/printk_support.c
@@ -38,20 +38,27 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 
+#if !defined(LEON3_APBUART_BASE)
 #include 
 
 int leon3_debug_uart_index __attribute__((weak)) = 0;
+
 apbuart *leon3_debug_uart = NULL;
+#endif
 
 static void bsp_debug_uart_init(void);
 
-static void bsp_debug_uart_discard(char c)
+static void apbuart_enable_receive_and_transmit(apbuart *regs)
 {
-  (void) c;
+  uint32_t ctrl;
+
+  ctrl = grlib_load_32(®s->ctrl);
+  ctrl |= APBUART_CTRL_RE | APBUART_CTRL_TE;
+  grlib_store_32(®s->ctrl, ctrl);
+  grlib_store_32(®s->status, 0);
 }
 
 static void bsp_debug_uart_output_char(char c)
@@ -71,6 +78,22 @@ static void bsp_debug_uart_pre_init_out(char c)
   (*BSP_output_char)(c);
 }
 
+#if defined(LEON3_APBUART_BASE)
+
+static void bsp_debug_uart_init(void)
+{
+  apbuart_enable_receive_and_transmit(leon3_debug_uart);
+  BSP_poll_char = bsp_debug_uart_poll_char;
+  BSP_output_char = bsp_debug_uart_output_char;
+}
+
+#else /* !LEON3_APBUART_BASE */
+
+static void bsp_debug_uart_discard(char c)
+{
+  (void) c;
+}
+
 /* Initialize the BSP system debug console layer. It will scan AMBA Plu&Play
  * for a debug APBUART and enable RX/TX for that UART.
  */
@@ -108,7 +131,6 @@ static void bsp_debug_uart_init(void)
  ambapp_find_by_idx, (void *)&i);
   if (adev != NULL) {
 struct ambapp_apb_info *apb;
-uint32_t ctrl;
 
 /*
  * Found a matching debug console, initialize debug UART if present for
@@ -116,16 +138,15 @@ static void bsp_debug_uart_init(void)
  */
 apb = (struct ambapp_apb_info *)adev->devinfo;
 leon3_debug_uart = (apbuart *)apb->start;
-ctrl = grlib_load_32(&leon3_debug_uart->ctrl);
-ctrl |= APBUART_CTRL_RE | APBUART_CTRL_TE;
-grlib_store_32(&leon3_debug_uart->ctrl, ctrl);
-grlib_store_32(&leon3_debug_uart->status, 0);
+apbuart_enable_receive_and_transmit(leon3_debug_uart);
 
 BSP_poll_char = bsp_debug_uart_poll_char;
 BSP_output_char = bsp_debug_uart_output_char;
   }
 }
 
+#endif /* LEON3_APBUART_BASE */
+
 RTEMS_SYSINIT_ITEM(
   bsp_debug_uart_init,
   RTEMS_SYSINIT_BSP_START,
diff --git a/bsps/sparc/leon3/include/bsp/leon3.h 
b/bsps/sparc/leon3/include/bsp/leon3.h
index aa3898e530..1402dfca1b 100644
--- a/bsps/sparc/leon3/include/bsp/leon3.h
+++ b/bsps/sparc/leon3/include/bsp/leon3.h
@@ -39,6 +39,7 @@
 #include 
 #include 
 
+#include 
 #include 
 
 #include 
@@ -266,7 +267,11 @@ static inline uint32_t leon3_up_counter_frequency( void )
 /**
  * @brief This pointer provides the debug APBUART register block address.
  */
+#if defined(LEON3_APBUART_BASE)
+#define leon3_debug_uart ((struct apbuart *) LEON3_APBUART_BASE)
+#else
 extern apbuart *leon3_debug_uart;
+#endif
 
 /** @} */
 
diff --git a/bsps/sparc/leon3/include/leon.h b/bsps/sparc/leon3/include/leon.h
index f5f6fa84e4..fba64addfe 100644
--- a/bsps/sparc/leon3/include/leon.h
+++ b/bsps/sparc/leon3/include/leon.h
@@ -329,6 +329,7 @@ static inline unsigned int leon_r32_no_cache(uintptr_t addr)
  */
 extern int syscon_uart_index;
 
+#if !defined(LEON3_APBUART_BASE)
 /* Let user override which on-chip APBUART will be debug UART
  * 0 = Default APBUART. On MP system CPU0=APBUART0, CPU1=APBUART1...
  * 1 = APBUART[0]
@@ -337,6 +338,7 @@ extern int syscon_uart_index;
  * ...
  */
 extern int leon3_debug_uart_index;
+#endif
 
 /* Let user override which on-chip TIMER core will be used for system clock
  * timer. This controls which timer core will be accociated with
diff --git a/spec/build/bsps/sparc/leon3/grp.yml 
b/spec/build/bsps/sparc/leon3/grp.yml
index ab72d911c5..48da9acba8 100644
--- a/spec/build/bsps/sparc/leon3/grp.yml
+++ b/spec/build/bsps/sparc/leon3/grp.yml
@@ -32,6 +32,8 @@ links:
   uid: objmpci
 - role: build-dependency
   uid: objsmp
+- role: build-dependency
+  uid: optapbuartbase
 - role: build-dependency
   uid: optconirq
 - role: build-dependency
diff --git a/spec/build/bsps/sparc/leon3/optapbuartbase.yml 
b/spec/build/bsps/sparc/leon3/optapbuartbase.yml
new file mode 100644
index 00..2986fc6324
--- /dev/null
+++ b/spec/build/bsps/sparc/leon3/optapbuartbase.yml
@@ -0,0 +1,20 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+actions:
+- get-integer: null
+- format-and-define: null
+build-type: o

[PATCH v3 23/38] bsp/leon3: Add LEON3_IRQAMP_BASE

[Sebastian Huber]

---
 bsps/sparc/leon3/include/bsp/irqimpl.h|  6 ++
 bsps/sparc/leon3/start/amba.c |  9 -
 spec/build/bsps/sparc/leon3/grp.yml   |  2 ++
 spec/build/bsps/sparc/leon3/optirqampbase.yml | 19 +++
 4 files changed, 35 insertions(+), 1 deletion(-)
 create mode 100644 spec/build/bsps/sparc/leon3/optirqampbase.yml

diff --git a/bsps/sparc/leon3/include/bsp/irqimpl.h 
b/bsps/sparc/leon3/include/bsp/irqimpl.h
index c957c7fbbc..ee5beaf72c 100644
--- a/bsps/sparc/leon3/include/bsp/irqimpl.h
+++ b/bsps/sparc/leon3/include/bsp/irqimpl.h
@@ -41,6 +41,8 @@
 #include 
 #include 
 
+#include 
+
 struct ambapp_dev;
 
 #ifdef __cplusplus
@@ -84,7 +86,11 @@ extern rtems_interrupt_lock LEON3_IrqCtrl_Lock;
 /**
  * @brief This pointer provides the IRQ(A)MP register block address.
  */
+#if defined(LEON3_IRQAMP_BASE)
+#define LEON3_IrqCtrl_Regs ((irqamp *) LEON3_IRQAMP_BASE)
+#else
 extern irqamp *LEON3_IrqCtrl_Regs;
+#endif
 
 /**
  * @brief This pointer provides the IRQ(A)MP device information block.
diff --git a/bsps/sparc/leon3/start/amba.c b/bsps/sparc/leon3/start/amba.c
index 36b988e90b..72f1f5e63b 100644
--- a/bsps/sparc/leon3/start/amba.c
+++ b/bsps/sparc/leon3/start/amba.c
@@ -115,9 +115,10 @@ RTEMS_SYSINIT_ITEM(
 );
 #endif
 
-/* Pointers to Interrupt Controller configuration registers */
+#if !defined(LEON3_IRQAMP_BASE)
 irqamp *LEON3_IrqCtrl_Regs;
 struct ambapp_dev *LEON3_IrqCtrl_Adev;
+#endif
 
 #if !defined(LEON3_GPTIMER_BASE)
 gptimer *LEON3_Timer_Regs;
@@ -140,7 +141,12 @@ static void amba_initialize(void)
   struct ambapp_bus *plb;
 
   plb = ambapp_plb();
+#if defined(LEON3_IRQAMP_BASE) && defined(LEON3_GPTIMER_BASE)
+  (void) plb;
+  (void) adev;
+#endif
 
+#if !defined(LEON3_IRQAMP_BASE)
   /* Find LEON3 Interrupt controller */
   adev = (void *)ambapp_for_each(plb, (OPTIONS_ALL|OPTIONS_APB_SLVS),
  VENDOR_GAISLER, GAISLER_IRQMP,
@@ -167,6 +173,7 @@ static void amba_initialize(void)
 icsel = (icsel >> ((7 - (LEON3_Cpu_Index & 0x7)) * 4)) & 0xf;
 LEON3_IrqCtrl_Regs += icsel;
   }
+#endif
 
 #if !defined(LEON3_GPTIMER_BASE)
   /* find GP Timer */
diff --git a/spec/build/bsps/sparc/leon3/grp.yml 
b/spec/build/bsps/sparc/leon3/grp.yml
index cce4c1dc06..7bb09d268f 100644
--- a/spec/build/bsps/sparc/leon3/grp.yml
+++ b/spec/build/bsps/sparc/leon3/grp.yml
@@ -36,6 +36,8 @@ links:
   uid: optapbuartbase
 - role: build-dependency
   uid: optgptimerbase
+- role: build-dependency
+  uid: optirqampbase
 - role: build-dependency
   uid: optconirq
 - role: build-dependency
diff --git a/spec/build/bsps/sparc/leon3/optirqampbase.yml 
b/spec/build/bsps/sparc/leon3/optirqampbase.yml
new file mode 100644
index 00..aad978406b
--- /dev/null
+++ b/spec/build/bsps/sparc/leon3/optirqampbase.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+actions:
+- get-integer: null
+- format-and-define: null
+build-type: option
+default:
+- enabled-by: sparc/gr712rc
+  value: 0x8200
+- enabled-by: sparc/gr740
+  value: 0xff904000
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: LEON3_IRQAMP_BASE
+description: |
+  This option defines the base address of the IRQ(A)MP register block.
+type: build
-- 
2.35.3

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[PATCH v3 26/38] bsp/leon3: Add LEON3_L2CACHE_BASE

[Sebastian Huber]

---
 bsps/sparc/leon3/start/cache.c| 36 ++-
 spec/build/bsps/sparc/leon3/grp.yml   |  2 ++
 .../build/bsps/sparc/leon3/optl2cachebase.yml | 19 ++
 3 files changed, 49 insertions(+), 8 deletions(-)
 create mode 100644 spec/build/bsps/sparc/leon3/optl2cachebase.yml

diff --git a/bsps/sparc/leon3/start/cache.c b/bsps/sparc/leon3/start/cache.c
index ed6fb5733d..5049b7f81c 100644
--- a/bsps/sparc/leon3/start/cache.c
+++ b/bsps/sparc/leon3/start/cache.c
@@ -11,7 +11,13 @@
 
 #include 
 
+#if !defined(LEON3_L2CACHE_BASE)
 #include 
+#endif
+
+#if !defined(LEON3_L2CACHE_BASE) || LEON3_L2CACHE_BASE != 0
+#define LEON3_MAYBE_HAS_L2CACHE
+#endif
 
 #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
 
@@ -23,6 +29,7 @@
 
 #define CPU_DATA_CACHE_ALIGNMENT 64
 
+#if !defined(LEON3_L2CACHE_BASE)
 static inline l2cache *get_l2c_regs(void)
 {
   struct ambapp_dev *adev;
@@ -42,7 +49,17 @@ static inline l2cache *get_l2c_regs(void)
 
   return (l2cache *) DEV_TO_AHB(adev)->start[1];
 }
+#endif
+
+static inline size_t get_l1_size(uint32_t l1_cfg)
+{
+  uint32_t ways = ((l1_cfg >> 24) & 0x7) + 1;
+  uint32_t wsize = UINT32_C(1) << (((l1_cfg >> 20) & 0xf) + 10);
+
+  return ways * wsize;
+}
 
+#if defined(LEON3_MAYBE_HAS_L2CACHE)
 static inline size_t get_l2_size(void)
 {
   l2cache *regs;
@@ -50,11 +67,15 @@ static inline size_t get_l2_size(void)
   unsigned ways;
   unsigned set_size;
 
+#if defined(LEON3_L2CACHE_BASE)
+  regs = (l2cache *) LEON3_L2CACHE_BASE;
+#else
   regs = get_l2c_regs();
 
   if (regs == NULL) {
 return 0;
   }
+#endif
 
   status = grlib_load_32(®s->l2cs);
   ways = L2CACHE_L2CS_WAY_GET(status) + 1;
@@ -63,18 +84,11 @@ static inline size_t get_l2_size(void)
   return ways * set_size;
 }
 
-static inline size_t get_l1_size(uint32_t l1_cfg)
-{
-  uint32_t ways = ((l1_cfg >> 24) & 0x7) + 1;
-  uint32_t wsize = UINT32_C(1) << (((l1_cfg >> 20) & 0xf) + 10);
-
-  return ways * wsize;
-}
-
 static inline size_t get_max_size(size_t a, size_t b)
 {
   return a < b ? b : a;
 }
+#endif
 
 static inline size_t get_cache_size(uint32_t level, uint32_t l1_cfg)
 {
@@ -82,14 +96,20 @@ static inline size_t get_cache_size(uint32_t level, 
uint32_t l1_cfg)
 
   switch (level) {
 case 0:
+#if defined(LEON3_MAYBE_HAS_L2CACHE)
   size = get_max_size(get_l1_size(l1_cfg), get_l2_size());
+#else
+  size = get_l1_size(l1_cfg);
+#endif
   break;
 case 1:
   size = get_l1_size(l1_cfg);
   break;
+#if defined(LEON3_MAYBE_HAS_L2CACHE)
 case 2:
   size = get_l2_size();
   break;
+#endif
 default:
   size = 0;
   break;
diff --git a/spec/build/bsps/sparc/leon3/grp.yml 
b/spec/build/bsps/sparc/leon3/grp.yml
index d044a6ca60..6d7a1b75c3 100644
--- a/spec/build/bsps/sparc/leon3/grp.yml
+++ b/spec/build/bsps/sparc/leon3/grp.yml
@@ -44,6 +44,8 @@ links:
   uid: optirqampts
 - role: build-dependency
   uid: optconirq
+- role: build-dependency
+  uid: optl2cachebase
 - role: build-dependency
   uid: optleon3smp
 - role: build-dependency
diff --git a/spec/build/bsps/sparc/leon3/optl2cachebase.yml 
b/spec/build/bsps/sparc/leon3/optl2cachebase.yml
new file mode 100644
index 00..759198f827
--- /dev/null
+++ b/spec/build/bsps/sparc/leon3/optl2cachebase.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+actions:
+- get-integer: null
+- format-and-define: null
+build-type: option
+default:
+- enabled-by: sparc/gr712rc
+  value: 0x
+- enabled-by: sparc/gr740
+  value: 0xf000
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: LEON3_L2CACHE_BASE
+description: |
+  This option defines the base address of the L2CACHE register block.
+type: build
-- 
2.35.3

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[PATCH v3 18/38] bsp/leon3: Use new GPTIMER register block API

[Sebastian Huber]

---
 bsps/shared/grlib/btimer/gptimer.c   | 178 +--
 bsps/sparc/leon3/btimer/btimer.c |  13 +-
 bsps/sparc/leon3/btimer/watchdog.c   |  27 ++--
 bsps/sparc/leon3/clock/ckinit.c  |  33 ++---
 bsps/sparc/leon3/include/bsp/leon3.h |  44 ++-
 bsps/sparc/leon3/include/leon.h  |  24 
 bsps/sparc/leon3/start/amba.c|   9 +-
 bsps/sparc/leon3/start/bspdelay.c|   8 +-
 bsps/sparc/leon3/start/cpucounter.c  |  20 +--
 9 files changed, 189 insertions(+), 167 deletions(-)

diff --git a/bsps/shared/grlib/btimer/gptimer.c 
b/bsps/shared/grlib/btimer/gptimer.c
index f31b7c052f..cbf058ccef 100644
--- a/bsps/shared/grlib/btimer/gptimer.c
+++ b/bsps/shared/grlib/btimer/gptimer.c
@@ -50,18 +50,15 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include 
-#include 
-#include 
-#include 
 #include 
 #include 
-#include 
 #include 
+#include 
+#include 
 #include 
 
 #if defined(LEON3)
-#include 
+#include 
 #endif
 
 #ifdef GPTIMER_INFO_AVAIL
@@ -75,49 +72,21 @@
 
 #include 
 
-/* GPTIMER Core Configuration Register (READ-ONLY) */
-#define GPTIMER_CFG_TIMERS_BIT 0
-#define GPTIMER_CFG_IRQ_BIT3
-#define GPTIMER_CFG_SI_BIT 8
-#define GPTIMER_CFG_DF_BIT 9
-
-#define GPTIMER_CFG_TIMERS (0x7info;
-   regs = (struct gptimer_regs *)pnpinfo->apb_slv->start;
+   regs = (gptimer *)pnpinfo->apb_slv->start;
 
DBG("GPTIMER[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name);
 
/* Get number of Timers */
-   timer_hw_cnt = regs->cfg & GPTIMER_CFG_TIMERS;
+   timer_hw_cnt = GPTIMER_CONFIG_TIMERS_GET(grlib_load_32(®s->config));
 
/* Let user spelect a range of timers to be used. In AMP systems
 * it is sometimes neccessary to leave timers for other CPU instances.
@@ -251,7 +220,7 @@ int gptimer_init1(struct drvmgr_dev *dev)
 * are present.
 */
size = sizeof(struct gptimer_priv) +
-   timer_cnt*sizeof(struct gptimer_timer);
+   timer_cnt*sizeof(struct gptimer_timer_priv);
priv = dev->priv = grlib_calloc(1, size);
if ( !priv )
return DRVMGR_NOMEM;
@@ -277,24 +246,24 @@ int gptimer_init1(struct drvmgr_dev *dev)
 */
value = drvmgr_dev_key_get(priv->dev, "prescaler", DRVMGR_KT_INT);
if ( value )
-   regs->scaler_reload = value->i;
+   grlib_store_32(®s->sreload, value->i);
 
/* Get Frequency that the timers are operating in (after prescaler) */
-   priv->base_freq = priv->base_clk / (priv->regs->scaler_reload + 1);
+   priv->base_freq = priv->base_clk / (grlib_load_32(®s->sreload) + 1);
 
/* Stop Timer and probe Pending bit. In newer hardware the
 * timer has pending bit is cleared by writing a one to it,
 * whereas older versions it is cleared with a zero.
 */
-   priv->regs->timer[timer_start].ctrl = GPTIMER_CTRL_IP;
-   if ((priv->regs->timer[timer_start].ctrl & GPTIMER_CTRL_IP) != 0)
-   irq_ack_mask = ~GPTIMER_CTRL_IP;
+   grlib_store_32(®s->timer[timer_start].tctrl, GPTIMER_TCTRL_IP);
+   if ((grlib_load_32(®s->timer[timer_start].tctrl) & GPTIMER_TCTRL_IP) 
!= 0)
+   irq_ack_mask = ~GPTIMER_TCTRL_IP;
else
-   irq_ack_mask = ~0;
+   irq_ack_mask = ~0U;
 
/* Probe timer register width mask */
-   priv->regs->timer[timer_start].value = 0x;
-   priv->widthmask = priv->regs->timer[timer_start].value;
+   grlib_store_32(®s->timer[timer_start].tcntval, 0x);
+   priv->widthmask = grlib_load_32(®s->timer[timer_start].tcntval);
 
priv->timer_cnt = timer_cnt;
for (i=0; iseparate_interrupt = (regs->cfg & GPTIMER_CFG_SI) != 0;
+   priv->separate_interrupt = (grlib_load_32(®s->config) & 
GPTIMER_CONFIG_SI) != 0;
 
return DRVMGR_OK;
 }
@@ -326,7 +295,7 @@ static int gptimer_info(
void *p, int argc, char *argv[])
 {
struct gptimer_priv *priv = dev->priv;
-   struct gptimer_timer *timer;
+   struct gptimer_timer_priv *timer;
char buf[64];
int i;
 
@@ -337,7 +306,7 @@ static int gptimer_info(
print_line(p, buf);
sprintf(buf, "REGS:0x%08x", (unsigned int)priv->regs);
print_line(p, buf);
-   sprintf(buf, "BASE SCALER: %d", priv->regs->scaler_reload);
+   sprintf(buf, "BASE SCALER: %d", grlib_load_32(&priv->regs->sreload));
print_line(p, buf);
sprintf(buf, "BASE FREQ:   %dkHz", priv->base_freq / 1000);
print_line(p, buf);
@@ -350,9 +319,9 @@ static int gptimer_info(
print_line(p, buf);
sprintf(buf, " TLIB Index: %d", timer->index);
print_line(p, buf);
-   sprintf(buf, " RELOAD REG: %d", timer->tregs->reload);
+   sprintf(buf, 

[PATCH v3 28/38] bsp/leon3: Simplify fatal error handling

[Sebastian Huber]

---
 bsps/sparc/leon3/include/bsp/leon3.h | 12 
 bsps/sparc/leon3/start/bspclean.c| 89 +++-
 bsps/sparc/leon3/start/bspsmp.c  | 16 +
 3 files changed, 77 insertions(+), 40 deletions(-)

diff --git a/bsps/sparc/leon3/include/bsp/leon3.h 
b/bsps/sparc/leon3/include/bsp/leon3.h
index 1394dd1c1c..476ed73647 100644
--- a/bsps/sparc/leon3/include/bsp/leon3.h
+++ b/bsps/sparc/leon3/include/bsp/leon3.h
@@ -161,6 +161,18 @@ static inline uint32_t 
leon3_get_data_cache_config_register( void )
   return leon3_get_system_register( 0xc );
 }
 
+/**
+ * @brief Gets the processor count.
+ *
+ * @param[in] regs is the IRQ(A)MP register block address.
+ *
+ * @return Returns the processor count.
+ */
+static inline uint32_t leon3_get_cpu_count( const irqamp *regs )
+{
+  return IRQAMP_MPSTAT_NCPU_GET( grlib_load_32( ®s->mpstat ) ) + 1;
+}
+
 /**
  * @brief This constant defines the index of the GPTIMER timer used by the
  *   clock driver.
diff --git a/bsps/sparc/leon3/start/bspclean.c 
b/bsps/sparc/leon3/start/bspclean.c
index acb2d6093c..4c9b385b43 100644
--- a/bsps/sparc/leon3/start/bspclean.c
+++ b/bsps/sparc/leon3/start/bspclean.c
@@ -35,14 +35,62 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
+#if defined(RTEMS_SMP)
+static void leon3_wait_for_power_down(irqamp *regs)
+{
+  uint32_t max_wait;
+  uint32_t cpu_self;
+  uint32_t cpu_count;
+  uint32_t halt_mask;
+  uint32_t i;
+
+  cpu_count = leon3_get_cpu_count(regs);
+
+  if (cpu_count > rtems_configuration_get_maximum_processors()) {
+cpu_count = rtems_configuration_get_maximum_processors();
+  }
+
+  cpu_self = rtems_scheduler_get_processor();
+  halt_mask = 0;
+
+  for (i = 0; i < cpu_count; ++i) {
+if (i != cpu_self && _SMP_Should_start_processor(i)) {
+  halt_mask |= UINT32_C(1) << i;
+}
+  }
+
+  /*
+   * Wait some time for secondary processors to halt.
+   *
+   * The value was chosen to get something in the magnitude of 1ms on a 200MHz
+   * processor.
+   */
+
+  max_wait = 1234567;
+  i = 0;
+
+  while (
+(grlib_load_32(®s->mpstat) & halt_mask) != halt_mask && i < max_wait
+  ) {
+++i;
+  }
+}
+#endif
+
 void bsp_fatal_extension(
   rtems_fatal_source source,
   bool always_set_to_false,
   rtems_fatal_code code
 )
 {
+  rtems_interrupt_level level;
+
+  rtems_interrupt_local_disable(level);
+  (void) level;
+
 #if defined(RTEMS_SMP)
   /*
* On SMP we must wait for all other CPUs not requesting a fatal halt, they
@@ -54,34 +102,18 @@ void bsp_fatal_extension(
   (code == SMP_FATAL_SHUTDOWN_RESPONSE)) {
 leon3_power_down_loop(); /* CPU didn't start shutdown sequence .. */
   } else {
-irqamp *regs = LEON3_IrqCtrl_Regs;
+irqamp *regs;
+
+_SMP_Request_shutdown();
 
+regs = LEON3_IrqCtrl_Regs;
+#if defined(LEON3_IRQAMP_BASE)
+leon3_wait_for_power_down(regs);
+#else
 if (regs != NULL) {
-  /*
-   * Value was chosen to get something in the magnitude of 1ms on a 200MHz
-   * processor.
-   */
-  uint32_t max_wait = 1234567;
-  uint32_t self_cpu = rtems_scheduler_get_processor();
-  uint32_t cpu_count = rtems_scheduler_get_processor_maximum();
-  uint32_t halt_mask = 0;
-  uint32_t i;
-
-  for (i = 0; i < cpu_count; ++i) {
-if ( (i != self_cpu) && _SMP_Should_start_processor( i ) ) {
-  halt_mask |= UINT32_C(1) << i;
-}
-  }
-
-  /* Wait some time for secondary processors to halt */
-  i = 0;
-  while (
-(grlib_load_32(®s->mpstat) & halt_mask) != halt_mask &&
-i < max_wait
-  ) {
-++i;
-  }
+  leon3_wait_for_power_down(regs);
 }
+#endif
   }
 #endif
 
@@ -92,7 +124,10 @@ void bsp_fatal_extension(
 #endif
 
 #if BSP_RESET_BOARD_AT_EXIT
-  /* If user wants to implement custom reset/reboot it can be done here */
-  bsp_reset();
+  /*
+   * Stop the system termination right now.  This skips the dynamically
+   * installed fatal error extensions and the generics shutdown procedure.
+   */
+  _CPU_Fatal_halt( source, code );
 #endif
 }
diff --git a/bsps/sparc/leon3/start/bspsmp.c b/bsps/sparc/leon3/start/bspsmp.c
index 7f8496289a..dc4065450a 100644
--- a/bsps/sparc/leon3/start/bspsmp.c
+++ b/bsps/sparc/leon3/start/bspsmp.c
@@ -39,14 +39,9 @@ static void bsp_inter_processor_interrupt( void *arg )
 
 void bsp_start_on_secondary_processor(Per_CPU_Control *cpu_self)
 {
-  /*
-   * If data cache snooping is not enabled we terminate using BSP_fatal_exit()
-   * instead of bsp_fatal().  This is done since the latter function tries to
-   * acquire a ticket lock, an operation which requires data cache snooping to
-   * be enabled.
-   */
-  if ( !leon3_data_cache_snooping_enabled() )
-BSP_fatal_exit( LEON3_FATAL_INVALID_CACHE_CONFIG_SECONDARY_PROCESSOR );
+  if ( !leon3_data_cache_snooping_enabled() ) {
+bsp_fatal( LEON3_FATAL_INVALID_CACHE_CONFIG_SECONDARY_PROCESSOR );
+  }
 
   _SMP_Start_multitasking_on_secondary_processor(cpu_self);
 }
@@

[PATCH v3 24/38] bsp/leon3: Add LEON3_IRQAMP_PROBE_TIMESTAMP

[Sebastian Huber]

---
 bsps/sparc/leon3/clock/ckinit.c | 198 
 bsps/sparc/leon3/start/cpucounter.c | 103 ++
 spec/build/bsps/sparc/leon3/grp.yml |   2 +
 spec/build/bsps/sparc/leon3/optirqampts.yml |  22 +++
 4 files changed, 207 insertions(+), 118 deletions(-)
 create mode 100644 spec/build/bsps/sparc/leon3/optirqampts.yml

diff --git a/bsps/sparc/leon3/clock/ckinit.c b/bsps/sparc/leon3/clock/ckinit.c
index fc20577634..fb07e0bf01 100644
--- a/bsps/sparc/leon3/clock/ckinit.c
+++ b/bsps/sparc/leon3/clock/ckinit.c
@@ -64,11 +64,29 @@
 /* LEON3 Timer system interrupt number */
 static int clkirq;
 
-static void (*leon3_tc_tick)(void);
-
 static struct timecounter leon3_tc;
 
-#ifdef RTEMS_PROFILING
+static void leon3_tc_tick_default(void)
+{
+#if !defined(RTEMS_SMP)
+  SPARC_Counter *counter;
+  rtems_interrupt_level level;
+
+  counter = &_SPARC_Counter_mutable;
+  rtems_interrupt_local_disable(level);
+
+  LEON3_IrqCtrl_Regs->iclear = counter->pending_mask;
+  counter->accumulated += counter->interval;
+
+  rtems_interrupt_local_enable(level);
+#endif
+
+  rtems_timecounter_tick();
+}
+
+#if defined(RTEMS_PROFILING)
+static void (*leon3_tc_tick)(void) = leon3_tc_tick_default;
+
 #define IRQMP_TIMESTAMP_S1_S2 ((1U << 25) | (1U << 26))
 
 static void leon3_tc_tick_irqmp_timestamp(void)
@@ -84,11 +102,9 @@ static void leon3_tc_tick_irqmp_timestamp(void)
 
   rtems_timecounter_tick();
 }
-#endif
 
 static void leon3_tc_tick_irqmp_timestamp_init(void)
 {
-#ifdef RTEMS_PROFILING
   /*
* Ignore the first clock interrupt, since it contains the sequential system
* initialization time.  Do the timestamp initialization on the fly.
@@ -113,32 +129,18 @@ static void leon3_tc_tick_irqmp_timestamp_init(void)
   if (done) {
 leon3_tc_tick = leon3_tc_tick_irqmp_timestamp;
   }
-#endif
-
-  rtems_timecounter_tick();
-}
-
-static void leon3_tc_tick_default(void)
-{
-#ifndef RTEMS_SMP
-  SPARC_Counter *counter;
-  rtems_interrupt_level level;
-
-  counter = &_SPARC_Counter_mutable;
-  rtems_interrupt_local_disable(level);
-
-  LEON3_IrqCtrl_Regs->iclear = counter->pending_mask;
-  counter->accumulated += counter->interval;
-
-  rtems_interrupt_local_enable(level);
-#endif
 
   rtems_timecounter_tick();
 }
+#endif /* RTEMS_PROFILING */
 
 static void leon3_tc_do_tick(void)
 {
+#if defined(RTEMS_PROFILING)
   (*leon3_tc_tick)();
+#else
+  leon3_tc_tick_default();
+#endif
 }
 
 #define Adjust_clkirq_for_node() do { clkirq += LEON3_CLOCK_INDEX; } while(0)
@@ -181,9 +183,87 @@ static void 
bsp_clock_handler_install(rtems_interrupt_handler isr)
 #define Clock_driver_support_set_interrupt_affinity(online_processors) \
   bsp_interrupt_set_affinity(clkirq, online_processors)
 
+static void leon3_clock_use_up_counter(struct timecounter *tc)
+{
+  tc->tc_get_timecount = _SPARC_Get_timecount_asr23;
+  tc->tc_frequency = leon3_up_counter_frequency();
+
+#if defined(RTEMS_PROFILING)
+  if (irqamp_get_timestamp_registers(LEON3_IrqCtrl_Regs) == NULL) {
+bsp_fatal(LEON3_FATAL_CLOCK_NO_IRQMP_TIMESTAMP_SUPPORT);
+  }
+
+  leon3_tc_tick = leon3_tc_tick_irqmp_timestamp_init;
+#endif
+
+  rtems_timecounter_install(tc);
+}
+
+#if defined(LEON3_IRQAMP_PROBE_TIMESTAMP)
+static void leon3_clock_use_irqamp_timestamp(
+  struct timecounter *tc,
+  irqamp_timestamp *irqmp_ts
+)
+{
+  tc->tc_get_timecount = _SPARC_Get_timecount_up;
+#if defined(LEON3_PLB_FREQUENCY_DEFINED_BY_GPTIMER)
+  tc->tc_frequency = leon3_processor_local_bus_frequency();
+#else
+  tc->tc_frequency = ambapp_freq_get(ambapp_plb(), LEON3_Timer_Adev);
+#endif
+
+#if defined(RTEMS_PROFILING)
+  leon3_tc_tick = leon3_tc_tick_irqmp_timestamp_init;
+#endif
+
+  /*
+   * At least one TSISEL field must be non-zero to enable the timestamp
+   * counter.  Use an arbitrary interrupt source.
+   */
+  grlib_store_32(&irqmp_ts->itstmpc, IRQAMP_ITSTMPC_TSISEL(1));
+
+  rtems_timecounter_install(tc);
+}
+#endif
+
+static void leon3_clock_use_gptimer(
+  struct timecounter *tc,
+  gptimer_timer *timer
+)
+{
+#ifdef RTEMS_SMP
+  /*
+   * The GR712RC for example has no timestamp unit in the interrupt
+   * controller.  At least on SMP configurations we must use a second timer
+   * in free running mode for the timecounter.  The timer is initialized by
+   * leon3_counter_initialize().
+   */
+  tc->tc_get_timecount = _SPARC_Get_timecount_down;
+#else
+  SPARC_Counter *counter;
+
+  counter = &_SPARC_Counter_mutable;
+  counter->read_isr_disabled = _SPARC_Counter_read_clock_isr_disabled;
+  counter->read = _SPARC_Counter_read_clock;
+  counter->counter_register = &timer->tcntval;
+  counter->pending_register = &LEON3_IrqCtrl_Regs->ipend;
+  counter->pending_mask = UINT32_C(1) << clkirq;
+  counter->accumulated = rtems_configuration_get_microseconds_per_tick();
+  counter->interval = rtems_configuration_get_microseconds_per_tick();
+
+  tc->tc_get_timecount = _SPARC_Get_timecount_clock;
+#endif
+
+  tc->tc_frequency = LEON3_GPTIMER_0_FREQUENCY_SET_BY_

[PATCH v3 25/38] bsp/leon3: Add LEON3_HAS_ASR_22_23_UP_COUNTER

[Sebastian Huber]

---
 bsps/sparc/leon3/clock/ckinit.c |  6 ++
 bsps/sparc/leon3/include/bsp/leon3.h|  2 ++
 bsps/sparc/leon3/start/cpucounter.c |  8 
 spec/build/bsps/sparc/leon3/grp.yml |  2 ++
 spec/build/bsps/sparc/leon3/optasrupcnt.yml | 17 +
 5 files changed, 35 insertions(+)
 create mode 100644 spec/build/bsps/sparc/leon3/optasrupcnt.yml

diff --git a/bsps/sparc/leon3/clock/ckinit.c b/bsps/sparc/leon3/clock/ckinit.c
index fb07e0bf01..0c8a0a8754 100644
--- a/bsps/sparc/leon3/clock/ckinit.c
+++ b/bsps/sparc/leon3/clock/ckinit.c
@@ -226,6 +226,7 @@ static void leon3_clock_use_irqamp_timestamp(
 }
 #endif
 
+#if !defined(LEON3_HAS_ASR_22_23_UP_COUNTER)
 static void leon3_clock_use_gptimer(
   struct timecounter *tc,
   gptimer_timer *timer
@@ -258,6 +259,7 @@ static void leon3_clock_use_gptimer(
 
   rtems_timecounter_install(tc);
 }
+#endif
 
 static void leon3_clock_initialize(void)
 {
@@ -284,6 +286,9 @@ static void leon3_clock_initialize(void)
 
   leon3_up_counter_enable();
 
+#if defined(LEON3_HAS_ASR_22_23_UP_COUNTER)
+  leon3_clock_use_up_counter(tc);
+#else /* LEON3_HAS_ASR_22_23_UP_COUNTER */
   if (leon3_up_counter_is_available()) {
 /* Use the LEON4 up-counter if available */
 leon3_clock_use_up_counter(tc);
@@ -301,6 +306,7 @@ static void leon3_clock_initialize(void)
 #endif
 
   leon3_clock_use_gptimer(tc, timer);
+#endif /* LEON3_HAS_ASR_22_23_UP_COUNTER */
 }
 
 #define Clock_driver_support_initialize_hardware() \
diff --git a/bsps/sparc/leon3/include/bsp/leon3.h 
b/bsps/sparc/leon3/include/bsp/leon3.h
index 18db7b8aea..f9717c364c 100644
--- a/bsps/sparc/leon3/include/bsp/leon3.h
+++ b/bsps/sparc/leon3/include/bsp/leon3.h
@@ -263,6 +263,7 @@ static inline void leon3_up_counter_enable( void )
   );
 }
 
+#if !defined(LEON3_HAS_ASR_22_23_UP_COUNTER)
 /**
  * @brief Checks if the LEON up-counter is available.
  *
@@ -274,6 +275,7 @@ static inline bool leon3_up_counter_is_available( void )
 {
   return leon3_up_counter_low() != leon3_up_counter_low();
 }
+#endif
 
 /**
  * @brief Gets the LEON up-counter frequency in Hz.
diff --git a/bsps/sparc/leon3/start/cpucounter.c 
b/bsps/sparc/leon3/start/cpucounter.c
index 18fc8099f2..d09dbe651b 100644
--- a/bsps/sparc/leon3/start/cpucounter.c
+++ b/bsps/sparc/leon3/start/cpucounter.c
@@ -68,6 +68,7 @@ static void leon3_counter_use_irqamp_timestamp(
 }
 #endif
 
+#if !defined(LEON3_HAS_ASR_22_23_UP_COUNTER)
 static void leon3_counter_use_gptimer(SPARC_Counter *counter, gptimer *gpt)
 {
   gptimer_timer *timer;
@@ -88,19 +89,25 @@ static void leon3_counter_use_gptimer(SPARC_Counter 
*counter, gptimer *gpt)
 (grlib_load_32(&gpt->sreload) + 1);
 #endif
 }
+#endif
 
 static void leon3_counter_initialize(void)
 {
 #if defined(LEON3_IRQAMP_PROBE_TIMESTAMP)
   irqamp_timestamp *irqmp_ts;
 #endif
+#if !defined(LEON3_HAS_ASR_22_23_UP_COUNTER)
   gptimer *gpt;
+#endif
   SPARC_Counter *counter;
 
   counter = &_SPARC_Counter_mutable;
 
   leon3_up_counter_enable();
 
+#if defined(LEON3_HAS_ASR_22_23_UP_COUNTER)
+  leon3_counter_use_up_counter(counter);
+#else /* LEON3_HAS_ASR_22_23_UP_COUNTER */
   if (leon3_up_counter_is_available()) {
 /* Use the LEON4 up-counter if available */
 leon3_counter_use_up_counter(counter);
@@ -123,6 +130,7 @@ static void leon3_counter_initialize(void)
 /* Fall back to the first GPTIMER if available */
 leon3_counter_use_gptimer(counter, gpt);
   }
+#endif /* LEON3_HAS_ASR_22_23_UP_COUNTER */
 }
 
 RTEMS_SYSINIT_ITEM(
diff --git a/spec/build/bsps/sparc/leon3/grp.yml 
b/spec/build/bsps/sparc/leon3/grp.yml
index 9d9f7d2750..d044a6ca60 100644
--- a/spec/build/bsps/sparc/leon3/grp.yml
+++ b/spec/build/bsps/sparc/leon3/grp.yml
@@ -34,6 +34,8 @@ links:
   uid: objsmp
 - role: build-dependency
   uid: optapbuartbase
+- role: build-dependency
+  uid: optasrupcnt
 - role: build-dependency
   uid: optgptimerbase
 - role: build-dependency
diff --git a/spec/build/bsps/sparc/leon3/optasrupcnt.yml 
b/spec/build/bsps/sparc/leon3/optasrupcnt.yml
new file mode 100644
index 00..77e923f205
--- /dev/null
+++ b/spec/build/bsps/sparc/leon3/optasrupcnt.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+default:
+- enabled-by: sparc/gr740
+  value: true
+enabled-by: true
+links: []
+name: LEON3_HAS_ASR_22_23_UP_COUNTER
+description: |
+  If this option is set to true, then the processor has the %asr22 and %asr23
+  up-counter.
+type: build
-- 
2.35.3

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[PATCH v3 34/38] bsp/leon3: Fix group memberships

[Sebastian Huber]

Update #3706.
---
 bsps/sparc/leon3/gnatsupp/gnatsupp.c | 2 +-
 bsps/sparc/leon3/include/bsp/irq.h   | 2 +-
 bsps/sparc/leon3/include/leon.h  | 2 +-
 bsps/sparc/leon3/include/tm27.h  | 2 +-
 bsps/sparc/leon3/start/bspclean.c| 2 +-
 bsps/sparc/leon3/start/bspsmp.c  | 2 +-
 bsps/sparc/leon3/start/setvec.c  | 2 +-
 7 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/bsps/sparc/leon3/gnatsupp/gnatsupp.c 
b/bsps/sparc/leon3/gnatsupp/gnatsupp.c
index cc5b1027a7..79e68eab7c 100644
--- a/bsps/sparc/leon3/gnatsupp/gnatsupp.c
+++ b/bsps/sparc/leon3/gnatsupp/gnatsupp.c
@@ -1,7 +1,7 @@
 /**
  * @file
  *
- * @ingroup sparc_leon3
+ * @ingroup RTEMSBSPsSPARCLEON3
  *
  * @brief Support for gnat/rtems interrupts and exception handling
  */
diff --git a/bsps/sparc/leon3/include/bsp/irq.h 
b/bsps/sparc/leon3/include/bsp/irq.h
index 38ea1de1f8..2e500622bf 100644
--- a/bsps/sparc/leon3/include/bsp/irq.h
+++ b/bsps/sparc/leon3/include/bsp/irq.h
@@ -2,7 +2,7 @@
 
 /**
  * @file
- * @ingroup sparc_leon3
+ * @ingroup RTEMSBSPsSPARCLEON3
  * @brief LEON3 generic shared IRQ setup
  *
  * Based on libbsp/shared/include/irq.h.
diff --git a/bsps/sparc/leon3/include/leon.h b/bsps/sparc/leon3/include/leon.h
index 54d566799a..812f691fd0 100644
--- a/bsps/sparc/leon3/include/leon.h
+++ b/bsps/sparc/leon3/include/leon.h
@@ -2,7 +2,7 @@
 
 /**
  * @file
- * @ingroup sparc_leon3
+ * @ingroup RTEMSBSPsSPARCLEON3
  * @brief LEON3 BSP data types and macros
  */
 
diff --git a/bsps/sparc/leon3/include/tm27.h b/bsps/sparc/leon3/include/tm27.h
index f078b12dd1..df30b738b2 100644
--- a/bsps/sparc/leon3/include/tm27.h
+++ b/bsps/sparc/leon3/include/tm27.h
@@ -2,7 +2,7 @@
 
 /**
  * @file
- * @ingroup sparc_leon3
+ * @ingroup RTEMSBSPsSPARCLEON3
  * @brief Implementations for interrupt mechanisms for Time Test 27
  */
 
diff --git a/bsps/sparc/leon3/start/bspclean.c 
b/bsps/sparc/leon3/start/bspclean.c
index 4c9b385b43..d52eb65ecf 100644
--- a/bsps/sparc/leon3/start/bspclean.c
+++ b/bsps/sparc/leon3/start/bspclean.c
@@ -2,7 +2,7 @@
 
 /**
  * @file
- * @ingroup sparc_leon3
+ * @ingroup RTEMSBSPsSPARCLEON3
  * @brief LEON3 BSP fatal extension
  *
  *  Copyright (c) 2014 embedded brains GmbH & Co. KG
diff --git a/bsps/sparc/leon3/start/bspsmp.c b/bsps/sparc/leon3/start/bspsmp.c
index dc4065450a..8c7c88da63 100644
--- a/bsps/sparc/leon3/start/bspsmp.c
+++ b/bsps/sparc/leon3/start/bspsmp.c
@@ -1,6 +1,6 @@
 /**
  * @file
- * @ingroup sparc_leon3
+ * @ingroup RTEMSBSPsSPARCLEON3
  * @brief LEON3 SMP BSP Support
  */
 
diff --git a/bsps/sparc/leon3/start/setvec.c b/bsps/sparc/leon3/start/setvec.c
index 31461893ff..b60796f3c4 100644
--- a/bsps/sparc/leon3/start/setvec.c
+++ b/bsps/sparc/leon3/start/setvec.c
@@ -1,6 +1,6 @@
 /**  
  * @file
- * @ingroup sparc_leon3
+ * @ingroup RTEMSBSPsSPARCLEON3
  * @brief Install an interrupt vector on SPARC
  */
 
-- 
2.35.3

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[PATCH v3 30/38] bsp/leon3: Add LEON3_IRQAMP_EXTENDED_INTERRUPT

[Sebastian Huber]

---
 bsps/sparc/leon3/include/bsp/irqimpl.h|  4 
 bsps/sparc/leon3/start/eirq.c |  8 
 spec/build/bsps/sparc/leon3/grp.yml   |  2 ++
 .../bsps/sparc/leon3/optirqampextirq.yml  | 19 +++
 4 files changed, 33 insertions(+)
 create mode 100644 spec/build/bsps/sparc/leon3/optirqampextirq.yml

diff --git a/bsps/sparc/leon3/include/bsp/irqimpl.h 
b/bsps/sparc/leon3/include/bsp/irqimpl.h
index ee5beaf72c..f5b0c205e0 100644
--- a/bsps/sparc/leon3/include/bsp/irqimpl.h
+++ b/bsps/sparc/leon3/include/bsp/irqimpl.h
@@ -103,7 +103,11 @@ extern struct ambapp_dev *LEON3_IrqCtrl_Adev;
  *
  * This object should be read-only after initialization.
  */
+#if defined(LEON3_IRQAMP_EXTENDED_INTERRUPT)
+#define LEON3_IrqCtrl_EIrq LEON3_IRQAMP_EXTENDED_INTERRUPT
+#else
 extern uint32_t LEON3_IrqCtrl_EIrq;
+#endif
 
 /**
  * @brief Initializes the interrupt controller for the boot processor.
diff --git a/bsps/sparc/leon3/start/eirq.c b/bsps/sparc/leon3/start/eirq.c
index 5576c37c22..05e6789f69 100644
--- a/bsps/sparc/leon3/start/eirq.c
+++ b/bsps/sparc/leon3/start/eirq.c
@@ -35,8 +35,10 @@
 #include 
 #include 
 
+#if !defined(LEON3_IRQAMP_EXTENDED_INTERRUPT)
 /* GRLIB extended IRQ controller IRQ number */
 uint32_t LEON3_IrqCtrl_EIrq;
+#endif
 
 rtems_interrupt_lock LEON3_IrqCtrl_Lock =
   RTEMS_INTERRUPT_LOCK_INITIALIZER("LEON3 IrqCtrl");
@@ -47,7 +49,9 @@ void leon3_ext_irq_init(irqamp *regs)
   grlib_store_32(®s->pimask[LEON3_Cpu_Index], 0);
   grlib_store_32(®s->piforce[LEON3_Cpu_Index], 0);
   grlib_store_32(®s->iclear, 0x);
+#if !defined(LEON3_IRQAMP_EXTENDED_INTERRUPT)
   LEON3_IrqCtrl_EIrq = IRQAMP_MPSTAT_EIRQ_GET(grlib_load_32(®s->mpstat));
+#endif
 }
 
 bool bsp_interrupt_is_valid_vector(rtems_vector_number vector)
@@ -56,11 +60,15 @@ bool bsp_interrupt_is_valid_vector(rtems_vector_number 
vector)
 return false;
   }
 
+#if defined(LEON3_IRQAMP_EXTENDED_INTERRUPT)
+  return vector <= BSP_INTERRUPT_VECTOR_MAX_EXT;
+#else
   if (LEON3_IrqCtrl_EIrq > 0) {
 return vector <= BSP_INTERRUPT_VECTOR_MAX_EXT;
   }
 
   return vector <= BSP_INTERRUPT_VECTOR_MAX_STD;
+#endif
 }
 
 #if defined(RTEMS_SMP)
diff --git a/spec/build/bsps/sparc/leon3/grp.yml 
b/spec/build/bsps/sparc/leon3/grp.yml
index 94d11bed55..126ba0df65 100644
--- a/spec/build/bsps/sparc/leon3/grp.yml
+++ b/spec/build/bsps/sparc/leon3/grp.yml
@@ -42,6 +42,8 @@ links:
   uid: optgptimerbase
 - role: build-dependency
   uid: optirqampbase
+- role: build-dependency
+  uid: optirqampextirq
 - role: build-dependency
   uid: optirqampts
 - role: build-dependency
diff --git a/spec/build/bsps/sparc/leon3/optirqampextirq.yml 
b/spec/build/bsps/sparc/leon3/optirqampextirq.yml
new file mode 100644
index 00..61e077de5d
--- /dev/null
+++ b/spec/build/bsps/sparc/leon3/optirqampextirq.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+actions:
+- get-integer: null
+- format-and-define: null
+build-type: option
+default:
+- enabled-by: sparc/gr712rc
+  value: 12
+- enabled-by: sparc/gr740
+  value: 10
+enabled-by: true
+format: '{}'
+links: []
+name: LEON3_IRQAMP_EXTENDED_INTERRUPT
+description: |
+  This option specifies the interrupt line of the IRQ(A)MP extended interrupt.
+type: build
-- 
2.35.3

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[PATCH v3 38/38] bsp/leon3: Simplify shutdown

[Sebastian Huber]

Do not wait for other processors to halt.
---
 bsps/sparc/leon3/start/bspclean.c | 63 +--
 .../bsps/fatal-sparc-leon3-shutdown.yml   |  3 +-
 2 files changed, 4 insertions(+), 62 deletions(-)

diff --git a/bsps/sparc/leon3/start/bspclean.c 
b/bsps/sparc/leon3/start/bspclean.c
index d52eb65ecf..0324c45326 100644
--- a/bsps/sparc/leon3/start/bspclean.c
+++ b/bsps/sparc/leon3/start/bspclean.c
@@ -38,48 +38,6 @@
 #include 
 #include 
 
-#if defined(RTEMS_SMP)
-static void leon3_wait_for_power_down(irqamp *regs)
-{
-  uint32_t max_wait;
-  uint32_t cpu_self;
-  uint32_t cpu_count;
-  uint32_t halt_mask;
-  uint32_t i;
-
-  cpu_count = leon3_get_cpu_count(regs);
-
-  if (cpu_count > rtems_configuration_get_maximum_processors()) {
-cpu_count = rtems_configuration_get_maximum_processors();
-  }
-
-  cpu_self = rtems_scheduler_get_processor();
-  halt_mask = 0;
-
-  for (i = 0; i < cpu_count; ++i) {
-if (i != cpu_self && _SMP_Should_start_processor(i)) {
-  halt_mask |= UINT32_C(1) << i;
-}
-  }
-
-  /*
-   * Wait some time for secondary processors to halt.
-   *
-   * The value was chosen to get something in the magnitude of 1ms on a 200MHz
-   * processor.
-   */
-
-  max_wait = 1234567;
-  i = 0;
-
-  while (
-(grlib_load_32(®s->mpstat) & halt_mask) != halt_mask && i < max_wait
-  ) {
-++i;
-  }
-}
-#endif
-
 void bsp_fatal_extension(
   rtems_fatal_source source,
   bool always_set_to_false,
@@ -92,29 +50,12 @@ void bsp_fatal_extension(
   (void) level;
 
 #if defined(RTEMS_SMP)
-  /*
-   * On SMP we must wait for all other CPUs not requesting a fatal halt, they
-   * are responding to another CPU's fatal request. These CPUs goes into
-   * power-down. The CPU requesting fatal halt waits for the others and then
-   * handles the system shutdown via the normal procedure.
-   */
   if ((source == RTEMS_FATAL_SOURCE_SMP) &&
   (code == SMP_FATAL_SHUTDOWN_RESPONSE)) {
 leon3_power_down_loop(); /* CPU didn't start shutdown sequence .. */
-  } else {
-irqamp *regs;
-
-_SMP_Request_shutdown();
-
-regs = LEON3_IrqCtrl_Regs;
-#if defined(LEON3_IRQAMP_BASE)
-leon3_wait_for_power_down(regs);
-#else
-if (regs != NULL) {
-  leon3_wait_for_power_down(regs);
-}
-#endif
   }
+
+  _SMP_Request_shutdown();
 #endif
 
 #if BSP_PRINT_EXCEPTION_CONTEXT
diff --git 
a/spec/build/testsuites/validation/bsps/fatal-sparc-leon3-shutdown.yml 
b/spec/build/testsuites/validation/bsps/fatal-sparc-leon3-shutdown.yml
index c12f447e84..e1a0f32900 100644
--- a/spec/build/testsuites/validation/bsps/fatal-sparc-leon3-shutdown.yml
+++ b/spec/build/testsuites/validation/bsps/fatal-sparc-leon3-shutdown.yml
@@ -11,7 +11,8 @@ enabled-by:
   - bsps/sparc/leon3
 features: c cprogram
 includes: []
-ldflags: []
+ldflags:
+- -Wl,--wrap=_CPU_Fatal_halt
 links: []
 source:
 - testsuites/validation/bsps/tc-fatal-sparc-leon3-shutdown.c
-- 
2.35.3

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[PATCH v3 31/38] bsp/leon3: Use LEON3_GPTIMER_BASE

[Sebastian Huber]

---
 bsps/sparc/leon3/start/cpucounter.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/bsps/sparc/leon3/start/cpucounter.c 
b/bsps/sparc/leon3/start/cpucounter.c
index 46e0b304e5..05ac62ace8 100644
--- a/bsps/sparc/leon3/start/cpucounter.c
+++ b/bsps/sparc/leon3/start/cpucounter.c
@@ -131,10 +131,14 @@ static void leon3_counter_initialize(void)
 
   gpt = LEON3_Timer_Regs;
 
+#if defined(LEON3_GPTIMER_BASE)
+  leon3_counter_use_gptimer(counter, gpt);
+#else
   if (gpt != NULL) {
 /* Fall back to the first GPTIMER if available */
 leon3_counter_use_gptimer(counter, gpt);
   }
+#endif
 #endif /* LEON3_HAS_ASR_22_23_UP_COUNTER */
 }
 
-- 
2.35.3

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[PATCH v3 33/38] bsps/sparc: Remove BSP_POWER_DOWN_AT_FATAL_HALT

[Sebastian Huber]

Remove the BSP_POWER_DOWN_AT_FATAL_HALT BSP option.  Applications should
do the customization of the system termination with an initial fatal
extension.
---
 bsps/sparc/leon3/start/bsp_fatal_halt.c  | 50 ---
 bsps/sparc/shared/start/bsp_fatal_halt.c | 52 
 cpukit/score/cpu/sparc/syscall.S |  2 +
 spec/build/bsps/sparc/erc32/bsperc32.yml |  3 --
 spec/build/bsps/sparc/erc32/optpwrdwnhlt.yml | 16 --
 spec/build/bsps/sparc/leon2/grp.yml  |  2 -
 spec/build/bsps/sparc/leon2/obj.yml  |  1 -
 spec/build/bsps/sparc/leon2/optpwrdwnhlt.yml | 16 --
 spec/build/bsps/sparc/leon3/grp.yml  |  2 -
 spec/build/bsps/sparc/leon3/obj.yml  |  1 -
 spec/build/bsps/sparc/leon3/optpwrdwnhlt.yml | 16 --
 11 files changed, 2 insertions(+), 159 deletions(-)
 delete mode 100644 bsps/sparc/leon3/start/bsp_fatal_halt.c
 delete mode 100644 bsps/sparc/shared/start/bsp_fatal_halt.c
 delete mode 100644 spec/build/bsps/sparc/erc32/optpwrdwnhlt.yml
 delete mode 100644 spec/build/bsps/sparc/leon2/optpwrdwnhlt.yml
 delete mode 100644 spec/build/bsps/sparc/leon3/optpwrdwnhlt.yml

diff --git a/bsps/sparc/leon3/start/bsp_fatal_halt.c 
b/bsps/sparc/leon3/start/bsp_fatal_halt.c
deleted file mode 100644
index ce628065b7..00
--- a/bsps/sparc/leon3/start/bsp_fatal_halt.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/**
- * @file
- * @ingroup sparc_leon3
- * @brief LEON3 BSP Fatal_halt handler.
- *
- *  COPYRIGHT (c) 2014.
- *  Aeroflex Gaisler AB.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *notice, this list of conditions and the following disclaimer in the
- *documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include 
-#include 
-#include 
-
-void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
-{
-#ifdef BSP_POWER_DOWN_AT_FATAL_HALT
-  /* Power down LEON CPU on fatal error exit */
-  sparc_disable_interrupts();
-  leon3_power_down_loop();
-#else
-  /*
-   * Return to debugger, simulator, hypervisor or similar by exiting
-   * with an error code. g1=1, g2=FATAL_SOURCE, G3=error-code.
-   */
-  sparc_syscall_exit(source, error);
-#endif
-}
diff --git a/bsps/sparc/shared/start/bsp_fatal_halt.c 
b/bsps/sparc/shared/start/bsp_fatal_halt.c
deleted file mode 100644
index ebce8c1928..00
--- a/bsps/sparc/shared/start/bsp_fatal_halt.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/**
- * @file
- * @ingroup RTEMSBSPsSPARCShared
- * @brief ERC32/LEON2 BSP Fatal_halt handler.
- *
- *  COPYRIGHT (c) 2014.
- *  Aeroflex Gaisler AB.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *notice, this list of conditions and the following disclaimer in the
- *documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * 

Re: [PATCH v2 01/32] bsps/grlib: Add generated headers

[Sebastian Huber]

Hello Martin,

thanks a lot for your thorough review. I tried to address your review 
comments in v3:


https://lists.rtems.org/pipermail/devel/2023-July/075713.html

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Re: [PATCH v3 12/38] bsps/grlib: Use GRLIB definition of GRSPWROUTER

[Sebastian Huber]

On 12.07.23 15:49, Sebastian Huber wrote:

+  /**
+   * @brief See @ref RTEMSDeviceGRSPWROUTERGPO0.
+   */
+  uint32_t gpo0;
+
+  /**
+   * @brief See @ref RTEMSDeviceGRSPWROUTERGPO1.
+   */
+  uint32_t gpo1;
+
+  /**
+   * @brief See @ref RTEMSDeviceGRSPWROUTERGPO2.
+   */
+  uint32_t gpo2;
+
+  /**
+   * @brief See @ref RTEMSDeviceGRSPWROUTERGPO3.
+   */
+  uint32_t gpo3;
+
+  /**
+   * @brief See @ref RTEMSDeviceGRSPWROUTERGPI0.
+   */
+  uint32_t gpi0;
+
+  /**
+   * @brief See @ref RTEMSDeviceGRSPWROUTERGPI1.
+   */
+  uint32_t gpi1;
+
+  /**
+   * @brief See @ref RTEMSDeviceGRSPWROUTERGPI2.
+   */
+  uint32_t gpi2;
+
+  /**
+   * @brief See @ref RTEMSDeviceGRSPWROUTERGPI3.
+   */
+  uint32_t gpi3;
+


I will change this to use arrays.

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Re: [PATCH] TMS570 console driver, SCI frame error (baudrate calculation error)

[Joel Sherrill]

Pavel this was filed as https://devel.rtems.org/ticket/4903. The ticket
submitter
didn't give a patch, just a code change snippet and explanation. Zack
turned it into
a patch. You will need to post that on the ticket to get the submitter's
feedback.

I hope you don't mind copying that to the ticket and seeing what you think
is
really up.

Thanks.

--joel

On Wed, Jul 12, 2023 at 8:49 AM Pavel Pisa  wrote:

> Hello Zack and Gedare,
>
> On Tuesday 11 of July 2023 19:52:27 Gedare Bloom wrote:
> > Thanks for the patch. Someone should probably test it, or identify in
> > the documentation why this calculation was off-by-1. Pavel, any clues?
> > On Sun, Jul 9, 2023 at 10:09 PM zack  wrote:
> > > Fixes #4903
> > > diff --git a/bsps/arm/tms570/console/tms570-sci.c
> > > b/bsps/arm/tms570/console/tms570-sci.c index 768770a4c8..59a0b7e6f1
> > > 100644
> > > --- a/bsps/arm/tms570/console/tms570-sci.c
> > > +++ b/bsps/arm/tms570/console/tms570-sci.c
> > > @@ -311,7 +311,7 @@ bool tms570_sci_set_attributes(
> > >/* Apply baudrate to the hardware */
> > >baudrate *= 2 * 16;
> > >bauddiv = (BSP_PLL_OUT_CLOCK + baudrate / 2) / baudrate;
> > > -  ctx->regs->BRS = bauddiv? bauddiv - 1: 0;
> > > +  ctx->regs->BRS = bauddiv? bauddiv - 2: 0;
>
> I think that change is not correct. The actual used values
> for BSP_PLL_OUT_CLOCK and baudrate should be provided to analyze
> the case. The code can result in some rounding error and can
> be enhanced if fractional divider is used or even super finegrained
> fractional divider. But these options are available only for
> for SCI/LIN peripheral case.
>
> According to
>
> TMS570LS31x/21x 16/32-Bit RISC Flash Microcontroller
> Technical Reference Manual
> Literature Number: SPNU499B
>
> 26.2.3 SCI Baud Rate
>
>   SCICLK Frequency = VCLK Frequency / (P + 1 + M / 16)
>
>   Asynchronous baud value = SCICLK Frequency / 16
>
> So the substraction of one corresponds to the manual.
>
> Actual code does not use M part. It would be problem if it is
> leftover from some boot/monitor but it is part of BRS 32-bit
> register which is overwritten in the whole, so such problem
> should not appear either.
>
> So I vote against the proposed change for now and suggest
> to do analysis what happens in the computation and what
> are input values and output. Change would/could affect
> negatively large number of combinations of the baudrate
> and clocks.
>
> I would consider to discuss if the rounding formula
> could/should be updated, but I think that it is the best
> which cane be achieved for rations which do not result
> in exact ratio.
>
>   (BSP_PLL_OUT_CLOCK + baudrate / 2) / baudrate;
>
> If there is interrest then code can be enhanced by fraction
> dividers for SCI/LIN peripheral case. The field with variant
> should be added into tms570_sci_context and in this case
> the alternative formula can be used
>
>   long long bauddiv;
>   bauddiv = (BSP_PLL_OUT_CLOCK * 16ll + baudrate / 2) / baudrate;
>   ctx->regs->BRS = ((bauddiv >> 4) & 0xff) | ((bauddiv & 0xf) << 24);
>
> which should be rewritten after header for SCI/LIN update to
>
>   ctx->regs->BRS = TMS570_LIN_BRS_P(bauddiv >> 4) |
> TMS570_LIN_BRS_M(bauddiv & 0xf);
>



>
> Best wishes,
>
>
> Pavel
> --
> Pavel Pisa
> phone:  +420 603531357
> e-mail: p...@cmp.felk.cvut.cz
> Department of Control Engineering FEE CVUT
> Karlovo namesti 13, 121 35, Prague 2
> university: http://control.fel.cvut.cz/
> personal:   http://cmp.felk.cvut.cz/~pisa
> projects:   https://www.openhub.net/accounts/ppisa
> CAN related:http://canbus.pages.fel.cvut.cz/
> RISC-V education: https://comparch.edu.cvut.cz/
> Open Technologies Research Education and Exchange Services
> https://gitlab.fel.cvut.cz/otrees/org/-/wikis/home
>
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Re: [PATCH] arm/stm32h7: Add support for STM32H750B-DK

[Kinsey Moore]

On 7/11/2023 4:58 PM, Karel Gardas wrote:

On 7/11/23 23:26, Kinsey Moore wrote:
I'm not sure that anything I've done for testing would have verified 
that the SDRAM is operating properly. I'll have to pull it back out 
and give it a shot.


If you write just few char or integer into the beginning of both 
regions you will see which one is working and which not. When "not" 
happen RTEMS will crash nicely.


btw: be aware of partial write like just a char or two. The MCU have 
ECC support permanently on and such partial writes may be and are 
delayed in expectation that more will write will happen soon and no 
need to update ECC bits. In that case you would also need to write 
somewhere else to enforce previous write to be committed...STMicro has 
a nice application note about it: AN5342.


I'm really curious what would be your result.


I took a look at an example application for this board in STM32CubeIDE 
and it's expecting SDRAM to be at 0xD000U which is definitely bank 
2. I'll get that updated and verified. Thanks for the review!



Kinsey

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Re: [PATCH] TMS570 console driver, SCI frame error (baudrate calculation error)

[Gedare Bloom]

On Wed, Jul 12, 2023 at 8:06 AM Joel Sherrill  wrote:
>
>
> Pavel this was filed as https://devel.rtems.org/ticket/4903. The ticket 
> submitter
> didn't give a patch, just a code change snippet and explanation. Zack turned 
> it into
> a patch. You will need to post that on the ticket to get the submitter's 
> feedback.
>
> I hope you don't mind copying that to the ticket and seeing what you think is
> really up.
>
I posted it over there. Thanks Pavel and Joel.

> Thanks.
>
> --joel
>
> On Wed, Jul 12, 2023 at 8:49 AM Pavel Pisa  wrote:
>>
>> Hello Zack and Gedare,
>>
>> On Tuesday 11 of July 2023 19:52:27 Gedare Bloom wrote:
>> > Thanks for the patch. Someone should probably test it, or identify in
>> > the documentation why this calculation was off-by-1. Pavel, any clues?
>> > On Sun, Jul 9, 2023 at 10:09 PM zack  wrote:
>> > > Fixes #4903
>> > > diff --git a/bsps/arm/tms570/console/tms570-sci.c
>> > > b/bsps/arm/tms570/console/tms570-sci.c index 768770a4c8..59a0b7e6f1
>> > > 100644
>> > > --- a/bsps/arm/tms570/console/tms570-sci.c
>> > > +++ b/bsps/arm/tms570/console/tms570-sci.c
>> > > @@ -311,7 +311,7 @@ bool tms570_sci_set_attributes(
>> > >/* Apply baudrate to the hardware */
>> > >baudrate *= 2 * 16;
>> > >bauddiv = (BSP_PLL_OUT_CLOCK + baudrate / 2) / baudrate;
>> > > -  ctx->regs->BRS = bauddiv? bauddiv - 1: 0;
>> > > +  ctx->regs->BRS = bauddiv? bauddiv - 2: 0;
>>
>> I think that change is not correct. The actual used values
>> for BSP_PLL_OUT_CLOCK and baudrate should be provided to analyze
>> the case. The code can result in some rounding error and can
>> be enhanced if fractional divider is used or even super finegrained
>> fractional divider. But these options are available only for
>> for SCI/LIN peripheral case.
>>
>> According to
>>
>> TMS570LS31x/21x 16/32-Bit RISC Flash Microcontroller
>> Technical Reference Manual
>> Literature Number: SPNU499B
>>
>> 26.2.3 SCI Baud Rate
>>
>>   SCICLK Frequency = VCLK Frequency / (P + 1 + M / 16)
>>
>>   Asynchronous baud value = SCICLK Frequency / 16
>>
>> So the substraction of one corresponds to the manual.
>>
>> Actual code does not use M part. It would be problem if it is
>> leftover from some boot/monitor but it is part of BRS 32-bit
>> register which is overwritten in the whole, so such problem
>> should not appear either.
>>
>> So I vote against the proposed change for now and suggest
>> to do analysis what happens in the computation and what
>> are input values and output. Change would/could affect
>> negatively large number of combinations of the baudrate
>> and clocks.
>>
>> I would consider to discuss if the rounding formula
>> could/should be updated, but I think that it is the best
>> which cane be achieved for rations which do not result
>> in exact ratio.
>>
>>   (BSP_PLL_OUT_CLOCK + baudrate / 2) / baudrate;
>>
>> If there is interrest then code can be enhanced by fraction
>> dividers for SCI/LIN peripheral case. The field with variant
>> should be added into tms570_sci_context and in this case
>> the alternative formula can be used
>>
>>   long long bauddiv;
>>   bauddiv = (BSP_PLL_OUT_CLOCK * 16ll + baudrate / 2) / baudrate;
>>   ctx->regs->BRS = ((bauddiv >> 4) & 0xff) | ((bauddiv & 0xf) << 24);
>>
>> which should be rewritten after header for SCI/LIN update to
>>
>>   ctx->regs->BRS = TMS570_LIN_BRS_P(bauddiv >> 4) | TMS570_LIN_BRS_M(bauddiv 
>> & 0xf);
>
>
>
>>
>>
>> Best wishes,
>>
>>
>> Pavel
>> --
>> Pavel Pisa
>> phone:  +420 603531357
>> e-mail: p...@cmp.felk.cvut.cz
>> Department of Control Engineering FEE CVUT
>> Karlovo namesti 13, 121 35, Prague 2
>> university: http://control.fel.cvut.cz/
>> personal:   http://cmp.felk.cvut.cz/~pisa
>> projects:   https://www.openhub.net/accounts/ppisa
>> CAN related:http://canbus.pages.fel.cvut.cz/
>> RISC-V education: https://comparch.edu.cvut.cz/
>> Open Technologies Research Education and Exchange Services
>> https://gitlab.fel.cvut.cz/otrees/org/-/wikis/home
>>
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[PATCH v2 2/2] bsps/stm32h7: Move SDRAM1 to correct memory range

[Kinsey Moore]

According to the documentation in STM reference manuals RM0399 and
RM0433, the standard memory space for SDRAM bank 1 is 0xc000 to
0xcfff.
---
 spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml 
b/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml
index 88dd4e8c91..2b3aacce5d 100644
--- a/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml
+++ b/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml
@@ -14,9 +14,9 @@ content: |
 SRAM_BACKUP : ORIGIN = 0x3880, LENGTH = 
${STM32H7_MEMORY_SRAM_BACKUP_SIZE:#010x}
 PERIPHERAL  : ORIGIN = 0x4000, LENGTH = 
${STM32H7_MEMORY_PERIPHERAL_SIZE:#010x}
 NOR : ORIGIN = 0x6000, LENGTH = 
${STM32H7_MEMORY_NOR_SIZE:#010x}
-SDRAM_1 : ORIGIN = 0x7000, LENGTH = 
${STM32H7_MEMORY_SDRAM_1_SIZE:#010x}
 NAND: ORIGIN = 0x8000, LENGTH = 
${STM32H7_MEMORY_NAND_SIZE:#010x}
 QUADSPI : ORIGIN = 0x9000, LENGTH = 
${STM32H7_MEMORY_QUADSPI_SIZE:#010x}
+SDRAM_1 : ORIGIN = 0xc000, LENGTH = 
${STM32H7_MEMORY_SDRAM_1_SIZE:#010x}
 SDRAM_2 : ORIGIN = 0xd000, LENGTH = 
${STM32H7_MEMORY_SDRAM_2_SIZE:#010x}
   }
 
-- 
2.39.2

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[PATCH v2 1/2] arm/stm32h7: Add support for STM32H750B-DK

[Kinsey Moore]

This adds support for the STM32H750B-DK discovery kit. This kit includes
a built-in STLINKv3 debugger which provides a USB serial bridge for
USART3. USART1 is routed to the Arduino header and USART2 is routed to
the STMOD connector. This BSP reuses what would otherwise be duplicated
files from the stm32h747i-disco BSP. Note that system_stm32h7xx.c has
been imported from the STM repository with two minor changes wrapped
with #if __rtems__. This hardware has been tested with hello and ticker.
---
 .../stm/stm32h750b-dk/stm32h7-config-per.c|  40 ++
 .../stm/stm32h750b-dk/system_stm32h7xx.c  | 528 ++
 bsps/arm/stm32h7/console/console-usart2-cfg.c |   4 +-
 .../bsps/arm/stm32h7/bspstm32h750b-dk.yml |  23 +
 spec/build/bsps/arm/stm32h7/grp.yml   |   4 +
 spec/build/bsps/arm/stm32h7/optlinkcmds.yml   |   1 +
 .../bsps/arm/stm32h7/optmemquadspisz.yml  |   1 +
 .../build/bsps/arm/stm32h7/optmemsdram2sz.yml |   3 +
 .../bsps/arm/stm32h7/optprintkinstance.yml|   4 +-
 .../bsps/arm/stm32h7/optusart1gpiopins.yml|   3 +
 .../bsps/arm/stm32h7/optusart1gpioregs.yml|   1 +
 .../bsps/arm/stm32h7/optusart2gpiopins.yml|  20 +
 .../bsps/arm/stm32h7/optusart2gpioregs.yml|  19 +
 .../bsps/arm/stm32h7/optusart3gpiopins.yml|   2 +
 .../bsps/arm/stm32h7/optusart3gpioregs.yml|   2 +
 spec/build/bsps/arm/stm32h7/optvariant.yml|   3 +
 16 files changed, 655 insertions(+), 3 deletions(-)
 create mode 100644 
bsps/arm/stm32h7/boards/stm/stm32h750b-dk/stm32h7-config-per.c
 create mode 100644 bsps/arm/stm32h7/boards/stm/stm32h750b-dk/system_stm32h7xx.c
 create mode 100644 spec/build/bsps/arm/stm32h7/bspstm32h750b-dk.yml
 create mode 100644 spec/build/bsps/arm/stm32h7/optusart2gpiopins.yml
 create mode 100644 spec/build/bsps/arm/stm32h7/optusart2gpioregs.yml

diff --git a/bsps/arm/stm32h7/boards/stm/stm32h750b-dk/stm32h7-config-per.c 
b/bsps/arm/stm32h7/boards/stm/stm32h750b-dk/stm32h7-config-per.c
new file mode 100644
index 00..f34a633305
--- /dev/null
+++ b/bsps/arm/stm32h7/boards/stm/stm32h750b-dk/stm32h7-config-per.c
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2023 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include 
+
+const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = {
+  /* for stm32h750b-dk BSP we provide U(S)ART1/2/3 */
+  .PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2
+ | RCC_PERIPHCLK_USART3,
+  .Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2,
+  .Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1,
+};
diff --git a/bsps/arm/stm32h7/boards/stm/stm32h750b-dk/system_stm32h7xx.c 
b/bsps/arm/stm32h7/boards/stm/stm32h750b-dk/system_stm32h7xx.c
new file mode 100644
index 00..78029a90cf
--- /dev/null
+++ b/bsps/arm/stm32h7/boards/stm/stm32h750b-dk/system_stm32h7xx.c
@@ -0,0 +1,528 @@
+/**
+  
**
+  * @filesystem_stm32h7xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called 
from 
+  *   user application:
+  *  - SystemInit(): This function is called at startup just after reset 
and 
+  *  before branch to main program. This call is made 
inside
+  *  the "startup_stm32h7xx.s" file.
+  *
+  *  - SystemCoreClock variable: Contains the core clock (HCLK), it can be 
used
+  *  by the use

Re: [PATCH v2 2/2] bsps/stm32h7: Move SDRAM1 to correct memory range

[Karel Gardas]

Hello Kinsley,

you are indeed right. I've not fixed this bit since it also requires 
fixes in linker scripts and additional sdram region for sdram2 remap.


E.g. Original Sebastian's code is using SDRAM_1 as a remap of SDRAM_2. 
Linker script(s) then are using SDRAM_1 as an executable region (remap 
of SDRAM_2). If you fix SDRAM_1 to be real SDRAM_1, then we will need 
SDRAM_2_REMAP defined and fix also all SDRAM_1 occurances in linker 
scripts and replace those with SDRAM_2_REMAP.


Or that at least how I understand it...

Thanks,
Karel

On 7/12/23 18:00, Kinsey Moore wrote:

According to the documentation in STM reference manuals RM0399 and
RM0433, the standard memory space for SDRAM bank 1 is 0xc000 to
0xcfff.
---
  spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml 
b/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml
index 88dd4e8c91..2b3aacce5d 100644
--- a/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml
+++ b/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml
@@ -14,9 +14,9 @@ content: |
  SRAM_BACKUP : ORIGIN = 0x3880, LENGTH = 
${STM32H7_MEMORY_SRAM_BACKUP_SIZE:#010x}
  PERIPHERAL  : ORIGIN = 0x4000, LENGTH = 
${STM32H7_MEMORY_PERIPHERAL_SIZE:#010x}
  NOR : ORIGIN = 0x6000, LENGTH = 
${STM32H7_MEMORY_NOR_SIZE:#010x}
-SDRAM_1 : ORIGIN = 0x7000, LENGTH = 
${STM32H7_MEMORY_SDRAM_1_SIZE:#010x}
  NAND: ORIGIN = 0x8000, LENGTH = 
${STM32H7_MEMORY_NAND_SIZE:#010x}
  QUADSPI : ORIGIN = 0x9000, LENGTH = 
${STM32H7_MEMORY_QUADSPI_SIZE:#010x}
+SDRAM_1 : ORIGIN = 0xc000, LENGTH = 
${STM32H7_MEMORY_SDRAM_1_SIZE:#010x}
  SDRAM_2 : ORIGIN = 0xd000, LENGTH = 
${STM32H7_MEMORY_SDRAM_2_SIZE:#010x}
}
  


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Re: [PATCH v2 2/2] bsps/stm32h7: Move SDRAM1 to correct memory range

[Kinsey Moore]

Ok, it sounds like that's quite a bit more involved than just updating 
this mapping so I'll drop this patch for the time being.



Kinsey

On 7/12/2023 11:12 AM, Karel Gardas wrote:


Hello Kinsley,

you are indeed right. I've not fixed this bit since it also requires 
fixes in linker scripts and additional sdram region for sdram2 remap.


E.g. Original Sebastian's code is using SDRAM_1 as a remap of SDRAM_2. 
Linker script(s) then are using SDRAM_1 as an executable region (remap 
of SDRAM_2). If you fix SDRAM_1 to be real SDRAM_1, then we will need 
SDRAM_2_REMAP defined and fix also all SDRAM_1 occurances in linker 
scripts and replace those with SDRAM_2_REMAP.


Or that at least how I understand it...

Thanks,
Karel

On 7/12/23 18:00, Kinsey Moore wrote:

According to the documentation in STM reference manuals RM0399 and
RM0433, the standard memory space for SDRAM bank 1 is 0xc000 to
0xcfff.
---
  spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml 
b/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml

index 88dd4e8c91..2b3aacce5d 100644
--- a/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml
+++ b/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml
@@ -14,9 +14,9 @@ content: |
  SRAM_BACKUP : ORIGIN = 0x3880, LENGTH = 
${STM32H7_MEMORY_SRAM_BACKUP_SIZE:#010x}
  PERIPHERAL  : ORIGIN = 0x4000, LENGTH = 
${STM32H7_MEMORY_PERIPHERAL_SIZE:#010x}
  NOR : ORIGIN = 0x6000, LENGTH = 
${STM32H7_MEMORY_NOR_SIZE:#010x}
-    SDRAM_1 : ORIGIN = 0x7000, LENGTH = 
${STM32H7_MEMORY_SDRAM_1_SIZE:#010x}
  NAND    : ORIGIN = 0x8000, LENGTH = 
${STM32H7_MEMORY_NAND_SIZE:#010x}
  QUADSPI : ORIGIN = 0x9000, LENGTH = 
${STM32H7_MEMORY_QUADSPI_SIZE:#010x}
+    SDRAM_1 : ORIGIN = 0xc000, LENGTH = 
${STM32H7_MEMORY_SDRAM_1_SIZE:#010x}
  SDRAM_2 : ORIGIN = 0xd000, LENGTH = 
${STM32H7_MEMORY_SDRAM_2_SIZE:#010x}

    }



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Re: [PATCH v2 2/2] bsps/stm32h7: Move SDRAM1 to correct memory range

[Cedric Berger]

Hello Kinsley,

Yes, basically:

if you look at page 135 of the reference manual:

https://www.st.com/resource/en/reference_manual/rm0399-stm32h745755-and-stm32h747757-advanced-armbased-32bit-mcus-stmicroelectronics.pdf

SDRAM BANK 1 is at 0xc000 (behaving like device memory, not 
executable) or remapped at 0x6000 (behaving like real memory, 
executable and cached)


SDRAM BANK 2 is at 0xd000 (behaving like device memory, not 
executable) or remapped at 0x7000 (behaving like real memory, 
executable and cached)


Because you want SDRAM to behave like real memory, the remap should be 
enabled all the time for all boards and the 0x6000 or 0x7000 
adresses used.


So basically, to be logical and consistant with the documentation and usage:

SDRAM_1 : ORIGIN = 0x6000, LENGTH = 
${STM32H7_MEMORY_SDRAM_1_SIZE:#010x}


SDRAM_2     : ORIGIN = 0x7000, LENGTH = 
${STM32H7_MEMORY_SDRAM_2_SIZE:#010x}


And the demo boards should all be using SDRAM_2 (0x7000) with REMAP 
enabled.


But there is some work todo to clean that up.

Cedric

On 12.07.23 18:12, Karel Gardas wrote:


Hello Kinsley,

you are indeed right. I've not fixed this bit since it also requires 
fixes in linker scripts and additional sdram region for sdram2 remap.


E.g. Original Sebastian's code is using SDRAM_1 as a remap of SDRAM_2. 
Linker script(s) then are using SDRAM_1 as an executable region (remap 
of SDRAM_2). If you fix SDRAM_1 to be real SDRAM_1, then we will need 
SDRAM_2_REMAP defined and fix also all SDRAM_1 occurances in linker 
scripts and replace those with SDRAM_2_REMAP.


Or that at least how I understand it...

Thanks,
Karel

On 7/12/23 18:00, Kinsey Moore wrote:

According to the documentation in STM reference manuals RM0399 and
RM0433, the standard memory space for SDRAM bank 1 is 0xc000 to
0xcfff.
---
  spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml 
b/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml

index 88dd4e8c91..2b3aacce5d 100644
--- a/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml
+++ b/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml
@@ -14,9 +14,9 @@ content: |
  SRAM_BACKUP : ORIGIN = 0x3880, LENGTH = 
${STM32H7_MEMORY_SRAM_BACKUP_SIZE:#010x}
  PERIPHERAL  : ORIGIN = 0x4000, LENGTH = 
${STM32H7_MEMORY_PERIPHERAL_SIZE:#010x}
  NOR : ORIGIN = 0x6000, LENGTH = 
${STM32H7_MEMORY_NOR_SIZE:#010x}
-    SDRAM_1 : ORIGIN = 0x7000, LENGTH = 
${STM32H7_MEMORY_SDRAM_1_SIZE:#010x}
  NAND    : ORIGIN = 0x8000, LENGTH = 
${STM32H7_MEMORY_NAND_SIZE:#010x}
  QUADSPI : ORIGIN = 0x9000, LENGTH = 
${STM32H7_MEMORY_QUADSPI_SIZE:#010x}
+    SDRAM_1 : ORIGIN = 0xc000, LENGTH = 
${STM32H7_MEMORY_SDRAM_1_SIZE:#010x}
  SDRAM_2 : ORIGIN = 0xd000, LENGTH = 
${STM32H7_MEMORY_SDRAM_2_SIZE:#010x}

    }


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