Re: [PATCH rtems-lwip] rtemslwip/xil_shims: Perform flush with invalidate

2023-04-04 Thread Kinsey Moore 
On Mon, Apr 3, 2023 at 8:00 PM Chris Johns  wrote:

> On 31/3/2023 8:13 am, Kinsey Moore wrote:
> > Xilinx wrote their A53 HAL with the assumption that the CPU did not
> > support cache invalidation without a flush, so the flush and
> > invalidation functions were combined and all range invalidations are
> > promoted to flush/invalidate. The implementation written for lwIP was
> > written to the original intent of the function and thus was not flushing
> > in some cases when it needed to. This resolves that issue which prevents
> > DMA transmit errors in some cases.
> > ---
> >  rtemslwip/zynqmp/xil_shims.c | 7 ++-
> >  1 file changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/rtemslwip/zynqmp/xil_shims.c b/rtemslwip/zynqmp/xil_shims.c
> > index 2eda0c5..1b1b3cf 100644
> > --- a/rtemslwip/zynqmp/xil_shims.c
> > +++ b/rtemslwip/zynqmp/xil_shims.c
> > @@ -102,7 +102,12 @@ void XScuGic_DisableIntr ( u32 DistBaseAddress, u32
> Int_Id )
> >rtems_interrupt_vector_disable( Int_Id );
> >  }
> >
> > +/*
> > + * The Xilinx code was written such that it assumed there was no
> invalidate-only
> > + * functionality on A53 cores. This function must flush and invalidate
> because
> > + * of how they mapped things.
> > + */
> >  void Xil_DCacheInvalidateRange( INTPTR adr, INTPTR len )
> >  {
> > -  rtems_cache_invalidate_multiple_data_lines( (const void *) adr, len );
> > +  rtems_cache_flush_multiple_data_lines( (const void *) adr, len );
> >  }
>
> Does the Xilinx code use Xil_DCacheInvalidateRange in any DMA receive
> paths? If
> it does is this change correct as the invalidate has been removed?
>

It just so happens that the way the code was written, a flush and
invalidate works fine for the receive path. The invalidation that occurs in
the receive path occurs before the pointer to the memory is passed to the
DMA engine, so a flush there doesn't hurt anything (at least for this
particular driver). If more Xilinx drivers get pulled in, that may have to
be reevaluated.

Kinsey
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[PATCH v2 2/3] bsps/microblaze: Add support for multiple UARTs

2023-04-04 Thread Alex White 
From: "Maldonado, Sergio E. (GSFC-580.0)" 

---
 bsps/microblaze/include/dev/serial/uartlite.h |   2 +
 .../microblaze_fpga/console/console-io.c  | 229 --
 bsps/microblaze/shared/dev/serial/uartlite.c  |   8 +-
 .../bsps/microblaze/microblaze_fpga/grp.yml   |  32 +++
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   1 -
 .../microblaze_fpga/optconsoleuart.yml|  21 ++
 .../microblaze_fpga/optuart1irq.yml   |  20 ++
 .../optuart1litebaseaddress.yml   |  20 ++
 .../microblaze_fpga/optuart2irq.yml   |  20 ++
 .../optuart2litebaseaddress.yml   |  20 ++
 .../microblaze_fpga/optuart3irq.yml   |  20 ++
 .../optuart3litebaseaddress.yml   |  20 ++
 .../microblaze_fpga/optuart4irq.yml   |  20 ++
 .../optuart4litebaseaddress.yml   |  20 ++
 .../microblaze/microblaze_fpga/optuartirq.yml |  20 ++
 .../microblaze/microblaze_fpga/optuseuart.yml |  17 ++
 .../microblaze_fpga/optuseuart1.yml   |  17 ++
 .../microblaze_fpga/optuseuart2.yml   |  17 ++
 .../microblaze_fpga/optuseuart3.yml   |  17 ++
 .../microblaze_fpga/optuseuart4.yml   |  17 ++
 20 files changed, 534 insertions(+), 24 deletions(-)
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optconsoleuart.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuart1irq.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optuart1litebaseaddress.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuart2irq.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optuart2litebaseaddress.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuart3irq.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optuart3litebaseaddress.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuart4irq.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optuart4litebaseaddress.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuartirq.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart1.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart2.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart3.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart4.yml

diff --git a/bsps/microblaze/include/dev/serial/uartlite.h 
b/bsps/microblaze/include/dev/serial/uartlite.h
index 2fda3796b3..009f416508 100644
--- a/bsps/microblaze/include/dev/serial/uartlite.h
+++ b/bsps/microblaze/include/dev/serial/uartlite.h
@@ -49,8 +49,10 @@ typedef struct {
   rtems_termios_device_context base;
   uintptr_t address;
   uint32_t initial_baud;
+  uint32_t enabled;
 #ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
   bool transmitting;
+  uint32_t irq;
 #endif
 } uart_lite_context;
 
diff --git a/bsps/microblaze/microblaze_fpga/console/console-io.c 
b/bsps/microblaze/microblaze_fpga/console/console-io.c
index 81c4e73690..72c3a0c989 100644
--- a/bsps/microblaze/microblaze_fpga/console/console-io.c
+++ b/bsps/microblaze/microblaze_fpga/console/console-io.c
@@ -34,38 +34,235 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include 
+#include 
+
+#include 
 #include 
-#include 
+#include 
+#include 
 #include 
 
-#include 
+#ifdef BSP_MICROBLAZE_FPGA_USE_FDT
+#include 
+#include 
+#endif
 
-uart_lite_context microblaze_qemu_uart_context = {
-  .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE" ),
-  .initial_baud = 115200
+#include 
+
+static uart_lite_context uart_lite_instances[] = {
+  {
+.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE" ),
+.initial_baud = 115200,
+.address = BSP_MICROBLAZE_FPGA_UART_BASE,
+#if BSP_MICROBLAZE_FPGA_USE_UART
+.enabled = 1,
+#endif
+#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+.irq = BSP_MICROBLAZE_FPGA_UART_IRQ
+#endif
+  },
+  {
+.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE UART1" ),
+.initial_baud = 115200,
+.address = BSP_MICROBLAZE_FPGA_UART1_BASE,
+#if BSP_MICROBLAZE_FPGA_USE_UART1
+.enabled = 1,
+#endif
+#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+.irq = BSP_MICROBLAZE_FPGA_UART1_IRQ
+#endif
+  },
+  {
+.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE UART2" ),
+.initial_baud = 115200,
+.address = BSP_MICROBLAZE_FPGA_UART2_BASE,
+#if BSP_MICROBLAZE_FPGA_USE_UART2
+.enabled = 1,
+#endif
+#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+.irq = BSP_MICROBLAZE_FPGA_UART2_IRQ
+#endif
+  },
+  {
+.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE UART3" ),
+.initial_baud = 115200,
+.address = BSP_MICROBLAZE_FPGA_UART3_BASE,
+#if BSP_MICROBLAZE_FPGA_USE_UART3
+.enabled = 1,
+#endif
+#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+.irq = BSP_MICROBLAZE_FPGA_UART3_IRQ
+#endif
+  },
+  {
+.base =

[PATCH v2 0/3] bsps/microblaze: FDT support and UART driver improvements

2023-04-04 Thread Alex White 
v2:
- Allow UART driver to fill the transmit FIFO rather than just sending one byte
  at a time.

Maldonado, Sergio E. (GSFC-580.0) (3):
  bsps/microblaze: Allow copying FDT from U-Boot
  bsps/microblaze: Add support for multiple UARTs
  bsps/microblaze: Fix UART transmit interrupt

 bsps/microblaze/include/dev/serial/uartlite.h |   4 +
 .../microblaze_fpga/console/console-io.c  | 229 --
 bsps/microblaze/microblaze_fpga/include/bsp.h |   3 +
 .../microblaze_fpga/start/crtinit.S   |   6 +-
 .../microblaze_invalidate_dcache_range.S  | 104 
 bsps/microblaze/shared/dev/serial/uartlite.c  |  30 ++-
 .../shared/fdt/microblaze-fdt-support.c   |  36 ++-
 .../bsps/microblaze/microblaze_fpga/grp.yml   |  36 +++
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   2 +-
 .../microblaze_fpga/optconsoleuart.yml|  21 ++
 .../microblaze_fpga/optuart1irq.yml   |  20 ++
 .../optuart1litebaseaddress.yml   |  20 ++
 .../microblaze_fpga/optuart2irq.yml   |  20 ++
 .../optuart2litebaseaddress.yml   |  20 ++
 .../microblaze_fpga/optuart3irq.yml   |  20 ++
 .../optuart3litebaseaddress.yml   |  20 ++
 .../microblaze_fpga/optuart4irq.yml   |  20 ++
 .../optuart4litebaseaddress.yml   |  20 ++
 .../microblaze/microblaze_fpga/optuartirq.yml |  20 ++
 .../microblaze/microblaze_fpga/optuseuart.yml |  17 ++
 .../microblaze_fpga/optuseuart1.yml   |  17 ++
 .../microblaze_fpga/optuseuart2.yml   |  17 ++
 .../microblaze_fpga/optuseuart3.yml   |  17 ++
 .../microblaze_fpga/optuseuart4.yml   |  17 ++
 24 files changed, 705 insertions(+), 31 deletions(-)
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optconsoleuart.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuart1irq.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optuart1litebaseaddress.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuart2irq.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optuart2litebaseaddress.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuart3irq.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optuart3litebaseaddress.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuart4irq.yml
 create mode 100644 
spec/build/bsps/microblaze/microblaze_fpga/optuart4litebaseaddress.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuartirq.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart1.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart2.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart3.yml
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optuseuart4.yml

-- 
2.34.1

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[PATCH v2 3/3] bsps/microblaze: Fix UART transmit interrupt

2023-04-04 Thread Alex White 
From: "Maldonado, Sergio E. (GSFC-580.0)" 

---
 bsps/microblaze/include/dev/serial/uartlite.h |  2 ++
 bsps/microblaze/shared/dev/serial/uartlite.c  | 22 ++-
 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/bsps/microblaze/include/dev/serial/uartlite.h 
b/bsps/microblaze/include/dev/serial/uartlite.h
index 009f416508..f58ae92ef8 100644
--- a/bsps/microblaze/include/dev/serial/uartlite.h
+++ b/bsps/microblaze/include/dev/serial/uartlite.h
@@ -51,7 +51,9 @@ typedef struct {
   uint32_t initial_baud;
   uint32_t enabled;
 #ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+  struct rtems_termios_tty *tty;
   bool transmitting;
+  size_t tx_queued;
   uint32_t irq;
 #endif
 } uart_lite_context;
diff --git a/bsps/microblaze/shared/dev/serial/uartlite.c 
b/bsps/microblaze/shared/dev/serial/uartlite.c
index e2007ee24a..611c339371 100644
--- a/bsps/microblaze/shared/dev/serial/uartlite.c
+++ b/bsps/microblaze/shared/dev/serial/uartlite.c
@@ -48,8 +48,11 @@ static void microblaze_uart_interrupt( void *arg )
 rtems_termios_enqueue_raw_characters( tty, &c, 1 );
   }
 
-  while ( ctx->transmitting && !XUartLite_IsTransmitEmpty( ctx->address ) ) {
-rtems_termios_dequeue_characters( tty, 1 );
+  if ( ctx->transmitting && XUartLite_IsTransmitEmpty( ctx->address ) ) {
+size_t sent = ctx->tx_queued;
+ctx->transmitting = false;
+ctx->tx_queued = 0;
+rtems_termios_dequeue_characters( tty, sent );
   }
 }
 #endif
@@ -81,6 +84,8 @@ static bool uart_first_open(
   if ( sc != RTEMS_SUCCESSFUL ) {
 return false;
   }
+
+  ctx->tty = tty;
 #endif
 
   return true;
@@ -120,10 +125,17 @@ static void uart_write(
 
 #ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
   if ( n > 0 ) {
+size_t remaining = n;
+const char *p = &s[0];
+
+while (!XUartLite_IsTransmitFull( ctx->address ) && remaining > 0) {
+  XUartLite_SendByte( ctx->address, *p );
+  p++;
+  remaining--;
+}
+
 ctx->transmitting = true;
-XUartLite_SendByte( ctx->address, s[0] );
-  } else {
-ctx->transmitting = false;
+ctx->tx_queued = n - remaining;
   }
 #else
   size_t i = 0;
-- 
2.34.1

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[PATCH v2 1/3] bsps/microblaze: Allow copying FDT from U-Boot

2023-04-04 Thread Alex White 
From: "Maldonado, Sergio E. (GSFC-580.0)" 

---
 bsps/microblaze/microblaze_fpga/include/bsp.h |   3 +
 .../microblaze_fpga/start/crtinit.S   |   6 +-
 .../microblaze_invalidate_dcache_range.S  | 104 ++
 .../shared/fdt/microblaze-fdt-support.c   |  36 +-
 .../bsps/microblaze/microblaze_fpga/grp.yml   |   4 +
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   1 +
 6 files changed, 152 insertions(+), 2 deletions(-)
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S

diff --git a/bsps/microblaze/microblaze_fpga/include/bsp.h 
b/bsps/microblaze/microblaze_fpga/include/bsp.h
index 410d4483c6..6890f33395 100644
--- a/bsps/microblaze/microblaze_fpga/include/bsp.h
+++ b/bsps/microblaze/microblaze_fpga/include/bsp.h
@@ -49,14 +49,17 @@ extern "C" {
 
 #ifdef BSP_MICROBLAZE_FPGA_USE_FDT
 #define BSP_FDT_IS_SUPPORTED
+#ifndef BSP_START_COPY_FDT_FROM_U_BOOT
 extern const unsigned char system_dtb[];
 extern const size_t system_dtb_size;
+#endif /* BSP_START_COPY_FDT_FROM_U_BOOT */
 #endif /* BSP_MICROBLAZE_FPGA_USE_FDT */
 
 void microblaze_enable_icache(void);
 void microblaze_enable_dcache(void);
 void microblaze_invalidate_icache(void);
 void microblaze_invalidate_dcache(void);
+void microblaze_invalidate_dcache_range(unsigned int cacheaddr, unsigned int 
len);
 
 #ifdef __cplusplus
 }
diff --git a/bsps/microblaze/microblaze_fpga/start/crtinit.S 
b/bsps/microblaze/microblaze_fpga/start/crtinit.S
index d56bee3b19..6c7fc3af23 100644
--- a/bsps/microblaze/microblaze_fpga/start/crtinit.S
+++ b/bsps/microblaze/microblaze_fpga/start/crtinit.S
@@ -30,6 +30,8 @@
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include 
+
.globl _crtinit
.align 2
.ent _crtinit
@@ -75,7 +77,9 @@ _crtinit:
brlid   r15, __init  /* Invoke 
language initialization functions */
nop
 #endif /* __rtems__ */
-
+#ifdef BSP_START_COPY_FDT_FROM_U_BOOT  /* Boot loaders may pass the device 
tree in r5 */
+   brlid   r15, bsp_fdt_copy  /* Do not touch r5 until 
bsp_fdt_copy() is called */
+#endif /* BSP_START_COPY_FDT_FROM_U_BOOT */
addir6, r0, 0  /* 
Initialize argc = 1 and argv = NULL and envp = NULL  */
addir7, r0, 0
 #ifndef __rtems__
diff --git 
a/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S 
b/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S
new file mode 100644
index 00..89d5fff16b
--- /dev/null
+++ b/bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S
@@ -0,0 +1,104 @@
+/**
+* Copyright (c) 2008 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+**/
+/**
+*
+*
+* microblaze_invalidate_dcache_range (unsigned int cacheaddr, unsigned int len)
+*
+*Invalidate a Dcache range
+*
+*Parameters:
+*   'cacheaddr' - address in the Dcache where invalidation begins
+*  'len'   - length (in bytes) worth of Dcache to be invalidated
+*
+*
+***/
+
+#include 
+
+#define MICROBLAZE_MSR_DCACHE_ENABLE0x0080
+#define MICROBLAZE_MSR_INTR_ENABLE  0x0002
+
+#ifndef XPAR_MICROBLAZE_USE_DCACHE
+#define XPAR_MICROBLAZE_USE_DCACHE 1
+#endif
+
+#ifndef XPAR_MICROBLAZE_ALLOW_DCACHE_WR
+#define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1
+#endif
+
+#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
+#define MB_VERSION_LT_v720
+#define MB_HAS_WRITEBACK_SET 0
+#else
+#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
+#endif
+
+   .text
+   .globl  microblaze_invalidate_dcache_range
+   .entmicroblaze_invalidate_dcache_range
+   .align  2
+
+microblaze_invalidate_dcache_range:
+#if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1)
+
+#ifdef MB_VERSION_LT_v720   /* Disable 
Dcache and interrupts before invalidating */
+   mfs r9, rmsr
+   andir10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | 
MICROBLAZE_MSR_INTR_ENABLE)
+   mts rmsr, r10
+#endif
+
+BEQIr6, L_done  /* Skip loop 
if size is zero */
+
+ADDr6, r5, r6  /* Compute end 
address */
+ADDIK   r6, r6, -1
+
+ANDIr6, r6, -(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN)  /* Align 
end down to cache line */
+ANDIr5, r5, -(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN)  /* Align 
start down to cache line */
+
+#if MB_HAS_WRITEBACK_SET == 0   /* Use a 
different scheme for MB v

[PATCH 1/8] build: Add assert-in-set option action

2023-04-04 Thread Sebastian Huber 
---
 wscript | 8 
 1 file changed, 8 insertions(+)

diff --git a/wscript b/wscript
index 567f42db2f..a5c8b5f236 100755
--- a/wscript
+++ b/wscript
@@ -825,6 +825,13 @@ class OptionItem(Item):
 value, self.data["name"], arg))
 return value
 
+def _assert_in_set(self, conf, cic, value, arg):
+if value is not None and value not in arg:
+conf.fatal(
+"Value '{}' for option '{}' is not an element of {}"
+.format(value, self.data["name"], arg))
+return value
+
 def _assert_in_interval(self, conf, cic, value, arg):
 if value is not None and (value < arg[0] or value > arg[1]):
 conf.fatal(
@@ -1056,6 +1063,7 @@ class OptionItem(Item):
 "assert-eq": self._assert_eq,
 "assert-ge": self._assert_ge,
 "assert-gt": self._assert_gt,
+"assert-in-set": self._assert_in_set,
 "assert-int8": self._assert_int8,
 "assert-int16": self._assert_int16,
 "assert-int32": self._assert_int32,
-- 
2.35.3

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[PATCH 3/8] bsp/tms570: Enable cache manager implementation

2023-04-04 Thread Sebastian Huber 
---
 spec/build/bsps/arm/tms570/obj.yml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/spec/build/bsps/arm/tms570/obj.yml 
b/spec/build/bsps/arm/tms570/obj.yml
index 3c8e0ed0c4..6f6cd375c4 100644
--- a/spec/build/bsps/arm/tms570/obj.yml
+++ b/spec/build/bsps/arm/tms570/obj.yml
@@ -86,7 +86,8 @@ source:
 - bsps/arm/tms570/start/bspstart.c
 - bsps/arm/tms570/start/pinmux.c
 - bsps/arm/tms570/start/tms570-pom.c
-- bsps/shared/cache/nocache.c
+- bsps/arm/shared/cache/cache-cp15.c
+- bsps/arm/shared/cache/cache-v7ar-disable-data.S
 - bsps/shared/dev/btimer/btimer-cpucounter.c
 - bsps/shared/dev/getentropy/getentropy-cpucounter.c
 - bsps/shared/dev/serial/console-termios.c
-- 
2.35.3

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[PATCH 7/8] bsp/tms570: Add TMS570_VARIANT

2023-04-04 Thread Sebastian Huber 
---
 spec/build/bsps/arm/tms570/grp.yml|  2 ++
 spec/build/bsps/arm/tms570/optvariant.yml | 21 +
 2 files changed, 23 insertions(+)
 create mode 100644 spec/build/bsps/arm/tms570/optvariant.yml

diff --git a/spec/build/bsps/arm/tms570/grp.yml 
b/spec/build/bsps/arm/tms570/grp.yml
index 578cba29ee..1acd00f84b 100644
--- a/spec/build/bsps/arm/tms570/grp.yml
+++ b/spec/build/bsps/arm/tms570/grp.yml
@@ -10,6 +10,8 @@ includes: []
 install: []
 ldflags: []
 links:
+- role: build-dependency
+  uid: optvariant
 - role: build-dependency
   uid: ../grp
 - role: build-dependency
diff --git a/spec/build/bsps/arm/tms570/optvariant.yml 
b/spec/build/bsps/arm/tms570/optvariant.yml
new file mode 100644
index 00..2925b4bf04
--- /dev/null
+++ b/spec/build/bsps/arm/tms570/optvariant.yml
@@ -0,0 +1,21 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-in-set:
+  - 3137
+  - 4357
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2023 embedded brains GmbH (http://www.embedded-brains.de)
+default:
+- enabled-by: true
+  value: 3137
+description: |
+  Defines the TMS570 family variant.  Use 3137 for the TMS570LS3137 and 4357
+  for the TMSLC4357.
+enabled-by: true
+format: '{}'
+links: []
+name: TMS570_VARIANT
+type: build
-- 
2.35.3

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[PATCH 2/8] bsp/tms570: Export -mbe32 to pkg-config

2023-04-04 Thread Sebastian Huber 
---
 spec/build/bsps/arm/tms570/optlinkflags.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/spec/build/bsps/arm/tms570/optlinkflags.yml 
b/spec/build/bsps/arm/tms570/optlinkflags.yml
index 5d4f83fdcd..c1135c6616 100644
--- a/spec/build/bsps/arm/tms570/optlinkflags.yml
+++ b/spec/build/bsps/arm/tms570/optlinkflags.yml
@@ -3,6 +3,7 @@ actions:
 - get-string: null
 - split: null
 - env-append: LINKFLAGS
+- env-append: PKGCONFIG_LDFLAGS
 build-type: option
 copyrights:
 - Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de)
-- 
2.35.3

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[PATCH 5/8] bsp/tms570: Replace TMS570_MMR_SELECT_GMII_SEL

2023-04-04 Thread Sebastian Huber 
Replace TMS570_MMR_SELECT_GMII_SEL with TMS570_MMR_SELECT_MII_MODE and
TMS570_MMR_SELECT_RMII_MODE.
---
 bsps/arm/tms570/include/bsp/tms570lc4357-pins.h| 5 +
 bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h | 5 -
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/bsps/arm/tms570/include/bsp/tms570lc4357-pins.h 
b/bsps/arm/tms570/include/bsp/tms570lc4357-pins.h
index a7912d1547..fac705e60d 100644
--- a/bsps/arm/tms570/include/bsp/tms570lc4357-pins.h
+++ b/bsps/arm/tms570/include/bsp/tms570lc4357-pins.h
@@ -972,6 +972,11 @@
 TMS570_PIN_AND_FNC(TMS570_PIN_MMR_ALT_HET2_07, 0))
 #define TMS570_BALL_N3_MIBSPI2NCS_0 TMS570_PIN_AND_FNC(TMS570_BALL_N3, 4)
 
+#define TMS570_MMR_SELECT_MII_MODE \
+  TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(160, 3), TMS570_PIN_FNC_CLEAR)
+#define TMS570_MMR_SELECT_RMII_MODE \
+  TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(160, 3), 0)
+
 /* Default pinmux select */
 
 #define TMS570_PINMMR_DEFAULT_INIT_LIST(per_pin_action, common_arg) \
diff --git a/bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h 
b/bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h
index 089f0d4248..aa3c0f2185 100644
--- a/bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h
+++ b/bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h
@@ -555,7 +555,10 @@
 #define TMS570_BALL_F2 TMS570_BALL_WITH_MMR(29, 2)
 #define TMS570_BALL_F2_GIOB_2 TMS570_PIN_AND_FNC(TMS570_BALL_F2, 0)
 
-#define TMS570_MMR_SELECT_GMII_SEL TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(29, 
3), 0)
+#define TMS570_MMR_SELECT_MII_MODE \
+  TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(29, 3), 0)
+#define TMS570_MMR_SELECT_RMII_MODE \
+  TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(29, 3), TMS570_PIN_FNC_CLEAR)
 
 #define TMS570_MMR_SELECT_ADC_TRG1 TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(30, 
0), 0)
 #define TMS570_MMR_SELECT_ADC_TRG2 TMS570_PIN_AND_FNC(TMS570_BALL_WITH_MMR(30, 
0), 1)
-- 
2.35.3

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[PATCH 4/8] bsp/tms570: Add pin configuration variants

2023-04-04 Thread Sebastian Huber 
Rearrange pin function bit fields to allow the clearing of all function
bits through TMS570_PIN_AND_FNC().

Move implementation details to source file.
---
 bsps/arm/tms570/include/bsp/tms570-pinmux.h |  76 +++
 bsps/arm/tms570/start/pinmux.c  | 103 ++--
 2 files changed, 133 insertions(+), 46 deletions(-)

diff --git a/bsps/arm/tms570/include/bsp/tms570-pinmux.h 
b/bsps/arm/tms570/include/bsp/tms570-pinmux.h
index f744b92737..f527073496 100644
--- a/bsps/arm/tms570/include/bsp/tms570-pinmux.h
+++ b/bsps/arm/tms570/include/bsp/tms570-pinmux.h
@@ -23,8 +23,8 @@
 #ifndef LIBBSP_ARM_TMS570_PINMUX_H
 #define LIBBSP_ARM_TMS570_PINMUX_H
 
-#ifndef ASM
-#include 
+#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
@@ -40,10 +40,18 @@ extern "C" {
  * connection is not enabled in parallel to other one.
  * Mask is ored with pin number in such list.
  */
-#define TMS570_PIN_CLEAR_RQ_MASK 0x0800
+#define TMS570_PIN_CLEAR_RQ_MASK 0x8000
 
-#define TMS570_PIN_FNC_SHIFT12
-#define TMS570_PIN_FNC_MASK 0xf000
+#define TMS570_PIN_FNC_SHIFT11
+#define TMS570_PIN_FNC_MASK 0x7800
+
+/**
+ * @brief This constant indicates that all eight function bits associated with
+ *   the pin shall be cleared.
+ *
+ * Use it as a special value for the pin function in TMS570_PIN_AND_FNC().
+ */
+#define TMS570_PIN_FNC_CLEAR 0x10U
 
 #define TMS570_PIN_NUM_FNC_MASK 0x
 
@@ -52,6 +60,15 @@ extern "C" {
 
 #define TMS570_PIN_FNC_AUTO  (-1)
 
+/**
+ * @brief Defines the function of the pin.
+ *
+ * @param pin is the pin identifier.  Use TMS570_BALL_WITH_MMR() to define the
+ *   pin identifier.
+ *
+ * param fnc is the pin function.  The pin function shall be the function bit
+ *   index or TMS570_PIN_FNC_CLEAR.
+ */
 #define TMS570_PIN_AND_FNC(pin, fnc) \
   ((pin) | ((fnc) << TMS570_PIN_FNC_SHIFT))
 
@@ -61,6 +78,43 @@ extern "C" {
 #define TMS570_BALL_WITH_MMR(mmrx, pos) \
   ((pos) | ((mmrx) << 2))
 
+/**
+ * @brief Prepares a pin configuration sequence.
+ *
+ * Use tms570_pin_config_apply() to apply pin configurations.  Use
+ * tms570_pin_config_complete() to complete the pin configuration sequence.
+ */
+void tms570_pin_config_prepare(void);
+
+/**
+ * @brief Applies a pin configuration.
+ *
+ * This function can only be used if the pin configuration was prepared by
+ * tms570_pin_config_prepare().
+ *
+ * @param config is the pin configuration defined by TMS570_PIN_AND_FNC() or
+ *   TMS570_PIN_WITH_IN_ALT().
+ */
+void tms570_pin_config_apply(uint32_t config);
+
+/**
+ * @brief Applies a pin configuration array.
+ *
+ * This function can only be used if the pin configuration was prepared by
+ * tms570_pin_config_prepare().
+ *
+ * @param config is the pin configuration array.  Calls
+ *   tms570_pin_config_apply() for each pin configuration in the array.
+ *
+ * @param count is the element count of the pin configuration array.
+ */
+void tms570_pin_config_array_apply(const uint32_t *config, size_t count);
+
+/**
+ * @brief Completes a pin configuration sequence.
+ */
+void tms570_pin_config_complete(void);
+
 /* Generic functions select pin to peripheral connection */
 
 void tms570_bsp_pin_set_function(int pin_num, int pin_fnc);
@@ -71,15 +125,6 @@ void tms570_bsp_pin_config_one(uint32_t pin_num_and_fnc);
 
 void tms570_bsp_pinmmr_config(const uint32_t *pinmmr_values, int reg_start, 
int reg_count);
 
-static inline void
-tms570_bsp_pin_to_pinmmrx(volatile uint32_t **pinmmrx, unsigned int *pin_shift,
-  int pin_num)
-{
-  pin_num = (pin_num & TMS570_PIN_NUM_MASK) >> TMS570_PIN_NUM_SHIFT;
-  *pinmmrx = &TMS570_IOMM.PINMUX.PINMMR0 + (pin_num >> 2);
-  *pin_shift = (pin_num & 0x3)*8;
-}
-
 #define TMS570_PINMMR_REG_SINGLE_VAL_ACTION(reg, pin) \
   (pin) & TMS570_PIN_NUM_MASK) >> 2 != (reg)) || ((pin) & 
TMS570_PIN_CLEAR_RQ_MASK))? 0: \
1 << pin) & TMS570_PIN_FNC_MASK) >> TMS570_PIN_FNC_SHIFT) + \
@@ -125,9 +170,6 @@ tms570_bsp_pin_to_pinmmrx(volatile uint32_t **pinmmrx, 
unsigned int *pin_shift,
 #define TMS570_PINMMR_COMA_LIST(pin_list) \
   pin_list(TMS570_PINMMR_COMA_LIST_ACTION, 0)
 
-
-#endif
-
 /** @} */
 
 #ifdef __cplusplus
diff --git a/bsps/arm/tms570/start/pinmux.c b/bsps/arm/tms570/start/pinmux.c
index 6aec5f7c32..a045891774 100644
--- a/bsps/arm/tms570/start/pinmux.c
+++ b/bsps/arm/tms570/start/pinmux.c
@@ -24,8 +24,19 @@
 #include 
 #include 
 
-uint32_t tms570_bsp_pinmmr_kick_key0 = 0x83E70B13U;
-uint32_t tms570_bsp_pinmmr_kick_key1 = 0x95A4F1E0U;
+RTEMS_STATIC_ASSERT(
+  TMS570_PIN_CLEAR_RQ_MASK == TMS570_PIN_FNC_CLEAR << TMS570_PIN_FNC_SHIFT,
+  TMS570_PIN_CONFIG
+);
+
+static inline void
+tms570_bsp_pin_to_pinmmrx(volatile uint32_t **pinmmrx, uint32_t *pin_shift,
+  uint32_t config)
+{
+  uint32_t pin_num = (config & TMS570_PIN_NUM_MASK) >> TMS570_PIN_NUM_SHIFT;
+  *pinmmrx = &TMS570_IOMM.PINMUX.PINMMR0 + (pin_num >> 2);
+  *pin_shift = (pin_num & 0x3)*8;
+}
 
 /**
  * @brief s

[PATCH 6/8] bsp/tms570: Use 0x for hex constants

2023-04-04 Thread Sebastian Huber 
---
 bsps/arm/tms570/include/bsp/tms570.h | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/bsps/arm/tms570/include/bsp/tms570.h 
b/bsps/arm/tms570/include/bsp/tms570.h
index f278a93606..86f33f896d 100644
--- a/bsps/arm/tms570/include/bsp/tms570.h
+++ b/bsps/arm/tms570/include/bsp/tms570.h
@@ -80,7 +80,7 @@
 
 #define TMS570_ADC1 (*(volatile tms570_adc_t*)0xFFF7C000)
 #define TMS570_ADC2 (*(volatile tms570_adc_t*)0xFFF7C200)
-#define TMS570_CCMSR (*(volatile tms570_ccmsr_t*)0XF600)
+#define TMS570_CCMSR (*(volatile tms570_ccmsr_t*)0xF600)
 #define TMS570_CRC (*(volatile tms570_crc_t*)0xFE00)
 #define TMS570_DCAN1 (*(volatile tms570_dcan_t*)0xFFF7DC00)
 #define TMS570_DCAN2 (*(volatile tms570_dcan_t*)0xFFF7DE00)
@@ -89,12 +89,12 @@
 #define TMS570_DCC2 (*(volatile tms570_dcc_t*)0xF400)
 #define TMS570_DMA (*(volatile tms570_dma_t*)0xF000)
 #define TMS570_DMM (*(volatile tms570_dmm_t*)0xF700)
-#define TMS570_EFUSE (*(volatile tms570_efuse_t*)0XFFF8C01C)
+#define TMS570_EFUSE (*(volatile tms570_efuse_t*)0xFFF8C01C)
 #define TMS570_EMACC (*(volatile tms570_emacc_t*)0xFCF78800)
 #define TMS570_EMACM (*(volatile tms570_emacm_t*)0xFCF78000)
 #define TMS570_EMIF (*(volatile tms570_emif_t*)0xFCFFE800)
-#define TMS570_ESM (*(volatile tms570_esm_t*)0XF500)
-#define TMS570_FLASH (*(volatile tms570_flash_t*)0XFFF87000)
+#define TMS570_ESM (*(volatile tms570_esm_t*)0xF500)
+#define TMS570_FLASH (*(volatile tms570_flash_t*)0xFFF87000)
 #define TMS570_FLEX_RAY (*(volatile tms570_flex_ray_t*)0xFFF7C800)
 #define TMS570_GIO (*(volatile tms570_gio_t*)0xFFF7BC00)
 #define TMS570_GIO_PORTA (*(volatile tms570_gio_port_t*)0xFFF7BC34)
@@ -108,14 +108,14 @@
 #define TMS570_HTU1 (*(volatile tms570_htu_t*)0xFFF7A400)
 #define TMS570_HTU2 (*(volatile tms570_htu_t*)0xFFF7A500)
 #define TMS570_I2C (*(volatile tms570_i2c_t*)0xFFF7D400)
-#define TMS570_IOMM (*(volatile tms570_iomm_t*)0XEA00)
+#define TMS570_IOMM (*(volatile tms570_iomm_t*)0xEA00)
 #define TMS570_PINMUX (*(volatile tms570_pinmux_t*)0xEB10)
 #define TMS570_LIN (*(volatile tms570_lin_t*)0xFFF7E400)
 #define TMS570_MDIO (*(volatile tms570_mdio_t*)0xFCF78900)
 #define TMS570_NHET1 (*(volatile tms570_nhet_t*)0xFFF7B800)
 #define TMS570_NHET2 (*(volatile tms570_nhet_t*)0xFFF7B900)
 #define TMS570_PBIST (*(volatile tms570_pbist_t*)0xE400)
-#define TMS570_PLL (*(volatile tms570_pll_t*)0XE100)
+#define TMS570_PLL (*(volatile tms570_pll_t*)0xE100)
 #define TMS570_PMM (*(volatile tms570_pmm_t*)0x)
 #define TMS570_RTI (*(volatile tms570_rti_t*)0xFC00)
 #define TMS570_RTP (*(volatile tms570_rtp_t*)0xFA00)
@@ -123,8 +123,8 @@
 #define TMS570_TCR (*(volatile tms570_tcr_t*)0xFFF7C800)
 #define TMS570_TCRAM1 (*(volatile tms570_tcram_t*)0xF800)
 #define TMS570_TCRAM2 (*(volatile tms570_tcram_t*)0xF900)
-#define TMS570_VIM (*(volatile tms570_vim_t*)0XFDEC)
-#define TMS570_POM (*(volatile tms570_pom_t*)0XFFA04000)
+#define TMS570_VIM (*(volatile tms570_vim_t*)0xFDEC)
+#define TMS570_POM (*(volatile tms570_pom_t*)0xFFA04000)
 #define TMS570_SPI1 (*(volatile tms570_spi_t*)0xFFF7F400)
 #define TMS570_SPI2 (*(volatile tms570_spi_t*)0xFFF7F600)
 #define TMS570_SPI3 (*(volatile tms570_spi_t*)0xFFF7F800)
-- 
2.35.3

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[PATCH 0/8] Add basic support for TMS570LC4357

2023-04-04 Thread Sebastian Huber 
Sebastian Huber (8):
  build: Add assert-in-set option action
  bsp/tms570: Export -mbe32 to pkg-config
  bsp/tms570: Enable cache manager implementation
  bsp/tms570: Add pin configuration variants
  bsp/tms570: Replace TMS570_MMR_SELECT_GMII_SEL
  bsp/tms570: Use 0x for hex constants
  bsp/tms570: Add TMS570_VARIANT
  bsp/tms570: Add TMS570LC4357 support

 bsps/arm/tms570/include/bsp/tms570-pinmux.h   |  76 ++---
 bsps/arm/tms570/include/bsp/tms570-pins.h |   6 +
 bsps/arm/tms570/include/bsp/tms570.h  |  38 +--
 .../tms570/include/bsp/tms570lc4357-pins.h|   5 +
 .../tms570/include/bsp/tms570ls3137zwt-pins.h |   5 +-
 bsps/arm/tms570/start/init_pinmux.c   |   4 +
 bsps/arm/tms570/start/pinmux.c| 103 +-
 spec/build/bsps/arm/tms570/grp.yml|   2 +
 spec/build/bsps/arm/tms570/obj.yml|   3 +-
 spec/build/bsps/arm/tms570/optlinkflags.yml   |   1 +
 spec/build/bsps/arm/tms570/optvariant.yml |  21 
 wscript   |   8 ++
 12 files changed, 216 insertions(+), 56 deletions(-)
 create mode 100644 spec/build/bsps/arm/tms570/optvariant.yml

-- 
2.35.3

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[PATCH 8/8] bsp/tms570: Add TMS570LC4357 support

2023-04-04 Thread Sebastian Huber 
---
 bsps/arm/tms570/include/bsp/tms570-pins.h |  6 ++
 bsps/arm/tms570/include/bsp/tms570.h  | 22 ++
 bsps/arm/tms570/start/init_pinmux.c   |  4 
 3 files changed, 32 insertions(+)

diff --git a/bsps/arm/tms570/include/bsp/tms570-pins.h 
b/bsps/arm/tms570/include/bsp/tms570-pins.h
index 32839138d0..058aa6bbab 100644
--- a/bsps/arm/tms570/include/bsp/tms570-pins.h
+++ b/bsps/arm/tms570/include/bsp/tms570-pins.h
@@ -7,4 +7,10 @@
  *Defaults to TMS570LS3137ZWT for now.
  */
 
+#include 
+
+#if TMS570_VARIANT == 4357
+#include 
+#else
 #include 
+#endif
diff --git a/bsps/arm/tms570/include/bsp/tms570.h 
b/bsps/arm/tms570/include/bsp/tms570.h
index 86f33f896d..d91e0cce50 100644
--- a/bsps/arm/tms570/include/bsp/tms570.h
+++ b/bsps/arm/tms570/include/bsp/tms570.h
@@ -78,13 +78,21 @@
 #include 
 #include 
 
+#include 
+
 #define TMS570_ADC1 (*(volatile tms570_adc_t*)0xFFF7C000)
 #define TMS570_ADC2 (*(volatile tms570_adc_t*)0xFFF7C200)
 #define TMS570_CCMSR (*(volatile tms570_ccmsr_t*)0xF600)
 #define TMS570_CRC (*(volatile tms570_crc_t*)0xFE00)
+#if TMS570_VARIANT == 4357
+#define TMS570_CRC2 (*(volatile tms570_crc_t*)0xFB00)
+#endif
 #define TMS570_DCAN1 (*(volatile tms570_dcan_t*)0xFFF7DC00)
 #define TMS570_DCAN2 (*(volatile tms570_dcan_t*)0xFFF7DE00)
 #define TMS570_DCAN3 (*(volatile tms570_dcan_t*)0xFFF7E000)
+#if TMS570_VARIANT == 4357
+#define TMS570_DCAN4 (*(volatile tms570_dcan_t*)0xFFF7E200)
+#endif
 #define TMS570_DCC1 (*(volatile tms570_dcc_t*)0xEC00)
 #define TMS570_DCC2 (*(volatile tms570_dcc_t*)0xF400)
 #define TMS570_DMA (*(volatile tms570_dma_t*)0xF000)
@@ -108,9 +116,20 @@
 #define TMS570_HTU1 (*(volatile tms570_htu_t*)0xFFF7A400)
 #define TMS570_HTU2 (*(volatile tms570_htu_t*)0xFFF7A500)
 #define TMS570_I2C (*(volatile tms570_i2c_t*)0xFFF7D400)
+#if TMS570_VARIANT == 4357
+#define TMS570_I2C2 (*(volatile tms570_i2c_t*)0xFFF7D500)
+#endif
+#if TMS570_VARIANT == 4357
+#define TMS570_IOMM (*(volatile tms570_iomm_t*)0x1C00)
+#define TMS570_PINMUX (*(volatile tms570_pinmux_t*)0x1D10)
+#else
 #define TMS570_IOMM (*(volatile tms570_iomm_t*)0xEA00)
 #define TMS570_PINMUX (*(volatile tms570_pinmux_t*)0xEB10)
+#endif
 #define TMS570_LIN (*(volatile tms570_lin_t*)0xFFF7E400)
+#if TMS570_VARIANT == 4357
+#define TMS570_LIN2 (*(volatile tms570_lin_t*)0xFFF7E600)
+#endif
 #define TMS570_MDIO (*(volatile tms570_mdio_t*)0xFCF78900)
 #define TMS570_NHET1 (*(volatile tms570_nhet_t*)0xFFF7B800)
 #define TMS570_NHET2 (*(volatile tms570_nhet_t*)0xFFF7B900)
@@ -120,6 +139,9 @@
 #define TMS570_RTI (*(volatile tms570_rti_t*)0xFC00)
 #define TMS570_RTP (*(volatile tms570_rtp_t*)0xFA00)
 #define TMS570_SCI (*(volatile tms570_sci_t*)0xFFF7E500)
+#if TMS570_VARIANT == 4357
+#define TMS570_SCI2 (*(volatile tms570_sci_t*)0xFFF7E700)
+#endif
 #define TMS570_TCR (*(volatile tms570_tcr_t*)0xFFF7C800)
 #define TMS570_TCRAM1 (*(volatile tms570_tcram_t*)0xF800)
 #define TMS570_TCRAM2 (*(volatile tms570_tcram_t*)0xF900)
diff --git a/bsps/arm/tms570/start/init_pinmux.c 
b/bsps/arm/tms570/start/init_pinmux.c
index e86a115541..e0d3a38f4c 100644
--- a/bsps/arm/tms570/start/init_pinmux.c
+++ b/bsps/arm/tms570/start/init_pinmux.c
@@ -45,6 +45,10 @@
  per_pin_action(common_arg, TMS570_BALL_E3_HET2_18)
 #endif
 
+#elif TMS570_VARIANT == 4357
+
+#define TMS570_PINMMR_INIT_LIST( per_pin_action, common_arg )
+
 #else
 
 /*
-- 
2.35.3

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[lwip 3/6] tms570: Use new pin configuration API

2023-04-04 Thread Sebastian Huber 
---
 uLan/ports/driver/tms570_emac/tms570_netif.c | 55 +---
 1 file changed, 25 insertions(+), 30 deletions(-)

diff --git a/uLan/ports/driver/tms570_emac/tms570_netif.c 
b/uLan/ports/driver/tms570_emac/tms570_netif.c
index c27f6d5..46e025a 100644
--- a/uLan/ports/driver/tms570_emac/tms570_netif.c
+++ b/uLan/ports/driver/tms570_emac/tms570_netif.c
@@ -78,10 +78,6 @@
 /* take in account oversized frames */
 #define MAX_TRANSFER_UNIT   1500
 
-#ifndef TMS570_MMR_SELECT_GMII_SEL
-  #define TMS570_MMR_SELECT_GMII_SEL TMS570_BALL_XX_GMII_SEL
-#endif
-
 #ifndef TMS570_BALL_K19_MII_RXCLK
   #define TMS570_BALL_K19_MII_RXCLK TMS570_BALL_K19_MII_RX_CLK
 #endif
@@ -333,35 +329,34 @@ tms570_eth_init_find_PHY(struct tms570_netif_state 
*nf_state)
   return ERR_OK;
 }
 
+static const uint32_t tms570_eth_pin_config[] = {
+  TMS570_MMR_SELECT_MII_MODE,
+  TMS570_BALL_V5_MDCLK,
+  TMS570_BALL_G3_MDIO,
+  TMS570_BALL_H19_MII_TXEN,
+  TMS570_BALL_E18_MII_TXD_3,
+  TMS570_BALL_R2_MII_TXD_2,
+  TMS570_BALL_J19_MII_TXD_1,
+  TMS570_BALL_J18_MII_TXD_0,
+  TMS570_BALL_D19_MII_TX_CLK,
+  TMS570_BALL_H18_MII_RXD_3,
+  TMS570_BALL_G19_MII_RXD_2,
+  TMS570_BALL_A14_MII_RXD_1,
+  TMS570_BALL_P1_MII_RXD_0,
+  TMS570_BALL_K19_MII_RXCLK,
+  TMS570_BALL_N19_MII_RX_ER,
+  TMS570_BALL_B11_MII_RX_DV,
+  TMS570_BALL_B4_MII_CRS,
+  TMS570_BALL_F3_MII_COL
+};
+
 static void
 tms570_eth_init_set_pinmux(void)
 {
-#if defined(__rtems__)
-  TMS570_IOMM.KICK_REG0 = 0x83E70B13U;
-  TMS570_IOMM.KICK_REG1 = 0x95A4F1E0U;
-
-  tms570_bsp_pin_set_function(TMS570_BALL_V5_MDCLK, TMS570_PIN_FNC_AUTO);
-  tms570_bsp_pin_set_function(TMS570_BALL_G3_MDIO, TMS570_PIN_FNC_AUTO);
-  tms570_bsp_pin_set_function(TMS570_BALL_H19_MII_TXEN, TMS570_PIN_FNC_AUTO);
-  tms570_bsp_pin_set_function(TMS570_BALL_E18_MII_TXD_3, TMS570_PIN_FNC_AUTO);
-  tms570_bsp_pin_set_function(TMS570_BALL_R2_MII_TXD_2, TMS570_PIN_FNC_AUTO);
-  tms570_bsp_pin_set_function(TMS570_BALL_J19_MII_TXD_1, TMS570_PIN_FNC_AUTO);
-  tms570_bsp_pin_set_function(TMS570_BALL_J18_MII_TXD_0, TMS570_PIN_FNC_AUTO);
-  tms570_bsp_pin_set_function(TMS570_BALL_D19_MII_TX_CLK, TMS570_PIN_FNC_AUTO);
-  tms570_bsp_pin_set_function(TMS570_BALL_H18_MII_RXD_3, TMS570_PIN_FNC_AUTO);
-  tms570_bsp_pin_set_function(TMS570_BALL_G19_MII_RXD_2, TMS570_PIN_FNC_AUTO);
-  tms570_bsp_pin_set_function(TMS570_BALL_A14_MII_RXD_1, TMS570_PIN_FNC_AUTO);
-  tms570_bsp_pin_set_function(TMS570_BALL_P1_MII_RXD_0, TMS570_PIN_FNC_AUTO);
-  tms570_bsp_pin_set_function(TMS570_BALL_K19_MII_RXCLK, TMS570_PIN_FNC_AUTO);
-  tms570_bsp_pin_set_function(TMS570_BALL_N19_MII_RX_ER, TMS570_PIN_FNC_AUTO);
-  tms570_bsp_pin_set_function(TMS570_BALL_B11_MII_RX_DV, TMS570_PIN_FNC_AUTO);
-  tms570_bsp_pin_set_function(TMS570_BALL_B4_MII_CRS, TMS570_PIN_FNC_AUTO);
-  tms570_bsp_pin_set_function(TMS570_BALL_F3_MII_COL, TMS570_PIN_FNC_AUTO);
-  tms570_bsp_pin_clear_function(TMS570_MMR_SELECT_GMII_SEL, 
TMS570_PIN_FNC_AUTO);
-
-  TMS570_IOMM.KICK_REG0 = 0;
-  TMS570_IOMM.KICK_REG1 = 0;
-#endif /*__rtems__*/
+  tms570_pin_config_prepare();
+  tms570_pin_config_array_apply(tms570_eth_pin_config,
+RTEMS_ARRAY_SIZE(tms570_eth_pin_config));
+  tms570_pin_config_complete();
 }
 
 static err_t
-- 
2.35.3

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[lwip 0/6] Add basic support for TMS570LC4357

2023-04-04 Thread Sebastian Huber 
In general, the lwIP stack lacks a generic MDIO/Phy framework.

Sebastian Huber (6):
  Generalize MDIO support
  tms570: Fix warning
  tms570: Use new pin configuration API
  tms570: Add EMACUse100Mbps()
  tms570: Add endianess support
  tms570: Add data cache support

 cpsw/src/include/hw_mdio.h   |  21 ++
 cpsw/src/include/mdio.h  |  59 +++--
 cpsw/src/include/phy.h   |  26 ++-
 cpsw/src/netif/cpswif.c  |  47 ++--
 cpsw/src/netif/mdio.c|  58 ++---
 cpsw/src/netif/phy.c | 100 
 uLan/ports/driver/tms570_emac/phy_dp83848h.c |  80 +++
 uLan/ports/driver/tms570_emac/phy_dp83848h.h |  26 +--
 uLan/ports/driver/tms570_emac/ti_drv_emac.h  |  19 ++
 uLan/ports/driver/tms570_emac/ti_drv_mdio.h  | 167 --
 uLan/ports/driver/tms570_emac/tms570_emac.h  |   5 +-
 uLan/ports/driver/tms570_emac/tms570_netif.c | 231 +++
 12 files changed, 377 insertions(+), 462 deletions(-)
 delete mode 100644 uLan/ports/driver/tms570_emac/ti_drv_mdio.h

-- 
2.35.3

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[lwip 5/6] tms570: Add endianess support

2023-04-04 Thread Sebastian Huber 
---
 uLan/ports/driver/tms570_emac/tms570_netif.c | 135 +++
 1 file changed, 81 insertions(+), 54 deletions(-)

diff --git a/uLan/ports/driver/tms570_emac/tms570_netif.c 
b/uLan/ports/driver/tms570_emac/tms570_netif.c
index b484a42..4149bcb 100644
--- a/uLan/ports/driver/tms570_emac/tms570_netif.c
+++ b/uLan/ports/driver/tms570_emac/tms570_netif.c
@@ -148,6 +148,30 @@ static void tms570_eth_init_netif_fill(struct netif 
*netif);
 static void tms570_eth_init_buffer_descriptors(struct tms570_netif_state 
*nf_state);
 static void tms570_eth_init_set_pinmux();
 
+static inline uint32_t tms570_eth_swap(uint32_t word)
+{
+#if TMS570_VARIANT == 4357
+  return __builtin_bswap32(word);
+#else
+  return word;
+#endif
+}
+
+static inline uint8_t *tms570_eth_swap_bufptr(volatile void *p)
+{
+  return (uint8_t *)tms570_eth_swap((uint32_t)p);
+}
+
+static inline struct emac_tx_bd *tms570_eth_swap_txp(volatile struct 
emac_tx_bd *p)
+{
+  return (struct emac_tx_bd *)tms570_eth_swap((uint32_t)p);
+}
+
+static inline struct emac_rx_bd *tms570_eth_swap_rxp(volatile struct 
emac_rx_bd *p)
+{
+  return (struct emac_rx_bd *)tms570_eth_swap((uint32_t)p);
+}
+
 /* initializing functions **/
 
 
@@ -518,8 +542,10 @@ tms570_eth_init_buffer_descriptors(struct 
tms570_netif_state *nf_state)
* Initialize the Descriptor Memory For TX and RX
* Only Channel 0 is supported for both TX and RX
*/
-  txch->inactive_head = (volatile struct emac_tx_bd *)nf_state->emac_ctrl_ram;
-  txch->inactive_tail = NULL;
+
+  /* Initialize all the TX buffer Descriptors */
+  curr_txbd = (volatile struct emac_tx_bd *)nf_state->emac_ctrl_ram;
+  txch->inactive_head = curr_txbd;
   txch->active_head = NULL;
   txch->active_tail = NULL;
 
@@ -531,38 +557,40 @@ tms570_eth_init_buffer_descriptors(struct 
tms570_netif_state *nf_state)
   tms570_eth_debug_printf("pocet bd %d\n", num_bd);
 #endif
 
-  curr_txbd = txch->inactive_head;
-
-  /* Initialize all the TX buffer Descriptors */
   while (num_bd > 0) {
-curr_txbd->next = curr_txbd + 1;
+volatile struct emac_tx_bd *next_txbd = curr_txbd + 1;
+curr_txbd->next = tms570_eth_swap_txp(next_txbd);
 curr_txbd->flags_pktlen = 0;
-txch->inactive_tail = curr_txbd;
-curr_txbd = curr_txbd->next;
-num_bd--;
+curr_txbd = next_txbd;
+--num_bd;
   }
+
+  --curr_txbd;
   curr_txbd->next = NULL;
+  txch->inactive_tail = curr_txbd;
 
   /* Initialize the descriptors for the RX channel */
-  rxch->inactive_head = ((volatile struct emac_rx_bd *)curr_txbd)+2;
+  curr_rxbd = (volatile struct emac_rx_bd *)(curr_txbd + 1);
+  rxch->inactive_head = curr_rxbd;
+  rxch->active_tail = NULL;
+  rxch->active_head = NULL;
   rxch->freed_pbuf_len = MAX_RX_PBUF_ALLOC*PBUF_LEN_MAX;
-  rxch->inactive_head->flags_pktlen = EMAC_DSC_FLAG_OWNER;
-  rxch->inactive_head->next = rxch->inactive_head + 1;
-  curr_rxbd = rxch->inactive_head;
 
   num_bd = ((SIZE_EMAC_CTRL_RAM >> 1) / sizeof(struct emac_rx_bd))-1;
 
   while (num_bd > 0) {
-curr_rxbd = curr_rxbd->next;
-curr_rxbd->next = curr_rxbd + 1;
-curr_rxbd->flags_pktlen = EMAC_DSC_FLAG_OWNER;
+volatile struct emac_rx_bd *next_rxbd = curr_rxbd + 1;
+curr_rxbd->next = tms570_eth_swap_rxp(next_rxbd);
+curr_rxbd->flags_pktlen = tms570_eth_swap(EMAC_DSC_FLAG_OWNER);
 curr_rxbd->pbuf = NULL;
-num_bd--;
+curr_rxbd = next_rxbd;
+--num_bd;
   }
+
+  --curr_rxbd;
   curr_rxbd->next = NULL;
   rxch->inactive_tail = curr_rxbd;
-  rxch->active_tail = NULL;
-  rxch->active_head = NULL;
+
 #if TMS570_NETIF_DEBUG
   tms570_eth_debug_show_rx(nf_state);
   tms570_eth_debug_show_tx(nf_state);
@@ -648,8 +676,8 @@ tms570_eth_send_raw(struct netif *netif, struct pbuf *pbuf)
   }
 
   /* First 'part' of packet flags */
-  curr_bd->flags_pktlen = pktlen | EMAC_DSC_FLAG_SOP |
-  EMAC_DSC_FLAG_OWNER;
+  curr_bd->flags_pktlen = tms570_eth_swap(pktlen | EMAC_DSC_FLAG_SOP |
+  EMAC_DSC_FLAG_OWNER);
 
   /* Copy pbuf information into TX BDs --
* remember that the pbuf for a single packet might be chained!
@@ -658,8 +686,8 @@ tms570_eth_send_raw(struct netif *netif, struct pbuf *pbuf)
 if (curr_bd == NULL)
   goto error_out_of_descriptors;
 
-curr_bd->bufptr = (uint8_t *)(q->payload);
-curr_bd->bufoff_len = (q->len) & 0x;
+curr_bd->bufptr = tms570_eth_swap_bufptr(q->payload);
+curr_bd->bufoff_len = tms570_eth_swap(q->len & 0x);
 
 /* This is an extra field that is not par of the in-HW BD.
  * This is used when freeing the pbuf after the TX processing
@@ -667,7 +695,7 @@ tms570_eth_send_raw(struct netif *netif, struct pbuf *pbuf)
  */
 curr_bd->pbuf = pbuf;
 packet_tail = curr_bd;
-curr_bd = curr_bd->next;
+curr_bd = tms570_eth_swap_txp(curr_bd->next);
   }
   if (padlen) {
 if (curr_bd == NULL)
@@ -679,14 +707,14 @@ tms570_eth_send_raw(struct netif *netif, struct pb

[lwip 2/6] tms570: Fix warning

2023-04-04 Thread Sebastian Huber 
---
 uLan/ports/driver/tms570_emac/tms570_netif.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/uLan/ports/driver/tms570_emac/tms570_netif.c 
b/uLan/ports/driver/tms570_emac/tms570_netif.c
index 74758e5..c27f6d5 100644
--- a/uLan/ports/driver/tms570_emac/tms570_netif.c
+++ b/uLan/ports/driver/tms570_emac/tms570_netif.c
@@ -130,7 +130,9 @@ static
 #endif /*__TI_COMPILER_VERSION__*/
 SYS_IRQ_HANDLER_FNC(tms570_eth_irq);
 static void tms570_eth_rx_pbuf_refill(struct tms570_netif_state *nf_state, 
int);
+#if LWIP_NETIF_API
 static void tms570_eth_rx_pbuf_refill_single(struct netif *);
+#endif
 static void tms570_eth_hw_set_RX_HDP(struct tms570_netif_state *nf_state, 
volatile struct emac_rx_bd *new_head);
 static void tms570_eth_hw_set_TX_HDP(struct tms570_netif_state *nf_state, 
volatile struct emac_tx_bd *new_head);
 static void tms570_eth_hw_set_hwaddr(struct tms570_netif_state *nf_state, 
uint8_t *mac_addr);
@@ -1014,11 +1016,13 @@ tms570_eth_hw_set_TX_HDP(struct tms570_netif_state 
*nf_state, volatile struct em
 CHANNEL);
 }
 
+#if LWIP_NETIF_API
 static void
 tms570_eth_rx_pbuf_refill_single(struct netif *netif)
 {
   tms570_eth_rx_pbuf_refill(netif->state, 1);
 }
+#endif
 
 static void
 tms570_eth_rx_pbuf_refill(struct tms570_netif_state *nf_state, int single_fl)
@@ -1119,6 +1123,7 @@ SYS_IRQ_HANDLER_FNC(tms570_eth_irq){
 sys_sem_signal_from_ISR(&nf_state->intPend_sem);
 }
 
+#if LWIP_NETIF_API
 void
 tms570_eth_memp_avaible(int type)
 {
@@ -1128,8 +1133,7 @@ tms570_eth_memp_avaible(int type)
 return;
   netifapi_netif_common(eth_lwip_get_netif(0), 
tms570_eth_rx_pbuf_refill_single, NULL);
 }
-
-
+#endif
 
 #if TMS570_NETIF_DEBUG
 
-- 
2.35.3

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[lwip 4/6] tms570: Add EMACUse100Mbps()

2023-04-04 Thread Sebastian Huber 
---
 uLan/ports/driver/tms570_emac/ti_drv_emac.h  | 19 +++
 uLan/ports/driver/tms570_emac/tms570_netif.c |  6 ++
 2 files changed, 25 insertions(+)

diff --git a/uLan/ports/driver/tms570_emac/ti_drv_emac.h 
b/uLan/ports/driver/tms570_emac/ti_drv_emac.h
index 54f22c8..a829edd 100644
--- a/uLan/ports/driver/tms570_emac/ti_drv_emac.h
+++ b/uLan/ports/driver/tms570_emac/ti_drv_emac.h
@@ -163,6 +163,25 @@ EMACDuplexSet(volatile tms570_emacm_t *emacBase, int 
duplexMode)
   }
 }
 
+/**
+ * \brief   This API sets the RMII interface speeed for MAC.
+ *
+ * \param   emacBase Base address of the EMAC Module registers.
+ * \param   use100Mbps   indicates if the RMII interface speed shall be 100 
Mbps.
+ *
+ * \return  None
+ *
+ **/
+static inline void
+EMACUse100Mbps(volatile tms570_emacm_t *emacBase, bool use100Mbps)
+{
+  if (use100Mbps) {
+emacBase->MACCONTROL |= TMS570_EMACM_MACCONTROL_RMIISPEED;
+  } else {
+emacBase->MACCONTROL &= ~TMS570_EMACM_MACCONTROL_RMIISPEED;
+  }
+}
+
 /**
  * \brief   API to enable the transmit in the TX Control Register
  *  After the transmit is enabled, any write to TXHDP of
diff --git a/uLan/ports/driver/tms570_emac/tms570_netif.c 
b/uLan/ports/driver/tms570_emac/tms570_netif.c
index 46e025a..b484a42 100644
--- a/uLan/ports/driver/tms570_emac/tms570_netif.c
+++ b/uLan/ports/driver/tms570_emac/tms570_netif.c
@@ -468,6 +468,12 @@ tms570_eth_init_hw_post_init(struct tms570_netif_state 
*nf_state)
 return UNKN_DUPLEX_MODE;
   }
 
+  if (regContent & (PHY_100BASETX_m | PHY_100BASETXDUPL_m)) {
+EMACUse100Mbps(nf_state->emac_base, true);
+  } else {
+EMACUse100Mbps(nf_state->emac_base, false);
+  }
+
   /* enable hostpend interrupts in emac module */
   nf_state->emac_base->MACINTMASKSET |= TMS570_EMACM_MACINTMASKSET_HOSTMASK;
 
-- 
2.35.3

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[lwip 6/6] tms570: Add data cache support

2023-04-04 Thread Sebastian Huber 
---
 uLan/ports/driver/tms570_emac/tms570_netif.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/uLan/ports/driver/tms570_emac/tms570_netif.c 
b/uLan/ports/driver/tms570_emac/tms570_netif.c
index 4149bcb..eac9527 100644
--- a/uLan/ports/driver/tms570_emac/tms570_netif.c
+++ b/uLan/ports/driver/tms570_emac/tms570_netif.c
@@ -1099,6 +1099,7 @@ tms570_eth_rx_pbuf_refill(struct tms570_netif_state 
*nf_state, int single_fl)
 } else {
   q = new_pbuf;
   for (;; ) {
+rtems_cache_invalidate_multiple_data_lines(q->payload, q->len);
 curr_bd->bufptr = tms570_eth_swap_bufptr(q->payload);
 curr_bd->bufoff_len = tms570_eth_swap(q->len);
 curr_bd->flags_pktlen = tms570_eth_swap(EMAC_DSC_FLAG_OWNER);
-- 
2.35.3

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[lwip 1/6] Generalize MDIO support

2023-04-04 Thread Sebastian Huber 
Add support for MDIO drivers.  This is just a first step to unify the
PHY/MDIO support in cpsw and uLan.  Defining a proper API needs more
work.
---
 cpsw/src/include/hw_mdio.h   |  21 +++
 cpsw/src/include/mdio.h  |  59 ---
 cpsw/src/include/phy.h   |  26 +--
 cpsw/src/netif/cpswif.c  |  47 +++---
 cpsw/src/netif/mdio.c|  58 ++-
 cpsw/src/netif/phy.c | 100 +--
 uLan/ports/driver/tms570_emac/phy_dp83848h.c |  80 -
 uLan/ports/driver/tms570_emac/phy_dp83848h.h |  26 +--
 uLan/ports/driver/tms570_emac/ti_drv_mdio.h  | 167 ---
 uLan/ports/driver/tms570_emac/tms570_emac.h  |   5 +-
 uLan/ports/driver/tms570_emac/tms570_netif.c |  26 +--
 11 files changed, 239 insertions(+), 376 deletions(-)
 delete mode 100644 uLan/ports/driver/tms570_emac/ti_drv_mdio.h

diff --git a/cpsw/src/include/hw_mdio.h b/cpsw/src/include/hw_mdio.h
index 1372a1d..e05200d 100755
--- a/cpsw/src/include/hw_mdio.h
+++ b/cpsw/src/include/hw_mdio.h
@@ -43,6 +43,10 @@
 #ifndef _HW_MDIO_H_
 #define _HW_MDIO_H_
 
+#include "mdio.h"
+
+#include 
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -249,6 +253,23 @@ extern "C" {
 #define MDIO_USERPHYSEL1_PHYADRMON (0x001Fu)
 #define MDIO_USERPHYSEL1_PHYADRMON_SHIFT (0xu)
 
+typedef struct {
+mdioControl base;
+uintptr_t baseAddr;
+} tiMDIOControl;
+
+void TIMDIOInit(mdioControl *self, unsigned int mdioInputFreq,
+unsigned int mdioOutputFreq);
+
+unsigned int TIMDIOPhyAliveStatusGet(mdioControl *self);
+
+unsigned int TIMDIOPhyLinkStatusGet(mdioControl *self);
+
+unsigned int TIMDIOPhyRegRead(mdioControl *self,
+unsigned int phyAddr, unsigned int regNum, unsigned short *dataPtr);
+
+void TIMDIOPhyRegWrite(mdioControl *self, unsigned int phyAddr,
+unsigned int regNum, unsigned short regVal);
 
 #ifdef __cplusplus
 }
diff --git a/cpsw/src/include/mdio.h b/cpsw/src/include/mdio.h
index 7b3c64c..326683a 100755
--- a/cpsw/src/include/mdio.h
+++ b/cpsw/src/include/mdio.h
@@ -43,32 +43,53 @@
 #ifndef __MDIO_H__
 #define __MDIO_H__
 
-#include "hw_mdio.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
-/*/
-/*
-** Structure to save CPSW context
-*/
-typedef struct mdioContext {
-unsigned int mdioCtrl;
-}MDIOCONTEXT;
+
+typedef struct mdioControl {
+void (*init)(struct mdioControl *self, unsigned int mdioInputFreq,
+  unsigned int mdioOutputFreq);
+unsigned int (*phyAliveStatusGet)(struct mdioControl *self);
+unsigned int (*phyLinkStatusGet)(struct mdioControl *self);
+unsigned int (*phyRegRead)(struct mdioControl *self, unsigned int phyAddr,
+   unsigned int regNum, unsigned short *dataPtr);
+void (*phyRegWrite)(struct mdioControl *self, unsigned int phyAddr,
+unsigned int regNum, unsigned short RegVal);
+} mdioControl;
 
 /*
 ** Prototypes for the APIs
 */
-extern unsigned int MDIOPhyAliveStatusGet(unsigned int baseAddr);
-extern unsigned int MDIOPhyLinkStatusGet(unsigned int baseAddr);
-extern void MDIOInit(unsigned int baseAddr, unsigned int mdioInputFreq,
- unsigned int mdioOutputFreq);
-extern unsigned int MDIOPhyRegRead(unsigned int baseAddr, unsigned int phyAddr,
-   unsigned int regNum, volatile unsigned 
short *dataPtr);
-extern void MDIOPhyRegWrite(unsigned int baseAddr, unsigned int phyAddr,
-unsigned int regNum, unsigned short RegVal);
-extern void MDIOContextSave(unsigned int baseAddr, MDIOCONTEXT *contextPtr);
-extern void MDIOContextRestore(unsigned int baseAddr, MDIOCONTEXT *contextPtr);
+
+static inline void MDIOInit(mdioControl *self, unsigned int mdioInputFreq,
+unsigned int mdioOutputFreq)
+{
+  return (*self->init)(self, mdioInputFreq, mdioOutputFreq);
+}
+
+static inline unsigned int MDIOPhyAliveStatusGet(mdioControl *self)
+{
+  return (*self->phyAliveStatusGet)(self);
+}
+
+static inline unsigned int MDIOPhyLinkStatusGet(mdioControl *self)
+{
+  return (*self->phyLinkStatusGet)(self);
+}
+
+static inline unsigned int MDIOPhyRegRead(mdioControl *self,
+unsigned int phyAddr, unsigned int regNum, unsigned short *dataPtr)
+{
+  return (*self->phyRegRead)(self, phyAddr, regNum, dataPtr);
+}
+
+static inline void MDIOPhyRegWrite(mdioControl *self, unsigned int phyAddr,
+unsigned int regNum, unsigned short regVal)
+{
+  return (*self->phyRegWrite)(self, phyAddr, regNum, regVal);
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/cpsw/src/include/phy.h b/cpsw/src/include/phy.h
index 26292bb..3d2caa2 100755
--- a/cpsw/src/include/phy.h
+++ b/cpsw/src/include/phy.h
@@ -42,6 +42,8 @@
 #ifndef _PHY_H_
 #define _PHY_H_
 
+#include "mdio.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -113,37 +115,37 @@ extern "C" {
 /

[PATCH 2/2] user/microblaze: Document device tree support

2023-04-04 Thread Alex White 
---
 user/bsps/bsps-microblaze.rst | 29 -
 1 file changed, 24 insertions(+), 5 deletions(-)

diff --git a/user/bsps/bsps-microblaze.rst b/user/bsps/bsps-microblaze.rst
index 2a8a6dd..864b3c8 100644
--- a/user/bsps/bsps-microblaze.rst
+++ b/user/bsps/bsps-microblaze.rst
@@ -21,13 +21,21 @@ Clock Driver
 
 
 The clock driver supports the QEMU emulated Xilinx AXI Timer v2.0. It is
-implemented as a simple downcounter.
+implemented as a simple downcounter. If device tree support is enabled in the
+build configuration, the clock driver will use the node that is compatible with
+`xlnx,xps-timer-1.00.a` from the device tree to configure the clock. The
+following device tree node properties are used to configure the clock driver:
+``reg``, ``clock-frequency``, and ``interrupts``.
 
 Console Driver
 --
 
 The console driver supports the QEMU emulated Xilinx AXI UART Lite v2.0. It is
-initialized to a baud rate of 115200.
+initialized to a baud rate of 115200. If device tree support is enabled in the
+build configuration, the console driver will use the node that is compatible
+with `xlnx,xps-uartlite-1.00.a` from the device tree to configure the console.
+The following device tree node properties are used to configure the console
+driver: ``reg``, ``status``, ``port-number``, and ``interrupts``.
 
 Network Driver
 --
@@ -68,7 +76,9 @@ The QSPI NOR JFFS2 driver supports the QEMU emulated 
n25q512a11 QSPI NOR flash
 device. It is initialized to a page size of 256 bytes and a sector size of 64
 KiB. If device tree support is enabled in the build configuration, the QSPI NOR
 JFFS2 driver will use the node that is compatible with `xlnx,xps-spi-2.00.a`
-from the device tree to configure the QSPI NOR JFFS2 driver.
+from the device tree to configure the QSPI NOR JFFS2 driver. The following
+device tree node properties are used to configure the QSPI NOR JFFS2 driver:
+``reg`` and ``interrupts``.
 
 
 Running Executables
@@ -124,12 +134,21 @@ Clock Driver
 
 
 The clock driver supports the Xilinx AXI Timer v2.0. It is implemented as a
-simple downcounter.
+simple downcounter. If device tree support is enabled in the
+build configuration, the clock driver will use the node that is compatible with
+`xlnx,xps-timer-1.00.a` from the device tree to configure the clock. The
+following device tree node properties are used to configure the clock driver:
+``reg``, ``clock-frequency``, and ``interrupts``.
 
 Console Driver
 --
 
-The console driver supports the Xilinx AXI UART Lite v2.0.
+The console driver supports the Xilinx AXI UART Lite v2.0. It is initialized to
+a baud rate of 115200. If device tree support is enabled in the build
+configuration, the console driver will use the node that is compatible with
+`xlnx,xps-uartlite-1.00.a` from the device tree to configure the console. The
+following device tree node properties are used to configure the console driver:
+``reg``, ``status``, ``port-number``, and ``interrupts``.
 
 Debugging
 -
-- 
2.34.1

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[PATCH 1/2] user/microblaze: Document QSPI NOR JFFS2 driver

2023-04-04 Thread Alex White 
---
 user/bsps/bsps-microblaze.rst | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/user/bsps/bsps-microblaze.rst b/user/bsps/bsps-microblaze.rst
index 32aad90..2a8a6dd 100644
--- a/user/bsps/bsps-microblaze.rst
+++ b/user/bsps/bsps-microblaze.rst
@@ -61,6 +61,16 @@ to include it in the BSP build.
   BSP_MICROBLAZE_FPGA_DTB_HEADER_PATH = /path/to/my_dtb.c
 
 
+QSPI NOR JFFS2 Driver
+-
+
+The QSPI NOR JFFS2 driver supports the QEMU emulated n25q512a11 QSPI NOR flash
+device. It is initialized to a page size of 256 bytes and a sector size of 64
+KiB. If device tree support is enabled in the build configuration, the QSPI NOR
+JFFS2 driver will use the node that is compatible with `xlnx,xps-spi-2.00.a`
+from the device tree to configure the QSPI NOR JFFS2 driver.
+
+
 Running Executables
 ---
 
-- 
2.34.1

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Re: [PATCH v2 3/3] bsps/microblaze: Fix UART transmit interrupt

2023-04-04 Thread Sebastian Huber 
Feel free to check in this patch. I just have a side note. I tried to 
write a Termios interrupt driver for a FIFO device some time ago:


bsps/arm/imx/console/console-config.c

It worked only without gaps because the device offered the ability to 
get the current FIFO level. Waiting for the FIFO to get completely empty 
resulted in transmission gaps sometimes.


--
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Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
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[PATCH 1/2] spec: Silence benign warnings in 3rd party code

2023-04-04 Thread Kinsey Moore 
Do not warn about excessive shifts in imported Xilinx driver code when
building with the ILP32 ABI. The two instances of this warning produce
the desired effect of setting the upper address bits to 0.
---
 spec/build/bsps/objnandpsu.yml | 3 ++-
 spec/build/bsps/objqspipsu.yml | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/spec/build/bsps/objnandpsu.yml b/spec/build/bsps/objnandpsu.yml
index 253c598e8c..3ed622fcc3 100644
--- a/spec/build/bsps/objnandpsu.yml
+++ b/spec/build/bsps/objnandpsu.yml
@@ -1,6 +1,7 @@
 SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
 build-type: objects
-cflags: []
+cflags:
+- -Wno-shift-count-overflow
 copyrights:
 - Copyright (C) 2022 On-Line Applications Research (OAR)
 cppflags: []
diff --git a/spec/build/bsps/objqspipsu.yml b/spec/build/bsps/objqspipsu.yml
index 205172146e..b4c63bc632 100644
--- a/spec/build/bsps/objqspipsu.yml
+++ b/spec/build/bsps/objqspipsu.yml
@@ -1,6 +1,7 @@
 SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
 build-type: objects
-cflags: []
+cflags:
+- -Wno-shift-count-overflow
 copyrights:
 - Copyright (C) 2022 On-Line Applications Research (OAR)
 cppflags: []
-- 
2.30.2

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[PATCH 2/2] cpukit/libdl: Resolve size mismatch warnings

2023-04-04 Thread Kinsey Moore 
Resolve warnings about mismatched pointer and integer sizes in AArch64
libdl when building with the ILP32 ABI.
---
 cpukit/libdl/rtl-elf.c |  4 ++--
 cpukit/libdl/rtl-mdreloc-aarch64.c | 31 +++---
 cpukit/libdl/rtl-rap.c |  4 ++--
 3 files changed, 20 insertions(+), 19 deletions(-)

diff --git a/cpukit/libdl/rtl-elf.c b/cpukit/libdl/rtl-elf.c
index 8a21c5df73..5754070518 100644
--- a/cpukit/libdl/rtl-elf.c
+++ b/cpukit/libdl/rtl-elf.c
@@ -192,7 +192,7 @@ rtems_rtl_elf_find_symbol (rtems_rtl_obj*  obj,
 if (!*symbol)
   return false;
 
-*value = (Elf_Addr) (*symbol)->value;
+*value = (Elf_Addr)(uintptr_t) (*symbol)->value;
 return true;
   }
 
@@ -202,7 +202,7 @@ rtems_rtl_elf_find_symbol (rtems_rtl_obj*  obj,
   if (!sect)
 return false;
 
-  *value = sym->st_value + (Elf_Addr) sect->base;
+  *value = sym->st_value + (Elf_Addr)(uintptr_t) sect->base;
 
   return true;
 }
diff --git a/cpukit/libdl/rtl-mdreloc-aarch64.c 
b/cpukit/libdl/rtl-mdreloc-aarch64.c
index e44238e636..25057ce9d7 100644
--- a/cpukit/libdl/rtl-mdreloc-aarch64.c
+++ b/cpukit/libdl/rtl-mdreloc-aarch64.c
@@ -107,7 +107,7 @@ checkoverflow(Elf_Addr addr, int bitwidth, Elf_Addr 
targetaddr,
   const Elf_Addr mask = ~__BITS(bitwidth - 1, 0);
 
   if (((addr & mask) != 0) && ((addr & mask) != mask)) {
-printf("kobj_reloc: Relocation 0x%jx too far from %p"
+printf("kobj_reloc: Relocation 0x%" PRIxPTR " too far from %p"
 " (base+0x%jx) for %dbit%s\n",
 (uintptr_t)targetaddr, where, off, bitwidth, bitscale);
 return true;
@@ -120,7 +120,7 @@ static inline bool
 checkalign(Elf_Addr addr, int alignbyte, void *where, Elf64_Addr off)
 {
   if ((addr & (alignbyte - 1)) != 0) {
-printf("kobj_reloc: Relocation 0x%jx unaligned at %p"
+printf("kobj_reloc: Relocation 0x%" PRIxPTR " unaligned at %p"
 " (base+0x%jx). must be aligned %d\n",
 (uintptr_t)addr, where, off, alignbyte);
 return true;
@@ -257,7 +257,7 @@ rtems_rtl_elf_reloc_rela (rtems_rtl_obj*obj,
 
 if (rtems_rtl_trace (RTEMS_RTL_TRACE_RELOC))
   printf ("rtl: reloc 64/GLOB_DAT in %s --> %p in %s\n",
-  sect->name, (void *)*where,
+  sect->name, (void *)(uintptr_t)*where,
   rtems_rtl_obj_oname (obj));
   }
   break;
@@ -270,10 +270,10 @@ rtems_rtl_elf_reloc_rela (rtems_rtl_obj*obj,
  */
 case R_TYPE(RELATIVE):  /* Delta(S) + A */
   if (!parsing) {
-*where = (Elf_Addr)(sect->base + rela->r_addend);
+*where = (Elf_Addr)(uintptr_t)(sect->base + rela->r_addend);
 if (rtems_rtl_trace (RTEMS_RTL_TRACE_RELOC))
   printf ("rtl: reloc RELATIVE in %s --> %p in %s\n",
-  sect->name, (void *)*where,
+  sect->name, (void *)(uintptr_t)*where,
   rtems_rtl_obj_oname (obj));
   }
   break;
@@ -304,7 +304,7 @@ rtems_rtl_elf_reloc_rela (rtems_rtl_obj*obj,
   shift = 12;
   break;
 default:
-  printf("illegal rtype: %ld\n", ELF_R_TYPE(rela->r_info));
+  printf("illegal rtype: %" PRIu64 "\n", ELF_R_TYPE(rela->r_info));
   break;
   }
 
@@ -344,7 +344,7 @@ rtems_rtl_elf_reloc_rela (rtems_rtl_obj*obj,
   shift = 3;
   break;
 default:
-  printf("illegal rtype: %ld\n", ELF_R_TYPE(rela->r_info));
+  printf("illegal rtype: %" PRIu64 "\n", ELF_R_TYPE(rela->r_info));
   break;
   }
 
@@ -360,9 +360,9 @@ rtems_rtl_elf_reloc_rela (rtems_rtl_obj*obj,
 target = (Elf_Addr)symvalue + rela->r_addend;
 if (checkalign(target, 1 << shift, where, off)) {
   printf ("rtl: reloc checkalign failed in %s --> %p in %s\n",
-  sect->name, (void *)*where,
+  sect->name, (void *)(uintptr_t)*where,
   rtems_rtl_obj_oname (obj));
-  printf("ELF_R_TYPE is : %ld\n", ELF_R_TYPE(rela->r_info));
+  printf("ELF_R_TYPE is : %" PRIu64 "\n", ELF_R_TYPE(rela->r_info));
   break;
 }
 target &= WIDTHMASK(12);
@@ -433,7 +433,7 @@ rtems_rtl_elf_reloc_rela (rtems_rtl_obj*obj,
   return rtems_rtl_elf_rel_failure;
 }
 
-tramp_addr = ((Elf_Addr) obj->tramp_brk) | (symvalue & 1);
+tramp_addr = ((Elf_Addr)(uintptr_t)obj->tramp_brk) | (symvalue & 1);
 obj->tramp_brk = set_veneer(obj->tramp_brk, symvalue);
 
 target = tramp_addr + rela->r_addend - (uintptr_t)where;
@@ -468,29 +468,30 @@ rtems_rtl_elf_reloc_rela (rtems_rtl_obj*obj,
 
 case R_TYPE(TLSDESC):
   printf ("rtl: reloc TLSDESC in %s --> %p in %s\n",
-  sect->name, (void *)*where,
+  sect->name, (void *)(uintptr_t)*where,
   rtems_rtl_obj_oname (obj));
   break;
 
 case R_TLS_TYPE(TLS_DTPREL):
   printf ("rtl

[PATCH 1/8] dtc: Disable warnings

2023-04-04 Thread chrisj 
From: Chris Johns 

Updates #4892
---
 source-builder/config/dtc-1-1.cfg | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/source-builder/config/dtc-1-1.cfg 
b/source-builder/config/dtc-1-1.cfg
index 686a1e0..d42e91e 100644
--- a/source-builder/config/dtc-1-1.cfg
+++ b/source-builder/config/dtc-1-1.cfg
@@ -37,7 +37,7 @@ URL: https://www.devicetree.org/
 
   %{build_build_flags}
 
-  %{__make} PREFIX=%{_prefix}
+  %{__make} PREFIX=%{_prefix} WARNINGS=
 
   cd ${build_top}
 
@@ -47,6 +47,6 @@ URL: https://www.devicetree.org/
   rm -rf $SB_BUILD_ROOT
 
   cd dtc-%{dtc_version}
-  %{__make} DESTDIR=$SB_BUILD_ROOT PREFIX=%{_prefix} install
+  %{__make} DESTDIR=$SB_BUILD_ROOT PREFIX=%{_prefix} WARNINGS= install
 
   cd ${build_top}
-- 
2.37.1

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[rtems-source-builder] Python Virtual Env and MacOS arm64

2023-04-04 Thread chrisj 
Hi,

These patches provide:

- GDB Python Virtual Env support

  If you start a build in a python virtual env it will be used as the
  path to python provided to GDB if GDB is version 13.* and later. Using
  a virtual env simplifes the support we need to maintain and in time
  this will become a requirement.

  GDB 13 requires Python 3 and so this means we are requiring users
  to move to Python 3. Python 2 and 3 support will remain in the RSB as
  we have planned until RTEMS 6 is released.

- MacOS M series support

  Support for M series is now stable. This work builds on the work
  Karel has done previously (thanks). There was a crash in xgcc when
  building the runtime libraires and it has been revolved with a configure 
  option to the GMP package.

  I have tested with Xcode 14.3 (14E222b) and MacOS 13.3.

  The GDB python virtual env support lets the python.org universal
  package installer be used. The ticket #4892 has the details.

  The need for a special configure option means the GMP package built
  and staged as part of the build set needs to be used so the internal
  GCC build of GMP has been removed. GMP is built as a package for
  GDB.

  I think in time we will move away from the GCC internally built
  packages to separate packages so we can provide the fine grain
  control we seem to need.

  MPFR has been updated to 4.2.0 for MacOS support. This is fetched
  from the MPFR home site.

  Microblaze's GCC does not build as the version does not recognize
  the machine `arm64-apple`.

  SH does not build on MacOS and I am not sure if this is happening
  on all hosts or just MacOS.

- DCT warnings

  These are now disabled as DTC had warnings with Xcode. I prefer
  we disable warnings or errors from warnings because newer compilers
  may generate new warnings and that breaks releases years later.

- MIPS STX GDB

  This failed to build GDB 13.1 because GMP is needed and the build
  set was not a separate staged build. This has been corrected and
  the config files have been cleaned up.
 
I have tested all buildable packages on MacOS arm64 and some on
FreeBSD and PowerPC on Linux Rocky.

Chris


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[PATCH 2/8] gdb: Use a virtual environment if present

2023-04-04 Thread chrisj 
From: Chris Johns 

- Detect and use a virtual environment if present

- Supports MacOS with python.org in a venv

Updates #4892
---
 rtems/config/tools/rtems-gdb-13.1.cfg  |  4 ++
 source-builder/config/gdb-common-1.cfg | 58 --
 2 files changed, 39 insertions(+), 23 deletions(-)

diff --git a/rtems/config/tools/rtems-gdb-13.1.cfg 
b/rtems/config/tools/rtems-gdb-13.1.cfg
index 5766594..1fd0f1c 100644
--- a/rtems/config/tools/rtems-gdb-13.1.cfg
+++ b/rtems/config/tools/rtems-gdb-13.1.cfg
@@ -14,4 +14,8 @@
 %hash sha512 gdb-13-freebsd-include.diff \

2oKUpRyZIwXwyKHXn5lxXte+jV853Zvg5UHLKLfmVCW4QLrLMFsnO5LvPamIqjXnqPztB8IPEY18pdw8vOYaOw==
 
+%patch add gdb -p1 --rsb-file=gdb-14067-python-config.diff 
https://sourceware.org/bugzilla/attachment.cgi?id=14783&format=raw
+%hash sha512 gdb-14067-python-config.diff \
+   
HiCV0eQulk0W+G5uu1gCvUn5Ns6bF6RxqOO9kcSi8zpfEHOMzphlOv5cz0IDN5Q8m94na1kRVy++4z6qc43t3w==
+
 %include %{_configdir}/gdb-common-1.cfg
diff --git a/source-builder/config/gdb-common-1.cfg 
b/source-builder/config/gdb-common-1.cfg
index 9d67da0..a52e64d 100644
--- a/source-builder/config/gdb-common-1.cfg
+++ b/source-builder/config/gdb-common-1.cfg
@@ -58,7 +58,7 @@
 %define gdb-enable-python %(command -v python2 || true)
   %endif
   %if %{gdb-enable-python} == %{nil}
-  %define gdb-enable-python %(command -v python || true})
+%define gdb-enable-python %(command -v python || true})
   %endif
 %endif
 %if %{gdb-enable-python} == %{nil}
@@ -79,6 +79,9 @@
 %endif
 %if %{gdb-python-config} == %{nil}
  %define gdb-python-config %(command -v %{gdb-enable-python}-config || true)
+ %if %{gdb-python-config} == %{nil}
+  %define gdb-python-config %(command -v %(basename 
%{gdb-enable-python})-config || true)
+ %endif
 %endif
 %define gdb-python-ver-mm %(%{gdb-enable-python} --version 2>&1 | sed -e 's/.* 
//g' | rev | cut -d'.' -f2- | rev)
 %define gdb-python-ver-major %(echo "%{gdb-python-ver-mm}" | sed -e 's/\..*//')
@@ -100,30 +103,39 @@
 %if %{gdb-python-header-check} == not-found && !%{_rsb_getting_source}
   %error "gdb: python: header file not found: %{gdb-python-ver-header}, please 
install"
 %endif
-#
-# Too hard to find on MacOS (darwin), the header is good enough.
-#
-%ifnos darwin
-  %if %{host_ldflags} == %{nil}
-%define gdb-host-libs %{nil}
-  %else
-%define gdb-host-libs -L '%{host_ldflags}'
-  %endif
-  %if %{gdb-python-config} != %{nil}
-%define gdb-python-lib-filter awk 'BEGIN{FS=" 
"}/python/{for(i=1;i= 13
+  %define python-venv %(echo $VIRTUAL_ENV)
+  %if %{python-venv} != %{nil}
+%define gdb-enable-python %{python-venv}
   %endif
 %endif
 
-- 
2.37.1

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[PATCH 3/8] rtems/gcc: Do not build GMP in GCC, use the staged build

2023-04-04 Thread chrisj 
From: Chris Johns 

- Do not build GMP when building GCC. GMP is now built
  as a package for GDB. Building as a separate package
  lets use control how it is built.

Updates #4892
---
 source-builder/config/gcc-common-1.cfg | 29 +++---
 1 file changed, 8 insertions(+), 21 deletions(-)

diff --git a/source-builder/config/gcc-common-1.cfg 
b/source-builder/config/gcc-common-1.cfg
index 933202a..42c8a7b 100644
--- a/source-builder/config/gcc-common-1.cfg
+++ b/source-builder/config/gcc-common-1.cfg
@@ -58,9 +58,6 @@ URL: http://gcc.gnu.org/
 %if %{!defined mpc_url}
  %define mpc_url https://gcc.gnu.org/pub/gcc/infrastructure
 %endif
-%if %{!defined gmp_url}
- %define gmp_url https://gcc.gnu.org/pub/gcc/infrastructure
-%endif
 %if %{!defined mpfr_url}
  %define mpfr_url https://gcc.gnu.org/pub/gcc/infrastructure
 %endif
@@ -75,7 +72,6 @@ URL: http://gcc.gnu.org/
 %source set isl %{isl_url}/isl-%{isl_version}.tar.bz2
 %endif
 %source set mpc %{mpc_url}/mpc-%{mpc_version}.tar.gz
-%source set gmp %{gmp_url}/gmp-%{gmp_version}.tar.bz2
 %source set mpfr %{mpfr_url}/mpfr-%{mpfr_version}.tar.bz2
 
 #
@@ -128,15 +124,6 @@ URL:  http://gcc.gnu.org/
   %{__ln_s} $PWD/${source_dir_isl} ${source_dir_gcc}/isl
 %endif
 
-  # MPFR
-  source_dir_mpfr="mpfr-%{mpfr_version}"
-  %source setup mpfr -q -D -n mpfr-%{mpfr_version}
-  %patch setup mpfr -p1
-  cd ${build_top}
-  # Build MPFR one-tree style
-  %{__rmfile} ${source_dir_gcc}/mpfr
-  %{__ln_s} $PWD/${source_dir_mpfr} ${source_dir_gcc}/mpfr
-
   # MPC
   source_dir_mpc="mpc-%{mpc_version}"
   %source setup mpc -q -D -n mpc-%{mpc_version}
@@ -146,14 +133,14 @@ URL: http://gcc.gnu.org/
   %{__rmfile} ${source_dir_gcc}/mpc
   %{__ln_s} $PWD/${source_dir_mpc} ${source_dir_gcc}/mpc
 
-  # GMP
-  source_dir_gmp="gmp-%{gmp_version}"
-  %source setup gmp -q -D -n gmp-%{gmp_version}
-  %patch setup gmp -p1
+  # MPFR
+  source_dir_mpfr="mpfr-%{mpfr_version}"
+  %source setup mpfr -q -D -n mpfr-%{mpfr_version}
+  %patch setup mpfr -p1
   cd ${build_top}
-  # Build GMP one-tree style
-  %{__rmfile} ${source_dir_gcc}/gmp
-  %{__ln_s} $PWD/${source_dir_gmp} ${source_dir_gcc}/gmp
+  # Build MPFR one-tree style
+  %{__rmfile} ${source_dir_gcc}/mpfr
+  %{__ln_s} $PWD/${source_dir_mpfr} ${source_dir_gcc}/mpfr
 
   echo "%{gcc_version_message}" > ${source_dir_gcc}/gcc/DEV-PHASE
 
@@ -232,7 +219,7 @@ URL:   http://gcc.gnu.org/
 cp ../${source_dir_gcc}/gcc/gsyslimits.h gcc/include/syslimits.h
   fi
 
-  %{__make} %{?_smp_mflags} all
+  %{__make} -w %{?_smp_mflags} all
 
   cd ${build_top}
 
-- 
2.37.1

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[PATCH 4/8] devel/gmp: Disable assemble builds on MacOS AARCH64

2023-04-04 Thread chrisj 
From: Chris Johns 

Updates #4892
---
 source-builder/config/gmp.cfg | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/source-builder/config/gmp.cfg b/source-builder/config/gmp.cfg
index ffd3b20..4e8d674 100644
--- a/source-builder/config/gmp.cfg
+++ b/source-builder/config/gmp.cfg
@@ -19,6 +19,15 @@ URL:https://gmplib.org/
 #
 %source set gmp 
https://gcc.gnu.org/pub/gcc/infrastructure/gmp-%{gmp_version}.tar.bz2
 
+%define gmp_extra_options %{nil}
+
+#
+# Do not use assembler if MacOS AARCH64
+#
+%if %{_host_os} == darwin && %{_host_arch} == arm64
+ %define gmp_extra_options %{gmp_extra_options} --disable-assembly
+%endif
+
 #
 # Prepare the source code.
 #
@@ -44,7 +53,8 @@ URL: https://gmplib.org/
 --exec-prefix=%{_exec_prefix} \
 --includedir=%{_includedir} --libdir=%{_libdir} \
 --mandir=%{_mandir} --infodir=%{_infodir} \
---disable-shared
+--disable-shared \
+%{gmp_extra_options}
 
   %{__make} %{?_smp_mflags} all
 
-- 
2.37.1

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[PATCH 7/8] rtems/mipsstx39: Update to GDB 13.1 and stage build GMP

2023-04-04 Thread chrisj 
From: Chris Johns 

- Use a build set file to stage GMP as recent GDB
  versions require GMP.

Update #4892
---
 rtems/config/6/rtems-mips.bset|  2 +-
 rtems/config/tools/rtems-mipstx39-gdb-11.2.cfg|  3 ---
 rtems/config/tools/rtems-mipstx39-gdb-7.5.1-1.cfg | 11 ---
 rtems/config/tools/rtems-mipstx39-gdb-7.6-1.cfg   | 11 ---
 rtems/config/tools/rtems-mipstx39-gdb-7.7-1.cfg   | 11 ---
 rtems/config/tools/rtems-mipstx39-gdb-7.9-1.cfg   | 11 ---
 rtems/config/tools/rtems-mipstx39-gdb-8.0.1-1.cfg |  3 ---
 rtems/config/tools/rtems-mipstx39-gdb-head.cfg|  3 ---
 rtems/config/tools/rtems-mipstx39-gdb.bset|  7 +++
 9 files changed, 8 insertions(+), 54 deletions(-)
 delete mode 100644 rtems/config/tools/rtems-mipstx39-gdb-11.2.cfg
 delete mode 100644 rtems/config/tools/rtems-mipstx39-gdb-7.5.1-1.cfg
 delete mode 100644 rtems/config/tools/rtems-mipstx39-gdb-7.6-1.cfg
 delete mode 100644 rtems/config/tools/rtems-mipstx39-gdb-7.7-1.cfg
 delete mode 100644 rtems/config/tools/rtems-mipstx39-gdb-7.9-1.cfg
 delete mode 100644 rtems/config/tools/rtems-mipstx39-gdb-8.0.1-1.cfg
 delete mode 100644 rtems/config/tools/rtems-mipstx39-gdb-head.cfg
 create mode 100644 rtems/config/tools/rtems-mipstx39-gdb.bset

diff --git a/rtems/config/6/rtems-mips.bset b/rtems/config/6/rtems-mips.bset
index 370e5ea..6289172 100644
--- a/rtems/config/6/rtems-mips.bset
+++ b/rtems/config/6/rtems-mips.bset
@@ -3,4 +3,4 @@
 %define gdb-sim-options --enable-sim-hardware
 %define win32-gdb-disable-sim
 %include 6/rtems-default.bset
-tools/rtems-mipstx39-gdb-head
+tools/rtems-mipstx39-gdb
diff --git a/rtems/config/tools/rtems-mipstx39-gdb-11.2.cfg 
b/rtems/config/tools/rtems-mipstx39-gdb-11.2.cfg
deleted file mode 100644
index 7707519..000
--- a/rtems/config/tools/rtems-mipstx39-gdb-11.2.cfg
+++ /dev/null
@@ -1,3 +0,0 @@
-%undefine _target
-%define _target mipstx39-rtems%{rtems_version}
-%include tools/rtems-gdb-11.2.cfg
diff --git a/rtems/config/tools/rtems-mipstx39-gdb-7.5.1-1.cfg 
b/rtems/config/tools/rtems-mipstx39-gdb-7.5.1-1.cfg
deleted file mode 100644
index 3c0bed5..000
--- a/rtems/config/tools/rtems-mipstx39-gdb-7.5.1-1.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# MIPS STX39 GDB 7.5.1.
-#
-
-%undefine _target
-%define _target mipstx39-rtems%{rtems_version}
-
-#
-# The gdb build instructions for RTEMS 7.5.1.
-#
-%include tools/rtems-gdb-7.5.1-1.cfg
diff --git a/rtems/config/tools/rtems-mipstx39-gdb-7.6-1.cfg 
b/rtems/config/tools/rtems-mipstx39-gdb-7.6-1.cfg
deleted file mode 100644
index 836c0bb..000
--- a/rtems/config/tools/rtems-mipstx39-gdb-7.6-1.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# MIPS STX39 GDB 7.6.
-#
-
-%undefine _target
-%define _target mipstx39-rtems%{rtems_version}
-
-#
-# The gdb build instructions for RTEMS 7.6.
-#
-%include tools/rtems-gdb-7.6-1.cfg
diff --git a/rtems/config/tools/rtems-mipstx39-gdb-7.7-1.cfg 
b/rtems/config/tools/rtems-mipstx39-gdb-7.7-1.cfg
deleted file mode 100644
index 0e65b5e..000
--- a/rtems/config/tools/rtems-mipstx39-gdb-7.7-1.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# MIPS STX39 GDB 7.7.
-#
-
-%undefine _target
-%define _target mipstx39-rtems%{rtems_version}
-
-#
-# The gdb build instructions for RTEMS 7.7.
-#
-%include tools/rtems-gdb-7.7-1.cfg
diff --git a/rtems/config/tools/rtems-mipstx39-gdb-7.9-1.cfg 
b/rtems/config/tools/rtems-mipstx39-gdb-7.9-1.cfg
deleted file mode 100644
index 5777b5f..000
--- a/rtems/config/tools/rtems-mipstx39-gdb-7.9-1.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# MIPS TX39 GDB 7.9.
-#
-
-%undefine _target
-%define _target mipstx39-rtems%{rtems_version}
-
-#
-# The gdb 7.9 build instructions for RTEMS.
-#
-%include tools/rtems-gdb-7.9-1.cfg
diff --git a/rtems/config/tools/rtems-mipstx39-gdb-8.0.1-1.cfg 
b/rtems/config/tools/rtems-mipstx39-gdb-8.0.1-1.cfg
deleted file mode 100644
index 05b270b..000
--- a/rtems/config/tools/rtems-mipstx39-gdb-8.0.1-1.cfg
+++ /dev/null
@@ -1,3 +0,0 @@
-%undefine _target
-%define _target mipstx39-rtems%{rtems_version}
-%include tools/rtems-gdb-8.0.1-1.cfg
diff --git a/rtems/config/tools/rtems-mipstx39-gdb-head.cfg 
b/rtems/config/tools/rtems-mipstx39-gdb-head.cfg
deleted file mode 100644
index d90ea33..000
--- a/rtems/config/tools/rtems-mipstx39-gdb-head.cfg
+++ /dev/null
@@ -1,3 +0,0 @@
-%undefine _target
-%define _target mipstx39-rtems%{rtems_version}
-%include tools/rtems-gdb-head.cfg
diff --git a/rtems/config/tools/rtems-mipstx39-gdb.bset 
b/rtems/config/tools/rtems-mipstx39-gdb.bset
new file mode 100644
index 000..392e24d
--- /dev/null
+++ b/rtems/config/tools/rtems-mipstx39-gdb.bset
@@ -0,0 +1,7 @@
+%define release 1
+%define rtems_arch mips
+%define gdb-sim-options --enable-sim-hardware
+%define win32-gdb-disable-sim
+%define _target mipstx39-rtems%{rtems_version}
+devel/gmp-6.2.1
+tools/rtems-gdb-13.1
-- 
2.37.1

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[PATCH 5/8] devel/mpfr: Update to 4.2.0 to support MacOS AARCH64

2023-04-04 Thread chrisj 
From: Chris Johns 

- Use base64 checksums

- Change MPFR URL

Updates #4892
---
 rtems/config/tools/rtems-gcc-12-newlib-head.cfg |  7 ++-
 source-builder/config/gcc-12.cfg| 17 +
 2 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/rtems/config/tools/rtems-gcc-12-newlib-head.cfg 
b/rtems/config/tools/rtems-gcc-12-newlib-head.cfg
index 4cd049d..bab73f6 100644
--- a/rtems/config/tools/rtems-gcc-12-newlib-head.cfg
+++ b/rtems/config/tools/rtems-gcc-12-newlib-head.cfg
@@ -25,17 +25,14 @@
 
fKI36r/Vs4JxMYbh/CkN/JmaNTMVeV7LjdDSL80at/W/MfQymVStq5GtBMEA3KwOhtQG/bzo+Cz53COELIjK9g==
 
 # Following patches are related to compilation on Apple M1/Darwin host 
platform.
-# They are here to workaround issues with ISL, MPFR and MPC libraries.
+# They are here to workaround issues with ISL and MPC libraries.
 # Upstream projects were already informed so hopefully when RSB moves
 # to more modern libraries versions they may be removed from here.
-# The patches are solely for libisl 0.24, libmpfr 4.1.0 and libmpc 1.2.1
+# The patches are solely for libisl 0.24 and libmpc 1.2.1
 # See #4657 for more information.
 %patch add isl -p1 
https://devel.rtems.org/raw-attachment/ticket/4657/fix-mac-arm64-isl-config.patch
 %hash sha512 fix-mac-arm64-isl-config.patch \
 
wH/bYFplINGUNYUEcx5jtUAhHvaAOD8cpOxltKxDridodTT9fYGWpNvoOg7PLEKkJUxx5gnuSEp2FFc7xJmi6A==
-%patch add mpfr -p1 
https://devel.rtems.org/raw-attachment/ticket/4657/fix-mac-arm64-mpfr-config.patch
-%hash sha512 fix-mac-arm64-mpfr-config.patch \
-
3FBp34cL0Ct+eO0ixq2emiu5yjcs4aa36PpbdjXc7zXCnyUf5RlcnCpDUTEWwSyrGw6WFxzzS9f7fQM0wsdA+w==
 %patch add mpc -p1 
https://devel.rtems.org/raw-attachment/ticket/4657/fix-mac-arm64-mpc-config.patch
 %hash sha512 fix-mac-arm64-mpc-config.patch \
 
KEmxHjYOqY4LTXCMZ3I60tbHusbR5GlnP0CLARHPAnhCnovDj9K3U43C1bsMxDDGRqD6fwtrEFoEgqVFX63IuQ==
diff --git a/source-builder/config/gcc-12.cfg b/source-builder/config/gcc-12.cfg
index 21b2b17..2885819 100644
--- a/source-builder/config/gcc-12.cfg
+++ b/source-builder/config/gcc-12.cfg
@@ -2,19 +2,20 @@
 # GCC 12
 #
 # This configuration file configure's, make's and install's gcc. It uses
-# newlib, ISL, MPFR, MPC, and GMP in a one-tree build configuration.
+# newlib, ISL, MPFR and MPC in a one-tree build configuration.
 #
 
 %define isl_version 0.24
-%hash sha512 isl-%{isl_version}.tar.bz2 
aab3bddbda96b801d0f56d2869f943157aad52a6f6e6a61745edd740234c635c38231af20bc3f1a08d416a5e973a90e18249078ed8e4ae2f1d5de57658738e95
+%hash sha512 isl-%{isl_version}.tar.bz2 \
+
qrO929qWuAHQ9W0oaflDFXqtUqb25qYXRe3XQCNMY1w4IxryC8PxoI1Bal6XOpDhgkkHjtjkri8dXeV2WHOOlQ==
 
-%define mpfr_version 4.1.0
-%hash sha512 mpfr-%{mpfr_version}.tar.bz2 
410208ee0d48474c1c10d3d4a59decd2dfa187064183b09358ec4c4666e34d74383128436b404123b831e585d81a9176b24c7ced9d913967c5fce35d4040a0b4
+%define mpfr_version 4.2.0
+%define mpfr_url https://www.mpfr.org/mpfr-%{mpfr_version}
+%hash sha512 mpfr-%{mpfr_version}.tar.bz2 \
+
yyqTFLlONKTqSc4mGYAulCDJguVSWKS8Qj+AJ0BjJkaj1CDn/PNzsZYYOFuLK0Eqv6En6PRzBThjQkysIziTwA==
 
 %define mpc_version 1.2.1
-%hash sha512 mpc-%{mpc_version}.tar.gz 
3279f813ab37f47fdcc800e4ac5f306417d07f539593ca715876e43e04896e1d5bceccfb288ef2908a3f24b760747d0dbd0392a24b9b341bc3e12082e5c836ee
-
-%define gmp_version 6.2.1
-%hash sha512 gmp-%{gmp_version}.tar.bz2 
8904334a3bcc5c896ececabc75cda9dec642e401fb5397c4992c4fabea5e962c9ce8bd44e8e4233c34e55c8010cc28db0545f5f750cbdbb5f00af538dc763be9
+%hash sha512 mpc-%{mpc_version}.tar.gz \
+
Mnn4E6s39H/cyADkrF8wZBfQf1OVk8pxWHbkPgSJbh1bzsz7KI7ykIo/JLdgdH0NvQOSokubNBvD4SCC5cg27g==
 
 %include %{_configdir}/gcc-common-1.cfg
-- 
2.37.1

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[PATCH 6/8] devel/mpfr: Add MPFR as a package

2023-04-04 Thread chrisj 
From: Chris Johns 

- This is a place holder incase we stop building MPFR in
  GCC.

Updates #4892
---
 bare/config/devel/mpfr-4.2.0.cfg | 18 ++
 source-builder/config/mpfr.cfg   | 62 
 2 files changed, 80 insertions(+)
 create mode 100644 bare/config/devel/mpfr-4.2.0.cfg
 create mode 100644 source-builder/config/mpfr.cfg

diff --git a/bare/config/devel/mpfr-4.2.0.cfg b/bare/config/devel/mpfr-4.2.0.cfg
new file mode 100644
index 000..77e9ffd
--- /dev/null
+++ b/bare/config/devel/mpfr-4.2.0.cfg
@@ -0,0 +1,18 @@
+#
+# MPFR 4.2.0
+#
+
+%if %{release} == %{nil}
+%define release 1
+%endif
+
+%include %{_configdir}/base.cfg
+
+%define mpfr_version 4.2.0
+%hash sha512 mpfr-%{mpfr_version}.tar.bz2 \
+
yyqTFLlONKTqSc4mGYAulCDJguVSWKS8Qj+AJ0BjJkaj1CDn/PNzsZYYOFuLK0Eqv6En6PRzBThjQkysIziTwA==
+
+#
+# The MPFR build instructions.
+#
+%include %{_configdir}/mpfr.cfg
diff --git a/source-builder/config/mpfr.cfg b/source-builder/config/mpfr.cfg
new file mode 100644
index 000..6d64c1a
--- /dev/null
+++ b/source-builder/config/mpfr.cfg
@@ -0,0 +1,62 @@
+#
+# The GNU Multiple-precision Floating-point computations with correct Rounding 
(MPFR)
+#
+# This configuration file configure's, make's and install's GMP.
+#
+
+%if %{release} == %{nil}
+%define release 1
+%endif
+
+Name:  mpfr-%{mpfr_version}-%{_host}-%{release}
+Summary:   The GNU Multiple-precision Floating-point computations with correct 
Rounding Library (MPFR)
+   v%{mpfr_version} for target %{_target} on host %{_host}
+Version:   %{mpfr_version}
+Release:   %{release}
+URL:  https://www.mpfr.org/
+
+#
+# Source
+#
+%source set mpfr 
https://www.mpfr.org/mpfr-%{mpfr_version}/mpfr-%{mpfr_version}.tar.bz2
+
+#
+# Prepare the source code.
+#
+%prep
+  build_top=$(pwd)
+
+  %source setup mpfr -q -n mpfr-%{mpfr_version}
+  %patch setup mpfr -p1
+
+  cd ${build_top}
+
+%build
+  build_top=$(pwd)
+
+  cd mpfr-%{mpfr_version}
+
+  %{host_build_flags}
+
+  ./configure \
+--build=%{_build} --host=%{_host} \
+--verbose \
+--prefix=%{_prefix} --bindir=%{_bindir} \
+--exec-prefix=%{_exec_prefix} \
+--includedir=%{_includedir} --libdir=%{_libdir} \
+--mandir=%{_mandir} --infodir=%{_infodir} \
+--disable-shared
+
+  %{__make} %{?_smp_mflags} all
+
+  cd ${build_top}
+
+%install
+  build_top=$(pwd)
+
+  rm -rf $SB_BUILD_ROOT
+
+  cd mpfr-%{mpfr_version}
+  %{__make} DESTDIR=$SB_BUILD_ROOT install
+
+  cd ${build_top}
-- 
2.37.1

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[PATCH 8/8] rtems/microblaze: Update to GDB 13.1

2023-04-04 Thread chrisj 
From: Chris Johns 

Note:
 GCC does not build on MacOS 13.3 due to the specific version
 of GCC the Microblaze is using.

Updates #4892
---
 rtems/config/6/rtems-microblaze.bset | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rtems/config/6/rtems-microblaze.bset 
b/rtems/config/6/rtems-microblaze.bset
index e05fd7b..95fe17e 100644
--- a/rtems/config/6/rtems-microblaze.bset
+++ b/rtems/config/6/rtems-microblaze.bset
@@ -13,7 +13,7 @@
 
 devel/expat-2.4.8-1
 devel/gmp-6.2.1
-tools/rtems-gdb-12.1
+tools/rtems-gdb-13.1
 
 tools/rtems-xilinx-binutils-2.36
 tools/rtems-xilinx-gcc-10-newlib-head
-- 
2.37.1

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Re: [PATCH rtems-lwip] rtemslwip/xil_shims: Perform flush with invalidate

2023-04-04 Thread Chris Johns 
On 4/4/2023 10:23 pm, Kinsey Moore wrote:
> On Mon, Apr 3, 2023 at 8:00 PM Chris Johns  > wrote:
> 
> On 31/3/2023 8:13 am, Kinsey Moore wrote:
> > Xilinx wrote their A53 HAL with the assumption that the CPU did not
> > support cache invalidation without a flush, so the flush and
> > invalidation functions were combined and all range invalidations are
> > promoted to flush/invalidate. The implementation written for lwIP was
> > written to the original intent of the function and thus was not flushing
> > in some cases when it needed to. This resolves that issue which prevents
> > DMA transmit errors in some cases.
> > ---
> >  rtemslwip/zynqmp/xil_shims.c | 7 ++-
> >  1 file changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/rtemslwip/zynqmp/xil_shims.c b/rtemslwip/zynqmp/xil_shims.c
> > index 2eda0c5..1b1b3cf 100644
> > --- a/rtemslwip/zynqmp/xil_shims.c
> > +++ b/rtemslwip/zynqmp/xil_shims.c
> > @@ -102,7 +102,12 @@ void XScuGic_DisableIntr ( u32 DistBaseAddress, u32
> Int_Id )
> >    rtems_interrupt_vector_disable( Int_Id );
> >  }
> > 
> > +/*
> > + * The Xilinx code was written such that it assumed there was no
> invalidate-only
> > + * functionality on A53 cores. This function must flush and invalidate
> because
> > + * of how they mapped things.
> > + */
> >  void Xil_DCacheInvalidateRange( INTPTR adr, INTPTR len )
> >  {
> > -  rtems_cache_invalidate_multiple_data_lines( (const void *) adr, len 
> );
> > +  rtems_cache_flush_multiple_data_lines( (const void *) adr, len );
> >  }
> 
> Does the Xilinx code use Xil_DCacheInvalidateRange in any DMA receive 
> paths? If
> it does is this change correct as the invalidate has been removed?
> 
> 
> It just so happens that the way the code was written, a flush and invalidate
> works fine for the receive path. The invalidation that occurs in the receive
> path occurs before the pointer to the memory is passed to the DMA engine, so a
> flush there doesn't hurt anything (at least for this particular driver). If 
> more
> Xilinx drivers get pulled in, that may have to be reevaluated.

Sure. If you think it is fine and are happy that is all that is need.

Chris
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Re: [PATCH 2/2] cpukit/libdl: Resolve size mismatch warnings

2023-04-04 Thread Chris Johns 
OK to the libdl patch

Chris

On 5/4/2023 7:33 am, Kinsey Moore wrote:
> Resolve warnings about mismatched pointer and integer sizes in AArch64
> libdl when building with the ILP32 ABI.
> ---
>  cpukit/libdl/rtl-elf.c |  4 ++--
>  cpukit/libdl/rtl-mdreloc-aarch64.c | 31 +++---
>  cpukit/libdl/rtl-rap.c |  4 ++--
>  3 files changed, 20 insertions(+), 19 deletions(-)
> 
> diff --git a/cpukit/libdl/rtl-elf.c b/cpukit/libdl/rtl-elf.c
> index 8a21c5df73..5754070518 100644
> --- a/cpukit/libdl/rtl-elf.c
> +++ b/cpukit/libdl/rtl-elf.c
> @@ -192,7 +192,7 @@ rtems_rtl_elf_find_symbol (rtems_rtl_obj*  obj,
>  if (!*symbol)
>return false;
>  
> -*value = (Elf_Addr) (*symbol)->value;
> +*value = (Elf_Addr)(uintptr_t) (*symbol)->value;
>  return true;
>}
>  
> @@ -202,7 +202,7 @@ rtems_rtl_elf_find_symbol (rtems_rtl_obj*  obj,
>if (!sect)
>  return false;
>  
> -  *value = sym->st_value + (Elf_Addr) sect->base;
> +  *value = sym->st_value + (Elf_Addr)(uintptr_t) sect->base;
>  
>return true;
>  }
> diff --git a/cpukit/libdl/rtl-mdreloc-aarch64.c 
> b/cpukit/libdl/rtl-mdreloc-aarch64.c
> index e44238e636..25057ce9d7 100644
> --- a/cpukit/libdl/rtl-mdreloc-aarch64.c
> +++ b/cpukit/libdl/rtl-mdreloc-aarch64.c
> @@ -107,7 +107,7 @@ checkoverflow(Elf_Addr addr, int bitwidth, Elf_Addr 
> targetaddr,
>const Elf_Addr mask = ~__BITS(bitwidth - 1, 0);
>  
>if (((addr & mask) != 0) && ((addr & mask) != mask)) {
> -printf("kobj_reloc: Relocation 0x%jx too far from %p"
> +printf("kobj_reloc: Relocation 0x%" PRIxPTR " too far from %p"
>  " (base+0x%jx) for %dbit%s\n",
>  (uintptr_t)targetaddr, where, off, bitwidth, bitscale);
>  return true;
> @@ -120,7 +120,7 @@ static inline bool
>  checkalign(Elf_Addr addr, int alignbyte, void *where, Elf64_Addr off)
>  {
>if ((addr & (alignbyte - 1)) != 0) {
> -printf("kobj_reloc: Relocation 0x%jx unaligned at %p"
> +printf("kobj_reloc: Relocation 0x%" PRIxPTR " unaligned at %p"
>  " (base+0x%jx). must be aligned %d\n",
>  (uintptr_t)addr, where, off, alignbyte);
>  return true;
> @@ -257,7 +257,7 @@ rtems_rtl_elf_reloc_rela (rtems_rtl_obj*obj,
>  
>  if (rtems_rtl_trace (RTEMS_RTL_TRACE_RELOC))
>printf ("rtl: reloc 64/GLOB_DAT in %s --> %p in %s\n",
> -  sect->name, (void *)*where,
> +  sect->name, (void *)(uintptr_t)*where,
>rtems_rtl_obj_oname (obj));
>}
>break;
> @@ -270,10 +270,10 @@ rtems_rtl_elf_reloc_rela (rtems_rtl_obj*obj,
>   */
>  case R_TYPE(RELATIVE):  /* Delta(S) + A */
>if (!parsing) {
> -*where = (Elf_Addr)(sect->base + rela->r_addend);
> +*where = (Elf_Addr)(uintptr_t)(sect->base + rela->r_addend);
>  if (rtems_rtl_trace (RTEMS_RTL_TRACE_RELOC))
>printf ("rtl: reloc RELATIVE in %s --> %p in %s\n",
> -  sect->name, (void *)*where,
> +  sect->name, (void *)(uintptr_t)*where,
>rtems_rtl_obj_oname (obj));
>}
>break;
> @@ -304,7 +304,7 @@ rtems_rtl_elf_reloc_rela (rtems_rtl_obj*obj,
>shift = 12;
>break;
>  default:
> -  printf("illegal rtype: %ld\n", ELF_R_TYPE(rela->r_info));
> +  printf("illegal rtype: %" PRIu64 "\n", ELF_R_TYPE(rela->r_info));
>break;
>}
>  
> @@ -344,7 +344,7 @@ rtems_rtl_elf_reloc_rela (rtems_rtl_obj*obj,
>shift = 3;
>break;
>  default:
> -  printf("illegal rtype: %ld\n", ELF_R_TYPE(rela->r_info));
> +  printf("illegal rtype: %" PRIu64 "\n", ELF_R_TYPE(rela->r_info));
>break;
>}
>  
> @@ -360,9 +360,9 @@ rtems_rtl_elf_reloc_rela (rtems_rtl_obj*obj,
>  target = (Elf_Addr)symvalue + rela->r_addend;
>  if (checkalign(target, 1 << shift, where, off)) {
>printf ("rtl: reloc checkalign failed in %s --> %p in %s\n",
> -  sect->name, (void *)*where,
> +  sect->name, (void *)(uintptr_t)*where,
>rtems_rtl_obj_oname (obj));
> -  printf("ELF_R_TYPE is : %ld\n", ELF_R_TYPE(rela->r_info));
> +  printf("ELF_R_TYPE is : %" PRIu64 "\n", ELF_R_TYPE(rela->r_info));
>break;
>  }
>  target &= WIDTHMASK(12);
> @@ -433,7 +433,7 @@ rtems_rtl_elf_reloc_rela (rtems_rtl_obj*obj,
>return rtems_rtl_elf_rel_failure;
>  }
>  
> -tramp_addr = ((Elf_Addr) obj->tramp_brk) | (symvalue & 1);
> +tramp_addr = ((Elf_Addr)(uintptr_t)obj->tramp_brk) | (symvalue & 1);
>  obj->tramp_brk = set_veneer(obj->tramp_brk, symvalue);
>  
>  target = tramp_addr + rela->r_addend - (uintptr_t)where;
> @@ -468,29 +468,30 @@ rtems_rtl_elf_reloc_rela (rtems_rtl_obj*

[PATCH] bsps/mvme2700: Add MVME2700 BSP

2023-04-04 Thread chrisj 
From: Chris Johns 

---
 bsps/powerpc/motorola_powerpc/include/bsp.h   |  8 
 .../bsps/powerpc/motorola_powerpc/abi.yml |  2 +-
 .../powerpc/motorola_powerpc/bspmvme2700.yml  | 19 +++
 3 files changed, 24 insertions(+), 5 deletions(-)
 create mode 100644 spec/build/bsps/powerpc/motorola_powerpc/bspmvme2700.yml

diff --git a/bsps/powerpc/motorola_powerpc/include/bsp.h 
b/bsps/powerpc/motorola_powerpc/include/bsp.h
index 1c35d8e1b7..db0995fa5c 100644
--- a/bsps/powerpc/motorola_powerpc/include/bsp.h
+++ b/bsps/powerpc/motorola_powerpc/include/bsp.h
@@ -50,8 +50,8 @@ extern "C" {
  * _VME_A32_WIN0_ON_VME: VME address of that same window
  *
  * AFAIK, only PreP boards have a non-zero PCI_MEM_BASE (i.e., an offset 
between
- * CPU and PCI addresses). The mvme2300 'ppcbug' firmware configures the PCI
- * bus using PCI base addresses! I.e., drivers need to add PCI_MEM_BASE to
+ * CPU and PCI addresses). The mvme2307/mvme2700 'ppcbug' firmware configures 
the
+ * PCI bus using PCI base addresses! I.e., drivers need to add PCI_MEM_BASE to
  * the base address read from PCI config.space in order to translate that
  * into a CPU address.
  *
@@ -169,7 +169,7 @@ extern "C" {
 #define BSP_VGA_IOBASE   ((_IO_BASE)+0x3c0)
 #endif
 
-#if defined(mvme2300)
+#if defined(mvme2300) || defined(mvme2307) || defined(mvme2700)
 #define MVME_HAS_DEC21140
 #endif
 #endif
@@ -271,7 +271,7 @@ extern int BSP_connect_clock_handler (void);
  *   It returns and clears the error bits of the PCI status register.
  *   MCP support is disabled because:
  * a) the 2100 has no raven chip
- * b) the raven (2300) would raise machine check interrupts
+ * b) the raven (2300, 2307, 2700) would raise machine check interrupts
  *on PCI config space access to empty slots.
  */
 extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet);
diff --git a/spec/build/bsps/powerpc/motorola_powerpc/abi.yml 
b/spec/build/bsps/powerpc/motorola_powerpc/abi.yml
index 94ac120f77..3965822a47 100644
--- a/spec/build/bsps/powerpc/motorola_powerpc/abi.yml
+++ b/spec/build/bsps/powerpc/motorola_powerpc/abi.yml
@@ -17,7 +17,7 @@ default:
   - -mcpu=powerpc
   - -mmultiple
   - -mstrict-align
-- enabled-by: powerpc/mvme2307
+- enabled-by: [powerpc/mvme2307, powerpc/mvme2700]
   value:
   - -mcpu=604
   - -mmultiple
diff --git a/spec/build/bsps/powerpc/motorola_powerpc/bspmvme2700.yml 
b/spec/build/bsps/powerpc/motorola_powerpc/bspmvme2700.yml
new file mode 100644
index 00..f880848926
--- /dev/null
+++ b/spec/build/bsps/powerpc/motorola_powerpc/bspmvme2700.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: powerpc
+bsp: mvme2700
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2023 Chris Johns
+cppflags: []
+enabled-by: true
+family: motorola_powerpc
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: ../../opto2
+- role: build-dependency
+  uid: grp
+source: []
+type: build
-- 
2.37.1

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powerpc/motorola_powerpc: Add MVME2700 BSP

2023-04-04 Thread chrisj 
Hi,

The MVME2700 can run the MVME2307 BSP. It is confusing in 
EPICS to have the MVME2700 referencing the mvme2307 BSP.
This patch adds the BSP powerpc/mvme2700.

The bsp.h header for the motorola_powerpc family needs the
RTEMS_BSP device to control the legacy network stack's
interface and attach defines. The rtems-net-legacy repo
needs those defines to build and run tests. The patch adds
the required defines for the mvme2307 and mvme2700.

Chris



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