bsps/riscv: interrupt number mismatch
Hi, The interrupt number(vector) mention in the device tree node is working when the driver is used the RISCV_INTERRUPT_VECTOR_EXTERNAL() and later called the RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX() in the RTEMS but the interrupt number is decreased by 2 when registering the interrupt from the RTEMS-LIBBSD driver(ex: Cadence GEM). The RTEMS-LIBBSD doesn't call the RISCV_INTERRUPT_VECTOR_EXTERNAL() but called the RISCV_INTERRU PT_VECTOR_EXTERNAL_TO_INDEX() for interrupt enable. In "bsps/riscv/riscv/include/bsp/irq.h" #define RISCV_INTERRUPT_VECTOR_EXTERNAL(x) ((x) + 2) #define RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(x) ((x) >= 2) #define RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(x) ((x) - 2) Can we create a config file for non-external interrupt vector index instead of '2'? like '2' for RISC-V GENERIC and '0' for PolarFire SoC. Regards Padmarao ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: bsps/riscv: interrupt number mismatch
On 21/11/2022 10:50, padmarao.beg...@microchip.com wrote: The interrupt number(vector) mention in the device tree node is working when the driver is used the RISCV_INTERRUPT_VECTOR_EXTERNAL() and later called the RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX() in the RTEMS but the interrupt number is decreased by 2 when registering the interrupt from the RTEMS-LIBBSD driver(ex: Cadence GEM). The RTEMS-LIBBSD doesn't call the RISCV_INTERRUPT_VECTOR_EXTERNAL() but called the RISCV_INTERRU PT_VECTOR_EXTERNAL_TO_INDEX() for interrupt enable. In "bsps/riscv/riscv/include/bsp/irq.h" #define RISCV_INTERRUPT_VECTOR_EXTERNAL(x) ((x) + 2) #define RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(x) ((x) >= 2) #define RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(x) ((x) - 2) Can we create a config file for non-external interrupt vector index instead of '2'? like '2' for RISC-V GENERIC and '0' for PolarFire SoC. To which number would you map the software and timer interrupts? Can't this off by two problem be fixed by bsp_fdt_map_intr()? -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: bsps/riscv: interrupt number mismatch
Hi Sebastian, > On Mon, 2022-11-21 at 10:53 +0100, Sebastian Huber wrote: > > On 21/11/2022 10:50, padmarao.beg...@microchip.com wrote: > > The interrupt number(vector) mention in the device tree node is > > working > > when the driver is used the RISCV_INTERRUPT_VECTOR_EXTERNAL() and > > later > > called the RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX() in the RTEMS > > but > > the interrupt number is decreased by 2 when registering the > > interrupt > > from the RTEMS-LIBBSD driver(ex: Cadence GEM). The RTEMS-LIBBSD > > doesn't > > call the RISCV_INTERRUPT_VECTOR_EXTERNAL() but called the > > RISCV_INTERRU > > PT_VECTOR_EXTERNAL_TO_INDEX() for interrupt enable. > > > > In "bsps/riscv/riscv/include/bsp/irq.h" > > > > #define RISCV_INTERRUPT_VECTOR_EXTERNAL(x) ((x) + 2) > > > > #define RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(x) ((x) >= 2) > > > > #define RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(x) ((x) - 2) > > > > Can we create a config file for non-external interrupt vector index > > instead of '2'? > > > > like '2' for RISC-V GENERIC and '0' for PolarFire SoC. > > To which number would you map the software and timer interrupts? > The Software and Timer interrupts(numbers 0 & 1) are mapped by the Machine cause register (mcause) and enabled by the CLINT but not by the PLIC. > Can't this off by two problem be fixed by bsp_fdt_map_intr()? will check this option. Regards Padmarao > -- > embedded brains GmbH > Herr Sebastian HUBER > Dornierstr. 4 > 82178 Puchheim > Germany > email: sebastian.hu...@embedded-brains.de > phone: +49-89-18 94 741 - 16 > fax: +49-89-18 94 741 - 08 > > Registergericht: Amtsgericht München > Registernummer: HRB 157899 > Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas > Dörfler > Unsere Datenschutzerklärung finden Sie hier: > https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: bsps/riscv: interrupt number mismatch
On 21/11/2022 11:17, padmarao.beg...@microchip.com wrote: To which number would you map the software and timer interrupts? The Software and Timer interrupts(numbers 0 & 1) are mapped by the Machine cause register (mcause) and enabled by the CLINT but not by the PLIC. Yes, this is the problem. We need an interrupt vector number for all interrupts (PLIC and CLINT). -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH] aarch64/versal: Add UART interrupt support
From: Chris Johns
---
.../dev/serial/versal-uart-polled.c | 37 --
.../xilinx-versal/dev/serial/versal-uart.c| 330 ++
.../include/dev/serial/versal-uart-regs.h | 1 -
.../include/dev/serial/versal-uart.h | 5 +-
spec/build/bsps/aarch64/xilinx-versal/grp.yml | 2 +
spec/build/bsps/aarch64/xilinx-versal/obj.yml | 1 +
6 files changed, 337 insertions(+), 39 deletions(-)
create mode 100644 bsps/aarch64/xilinx-versal/dev/serial/versal-uart.c
diff --git a/bsps/aarch64/xilinx-versal/dev/serial/versal-uart-polled.c
b/bsps/aarch64/xilinx-versal/dev/serial/versal-uart-polled.c
index 83493db909..9453dc248b 100644
--- a/bsps/aarch64/xilinx-versal/dev/serial/versal-uart-polled.c
+++ b/bsps/aarch64/xilinx-versal/dev/serial/versal-uart-polled.c
@@ -152,23 +152,6 @@ int versal_uart_initialize(rtems_termios_device_context
*base)
return 0;
}
-static bool versal_uart_first_open(
- struct rtems_termios_tty *tty,
- rtems_termios_device_context *base,
- struct termios *term,
- rtems_libio_open_close_args_t *args
-)
-{
- int rc = versal_uart_initialize(base);
- if ( rc < 0 ) {
-return false;
- }
-
- rtems_termios_set_initial_baud(tty, VERSAL_UART_DEFAULT_BAUD);
-
- return true;
-}
-
int versal_uart_read_polled(rtems_termios_device_context *base)
{
volatile versal_uart *regs = versal_uart_get_regs(base);
@@ -209,23 +192,3 @@ void
versal_uart_reset_tx_flush(rtems_termios_device_context *base)
/* Wait for empty */
}
}
-
-static void versal_uart_write_support(
- rtems_termios_device_context *base,
- const char *s,
- size_t n
-)
-{
- size_t i;
-
- for (i = 0; i < n; i++) {
-versal_uart_write_polled(base, s[i]);
- }
-}
-
-const rtems_termios_device_handler versal_uart_handler = {
- .first_open = versal_uart_first_open,
- .write = versal_uart_write_support,
- .poll_read = versal_uart_read_polled,
- .mode = TERMIOS_POLLED
-};
diff --git a/bsps/aarch64/xilinx-versal/dev/serial/versal-uart.c
b/bsps/aarch64/xilinx-versal/dev/serial/versal-uart.c
new file mode 100644
index 00..7076452588
--- /dev/null
+++ b/bsps/aarch64/xilinx-versal/dev/serial/versal-uart.c
@@ -0,0 +1,330 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2022 Chris Johns
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+#include
+
+#include
+
+#ifdef VERSAL_CONSOLE_USE_INTERRUPTS
+static uint32_t versal_uart_intr_all(void)
+{
+ return VERSAL_UARTI_OEI |
+VERSAL_UARTI_BEI |
+VERSAL_UARTI_PEI |
+VERSAL_UARTI_FEI |
+VERSAL_UARTI_RTI |
+VERSAL_UARTI_TXI |
+VERSAL_UARTI_RXI |
+VERSAL_UARTI_DSRMI |
+VERSAL_UARTI_DCDMI |
+VERSAL_UARTI_CTSMI |
+VERSAL_UARTI_RIMI;
+}
+
+static void versal_uart_intr_clear(volatile versal_uart *regs, uint32_t ints)
+{
+ regs->uarticr = ints;
+}
+
+static void versal_uart_intr_clearall(volatile versal_uart *regs)
+{
+ versal_uart_intr_clear(regs, versal_uart_intr_all());
+}
+
+static void versal_uart_intr_enable(volatile versal_uart *regs, uint32_t ints)
+{
+ regs->uartimsc |= ints;
+}
+
+static void versal_uart_intr_disable(volatile versal_uart *regs, uint32_t ints)
+{
+ regs->uartimsc &= ~ints;
+}
+
+static void versal_uart_intr_disableall(volatile versal_uart *regs)
+{
+ versal_uart_intr_disable(regs, versal_uart_intr_all());
+}
+
+static bool versal_uart_flags_clear(volatile versal_uart *regs, uint32_t flags)
+{
+ return (regs->uartfr & flags) == 0;
+}
+
+static void versal_uart_interrupt(void *arg)
+{
+ rtems_termios_tty *tty = arg;
+ versal_uart_context *ctx = rtems_termios_get_device_context(tty);
+ volatile versal_uart *regs = ctx->regs;
+ uint32_t uartmis = regs->uartmis;
+
Re: [PATCH] aarch64/versal: Add UART interrupt support
Hello Chris,
On 22/11/2022 03:03, chr...@rtems.org wrote:
+static void versal_uart_write_support(
+ rtems_termios_device_context *base,
+ const char *buf,
+ size_t len
+)
+{
+#ifdef VERSAL_CONSOLE_USE_INTERRUPTS
+ versal_uart_context *ctx = (versal_uart_context *) base;
+ volatile versal_uart *regs = ctx->regs;
+
+ if (len > 0) {
+rtems_interrupt_lock_context lock_context;
+size_t len_remaining = len;
+const char *p = &buf[0];
+rtems_interrupt_lock_acquire(&ctx->interrupt_lock, &lock_context);
you don't need an extra interrupt lock. The rtems_termios_device_context
already contains an interrupt lock, see
rtems_termios_device_lock_acquire(). This lock is held while the write
support handler is called.
--
embedded brains GmbH
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
Unsere Datenschutzerklärung finden Sie hier:
https://embedded-brains.de/datenschutzerklaerung/
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