Re: [rtems-test] riscv/griscv: RTEMS_POSIX_API: Passed:597 Failed:7 Timeout:0 Test-Too-long:0 Invalid:0 Wrong:0

[Sebastian Huber]

On 19/09/2022 18:39, OAR Tester wrote:

] test SHA512-224
] 4634270f707b6a54 daae7530460842e2 0e37ed265ceee9a4 2fa08086
] ../../../testsuites/libtests/sha/init.c: 356 memcmp(&r[0], 
&test_sha512_224_results[i][0], sizeof(r)) == 0


This is an interesting failure. It could be a GCC or SIS bug.

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[PATCH] bsps/arm: Fix start in hypervisor mode

[Sebastian Huber]

Only clear the HSCTLR[TE] bit to take exceptions in A32 state.  Keep the
other HSCTLR bits as is since they control the current execution.
Assume that the chip or boot loader did initialize this register
correctly.

Add comments.
---
 bsps/arm/shared/start/start.S | 21 -
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/bsps/arm/shared/start/start.S b/bsps/arm/shared/start/start.S
index 32b168917a..c7fad5ae58 100644
--- a/bsps/arm/shared/start/start.S
+++ b/bsps/arm/shared/start/start.S
@@ -249,22 +249,25 @@ _start:
mov sp, r3
sub r3, r3, r1
 
+   /* Set HVBAR */
ldr r0, =bsp_start_hyp_vector_table_begin
mcr p15, 4, r0, c12, c0, 0
 
+   /* Set HVC, HCPTR, and HSTR to zero */
mov r0, #0
mcr p15, 4, r0, c1, c1, 0
mcr p15, 4, r0, c1, c1, 2
mcr p15, 4, r0, c1, c1, 3
-/*
- * HSCTLR.TE
- * optional start of hypervisor handlers in Thumb mode
- * orr r0, #(1 << 30)
- */
-   mcr p15, 4, r0, c1, c0, 0   /* HSCTLR */
-   mrc p15, 4, r0, c1, c1, 1   /* HDCR */
-   and r0, #0x1f   /* Preserve HPMN */
-   mcr p15, 4, r0, c1, c1, 1   /* HDCR */
+
+   /* Clear HSCTLR[TE] to take exceptions in A32 state */
+   mrc p15, 4, r0, c1, c0, 0
+   bic r0, #(1 << 30)
+   mcr p15, 4, r0, c1, c0, 0
+
+   /* Set HDCR to zero except HDCR[HPMN] */
+   mrc p15, 4, r0, c1, c1, 1
+   and r0, #0x1f
+   mcr p15, 4, r0, c1, c1, 1
 
/* Prepare SVC mode for eret */
mrs r0, cpsr
-- 
2.35.3

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Re: [PATCH v2 0/4] Microchip PolarFire SoC support

[Joel Sherrill]

This procedure should be added to the Users Guide under the BSPs section.

Otherwise, it looks like I should coordinate with Padmarao to make sure
it's ok after I merged it

On Tue, Sep 20, 2022, 1:50 AM  wrote:

> RTEMS SMP on the Microchip PolarFire Icicle Kit
>
> Test Procedure:
>
> 1. Create the "config.ini" file with below content at rtems root
>
> [riscv/mpfs64imafdc]
> BUILD_TESTS = True
> RTEMS_POSIX_API=True
> RTEMS_SMP = True
> BSP_START_COPY_FDT_FROM_U_BOOT=False
> BSP_VERBOSE_FATAL_EXTENSION = False
>
> 2. Build RTEMS
> $ ./waf configure --prefix=$HOME/rtems-start/rtems/6
> $ ./waf
>
> 3. Convert .exe to .elf file
>
> $ riscv-rtems6-objcopy  build/riscv/mpfs64imafdc/testsuites/smptests/sm
> p01.exe
>  build/riscv/mpfs64imafdc/testsuites/smptests/smp01.elf
>
> 4. Generate the payload for the smp01.elf using the hss-payload-
> generator with hart-entry-points/exec-addr: 0x10
>
>
> https://github.com/polarfire-soc/hart-software-services/tree/master/tools/hss-payload-generator
>
> 5. Programming the'payload.bin' for the eMMC/SD
>
>  5.1) Board setting and FPGA Programing
>
>
> https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md
>
>
>  5.2). Power Cycle the Microchip PolarFire Icicle Kit and stop at the
>HSS.
>
>  5.3) type "mmc" and then "usbdmsc" on the HSS terminal(UART0).
>
>  5.4) Load payload from the Host PC.
> $ sudo dd if=payload.bin of=/dev/sdb bs=512
>
>  5.5) Quit USB and Reset the Icicle Kit
>
>  5.6) Serial terminal UART1 displays the SMP example messages
>
> *** BEGIN OF TEST SMP 1 ***
> *** TEST VERSION: 6.0.0.ef33f861e16de9bf4190a36e4d18062c7300986c
> *** TEST STATE: EXPECTED_PASS
> *** TEST BUILD: RTEMS_POSIX_API RTEMS_SMP
> *** TEST TOOLS: 12.1.1 20220622 (RTEMS 6, RSB 3cb78b0b815ba05d17f5c6
> 5865d246a8333aa087, Newlib ea99f21)
>
> CPU 3 start task TA0
> CPU 2 running Task TA0
> CPU 3 start task TA1
> CPU 1 running Task TA1
> CPU 3 start task TA2
> CPU 0 running Task TA2
>
> *** END OF TEST SMP 1 ***
>
> Regards
> Padmarao
> On Mon, 2022-09-19 at 18:30 +0530, Padmarao Begari wrote:
> > This patch set adds the Microchip PolarFire SoC BSP Variant
> > support to RISC-V RTEMS.
> >
> > The PolarFire SoC is the 4x 64-bit RISC-V U54 cores and
> > a 64-bit RISC-V E51 monitor core SoC from Microchip, more
> > info available here:
> >   https://www.microchip.com/en-us/products/fpgas-and-plds/
> >   system-on-chip-fpgas/polarfire-soc-fpgas#Overview
> >
> > This new BSP variant is added for the 4x U54 cores not for E51
> > because the E51 monitor core is resreved for first stage
> > bootloader (Hart Software Services).
> >
> > The boot HARTID configurable is implemented for the riscv BSP
> > to work with individual hart(cpu core) or SMP.
> >
> > This BSP support components: 4 CPU Cores (U54), Interrupt
> > controller (PLIC), Timer (CLINT), UART (16550-compatible)
> > work fine on actual Microchip PolarFire SoC Icicle Kit.
> >
> > v2:
> > - Add a license and copyright information in dtb header file
> > - Use RISCV_BOOT_HARDID instead of RTEMS_BOOT_HARDID
> > - Add '_RISCV_Map_hardid_to_cpu_index()' and
> > '_RISCV_Map_cpu_index_to_hardid()' functions
> > - Change bsp_fdt_get() instead of bsp_fdt_copy() function for dtb
> > - Move dtb and dtb header configurable build option to the bsps
> >
> > Padmarao Begari (4):
> >   bsps/riscv: Add device tree blob
> >   spec/build/bsps: Add dtb support
> >   bsps/riscv: Add Microchip PolarFire SoC BSP variant
> >   bsps/shared/: Use device tree blob
> >
> >  bsps/riscv/riscv/clock/clockdrv.c |   6 +-
> >  bsps/riscv/riscv/config/mpfs64imafdc.cfg  |   9 +
> >  bsps/riscv/riscv/dts/mpfs.dts | 365 +++
> >  bsps/riscv/riscv/include/bsp/mpfs-dtb.h   | 602
> > ++
> >  bsps/riscv/riscv/include/bsp/riscv.h  |  14 +
> >  bsps/riscv/riscv/irq/irq.c|  81 +++
> >  bsps/riscv/riscv/start/bsp_fatal_halt.c   |   3 +
> >  bsps/riscv/riscv/start/bspsmp.c   |   2 +-
> >  bsps/riscv/riscv/start/bspstart.c |  19 +-
> >  bsps/riscv/shared/start/start.S   |   2 +
> >  bsps/shared/start/bsp-fdt.c   |   8 +
> >  .../score/cpu/riscv/include/rtems/score/cpu.h |   2 +-
> >  .../cpu/riscv/include/rtems/score/cpuimpl.h   |   2 +-
> >  spec/build/bsps/optdtb.yml|  19 +
> >  spec/build/bsps/optdtbheaderpath.yml  |  20 +
> >  spec/build/bsps/riscv/optextirqmax.yml|   5 +-
> >  spec/build/bsps/riscv/optrambegin.yml |   5 +-
> >  spec/build/bsps/riscv/optramsize.yml  |   5 +-
> >  spec/build/bsps/riscv/riscv/abi.yml   |   6 +
> >  .../bsps/riscv/riscv/bspmpfs64imafdc.yml  |  19 +
> >  spec/build/bsps/riscv/riscv/grp.yml   |   6 +
> >  spec/build/bsps/riscv/risc

Re: Successful Hello world from RPi4B AArch64 over serial

[Noor Aman]

>
>
> Try the fileio, cdtest, nsecs, and paranoia samples next. If those
> look ok, it is highly likely that most of the single processor tests
> will run.
>
> fileio requires working console input.
>

I've tried them all, they look pretty fine. Fileio worked fine too.

Now work to get this all cleaned up, merged, and documented. Kinsey
> now has a Pi4 ready to double check your work is repeatable from
> rtems.org sources.
>

 Yeah, I'm on my way to create good looking patches for merge.

Are any other peripherals from previous Pi generations the same? Curious if
> wired networking might be low hanging fruit.
>

Wired networking is the least possible hanging fruit. Raspberry pi 3 uses
an "SMSC9512/9514 Fast Ethernet Adapter" which is connected through the
"SMC9514 Hub" USB controller. Whereas the raspberry pi 4 on the other hand
uses a "BCM54213PE" Ethernet controller which is directly connected through
the PCIe bridge.

But some of the same peripheral which are very likely to be same are GPIO,
UART using mini UART, SPI, I2C and Framebuffer
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Re: [PATCH v2 0/4] Microchip PolarFire SoC support

[Joel Sherrill]

I have pushed this patch set. Please check that the merge is OK and follow
up with an update to the Users Guide for those looking for this BSP.

Thanks.

On Tue, Sep 20, 2022 at 8:56 AM Joel Sherrill 
wrote:

> This procedure should be added to the Users Guide under the BSPs section.
>
> Otherwise, it looks like I should coordinate with Padmarao to make sure
> it's ok after I merged it
>
> On Tue, Sep 20, 2022, 1:50 AM  wrote:
>
>> RTEMS SMP on the Microchip PolarFire Icicle Kit
>>
>> Test Procedure:
>>
>> 1. Create the "config.ini" file with below content at rtems root
>>
>> [riscv/mpfs64imafdc]
>> BUILD_TESTS = True
>> RTEMS_POSIX_API=True
>> RTEMS_SMP = True
>> BSP_START_COPY_FDT_FROM_U_BOOT=False
>> BSP_VERBOSE_FATAL_EXTENSION = False
>>
>> 2. Build RTEMS
>> $ ./waf configure --prefix=$HOME/rtems-start/rtems/6
>> $ ./waf
>>
>> 3. Convert .exe to .elf file
>>
>> $ riscv-rtems6-objcopy  build/riscv/mpfs64imafdc/testsuites/smptests/sm
>> p01.exe
>>  build/riscv/mpfs64imafdc/testsuites/smptests/smp01.elf
>>
>> 4. Generate the payload for the smp01.elf using the hss-payload-
>> generator with hart-entry-points/exec-addr: 0x10
>>
>>
>> https://github.com/polarfire-soc/hart-software-services/tree/master/tools/hss-payload-generator
>>
>> 5. Programming the'payload.bin' for the eMMC/SD
>>
>>  5.1) Board setting and FPGA Programing
>>
>>
>> https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md
>>
>>
>>  5.2). Power Cycle the Microchip PolarFire Icicle Kit and stop at the
>>HSS.
>>
>>  5.3) type "mmc" and then "usbdmsc" on the HSS terminal(UART0).
>>
>>  5.4) Load payload from the Host PC.
>> $ sudo dd if=payload.bin of=/dev/sdb bs=512
>>
>>  5.5) Quit USB and Reset the Icicle Kit
>>
>>  5.6) Serial terminal UART1 displays the SMP example messages
>>
>> *** BEGIN OF TEST SMP 1 ***
>> *** TEST VERSION: 6.0.0.ef33f861e16de9bf4190a36e4d18062c7300986c
>> *** TEST STATE: EXPECTED_PASS
>> *** TEST BUILD: RTEMS_POSIX_API RTEMS_SMP
>> *** TEST TOOLS: 12.1.1 20220622 (RTEMS 6, RSB 3cb78b0b815ba05d17f5c6
>> 5865d246a8333aa087, Newlib ea99f21)
>>
>> CPU 3 start task TA0
>> CPU 2 running Task TA0
>> CPU 3 start task TA1
>> CPU 1 running Task TA1
>> CPU 3 start task TA2
>> CPU 0 running Task TA2
>>
>> *** END OF TEST SMP 1 ***
>>
>> Regards
>> Padmarao
>> On Mon, 2022-09-19 at 18:30 +0530, Padmarao Begari wrote:
>> > This patch set adds the Microchip PolarFire SoC BSP Variant
>> > support to RISC-V RTEMS.
>> >
>> > The PolarFire SoC is the 4x 64-bit RISC-V U54 cores and
>> > a 64-bit RISC-V E51 monitor core SoC from Microchip, more
>> > info available here:
>> >   https://www.microchip.com/en-us/products/fpgas-and-plds/
>> >   system-on-chip-fpgas/polarfire-soc-fpgas#Overview
>> >
>> > This new BSP variant is added for the 4x U54 cores not for E51
>> > because the E51 monitor core is resreved for first stage
>> > bootloader (Hart Software Services).
>> >
>> > The boot HARTID configurable is implemented for the riscv BSP
>> > to work with individual hart(cpu core) or SMP.
>> >
>> > This BSP support components: 4 CPU Cores (U54), Interrupt
>> > controller (PLIC), Timer (CLINT), UART (16550-compatible)
>> > work fine on actual Microchip PolarFire SoC Icicle Kit.
>> >
>> > v2:
>> > - Add a license and copyright information in dtb header file
>> > - Use RISCV_BOOT_HARDID instead of RTEMS_BOOT_HARDID
>> > - Add '_RISCV_Map_hardid_to_cpu_index()' and
>> > '_RISCV_Map_cpu_index_to_hardid()' functions
>> > - Change bsp_fdt_get() instead of bsp_fdt_copy() function for dtb
>> > - Move dtb and dtb header configurable build option to the bsps
>> >
>> > Padmarao Begari (4):
>> >   bsps/riscv: Add device tree blob
>> >   spec/build/bsps: Add dtb support
>> >   bsps/riscv: Add Microchip PolarFire SoC BSP variant
>> >   bsps/shared/: Use device tree blob
>> >
>> >  bsps/riscv/riscv/clock/clockdrv.c |   6 +-
>> >  bsps/riscv/riscv/config/mpfs64imafdc.cfg  |   9 +
>> >  bsps/riscv/riscv/dts/mpfs.dts | 365 +++
>> >  bsps/riscv/riscv/include/bsp/mpfs-dtb.h   | 602
>> > ++
>> >  bsps/riscv/riscv/include/bsp/riscv.h  |  14 +
>> >  bsps/riscv/riscv/irq/irq.c|  81 +++
>> >  bsps/riscv/riscv/start/bsp_fatal_halt.c   |   3 +
>> >  bsps/riscv/riscv/start/bspsmp.c   |   2 +-
>> >  bsps/riscv/riscv/start/bspstart.c |  19 +-
>> >  bsps/riscv/shared/start/start.S   |   2 +
>> >  bsps/shared/start/bsp-fdt.c   |   8 +
>> >  .../score/cpu/riscv/include/rtems/score/cpu.h |   2 +-
>> >  .../cpu/riscv/include/rtems/score/cpuimpl.h   |   2 +-
>> >  spec/build/bsps/optdtb.yml|  19 +
>> >  spec/build/bsps/optdtbheaderpath.yml  |  20 +
>> >  spec/build/bsps/riscv/optextirqmax.yml  

RE: libbsd fails to link on i386

[Jan.Sommer]

Hi Joel,



Sorry for the long delay.

I tried to reproduce the error locally. For me building rtems and rtems-libbsd 
master for pc386 and pc686 works.

I get some undefined references for the 6-freebsd-12 branch though.

Which branch of rtems-libbsd did you use?



Best regards,



Jan





From: devel  On Behalf Of jan.som...@dlr.de
Sent: Thursday, August 18, 2022 8:09 PM
To: j...@rtems.org; devel@rtems.org
Subject: RE: libbsd fails to link on i386



Hi Joel,



I remember I spent some time fiddling with the bus.h include order.

I can try to have a look at it some time next week.



Best regards,



Jan



From: devel <  devel-boun...@rtems.org> On 
Behalf Of Joel Sherrill
Sent: Wednesday, August 17, 2022 11:24 PM
To:   rtems-de...@rtems.org < 
 devel@rtems.org>
Subject: libbsd fails to link on i386



Hi



I think the wrong bus.h must be being included somewhere. These are static 
inline methods on the i386. Hopefully a simple patch for someone who knows 
what to do:



[1992/2039] Linking build/i386-rtems6-pc386-default/ftpd01.exe
/home/joel/rtems-work/tools/6/lib/gcc/i386-rtems6/12.1.1/../../../../i386-rtems6/bin/ld:
 
./libbsd.a(rtems-kernel-bus-dma.c.20.o): in function `_bsd_bus_dmamem_alloc':
/home/joel/rtems-work/rtems-libbsd/build/i386-rtems6-pc386-default/../../rtemsbsd/rtems/rtems-kernel-bus-dma.c:264:
 
undefined reference to `bsp_bus_space_write_1'
collect2: error: ld returned 1 exit status

/home/joel/rtems-work/tools/6/lib/gcc/i386-rtems6/12.1.1/../../../../i386-rtems6/bin/ld:
 
./libbsd.a(rtems-kernel-bus-dma.c.20.o): in function `_bsd_bus_dmamem_alloc':
/home/joel/rtems-work/rtems-libbsd/build/i386-rtems6-pc386-default/../../rtemsbsd/rtems/rtems-kernel-bus-dma.c:264:
 
undefined reference to `bsp_bus_space_write_1'
collect2: error: ld returned 1 exit status

/home/joel/rtems-work/tools/6/lib/gcc/i386-rtems6/12.1.1/../../../../i386-rtems6/bin/ld:
 
./libbsd.a(rtems-kernel-bus-dma.c.20.o): in function `_bsd_bus_dmamem_alloc':
/home/joel/rtems-work/rtems-libbsd/build/i386-rtems6-pc386-default/../../rtemsbsd/rtems/rtems-kernel-bus-dma.c:264:
 
undefined reference to `bsp_bus_space_write_1'
collect2: error: ld returned 1 exit status

/home/joel/rtems-work/tools/6/lib/gcc/i386-rtems6/12.1.1/../../../../i386-rtems6/bin/ld:
 
./libbsd.a(rtems-kernel-bus-dma.c.20.o): in function `_bsd_bus_dmamem_alloc':
/home/joel/rtems-work/rtems-libbsd/build/i386-rtems6-pc386-default/../../rtemsbsd/rtems/rtems-kernel-bus-dma.c:264:
 
undefined reference to `bsp_bus_space_write_1'
collect2: error: ld returned 1 exit status

/home/joel/rtems-work/tools/6/lib/gcc/i386-rtems6/12.1.1/../../../../i386-rtems6/bin/ld:
 
./libbsd.a(rtems-kernel-bus-dma.c.20.o): in function `_bsd_bus_dmamem_alloc':
/home/joel/rtems-work/rtems-libbsd/build/i386-rtems6-pc386-default/../../rtemsbsd/rtems/rtems-kernel-bus-dma.c:264:
 
undefined reference to `bsp_bus_space_write_1'
collect2: error: ld returned 1 exit status

/home/joel/rtems-work/tools/6/lib/gcc/i386-rtems6/12.1.1/../../../../i386-rtems6/bin/ld:
 
./libbsd.a(rtems-kernel-bus-dma.c.20.o): in function `_bsd_bus_dmamem_alloc':
/home/joel/rtems-work/rtems-libbsd/build/i386-rtems6-pc386-default/../../rtemsbsd/rtems/rtems-kernel-bus-dma.c:264:
 
undefined reference to `bsp_bus_space_write_1'
collect2: error: ld returned 1 exit status

/home/joel/rtems-work/tools/6/lib/gcc/i386-rtems6/12.1.1/../../../../i386-rtems6/bin/ld:
 
./libbsd.a(rtems-kernel-bus-dma.c.20.o): in function `_bsd_bus_dmamem_alloc':
/home/joel/rtems-work/rtems-libbsd/build/i386-rtems6-pc386-default/../../rtemsbsd/rtems/rtems-kernel-bus-dma.c:264:
 
undefined reference to `bsp_bus_space_write_1'
collect2: error: ld returned 1 exit status

/home/joel/rtems-work/tools/6/lib/gcc/i386-rtems6/12.1.1/../../../../i386-rtems6/bin/ld:
 
./libbsd.a(rtems-kernel-bus-dma.c.20.o): in function `_bsd_bus_dmamem_alloc':
/home/joel/rtems-work/rtems-libbsd/build/i386-rtems6-pc386-default/../../rtemsbsd/rtems/rtems-kernel-bus-dma.c:264:
 
undefined reference to `bsp_bus_space_write_1'
collect2: error: ld returned 1 exit status



smime.p7s
Description: S/MIME cryptographic signature
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Re: libbsd fails to link on i386

[Joel Sherrill]

On Tue, Sep 20, 2022 at 12:43 PM  wrote:

> Hi Joel,
>
>
>
> Sorry for the long delay.
>
> I tried to reproduce the error locally. For me building rtems and
> rtems-libbsd master for pc386 and pc686 works.
>
> I get some undefined references for the 6-freebsd-12 branch though.
>
> Which branch of rtems-libbsd did you use?
>

Hmmm.. builds today on 6-freebsd-12. No idea what was happening then.

Have you ever tried to build it for x86_64. I know there's work to get to
where
it even is an option to try to see if it works but I wondered what might be
missing
to even build it for x86_64 without any drivers.

--joel


>
>
> Best regards,
>
>
>
> Jan
>
>
>
>
>
> *From:* devel  *On Behalf Of *jan.som...@dlr.de
> *Sent:* Thursday, August 18, 2022 8:09 PM
> *To:* j...@rtems.org; devel@rtems.org
> *Subject:* RE: libbsd fails to link on i386
>
>
>
> Hi Joel,
>
>
>
> I remember I spent some time fiddling with the bus.h include order.
>
> I can try to have a look at it some time next week.
>
>
>
> Best regards,
>
>
>
> Jan
>
>
>
> *From:* devel  *On Behalf Of *Joel Sherrill
> *Sent:* Wednesday, August 17, 2022 11:24 PM
> *To:* rtems-de...@rtems.org 
> *Subject:* libbsd fails to link on i386
>
>
>
> Hi
>
>
>
> I think the wrong bus.h must be being included somewhere. These are static
> inline methods on the i386. Hopefully a simple patch for someone who knows
> what to do:
>
>
>
> [1992/2039] Linking build/i386-rtems6-pc386-default/ftpd01.exe
> /home/joel/rtems-work/tools/6/lib/gcc/i386-rtems6/12.1.1/../../../../i386-rtems6/bin/ld:
> ./libbsd.a(rtems-kernel-bus-dma.c.20.o): in function
> `_bsd_bus_dmamem_alloc':
> /home/joel/rtems-work/rtems-libbsd/build/i386-rtems6-pc386-default/../../rtemsbsd/rtems/rtems-kernel-bus-dma.c:264:
> undefined reference to `bsp_bus_space_write_1'
> collect2: error: ld returned 1 exit status
>
> /home/joel/rtems-work/tools/6/lib/gcc/i386-rtems6/12.1.1/../../../../i386-rtems6/bin/ld:
> ./libbsd.a(rtems-kernel-bus-dma.c.20.o): in function
> `_bsd_bus_dmamem_alloc':
> /home/joel/rtems-work/rtems-libbsd/build/i386-rtems6-pc386-default/../../rtemsbsd/rtems/rtems-kernel-bus-dma.c:264:
> undefined reference to `bsp_bus_space_write_1'
> collect2: error: ld returned 1 exit status
>
> /home/joel/rtems-work/tools/6/lib/gcc/i386-rtems6/12.1.1/../../../../i386-rtems6/bin/ld:
> ./libbsd.a(rtems-kernel-bus-dma.c.20.o): in function
> `_bsd_bus_dmamem_alloc':
> /home/joel/rtems-work/rtems-libbsd/build/i386-rtems6-pc386-default/../../rtemsbsd/rtems/rtems-kernel-bus-dma.c:264:
> undefined reference to `bsp_bus_space_write_1'
> collect2: error: ld returned 1 exit status
>
> /home/joel/rtems-work/tools/6/lib/gcc/i386-rtems6/12.1.1/../../../../i386-rtems6/bin/ld:
> ./libbsd.a(rtems-kernel-bus-dma.c.20.o): in function
> `_bsd_bus_dmamem_alloc':
> /home/joel/rtems-work/rtems-libbsd/build/i386-rtems6-pc386-default/../../rtemsbsd/rtems/rtems-kernel-bus-dma.c:264:
> undefined reference to `bsp_bus_space_write_1'
> collect2: error: ld returned 1 exit status
>
> /home/joel/rtems-work/tools/6/lib/gcc/i386-rtems6/12.1.1/../../../../i386-rtems6/bin/ld:
> ./libbsd.a(rtems-kernel-bus-dma.c.20.o): in function
> `_bsd_bus_dmamem_alloc':
> /home/joel/rtems-work/rtems-libbsd/build/i386-rtems6-pc386-default/../../rtemsbsd/rtems/rtems-kernel-bus-dma.c:264:
> undefined reference to `bsp_bus_space_write_1'
> collect2: error: ld returned 1 exit status
>
> /home/joel/rtems-work/tools/6/lib/gcc/i386-rtems6/12.1.1/../../../../i386-rtems6/bin/ld:
> ./libbsd.a(rtems-kernel-bus-dma.c.20.o): in function
> `_bsd_bus_dmamem_alloc':
> /home/joel/rtems-work/rtems-libbsd/build/i386-rtems6-pc386-default/../../rtemsbsd/rtems/rtems-kernel-bus-dma.c:264:
> undefined reference to `bsp_bus_space_write_1'
> collect2: error: ld returned 1 exit status
>
> /home/joel/rtems-work/tools/6/lib/gcc/i386-rtems6/12.1.1/../../../../i386-rtems6/bin/ld:
> ./libbsd.a(rtems-kernel-bus-dma.c.20.o): in function
> `_bsd_bus_dmamem_alloc':
> /home/joel/rtems-work/rtems-libbsd/build/i386-rtems6-pc386-default/../../rtemsbsd/rtems/rtems-kernel-bus-dma.c:264:
> undefined reference to `bsp_bus_space_write_1'
> collect2: error: ld returned 1 exit status
>
> /home/joel/rtems-work/tools/6/lib/gcc/i386-rtems6/12.1.1/../../../../i386-rtems6/bin/ld:
> ./libbsd.a(rtems-kernel-bus-dma.c.20.o): in function
> `_bsd_bus_dmamem_alloc':
> /home/joel/rtems-work/rtems-libbsd/build/i386-rtems6-pc386-default/../../rtemsbsd/rtems/rtems-kernel-bus-dma.c:264:
> undefined reference to `bsp_bus_space_write_1'
> collect2: error: ld returned 1 exit status
>
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Re: [PATCH] bsps/arm: Fix start in hypervisor mode

[Chris Johns]

On 20/9/2022 9:12 pm, Sebastian Huber wrote:
> Only clear the HSCTLR[TE] bit to take exceptions in A32 state.  Keep the
> other HSCTLR bits as is since they control the current execution.
> Assume that the chip or boot loader did initialize this register
> correctly.

I think this change should have a ticket that describe the reason you found the
problem and on which ARM variant(s)? I think a ticket would help someone dealing
with a boot loader that does not set this register correctly.

Chris

> 
> Add comments.
> ---
>  bsps/arm/shared/start/start.S | 21 -
>  1 file changed, 12 insertions(+), 9 deletions(-)
> 
> diff --git a/bsps/arm/shared/start/start.S b/bsps/arm/shared/start/start.S
> index 32b168917a..c7fad5ae58 100644
> --- a/bsps/arm/shared/start/start.S
> +++ b/bsps/arm/shared/start/start.S
> @@ -249,22 +249,25 @@ _start:
>   mov sp, r3
>   sub r3, r3, r1
>  
> + /* Set HVBAR */
>   ldr r0, =bsp_start_hyp_vector_table_begin
>   mcr p15, 4, r0, c12, c0, 0
>  
> + /* Set HVC, HCPTR, and HSTR to zero */
>   mov r0, #0
>   mcr p15, 4, r0, c1, c1, 0
>   mcr p15, 4, r0, c1, c1, 2
>   mcr p15, 4, r0, c1, c1, 3
> -/*
> - * HSCTLR.TE
> - * optional start of hypervisor handlers in Thumb mode
> - *   orr r0, #(1 << 30)
> - */
> - mcr p15, 4, r0, c1, c0, 0   /* HSCTLR */
> - mrc p15, 4, r0, c1, c1, 1   /* HDCR */
> - and r0, #0x1f   /* Preserve HPMN */
> - mcr p15, 4, r0, c1, c1, 1   /* HDCR */
> +
> + /* Clear HSCTLR[TE] to take exceptions in A32 state */
> + mrc p15, 4, r0, c1, c0, 0
> + bic r0, #(1 << 30)
> + mcr p15, 4, r0, c1, c0, 0
> +
> + /* Set HDCR to zero except HDCR[HPMN] */
> + mrc p15, 4, r0, c1, c1, 1
> + and r0, #0x1f
> + mcr p15, 4, r0, c1, c1, 1
>  
>   /* Prepare SVC mode for eret */
>   mrs r0, cpsr
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Re: [PATCH v2 0/4] Microchip PolarFire SoC support

[Chris Johns]

On 21/9/2022 3:03 am, Joel Sherrill wrote:
> I have pushed this patch set. Please check that the merge is OK and follow up
> with an update to the Users Guide for those looking for this BSP.

Thanks. Great to see the addition of this BSP.

I have updated the RSB to include this BSP. I have also added this BSP to my
deployment repo:

  https://git.rtems.org/chrisj/rtems-deployment.git/

https://git.rtems.org/chrisj/rtems-deployment.git/tree/config/6/polarfire-icicle-bsp-smp.ini

To build a tar file:

 git clone git://git.rtems.org/rtems-source-builder.git
 git clone git://git.rtems.org/chrisj/rtems-deployment.git
 cd rtems-deployment
 ./waf configure --prefix=/opt/rtems --rsb=../rtems-source-builder
 ./waf --targets=6/polarfire-icicle-bsp dry-run
 ./waf --targets=6/polarfire-icicle-bsp

The results:

$ ls tar
polarfire-icicle-bsp.tar.bz2

To have the tools and BSP installed when built add to configure `--install`.

Chris
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Re: [PATCH v2 0/4] Microchip PolarFire SoC support

[Padmarao.Begari]

Hi Joel,

> On Tue, 2022-09-20 at 12:03 -0500, Joel Sherrill wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> I have pushed this patch set. Please check that the merge is OK and
> follow up with an update to the Users Guide for those looking for
> this BSP.
> 

Thank You.

I have checked the merge is OK. Sure, will update the User Guide for
this BSP.

Thanks & Regards
Padmarao

> Thanks.
> 
> On Tue, Sep 20, 2022 at 8:56 AM Joel Sherrill <
> joel.sherr...@gmail.com> wrote:
> > This procedure should be added to the Users Guide under the BSPs
> > section.
> > 
> > Otherwise, it looks like I should coordinate with Padmarao to make
> > sure it's ok after I merged it
> > 
> > On Tue, Sep 20, 2022, 1:50 AM 
> > wrote:
> > > RTEMS SMP on the Microchip PolarFire Icicle Kit
> > > 
> > > Test Procedure:
> > > 
> > > 1. Create the "config.ini" file with below content at rtems root 
> > > 
> > > [riscv/mpfs64imafdc]
> > > BUILD_TESTS = True
> > > RTEMS_POSIX_API=True
> > > RTEMS_SMP = True
> > > BSP_START_COPY_FDT_FROM_U_BOOT=False
> > > BSP_VERBOSE_FATAL_EXTENSION = False
> > > 
> > > 2. Build RTEMS
> > > $ ./waf configure --prefix=$HOME/rtems-start/rtems/6
> > > $ ./waf
> > > 
> > > 3. Convert .exe to .elf file
> > > 
> > > $ riscv-rtems6-objcopy 
> > > build/riscv/mpfs64imafdc/testsuites/smptests/sm
> > > p01.exe
> > >  build/riscv/mpfs64imafdc/testsuites/smptests/smp01.elf
> > > 
> > > 4. Generate the payload for the smp01.elf using the hss-payload-
> > > generator with hart-entry-points/exec-addr: 0x10
> > > 
> > > https://github.com/polarfire-soc/hart-software-services/tree/master/tools/hss-payload-generator
> > > 
> > > 5. Programming the'payload.bin' for the eMMC/SD
> > > 
> > >  5.1) Board setting and FPGA Programing
> > > 
> > > https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md
> > > 
> > > 
> > >  5.2). Power Cycle the Microchip PolarFire Icicle Kit and stop at
> > > the  
> > >HSS.
> > > 
> > >  5.3) type "mmc" and then "usbdmsc" on the HSS terminal(UART0).
> > > 
> > >  5.4) Load payload from the Host PC.
> > > $ sudo dd if=payload.bin of=/dev/sdb bs=512
> > > 
> > >  5.5) Quit USB and Reset the Icicle Kit
> > > 
> > >  5.6) Serial terminal UART1 displays the SMP example messages   
> > > 
> > > *** BEGIN OF TEST SMP 1 ***
> > > *** TEST VERSION: 6.0.0.ef33f861e16de9bf4190a36e4d18062c7300986c
> > > *** TEST STATE: EXPECTED_PASS
> > > *** TEST BUILD: RTEMS_POSIX_API RTEMS_SMP
> > > *** TEST TOOLS: 12.1.1 20220622 (RTEMS 6, RSB
> > > 3cb78b0b815ba05d17f5c6
> > > 5865d246a8333aa087, Newlib ea99f21)
> > > 
> > > CPU 3 start task TA0
> > > CPU 2 running Task TA0 
> > > CPU 3 start task TA1
> > > CPU 1 running Task TA1 
> > > CPU 3 start task TA2
> > > CPU 0 running Task TA2 
> > > 
> > > *** END OF TEST SMP 1 ***
> > > 
> > > Regards
> > > Padmarao
> > > On Mon, 2022-09-19 at 18:30 +0530, Padmarao Begari wrote:
> > > > This patch set adds the Microchip PolarFire SoC BSP Variant
> > > > support to RISC-V RTEMS.
> > > > 
> > > > The PolarFire SoC is the 4x 64-bit RISC-V U54 cores and
> > > > a 64-bit RISC-V E51 monitor core SoC from Microchip, more
> > > > info available here:
> > > >   https://www.microchip.com/en-us/products/fpgas-and-plds/
> > > >   system-on-chip-fpgas/polarfire-soc-fpgas#Overview
> > > > 
> > > > This new BSP variant is added for the 4x U54 cores not for E51
> > > > because the E51 monitor core is resreved for first stage
> > > > bootloader (Hart Software Services).
> > > > 
> > > > The boot HARTID configurable is implemented for the riscv BSP
> > > > to work with individual hart(cpu core) or SMP.
> > > > 
> > > > This BSP support components: 4 CPU Cores (U54), Interrupt
> > > > controller (PLIC), Timer (CLINT), UART (16550-compatible)
> > > > work fine on actual Microchip PolarFire SoC Icicle Kit.
> > > > 
> > > > v2:
> > > > - Add a license and copyright information in dtb header file
> > > > - Use RISCV_BOOT_HARDID instead of RTEMS_BOOT_HARDID
> > > > - Add '_RISCV_Map_hardid_to_cpu_index()' and
> > > > '_RISCV_Map_cpu_index_to_hardid()' functions
> > > > - Change bsp_fdt_get() instead of bsp_fdt_copy() function for
> > > dtb
> > > > - Move dtb and dtb header configurable build option to the bsps
> > > > 
> > > > Padmarao Begari (4):
> > > >   bsps/riscv: Add device tree blob
> > > >   spec/build/bsps: Add dtb support
> > > >   bsps/riscv: Add Microchip PolarFire SoC BSP variant
> > > >   bsps/shared/: Use device tree blob
> > > > 
> > > >  bsps/riscv/riscv/clock/clockdrv.c |   6 +-
> > > >  bsps/riscv/riscv/config/mpfs64imafdc.cfg  |   9 +
> > > >  bsps/riscv/riscv/dts/mpfs.dts | 365
> > > +++
> > > >  bsps/riscv/riscv/include/bsp/mpfs-dtb.h   | 602
> > > > +++

Re: [PATCH v2 0/4] Microchip PolarFire SoC support

[Padmarao.Begari]

Hi Chris,

Thank You for a tar file build, will try to build same using your repo.

Regards
Padmarao

> On Wed, 2022-09-21 at 14:34 +1000, Chris Johns wrote:
> 
> On 21/9/2022 3:03 am, Joel Sherrill wrote:
> > I have pushed this patch set. Please check that the merge is OK and
> > follow up
> > with an update to the Users Guide for those looking for this BSP.
> 
> Thanks. Great to see the addition of this BSP.
> 
> I have updated the RSB to include this BSP. I have also added this
> BSP to my
> deployment repo:
> 
>   https://git.rtems.org/chrisj/rtems-deployment.git/
> 
> https://git.rtems.org/chrisj/rtems-deployment.git/tree/config/6/polarfire-icicle-bsp-smp.ini
> 
> To build a tar file:
> 
>  git clone git://git.rtems.org/rtems-source-builder.git
>  git clone git://git.rtems.org/chrisj/rtems-deployment.git
>  cd rtems-deployment
>  ./waf configure --prefix=/opt/rtems --rsb=../rtems-source-builder
>  ./waf --targets=6/polarfire-icicle-bsp dry-run
>  ./waf --targets=6/polarfire-icicle-bsp
> 
> The results:
> 
> $ ls tar
> polarfire-icicle-bsp.tar.bz2
> 
> To have the tools and BSP installed when built add to configure `
> --install`.
> 
> Chris
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