[PATCH v6 00/10] New GPIO, ADC API and STM32F4 BSP implementation
Dear all, These patches are to address the issues in my previous versions. These include GPIO API, ADC API and STM32F4 BSP implementation for them. My repository is at: https://github.com/dtbpkmte/GSoC-2022-RTEMS (master branch). The sample application code for these APIs can be found at: https://github.com/dtbpkmte/GSoC-2022-RTEMS-Sample-Apps. STM32F4 HAL source code is taken from ST's repo at: https://github.com/STMicroelectronics/STM32CubeF4.git (Commit ID: 52757b5, Release v1.27.1). v2: - Made get_gpio_from_base() a macro instead of a function - Added missing cppflags in spec/build/bsps/arm/grp.yml - Optimized STM32F4_GET_HAL_GPIO_PIN() and STM32F4_GET_LL_EXTI_LINE() - Optimized functions by switching from HAL to LL - Made stm32f4_gpio_deinit() return RTEMS_NOT_IMPLEMENTED, because disabling clock might affect all pins in a port - Add const to static helper arrays to make sure they are placed on ROM v3: - Removed rtems_gpio_begin() - bsp_gpio_register_controllers() now needs to be called from hook1 (can be configured by option STM32F4_ENABLE_GENERIC_GPIO) - Updated license text for API files and STM32F4 GPIO files v4: - Fixed GPIO port guards - Fixed potential memory-leak bug of STM32F4 GPIO interrupt system - Added comments to STM32F4 GPIO functions and made them extern v5: - Replace old HAL source code with the one from official repository to remove CRLF - Added a peripherals API, which is a framework to add more APIs that operates on a GPIO pin - Changed GPIO API to comply with the peripherals API - Changed ADC API to comply with the peripherals API - Changed STM32F4 implementation v6: - Split commits that add CMSIS and HAL - Removed peripheral API - Changed ADC API: this is now separate from GPIO API Duc Doan (10): bsps/arm: Convert CMSIS files from CRLF to LF bsps/arm: Changed CMSIS files to v5 build/bsps/arm: Add new CMSIS files v5 to build bsps/arm/stm32f4: Include STM32F4 HAL bsps/arm/stm32f4: Add HAL to build bsps/arm/stm32f4: Make bspstart use HAL bsps: Add GPIO API bsps/arm/stm32f4: GPIO Implementation bsps: Add ADC API bsps/arm/stm32f4: ADC API implementation bsps/arm/include/cmsis_compiler.h | 266 + bsps/arm/include/cmsis_gcc.h | 3460 +-- bsps/arm/include/cmsis_version.h |39 + bsps/arm/include/core_cm4.h | 524 +- bsps/arm/include/core_cm7.h | 5186 ++-- bsps/arm/include/core_cmFunc.h| 172 +- bsps/arm/include/core_cmInstr.h | 174 +- bsps/arm/include/core_cmSimd.h| 192 +- bsps/arm/include/mpu_armv7.h | 270 + bsps/arm/stm32f4/adc/adc.c| 495 + bsps/arm/stm32f4/gpio/gpio.c | 557 + .../stm32f4/hal/Legacy/stm32f4xx_hal_can.c| 1679 ++ .../stm32f4/hal/Legacy/stm32f4xx_hal_eth.c| 2307 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal.c | 615 + bsps/arm/stm32f4/hal/stm32f4xx_hal_adc.c | 2110 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_adc_ex.c | 1112 + bsps/arm/stm32f4/hal/stm32f4xx_hal_can.c | 2462 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cec.c | 996 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cortex.c | 502 + bsps/arm/stm32f4/hal/stm32f4xx_hal_crc.c | 328 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp.c | 7132 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp_ex.c | 680 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dac.c | 1341 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dac_ex.c | 495 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi.c | 1161 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dfsdm.c| 4423 bsps/arm/stm32f4/hal/stm32f4xx_hal_dma.c | 1305 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dma2d.c| 2126 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dma_ex.c | 313 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dsi.c | 2760 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_eth.c | 3220 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_exti.c | 547 + bsps/arm/stm32f4/hal/stm32f4xx_hal_flash.c| 775 + bsps/arm/stm32f4/hal/stm32f4xx_hal_flash_ex.c | 1347 + .../stm32f4/hal/stm32f4xx_hal_flash_ramfunc.c | 172 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpi2c.c | 6864 ++ .../arm/stm32f4/hal/stm32f4xx_hal_fmpi2c_ex.c | 258 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpsmbus.c | 2749 +++ .../stm32f4/hal/stm32f4xx_hal_fmpsmbus_ex.c | 145 + bsps/arm/stm32f4/hal/stm32f4xx_hal_gpio.c | 533 + bsps/arm/stm32f4/hal/stm32f4xx_hal_hash.c | 3514 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_hash_ex.c | 1040 + bsps/arm/stm32f4/hal/stm32f4xx_hal_hcd.c | 1728 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c.c | 7524 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s.c | 2094 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s_ex.c | 1135 + bsps/arm/stm32f4/hal/stm32f4xx_hal_irda.c | 2687 ++ bsps/arm/stm32f4/ha
[PATCH v6 03/10] build/bsps/arm: Add new CMSIS files v5 to build
--- spec/build/bsps/arm/grp.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/spec/build/bsps/arm/grp.yml b/spec/build/bsps/arm/grp.yml index 37229fddc2..52c2a9f4f3 100644 --- a/spec/build/bsps/arm/grp.yml +++ b/spec/build/bsps/arm/grp.yml @@ -13,6 +13,9 @@ install: - bsps/arm/include/cmsis_gcc.h - bsps/arm/include/core_cm7.h - bsps/arm/include/core_cm4.h + - bsps/arm/include/cmsis_version.h + - bsps/arm/include/cmsis_compiler.h + - bsps/arm/include/mpu_armv7.h - bsps/arm/include/core_cmFunc.h - bsps/arm/include/core_cmInstr.h - bsps/arm/include/core_cmSimd.h -- 2.37.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v6 04/10] bsps/arm/stm32f4: Include STM32F4 HAL
This patch adds STM32F4 HAL files taken from ST's repository at: https://github.com/STMicroelectronics/STM32CubeF4, Release v1.27.1, commit 52757b5e33259a088509a777a9e3a5b971194c7d. The device headers are copied from Drivers/CMSIS/Device/ST/STM32F4xx/Include. The HAL and LL files are copied from Drivers/STM32F4xx_HAL_Driver/Inc. The HAL and LL source files are copied from: Drivers/STM32F4xx_HAL_Driver/Src. Due to great size, I cannot send the patch via email. Please find it at https://github.com/dtbpkmte/GSoC-2022-RTEMS/commit/b8aeedfe8cfecf248b279e846d11080f9511910b --- .../stm32f4/hal/Legacy/stm32f4xx_hal_can.c| 1679 ++ .../stm32f4/hal/Legacy/stm32f4xx_hal_eth.c| 2307 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal.c | 615 + bsps/arm/stm32f4/hal/stm32f4xx_hal_adc.c | 2110 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_adc_ex.c | 1112 + bsps/arm/stm32f4/hal/stm32f4xx_hal_can.c | 2462 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cec.c | 996 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cortex.c | 502 + bsps/arm/stm32f4/hal/stm32f4xx_hal_crc.c | 328 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp.c | 7132 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp_ex.c | 680 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dac.c | 1341 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dac_ex.c | 495 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi.c | 1161 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dfsdm.c| 4423 bsps/arm/stm32f4/hal/stm32f4xx_hal_dma.c | 1305 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dma2d.c| 2126 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dma_ex.c | 313 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dsi.c | 2760 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_eth.c | 3220 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_exti.c | 547 + bsps/arm/stm32f4/hal/stm32f4xx_hal_flash.c| 775 + bsps/arm/stm32f4/hal/stm32f4xx_hal_flash_ex.c | 1347 + .../stm32f4/hal/stm32f4xx_hal_flash_ramfunc.c | 172 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpi2c.c | 6864 ++ .../arm/stm32f4/hal/stm32f4xx_hal_fmpi2c_ex.c | 258 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpsmbus.c | 2749 +++ .../stm32f4/hal/stm32f4xx_hal_fmpsmbus_ex.c | 145 + bsps/arm/stm32f4/hal/stm32f4xx_hal_gpio.c | 533 + bsps/arm/stm32f4/hal/stm32f4xx_hal_hash.c | 3514 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_hash_ex.c | 1040 + bsps/arm/stm32f4/hal/stm32f4xx_hal_hcd.c | 1728 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c.c | 7524 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s.c | 2094 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s_ex.c | 1135 + bsps/arm/stm32f4/hal/stm32f4xx_hal_irda.c | 2687 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_iwdg.c | 262 + bsps/arm/stm32f4/hal/stm32f4xx_hal_lptim.c| 2484 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc.c | 2215 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc_ex.c | 151 + bsps/arm/stm32f4/hal/stm32f4xx_hal_mmc.c | 3201 +++ .../stm32f4/hal/stm32f4xx_hal_msp_template.c | 100 + bsps/arm/stm32f4/hal/stm32f4xx_hal_nand.c | 2405 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_nor.c | 1543 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pccard.c | 946 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd.c | 2387 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd_ex.c | 341 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr.c | 571 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr_ex.c | 600 + bsps/arm/stm32f4/hal/stm32f4xx_hal_qspi.c | 2915 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rcc.c | 1122 + bsps/arm/stm32f4/hal/stm32f4xx_hal_rcc_ex.c | 3784 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rng.c | 867 + bsps/arm/stm32f4/hal/stm32f4xx_hal_rtc.c | 1896 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rtc_ex.c | 1878 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sai.c | 2554 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sai_ex.c | 310 + bsps/arm/stm32f4/hal/stm32f4xx_hal_sd.c | 3277 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sdram.c| 1308 + .../arm/stm32f4/hal/stm32f4xx_hal_smartcard.c | 2364 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_smbus.c| 2784 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_spdifrx.c | 1627 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_spi.c | 3915 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sram.c | 1110 + bsps/arm/stm32f4/hal/stm32f4xx_hal_tim.c | 7621 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_tim_ex.c | 2428 ++ ...tm32f4xx_hal_timebase_rtc_alarm_template.c | 318 + ...m32f4xx_hal_timebase_rtc_wakeup_template.c | 293 + .../hal/stm32f4xx_hal_timebase_tim_template.c | 177 + bsps/arm/stm32f4/hal/stm32f4xx_hal_uart.c | 3751 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_usart.c| 2838 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_wwdg.c | 420 + bsps/arm/stm32f4/hal/stm32f4xx_ll_adc.c | 922 + bsps/arm/stm32f4/hal/stm32f4xx_ll_crc.c | 103 + bsps/arm/stm32f4/ha
[PATCH v6 05/10] bsps/arm/stm32f4: Add HAL to build
This patch modifies some HAL headers to connect with RTEMS
and add HAL code to build. It also adds some options to
enable HAL, specify clock source and chip variant.
---
bsps/arm/stm32f4/include/bsp/io.h | 4 +
bsps/arm/stm32f4/include/stm32f4xx.h | 4 +
bsps/arm/stm32f4/include/stm32f4xx_hal_conf.h | 506 ++
spec/build/bsps/arm/stm32f4/grp.yml | 12 +-
spec/build/bsps/arm/stm32f4/obj.yml | 220 +++-
spec/build/bsps/arm/stm32f4/optenhal.yml | 16 +
spec/build/bsps/arm/stm32f4/opthse.yml| 17 +
spec/build/bsps/arm/stm32f4/optusehse.yml | 16 +
spec/build/bsps/arm/stm32f4/optvariant.yml| 24 +
9 files changed, 816 insertions(+), 3 deletions(-)
create mode 100644 bsps/arm/stm32f4/include/stm32f4xx_hal_conf.h
create mode 100644 spec/build/bsps/arm/stm32f4/optenhal.yml
create mode 100644 spec/build/bsps/arm/stm32f4/opthse.yml
create mode 100644 spec/build/bsps/arm/stm32f4/optusehse.yml
create mode 100644 spec/build/bsps/arm/stm32f4/optvariant.yml
diff --git a/bsps/arm/stm32f4/include/bsp/io.h
b/bsps/arm/stm32f4/include/bsp/io.h
index 4fa39bdca9..9cdb96fa49 100644
--- a/bsps/arm/stm32f4/include/bsp/io.h
+++ b/bsps/arm/stm32f4/include/bsp/io.h
@@ -19,6 +19,10 @@
#include
#include
+#ifdef __rtems__
+#include
+#endif /* __rtems__ */
+
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
diff --git a/bsps/arm/stm32f4/include/stm32f4xx.h
b/bsps/arm/stm32f4/include/stm32f4xx.h
index 2c3482db4f..e246f579ce 100644
--- a/bsps/arm/stm32f4/include/stm32f4xx.h
+++ b/bsps/arm/stm32f4/include/stm32f4xx.h
@@ -37,6 +37,10 @@
#ifndef __STM32F4xx_H
#define __STM32F4xx_H
+#ifdef __rtems__
+#include
+#endif /* __rtems__ */
+
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
diff --git a/bsps/arm/stm32f4/include/stm32f4xx_hal_conf.h
b/bsps/arm/stm32f4/include/stm32f4xx_hal_conf.h
new file mode 100644
index 00..51603cae20
--- /dev/null
+++ b/bsps/arm/stm32f4/include/stm32f4xx_hal_conf.h
@@ -0,0 +1,506 @@
+/**
+
**
+ * @filestm32f4xx_hal_conf_template.h
+ * @author MCD Application Team
+ * @brief HAL configuration template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32f4xx_hal_conf.h.
+
**
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+
**
+ */
+
+/* Define to prevent recursive inclusion
-*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __rtems__
+#include
+
+#define HSE_VALUE ((uint32_t) STM32F4_HSE_FREQUENCY)
+#endif /* __rtems__ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types
*/
+/* Exported constants
*/
+
+/* ## Module Selection ##
*/
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CEC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_DMA2D_MODULE_ENABLED
+#define HAL_ETH_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_PCCARD_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_SDRAM_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_SMBUS_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_DSI_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_QSPI_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+#define HAL_FMPI2C_MODULE_ENABLED
+#define
[PATCH v6 06/10] bsps/arm/stm32f4: Make bspstart use HAL
This patch changes bspstart to use HAL for clock and sysyem
initialization.
---
bsps/arm/stm32f4/start/bspstart.c | 199 --
1 file changed, 186 insertions(+), 13 deletions(-)
diff --git a/bsps/arm/stm32f4/start/bspstart.c
b/bsps/arm/stm32f4/start/bspstart.c
index 0ec5ac27b5..2297430844 100644
--- a/bsps/arm/stm32f4/start/bspstart.c
+++ b/bsps/arm/stm32f4/start/bspstart.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2012 Sebastian Huber. All rights reserved.
+ * Copyright (c) 2022 Duc Doan (dtbpkmte at gmail.com).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -7,15 +8,23 @@
*/
#include
+#include
#include
#include
#include
#include
#include
+#ifndef __rtems__
#include
+#endif /* __rtems__ */
+#ifdef __rtems__
+#include
+#include
+#endif /* __rtems__ */
#ifdef STM32F4_FAMILY_F4
+#ifndef __rtems__
#include
#include
@@ -24,28 +33,191 @@ static rtems_status_code set_system_clk(
uint32_t hse_clk,
uint32_t hse_flag
);
+#endif /* __rtems__ */
+
+#ifdef __rtems__
+/* Get number of milliseconds elapsed since startup */
+uint32_t HAL_GetTick(void)
+{
+ return rtems_clock_get_ticks_since_boot() *
+rtems_configuration_get_milliseconds_per_tick();
+}
+
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+static void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state
*/
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
+}
+
+static rtems_status_code SystemClock_Config(void)
+{
+/** Configure the main internal regulator output voltage
+*/
+__HAL_RCC_PWR_CLK_ENABLE();
+__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+uint32_t use_hse = STM32F4_USE_HSE, sys_clk = STM32F4_SYSCLK / 100L,
hse_clk = STM32F4_HSE_FREQUENCY / 100L, src_clk;
+uint32_t sys_clk_src;
+uint32_t flash_latency = FLASH_LATENCY_0;
+uint32_t pll_m = 0, pll_n = 0, pll_p = 0, pll_q = 0;
+uint32_t apbpre1 = 0, apbpre2 = 0;
+
+if (sys_clk == 16 && hse_clk != 16) {
+sys_clk_src = RCC_SYSCLKSOURCE_HSI;
+RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+flash_latency = FLASH_LATENCY_0;
+} else if (sys_clk == hse_clk) {
+sys_clk_src = RCC_SYSCLKSOURCE_HSE;
+RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+flash_latency = FLASH_LATENCY_0;
+} else {
+sys_clk_src = RCC_SYSCLKSOURCE_PLLCLK;
+if (sys_clk > 180) {
+return RTEMS_INVALID_NUMBER;
+} else if (sys_clk >= 96) {
+pll_n = sys_clk << 1;
+pll_p = RCC_PLLP_DIV2;
+} else if (sys_clk >= 48) {
+pll_n = sys_clk << 2;
+pll_p = RCC_PLLP_DIV4;
+} else if (sys_clk >= 24) {
+pll_n = sys_clk << 3;
+pll_p = RCC_PLLP_DIV8;
+} else {
+return RTEMS_INVALID_NUMBER;
+}
+
+if (hse_clk == 0 || use_hse == 0) {
+src_clk = 16;
+use_hse = 0;
+} else {
+src_clk = hse_clk;
+}
+
+pll_m = src_clk;
+
+pll_q = ((long) (src_clk * pll_n)) / pll_m / 48;
+if (pll_q < 2) {
+pll_q = 2;
+}
+
+/* APB1 prescaler, APB1 clock must be < 42MHz */
+apbpre1 = (sys_clk * 100) / 42;
+
+if ( apbpre1 <= 100 ) {
+apbpre1 = RCC_HCLK_DIV1;
+} else if (apbpre1 <= 200) {
+apbpre1 = RCC_HCLK_DIV2;
+} else if (apbpre1 <= 400) {
+apbpre1 = RCC_HCLK_DIV4;
+} else if (apbpre1 <= 800) {
+apbpre1 = RCC_HCLK_DIV8;
+} else if (apbpre1) {
+apbpre1 = RCC_HCLK_DIV16;
+}
+
+/* APB2 prescaler, APB2 clock must be < 84MHz */
+apbpre2 = (sys_clk * 100) / 84;
+
+if (apbpre2 <= 100) {
+apbpre2 = RCC_HCLK_DIV1;
+} else if (apbpre2 <= 200) {
+apbpre2 = RCC_HCLK_DIV2;
+} else if (apbpre2 <= 400) {
+apbpre2 = RCC_HCLK_DIV4;
+} else if (apbpre2 <= 800) {
+apbpre2 = RCC_HCLK_DIV8;
+} else {
+apbpre2 = RCC_HCLK_DIV16;
+}
+
+if (use_hse) {
+RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+} else {
+RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+RCC_OscInitStruct.HS
[PATCH v6 07/10] bsps: Add GPIO API
---
bsps/include/bsp/gpio2.h | 524 ++
bsps/shared/dev/gpio/gpio2.c | 207
spec/build/bsps/bspopts.yml | 2 +
spec/build/bsps/obj.yml | 2 +-
spec/build/bsps/optmaxnumgpio.yml | 16 +
5 files changed, 750 insertions(+), 1 deletion(-)
create mode 100644 bsps/include/bsp/gpio2.h
create mode 100644 bsps/shared/dev/gpio/gpio2.c
create mode 100644 spec/build/bsps/optmaxnumgpio.yml
diff --git a/bsps/include/bsp/gpio2.h b/bsps/include/bsp/gpio2.h
new file mode 100644
index 00..e2a2e3b1e5
--- /dev/null
+++ b/bsps/include/bsp/gpio2.h
@@ -0,0 +1,524 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup gpio2
+ *
+ * RTEMS new GPIO API.
+ *
+ * This API is created to improve portability and simplicity for GPIO.
+ *
+ * This API maps GPIO pins into a flat numbering system, counting from 0.
+ * This pin number is often referred to as a virtual pin number. A GPIO pin
+ * is represented by the structure @ref rtems_gpio. This structure may also
+ * be referred to as a "GPIO object". A "driver" could mean a BSP or a
+ * device driver. A GPIO controller may refer to a physical GPIO controller,
+ * an ADC, a DAC, or just a group of pins that contains one or more pins.
+ *
+ */
+
+/*
+ * Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_BSP_GPIO2_H
+#define LIBBSP_BSP_GPIO2_H
+
+#include
+#include
+
+/**
+ * Configure the maximum number of GPIO controllers used in
+ * a application.
+ *
+ * The macro CONFIGURE_GPIO_MAXIMUM_CONTROLLERS is a build option.
+ * If it is not defined, it will default to BSP_GPIO_NUM_CONTROLLERS.
+ * If BSP's number of controllers is not defined, it will default
+ * to 16.
+ */
+#ifndef CONFIGURE_GPIO_MAXIMUM_CONTROLLERS
+
+#ifndef BSP_GPIO_NUM_CONTROLLERS
+#define CONFIGURE_GPIO_MAXIMUM_CONTROLLERS 16
+#else
+#define CONFIGURE_GPIO_MAXIMUM_CONTROLLERS BSP_GPIO_NUM_CONTROLLERS
+#endif /* BSP_GPIO_NUM_CONTROLLERS */
+
+#endif /* CONFIGURE_GPIO_MAXIMUM_CONTROLLERS */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @brief Macro to initialize rtems_gpio.
+ *
+ * @param gpioh pointer to GPIO handlers
+ */
+#define RTEMS_GPIO_BUILD_BASE(_gpio_handlers) \
+(rtems_gpio) { .virtual_pin = 0,\
+ .gpio_handlers = ( _gpio_handlers ) \
+};
+
+extern int *gpio_dummy;
+/**
+ * @brief Macro to link BSP source file.
+ *
+ * There might be a case that a BSP GPIO source file is not linked because
+ * of no reference. Use this macro to create a dummy variable to link with
+ * GPIO API. This macro should be placed outside of any function.
+ */
+#define RTEMS_GPIO_LINK() \
+static int ___dummy___ = 0; \
+int *gpio_dummy = &___dummy___;
+
+/**
+ * @name GPIO data structures
+ *
+ * @{
+ */
+
+/**
+ * @brief GPIO bit set and reset enumeration.
+ */
+typedef enum {
+RTEMS_GPIO_PIN_RESET = 0,
+RTEMS_GPIO_PIN_SET = 1
+} rtems_gpio_pin_state;
+
+/**
+ * @brief GPIO pin modes.
+ */
+typedef enum {
+RTEMS_GPIO_PINMODE_OUTPUT = 0,
+RTEMS_GPIO_PINMODE_OUTPUT_PP = 0,
+RTEMS_GPIO_PINMODE_OUTPUT_OD = 1,
+RTEMS_GPIO_PINMODE_INPUT = 2,
+RTEMS_GPIO_PINMODE_ANALOG = 3,
+RTEMS_GPIO_PINMODE_BSP_SPECIFIC = 100
+} rtems_gpio_pin_mode;
+
+/**
+ * @brief GPIO pull resistor configuration. Defines pull-up or
+ *pull-down activation.
+ */
+typedef enum {
+RTEMS_GPIO_NOPULL = 0,
+RTEMS_GPIO_PULLUP = 1,
+RTEMS_GPIO_PULLDOWN = 2,
+RTEMS_GPIO_PULL_BSP_SPECIFIC = 100
+} rt
[PATCH v6 08/10] bsps/arm/stm32f4: GPIO Implementation
---
bsps/arm/stm32f4/gpio/gpio.c | 557 ++
bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h | 281 +
spec/build/bsps/arm/stm32f4/grp.yml | 6 +-
spec/build/bsps/arm/stm32f4/obj.yml | 4 +
.../build/bsps/arm/stm32f4/optnumgpioctrl.yml | 16 +
5 files changed, 862 insertions(+), 2 deletions(-)
create mode 100644 bsps/arm/stm32f4/gpio/gpio.c
create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h
create mode 100644 spec/build/bsps/arm/stm32f4/optnumgpioctrl.yml
diff --git a/bsps/arm/stm32f4/gpio/gpio.c b/bsps/arm/stm32f4/gpio/gpio.c
new file mode 100644
index 00..34b1d62cc0
--- /dev/null
+++ b/bsps/arm/stm32f4/gpio/gpio.c
@@ -0,0 +1,557 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup stm32f4_gpio
+ */
+
+/*
+ * Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+/*** GPIO API ***/
+static rtems_status_code stm32f4_gpio_get(
+uint32_t interm_pin,
+rtems_gpio **out
+);
+
+static rtems_status_code stm32f4_gpio_destroy(
+rtems_gpio *base
+);
+
+/*/
+
+/**
+ * @brief STM32F4 GPIO handlers
+ */
+static const rtems_gpio_handlers stm32f4_gpio_handlers = {
+.set_pin_mode = stm32f4_gpio_set_pin_mode,
+.set_pull = stm32f4_gpio_set_pull,
+.configure_interrupt = stm32f4_gpio_configure_interrupt,
+.remove_interrupt = stm32f4_gpio_remove_interrupt,
+.enable_interrupt = stm32f4_gpio_enable_interrupt,
+.disable_interrupt = stm32f4_gpio_disable_interrupt,
+.read = stm32f4_gpio_read,
+.write = stm32f4_gpio_write,
+.toggle = stm32f4_gpio_toggle
+};
+
+static GPIO_TypeDef * const GPIOx[] = {
+#ifdef GPIOA_BASE
+GPIOA
+#endif /* GPIOA_BASE */
+#ifdef GPIOB_BASE
+, GPIOB
+#endif /* GPIOB_BASE */
+#ifdef GPIOC_BASE
+, GPIOC
+#endif /* GPIOC_BASE */
+#ifdef GPIOD_BASE
+, GPIOD
+#endif /* GPIOD_BASE */
+#ifdef GPIOE_BASE
+, GPIOE
+#endif /* GPIOE_BASE */
+#ifdef GPIOF_BASE
+, GPIOF
+#endif /* GPIOF_BASE */
+#ifdef GPIOG_BASE
+, GPIOG
+#endif /* GPIOG_BASE */
+#ifdef GPIOH_BASE
+, GPIOH
+#endif /* GPIOH_BASE */
+#ifdef GPIOI_BASE
+, GPIOI
+#endif /* GPIOI_BASE */
+#ifdef GPIOJ_BASE
+, GPIOJ
+#endif /* GPIOJ_BASE */
+#ifdef GPIOK_BASE
+, GPIOK
+#endif /* GPIOK_BASE */
+};
+
+static unsigned int const EXTIx_IRQn[] = {
+EXTI0_IRQn,
+EXTI1_IRQn,
+EXTI2_IRQn,
+EXTI3_IRQn,
+EXTI4_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn
+};
+
+/**
+ * @brief Converts intermediate pin number to port pointer.
+ *
+ * Intermediate pin number is a way of numerically labeling
+ * pins. Pins are labeled incrementally across all ports.
+ * Pins 0-15 from port A are 0-15. Pins 0-15 from port B are
+ * 16-31. And so on.
+ *
+ * @param interm_pin is the intermediate pin number
+ */
+#define STM32F4_GET_PORT(interm_pin) (GPIOx[ ( interm_pin ) / 16 ])
+
+/**
+ * @brief Converts intermediate pin number to 0-15.
+ *
+ * Intermediate pin number is a way of numerically labeling
+ * pins. Pins are labeled incrementally across all ports.
+ * Pins 0-15 from port A are 0-15. Pins 0-15 from port B are
+ * 16-31. And so on.
+ *
+ * @param interm_pin is the intermediate pin number
+ */
+#define STM32F4_GET_PIN_0_15(interm_pin) (( interm_pin ) % 16)
+
+/**
+ * @brief Converts pin number from 0-15 to HAL pin mask.
[PATCH v6 09/10] bsps: Add ADC API
---
bsps/include/bsp/adc.h | 407 +++
bsps/shared/dev/adc/adc.c| 249 +++
spec/build/bsps/bspopts.yml | 2 +
spec/build/bsps/obj.yml | 1 +
spec/build/bsps/optmaxnumadc.yml | 16 ++
5 files changed, 675 insertions(+)
create mode 100644 bsps/include/bsp/adc.h
create mode 100644 bsps/shared/dev/adc/adc.c
create mode 100644 spec/build/bsps/optmaxnumadc.yml
diff --git a/bsps/include/bsp/adc.h b/bsps/include/bsp/adc.h
new file mode 100644
index 00..97e596317b
--- /dev/null
+++ b/bsps/include/bsp/adc.h
@@ -0,0 +1,407 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup adc
+ *
+ * RTEMS ADC API.
+ *
+ * This API is created to improve portability for ADC-related operations.
+ *
+ * Drivers need to register each ADC controller to the manager using
+ * @ref rtems_adc_register(). Then, users can get an ADC object of a controller
+ * by specifying the index of that controller (starting from 0, the first
+ * registered ADC).
+ *
+ * Sometimes, ADCs are integrated into a GPIO pin (such as on-chip ADC). If so,
+ * additional effort to set the pin mode to analog might be required.
+ *
+ * The general process to use ADC API:
+ * - Get an ADC object using @ref rtems_adc_get()
+ * - Configure ADC object with rtems_adc_set_* functions
+ * - Call @ref rtems_adc_init()
+ * - The ADC object should be ready by now
+ */
+
+/*
+ * Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_BSP_ADC_H
+#define LIBBSP_BSP_ADC_H
+
+#include
+#include
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+extern volatile int *adc_dummy;
+/**
+ * @brief Macro to link BSP source file.
+ *
+ * There might be a case that a BSP GPIO source file is not linked because
+ * of no reference. Use this macro to create a dummy variable to link with
+ * GPIO API. This macro should be placed outside of any function.
+ */
+#define RTEMS_ADC_LINK() \
+static int ___dummy___ = 0;\
+volatile int *adc_dummy = &___dummy___;
+
+/**
+ * Configure the maximum number of ADC controllers used in
+ * a application.
+ *
+ * The macro CONFIGURE_ADC_MAXIMUM_CONTROLLERS is a build option.
+ * If it is not defined, it will default to BSP_ADC_NUM_CONTROLLERS.
+ * If BSP's number of controllers is not defined, it will default
+ * to 0.
+ */
+#ifndef CONFIGURE_ADC_MAXIMUM_CONTROLLERS
+
+#ifndef BSP_ADC_NUM_CONTROLLERS
+#define CONFIGURE_ADC_MAXIMUM_CONTROLLERS 0
+#else
+#define CONFIGURE_ADC_MAXIMUM_CONTROLLERS BSP_ADC_NUM_CONTROLLERS
+#endif /* BSP_ADC_NUM_CONTROLLERS */
+
+#endif /* CONFIGURE_ADC_MAXIMUM_CONTROLLERS */
+
+typedef enum {
+RTEMS_ADC_NOT_STARTED = 0,
+RTEMS_ADC_NOT_READY,
+RTEMS_ADC_READY
+} rtems_adc_status;
+
+/**
+ * @brief Data alignment.
+ */
+typedef enum {
+RTEMS_ADC_ALIGN_LEFT,
+RTEMS_ADC_ALIGN_RIGHT
+} rtems_adc_align;
+
+/**
+ * @brief Enumeration of reference voltages.
+ */
+typedef enum {
+RTEMS_ADC_REF_DEFAULT = 0,
+RTEMS_ADC_REF_INTERNAL,
+RTEMS_ADC_REF_EXTERNAL,
+RTEMS_ADC_REF_BSP_SPECIFIC = 100
+} rtems_adc_ref;
+
+#define RTEMS_ADC_NO_TIMEOUT 0xU
+
+typedef void (*rtems_adc_isr)(void *);
+typedef double (*rtems_adc_tf) (void *params, uint32_t raw_value);
+typedef struct rtems_adc_handlers rtems_adc_handlers;
+typedef struct rtems_adc_config rtems_adc_config;
+typedef struct rtems_adc rtems_adc;
+
+/**
+ * @brief Driver-specific handlers.
+ * Each driver need to create an object of this structure to supply to
+ * the API.
+ */
+struct rtems_adc_handlers {
+void
[PATCH v6 10/10] bsps/arm/stm32f4: ADC API implementation
---
bsps/arm/stm32f4/adc/adc.c| 495 ++
bsps/arm/stm32f4/include/bsp/stm32f4_adc.h| 198 +++
spec/build/bsps/arm/stm32f4/grp.yml | 2 +
spec/build/bsps/arm/stm32f4/obj.yml | 3 +
spec/build/bsps/arm/stm32f4/optnumadcctrl.yml | 16 +
5 files changed, 714 insertions(+)
create mode 100644 bsps/arm/stm32f4/adc/adc.c
create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4_adc.h
create mode 100644 spec/build/bsps/arm/stm32f4/optnumadcctrl.yml
diff --git a/bsps/arm/stm32f4/adc/adc.c b/bsps/arm/stm32f4/adc/adc.c
new file mode 100644
index 00..61ced0f4c9
--- /dev/null
+++ b/bsps/arm/stm32f4/adc/adc.c
@@ -0,0 +1,495 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup stm32f4_adc
+ */
+
+/*
+ * Copyright (C) 2022 Duc Doan (dtbpkmte at gmail.com)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+
+#if defined(ADC3)
+#define NUM_ADC 3
+#elif defined(ADC2)
+#define NUM_ADC 2
+#else
+#define NUM_ADC 1
+#endif
+
+/** Helpers */
+/**
+ * @brief Macro to get stm32f4_gpio object from a base rtems_gpio
+ *object.
+ *
+ * This is a wrapper of RTEMS_CONTAINER_OF macro
+ *
+ * @param base The pointer to a rtems_gpio object
+ * @retval The pointer to the stm32f4_gpio object owning
+ * the specified rtems_gpio object
+ */
+#define stm32f4_adc_get_adc_from_base(_base) \
+RTEMS_CONTAINER_OF(_base, stm32f4_adc, base)
+
+void adc_irq_handler(void *arg);
+
+/**
+ * @brief Data structure for non-blocking read.
+ */
+typedef struct {
+uint32_t adc_value;
+rtems_adc_status status;
+} stm32f4_adc_data;
+static stm32f4_adc_data adc_data[NUM_ADC] = {0};
+
+/**
+ * @brief Configure the ADC channel to be the specified one.
+ * An ADC contains multiple channels, so before each operation, we should
+ * select the wanted channel.
+ */
+static rtems_status_code stm32f4_adc_select_channel(
+rtems_adc *base
+);
+
+/***/
+/**
+ * ADC objects that have simple lock for mutex.
+ */
+#ifdef ADC1
+static ADC_TypeDef_Protected _ADC1_protected = { ADC1, false };
+ADC_TypeDef_Protected *const ADC1_protected = &_ADC1_protected;
+
+static rtems_status_code stm32f4_adc_get_adc1(uint32_t id, rtems_adc **out);
+#endif
+#ifdef ADC2
+static ADC_TypeDef_Protected _ADC2_protected = { ADC2, false };
+ADC_TypeDef_Protected *const ADC2_protected = &_ADC2_protected;
+
+static rtems_status_code stm32f4_adc_get_adc2(uint32_t id, rtems_adc **out);
+#endif
+#ifdef ADC3
+static ADC_TypeDef_Protected _ADC3_protected = { ADC3, false };
+ADC_TypeDef_Protected *const ADC3_protected = &_ADC3_protected;
+
+static rtems_status_code stm32f4_adc_get_adc3(uint32_t id, rtems_adc **out);
+#endif
+
+/* Helpers */
+#define STM32F4_GET_ADC_NUMBER(ADCx) \
+( (uintptr_t) ( ADCx ) == (uintptr_t) ADC1 ? 1 : \
+ (uintptr_t) ( ADCx ) == (uintptr_t) ADC2 ? 2 : \
+ (uintptr_t) ( ADCx ) == (uintptr_t) ADC3 ? 3 : \
+ 0 )
+#define STM32F4_GET_ADCx_FROM_NUMBER(num) (\
+( num ) == 1 ? ADC1 :\
+( num ) == 2 && NUM_ADC >= 2 ? ADC2 :\
+( num ) == 3 && NUM_ADC == 3 ? ADC3 :\
+ NULL)
+#define STM32F4_GET_ADCx_PROTECTED_FROM_NUMBER(num) (\
+( num ) == 1 ? ADC1_protected : \
+( num ) == 2 && NUM_ADC >= 2 ? ADC2_protected : \
+( num ) == 3 && NUM_ADC == 3 ? ADC3_protected : \
+ NULL)
+#define STM32F4_GET_LL_ADC_CHANNEL(num)(\
+( num ) == 0 ? LL_ADC_CHANNEL_0 : \
+( num ) ==
Adding third-party source with Apache-2.0 license
Dear all, I am working on a project that needs to include ST's STM32F4 HAL into RTEMS, specifically release v1.27.1 at: https://github.com/STMicroelectronics/STM32CubeF4. However, the CMSIS files in this repository have Apache-2.0 license. What do you think about this? Should I add them to RTEMS, or is there anything I need to do to include these sources? Thank you, Duc Doan ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: Adding third-party source with Apache-2.0 license
Hello Duc, Am 07.08.22 um 13:06 schrieb Duc Doan: Dear all, I am working on a project that needs to include ST's STM32F4 HAL into RTEMS, specifically release v1.27.1 at: https://github.com/STMicroelectronics/STM32CubeF4. However, the CMSIS files in this repository have Apache-2.0 license. What do you think about this? Should I add them to RTEMS, or is there anything I need to do to include these sources? Thanks for bringing up this issue. I think one important point is that all newer ARM CMSIS files are Apache 2.0: https://github.com/ARM-software/CMSIS_5 So that affects all ARM cores and not only STM32. From my point of view, we sooner or later have to accept this license if we don't want to maintain our own fork of ARM CMSIS. Best regards Christian Thank you, Duc Doan ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v3] cpukit/dev/can: Added CAN support
---
cpukit/dev/can/can.c | 515 +++
cpukit/include/dev/can/can-msg.h | 105 +
cpukit/include/dev/can/can-queue.h | 219 ++
cpukit/include/dev/can/can.h | 258
spec/build/cpukit/librtemscpu.yml| 6 +
spec/build/testsuites/libtests/can01.yml | 19 +
spec/build/testsuites/libtests/grp.yml | 2 +
testsuites/libtests/can01/init.c | 255 +++
8 files changed, 1379 insertions(+)
create mode 100644 cpukit/dev/can/can.c
create mode 100644 cpukit/include/dev/can/can-msg.h
create mode 100644 cpukit/include/dev/can/can-queue.h
create mode 100644 cpukit/include/dev/can/can.h
create mode 100644 spec/build/testsuites/libtests/can01.yml
create mode 100644 testsuites/libtests/can01/init.c
diff --git a/cpukit/dev/can/can.c b/cpukit/dev/can/can.c
new file mode 100644
index 00..59c95d0b99
--- /dev/null
+++ b/cpukit/dev/can/can.c
@@ -0,0 +1,515 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup CANBus
+ *
+ * @brief Controller Area Network (CAN) Bus Implementation
+ *
+ */
+
+/*
+ * Copyright (C) 2022 Prashanth S (fishesprasha...@gmail.com)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+
+#include
+
+#define can_interrupt_lock_acquire(bus) \
+ do { \
+ CAN_DEBUG_LOCK("acquiring lock %s:%d\n", __FILE__,
__LINE__); \
+ real_can_interrupt_lock_acquire(bus);
\
+ } while (0);
+
+#define can_interrupt_lock_release(bus) \
+ do { \
+ CAN_DEBUG_LOCK("releasing lock %s:%d\n", __FILE__,
__LINE__); \
+ real_can_interrupt_lock_release(bus);
\
+ } while (0);
+
+static ssize_t
+can_bus_open(rtems_libio_t *iop, const char *path, int oflag, mode_t mode);
+static ssize_t
+can_bus_read(rtems_libio_t *iop, void *buffer, size_t count);
+static ssize_t
+can_bus_write(rtems_libio_t *iop, const void *buffer, size_t count);
+static ssize_t
+can_bus_ioctl(rtems_libio_t *iop, ioctl_command_t request, void *buffer);
+
+static int can_xmit(struct can_bus *bus);
+
+static int can_create_sem(struct can_bus *);
+static int try_sem(struct can_bus *);
+static int take_sem(struct can_bus *);
+static int give_sem(struct can_bus *);
+
+/* sem_count this is for debug purpose, for debugging
+the take_sem and give_sem
+*/
+static int sem_count = 0;
+
+static void can_bus_obtain(can_bus *bus)
+{
+ rtems_recursive_mutex_lock(&bus->mutex);
+}
+
+static void can_bus_release(can_bus *bus)
+{
+ rtems_recursive_mutex_unlock(&bus->mutex);
+}
+
+static void can_bus_destroy_mutex(struct can_bus *bus)
+{
+ rtems_recursive_mutex_destroy(&bus->mutex);
+}
+
+static int can_create_sem(struct can_bus *bus)
+{
+ int ret = 0;
+
+ ret = rtems_semaphore_create(rtems_build_name('c', 'a', 'n', bus->index),
+ CAN_TX_BUF_COUNT, RTEMS_FIFO | RTEMS_COUNTING_SEMAPHORE | RTEMS_LOCAL,
+ 0, &bus->tx_fifo_sem_id);
+
+ if (ret != 0) {
+printf("can_create_sem: rtems_semaphore_create failed %d\n", ret);
+ }
+
+ return ret;
+}
+
+static void can_free_tx_semaphore(struct can_bus *bus)
+{
+ rtems_semaphore_delete(bus->tx_fifo_sem_id);
+}
+
+static void real_can_interrupt_lock_acquire(struct can_bus *bus)
+{
+ can_bus_obtain(bus);
+ bus->can_dev_ops->dev_int(bus->priv, false);
+}
+
+static void real_can_interrupt_lock_release(struct can_bus *bus)
+{
+ bus->can_dev_ops->dev_int(bus->priv, true);
+ can_bus_rel
Re: [PATCH] cpukit/dev/can: Added CAN support
Hi Christian,
general note: You add an API to cpukit. Most APIs there should have a
> test case in the testsuite. In this case the test case would have to
> create some dummy CAN driver and check whether everything works like
> expected. As an example take a look at the SPI test:
>
>https://git.rtems.org/rtems/tree/testsuites/libtests/spi01/init.c
>
> It creates a dummy device and checks whether the SPI layer does
> everything as expected. Would be great if you could add something like
> this. Target of such a test should be more or less that every branch in
> your code is triggered at least once (code coverage). It doesn't has to
> be every combination but it shows that the code is at least reachable
> and works as expected.
>
Adding a test application in testsuites/libtests/can01/init.c
Do you really mean "LOCK" or should it be a "LOG"? Both is reasonable
> here so I'm not entirely sure. But you use the LOCK macro also in
> can_xmit and similar so I'm a bit unsure.
>
It is a log for the lock. Now moved the logs and call to the lock
acquire/release to #defines.
> +if (sem_count > CAN_TX_BUF_COUNT) {
>
> If you increment sem_count only in a debug macro, you must not use it
> for any other code. The macro is processed by the preprocessor. So if
> you define the CAN_DEBUG_LOCK to something empty, the ++sem_count from
> above will never happen. If CAN_DEBUG_LOCK interpretes the argument
> twice, you will get the wrong value.
>
> Please note: It's in general a good idea not to use anything that
> changes a variable or has any side effect in a macro. For example if I
> define the following
>
>#define SQUARE(x) ((x) * (x))
>
> And use it like this:
>
>int a = 2;
>int b;
>b = SQUARE(++a);
>
> The result that I would expect from reading the code would be that b is
> 9 and a is 3 afterwards. But instead I will get b = 16 and a = 4. The
> reason for this is that the preprocessor will replace the code with the
> following one:
>
>int a = 2;
>int b;
>b = ((++a) * (++a));
>
> Therefore: Try to avoid statements with a side effect as a parameter to
> something if you are not 100% sure that the something is a function or
> is allways executed. You don't have to save lines. We don't have a limit
> on the maximum lines in a file. Readability is much more important than
> compact code.
>
> PS: Also true for "if". I wouldn't be sure whether the printf in the
> following code will be executed:
>
>if (0 || printf("Will someone call me?")) {
>}
>
> In general: Try to avoid anything where you have to think about the
> order of execution except if you can't avoid it or if it is really obvious.
Moved the increment out of the #define.
> +static int can_xmit(struct can_bus *bus)
> > +{
> > + int ret = RTEMS_SUCCESSFUL;
> > +
> > + struct can_msg *msg = NULL;
> > +
> > + while (1) {
> > +CAN_DEBUG_LOCK("can_xmit: acquiring lock\n");
> > +can_interrupt_lock_acquire(bus);
> > +
> > +ret = bus->can_dev_ops->dev_tx_ready(bus->priv);
> > +if (ret != true) {
> > + goto return_with_lock_release;
> > +}
> > +
> > +msg = can_tx_get_data_buf(bus);
> > +if (msg == NULL) {
> > + goto return_with_lock_release;
> > +}
> > +
> > +ret = bus->can_dev_ops->dev_tx(bus->priv, msg);
> > +if (ret != RTEMS_SUCCESSFUL) {
> > +printf("can_xmit: dev_send failed\n");
> > +}
> > +
> > +ret = give_sem(bus);
> > +if (ret != RTEMS_SUCCESSFUL) {
> > + printf("can_tx_done: rtems_semaphore_release failed = %d\n", ret);
> > +}
> > +
> > +CAN_DEBUG_LOCK("can_xmit: releasing lock\n");
> > +can_interrupt_lock_release(bus);
> > +
> > +//can_tx_done(bus);
> > + }
> > +
> > + return ret;
>
> If I see it correctly, you can never reach this return. You have a
> while(1) without any break condition. By the way: Code with goto, loops
> and break tends to get sphaghetti code. You should only use these
> constructions if it improves readability compared to a solution without
> these.
Updated to release the lock and break.
You use the macros a lot. You are aware that you could do something like
> that:
>
> - Declare the original can_interrupt_lock_acquire() as something with a
> prefix or postifix for example as real_can_interrupt_lock_acquire.
>
> - Then add a define that wrapps it with:
>
> #define can_interrupt_lock_acquire(...) do { \
> CAN_DEBUG_LOCK("%s:%d\n", __FILE__, __LINE__); \
> real_can_interrupt_lock_acquire(__VA_ARGS__);
> } while(0)
>
Then you can just write it as normal can_interrupt_lock_acquire but get
> a debug print with file and line on every call.
>
now moved the logs and call to the lock acquire/release to #defines.
> +can_interrupt_lock_acquire(bus);
> > +bus->can_tx_buf_waiters++;
> > +CAN_DEBUG_LOCK("can_bus_write: release lock
> can_tx_buf_waiters++\n");
> > +can_interrupt_lock_release(bus);
> > +
> > +ret = take_sem(bus);
> > +
> > +CAN_DEBUG_LOCK("can_bus_write: acqu
Re: [tools] tester: Sort test reports for JSON/YAML
OK I was also looking at sorting the tests in summary but for some reason I could not get it to work as I expected. I am still looking into it. Chris On 6/8/2022 12:42 am, Sebastian Huber wrote: > This makes the reports more git friendly. > > Update 4671. > --- > tester/rt/test.py | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tester/rt/test.py b/tester/rt/test.py > index 9549765..2b5ad85 100644 > --- a/tester/rt/test.py > +++ b/tester/rt/test.py > @@ -248,7 +248,7 @@ def results_to_data(args, reports, start_time, end_time): > run_data['arch'] = run['bsp_arch'] > reports_data.append(run_data) > > -data['reports'] = reports_data > +data['reports'] = sorted(reports_data, key=lambda x: x["executable"]) > return data > > ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] cpukit/dev/can: Added CAN support
Hi Could you please configure your email client to not send HTML emails to the list? I am reluctant to enable filtering in mailman and have managed to avoid it so far. Thanks Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: Adding third-party source with Apache-2.0 license
On 7/8/2022 10:20 pm, o...@c-mauderer.de wrote: > Am 07.08.22 um 13:06 schrieb Duc Doan: >> Dear all, >> >> I am working on a project that needs to include ST's STM32F4 HAL into >> RTEMS, specifically release v1.27.1 at: >> https://github.com/STMicroelectronics/STM32CubeF4. However, the CMSIS >> files in this repository have Apache-2.0 license. What do you think >> about this? Should I add them to RTEMS, or is there anything I need to >> do to include these sources? > > Thanks for bringing up this issue. I think one important point is that all > newer > ARM CMSIS files are Apache 2.0: > > https://github.com/ARM-software/CMSIS_5 > > So that affects all ARM cores and not only STM32. From my point of view, we > sooner or later have to accept this license if we don't want to maintain our > own > fork of ARM CMSIS. Apache requires any update carry a prominent notice plus NOTICE text files need special handling. How do you see that being handled? Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: Adding third-party source with Apache-2.0 license
Am 08.08.22 um 06:09 schrieb Chris Johns: On 7/8/2022 10:20 pm, o...@c-mauderer.de wrote: Am 07.08.22 um 13:06 schrieb Duc Doan: Dear all, I am working on a project that needs to include ST's STM32F4 HAL into RTEMS, specifically release v1.27.1 at: https://github.com/STMicroelectronics/STM32CubeF4. However, the CMSIS files in this repository have Apache-2.0 license. What do you think about this? Should I add them to RTEMS, or is there anything I need to do to include these sources? Thanks for bringing up this issue. I think one important point is that all newer ARM CMSIS files are Apache 2.0: https://github.com/ARM-software/CMSIS_5 So that affects all ARM cores and not only STM32. From my point of view, we sooner or later have to accept this license if we don't want to maintain our own fork of ARM CMSIS. Apache requires any update carry a prominent notice plus NOTICE text files need special handling. How do you see that being handled? Chris We have three problems: 1. NOTICE files. We have to add them to the code if they are there. We maybe need a decision whether we want to collect them at the root level or put them together with the code. Both have advantages and disadvantages, but that should be solvable. 2. The clause 4 b of the license: "You must cause any modified files to carry prominent notices stating that You changed the files". I think that's a two part solution: a) Mark all changes with "#ifdef __RTEMS__" like we do in libbsd. That's a good idea for all third party code that we might want to update in the future. b) Make a general statement that "Apache Code is adapted to work with RTEMS". That is oversimplified and needs fine-tuning like where the statement should be located, but I think that part is solvable too. 3. The most difficult problem: How can we manage the patch review. Every file that changes an Apache licensed file needs special review. Note that a good solution to this problem wouldn't be only useful for Apache license but could also help make changes in third party code more visible and therefore help with upgrading that code. At the moment I only have some rough ideas. Let's try to discuss them and see whether one of them could be an useable solution: a) Something that we could use as a general rule for third-party code: A special subdirectory like "third-party", "contrib" or "external". If one of these subdirectories appears in a patch, we know that we have to take a thorough look at these files. It's still manual and therefore error-prone. But it would be a start. b) We could add an option to have checksums for these files in the yaml files. If someone changes one of the files, the build system could throw a warning. Will need some work to change the build system and therefore is not a simple and quick solution, but it would automate the process. c) We could pull in external code only as submodules. That would prevent changes to that code at all. The big disadvantage is that it adds nasty external dependencies. The big problem with this is that the location of the external code can change or can be no longer available. It also is a big problem with the release process. Most likely not a good solution. Please feel free to add more ideas. Regardless what we decide: Maybe we should generate a documentation point about "Best Practices When Adding Third-Party Code" out the discussion? Best regards Christian -- embedded brains GmbH Herr Christian MAUDERER Dornierstr. 4 82178 Puchheim Germany email: christian.maude...@embedded-brains.de phone: +49-89-18 94 741 - 18 mobile: +49-176-152 206 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
