[PATCH] score: Use RTEMS_SMP in _Thread_Create_idle()
Conditional expressions with inline functions are not optimized away if
optimization is disabled. Avoid such expressions to prevent dead
branches.
---
cpukit/score/src/threadcreateidle.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/cpukit/score/src/threadcreateidle.c
b/cpukit/score/src/threadcreateidle.c
index 9f3c01d118..2f3b09c323 100644
--- a/cpukit/score/src/threadcreateidle.c
+++ b/cpukit/score/src/threadcreateidle.c
@@ -111,10 +111,10 @@ static void _Thread_Create_idle_for_CPU( Per_CPU_Control
*cpu )
void _Thread_Create_idle( void )
{
+#if defined(RTEMS_SMP)
uint32_t cpu_max;
uint32_t cpu_index;
- _System_state_Set( SYSTEM_STATE_BEFORE_MULTITASKING );
cpu_max = _SMP_Get_processor_maximum();
for ( cpu_index = 0 ; cpu_index < cpu_max ; ++cpu_index ) {
@@ -124,4 +124,9 @@ void _Thread_Create_idle( void )
_Thread_Create_idle_for_CPU( cpu );
}
}
+#else
+ _Thread_Create_idle_for_CPU( _Per_CPU_Get() );
+#endif
+
+ _System_state_Set( SYSTEM_STATE_BEFORE_MULTITASKING );
}
--
2.35.3
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[PATCH] validation: Test thread free of FPU owner
---
testsuites/validation/tc-score-thread.c | 74 +
1 file changed, 74 insertions(+)
diff --git a/testsuites/validation/tc-score-thread.c
b/testsuites/validation/tc-score-thread.c
index 53b939e3c5..88e86ca189 100644
--- a/testsuites/validation/tc-score-thread.c
+++ b/testsuites/validation/tc-score-thread.c
@@ -56,6 +56,7 @@
#include
#include
+#include "ts-config.h"
#include "tx-support.h"
#include
@@ -86,6 +87,14 @@
*
* - Clean up all used resources.
*
+ * - Delete a thread which least recently used the floating point coprocessor.
+ *
+ * - Start the worker thread. Let it use the floating point coprocessor.
+ *
+ * - Delete the worker thread and free the thread resources.
+ *
+ * - Clean up all used resources.
+ *
* @{
*/
@@ -102,6 +111,11 @@ typedef struct {
* @brief This member contains the killer task identifier.
*/
rtems_id killer_id;
+
+ /**
+ * @brief This member contains a floating-point object.
+ */
+ volatile double fp_obj;;
} ScoreThreadValThread_Context;
static ScoreThreadValThread_Context
@@ -126,6 +140,29 @@ static void WorkerTask( rtems_task_argument arg )
SuspendSelf();
}
+static void GoBackToRunner( void *arg )
+{
+ Context *ctx;
+
+ ctx = arg;
+ SetPriority( ctx->worker_id, PRIO_LOW );
+}
+
+static void FloatingPointTask( rtems_task_argument arg )
+{
+ Context *ctx;
+
+ ctx = (Context *) arg;
+ ctx->fp_obj *= 1.23;
+
+ /*
+ * We use an interrupt to go back to the runner since on some
+ * architectures, the floating-point context is only saved during interrupt
+ * processing and not for synchronous thread switches.
+ */
+ CallWithinISR( GoBackToRunner, ctx );
+}
+
static void KillerTask( rtems_task_argument arg )
{
Context *ctx;
@@ -216,6 +253,42 @@ static void ScoreThreadValThread_Action_0(
ScoreThreadValThread_Context *ctx )
T_rsc_success( sc );
}
+/**
+ * @brief Delete a thread which least recently used the floating point
+ * coprocessor.
+ */
+static void ScoreThreadValThread_Action_1( ScoreThreadValThread_Context *ctx )
+{
+ rtems_status_code sc;
+
+ SetSelfPriority( PRIO_NORMAL );
+ sc = rtems_task_create(
+rtems_build_name( 'W', 'O', 'R', 'K'),
+PRIO_HIGH,
+TEST_MINIMUM_STACK_SIZE,
+RTEMS_DEFAULT_MODES,
+RTEMS_FLOATING_POINT,
+&ctx->worker_id
+ );
+ T_rsc_success( sc );
+
+ /*
+ * Start the worker thread. Let it use the floating point coprocessor.
+ */
+ StartTask( ctx->worker_id, FloatingPointTask, ctx );
+
+ /*
+ * Delete the worker thread and free the thread resources.
+ */
+ DeleteTask( ctx->worker_id );
+ KillZombies();
+
+ /*
+ * Clean up all used resources.
+ */
+ RestoreRunnerPriority();
+}
+
/**
* @fn void T_case_body_ScoreThreadValThread( void )
*/
@@ -226,6 +299,7 @@ T_TEST_CASE_FIXTURE( ScoreThreadValThread,
&ScoreThreadValThread_Fixture )
ctx = T_fixture_context();
ScoreThreadValThread_Action_0( ctx );
+ ScoreThreadValThread_Action_1( ctx );
}
/** @} */
--
2.35.3
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[PATCH] rtems: Simplify rtems_scheduler_ident()
Use early returns to simplify rtems_scheduler_ident().
---
cpukit/rtems/src/schedulerident.c | 27 +++
1 file changed, 11 insertions(+), 16 deletions(-)
diff --git a/cpukit/rtems/src/schedulerident.c
b/cpukit/rtems/src/schedulerident.c
index e73d3d743a..60e7765ccd 100644
--- a/cpukit/rtems/src/schedulerident.c
+++ b/cpukit/rtems/src/schedulerident.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2014 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2014, 2022 embedded brains GmbH
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -46,25 +46,20 @@ rtems_status_code rtems_scheduler_ident(
rtems_id *id
)
{
- rtems_status_code sc;
+ size_t i;
- if ( id != NULL ) {
-size_t n = _Scheduler_Count;
-size_t i;
-
-sc = RTEMS_INVALID_NAME;
+ if ( id == NULL ) {
+return RTEMS_INVALID_ADDRESS;
+ }
-for ( i = 0 ; i < n && sc == RTEMS_INVALID_NAME ; ++i ) {
- const Scheduler_Control *scheduler = &_Scheduler_Table[ i ];
+ for ( i = 0; i < _Scheduler_Count; ++i ) {
+const Scheduler_Control *scheduler = &_Scheduler_Table[ i ];
- if ( scheduler->name == name ) {
-*id = _Scheduler_Build_id( i );
-sc = RTEMS_SUCCESSFUL;
- }
+if ( scheduler->name == name ) {
+ *id = _Scheduler_Build_id( i );
+ return RTEMS_SUCCESSFUL;
}
- } else {
-sc = RTEMS_INVALID_ADDRESS;
}
- return sc;
+ return RTEMS_INVALID_NAME;
}
--
2.35.3
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Re: [tools] tester: Remove hard coded time limits for SIS
On 5/7/2022 4:29 pm, Sebastian Huber wrote: > On 05/07/2022 08:23, Chris Johns wrote: >> On 5/7/2022 4:02 pm, Sebastian Huber wrote: >>> On 05/07/2022 07:14, Chris Johns wrote: On 5/7/2022 2:58 pm, Sebastian Huber wrote: > On 05/07/2022 03:08, Chris Johns wrote: >> On 5/7/2022 9:44 am, Joel Sherrill wrote: >>> The limit removed in sis and tsim is the simulated cpu time used. If not >>> using >>> that, the behavior of the tester is to let the simulator run for so much >>> real >>> processor time. >>> >>> Replacing these with a command line argument is probably good but just >>> removing >>> these mean these simulators will just run much longer before being >>> killed. >>> >>> How best to capture the distinction between target run time and host run >>> time? >> Thank you for the explanation. I was not sure how the option effected >> things >> and >> yes it does matter we have this set correctly. >> >> Options can be set in the $HOME/.rtemstesterrc is via the --user-config >> option. >> Maybe this can be used to control the time out for specific user tests? > I would not make this more complicated than necessary. We have a --timeout > command line option and the default timeout value can be set by *.ini > files. The > simulator speed is just a detail similar to running a target at 100MHz or > 1GHz. It is actually simpler to have this option and to measure time against the cpu time. The work loads on SMP hosts with qemu shows simulation timeouts are difficult to get right. >>> I don't know what is wrong with the patch. Overruling command line options >>> is >>> just bad. >> It does not work that way. When simulating the timeout in the tester is a >> catch >> all. It may triggered if the simulator locks up. With real hardware it is the >> timeout but that is a different use case. A simulator timeout is preferred >> when >> available. > > Ok, good. Who will fix this? I am sorry I am not following. The tests have valid times for the default optimisation. What is broken? Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [tools] tester: Remove hard coded time limits for SIS
On 05/07/2022 10:21, Chris Johns wrote: On 5/7/2022 4:29 pm, Sebastian Huber wrote: On 05/07/2022 08:23, Chris Johns wrote: On 5/7/2022 4:02 pm, Sebastian Huber wrote: On 05/07/2022 07:14, Chris Johns wrote: On 5/7/2022 2:58 pm, Sebastian Huber wrote: On 05/07/2022 03:08, Chris Johns wrote: On 5/7/2022 9:44 am, Joel Sherrill wrote: The limit removed in sis and tsim is the simulated cpu time used. If not using that, the behavior of the tester is to let the simulator run for so much real processor time. Replacing these with a command line argument is probably good but just removing these mean these simulators will just run much longer before being killed. How best to capture the distinction between target run time and host run time? Thank you for the explanation. I was not sure how the option effected things and yes it does matter we have this set correctly. Options can be set in the $HOME/.rtemstesterrc is via the --user-config option. Maybe this can be used to control the time out for specific user tests? I would not make this more complicated than necessary. We have a --timeout command line option and the default timeout value can be set by *.ini files. The simulator speed is just a detail similar to running a target at 100MHz or 1GHz. It is actually simpler to have this option and to measure time against the cpu time. The work loads on SMP hosts with qemu shows simulation timeouts are difficult to get right. I don't know what is wrong with the patch. Overruling command line options is just bad. It does not work that way. When simulating the timeout in the tester is a catch all. It may triggered if the simulator locks up. With real hardware it is the timeout but that is a different use case. A simulator timeout is preferred when available. Ok, good. Who will fix this? I am sorry I am not following. The tests have valid times for the default optimisation. What is broken? What is broken is that the --timeout command line option doesn't work with SIS because it uses hard coded values. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH] validation: Always test spurious interrupts
---
.../testsuites/validation/validation-intr.yml | 4 +++-
.../validation/validation-smp-only-0.yml | 2 --
.../validation/tc-bsp-interrupt-spurious.c| 24 ---
3 files changed, 13 insertions(+), 17 deletions(-)
diff --git a/spec/build/testsuites/validation/validation-intr.yml
b/spec/build/testsuites/validation/validation-intr.yml
index 3bef9b7c9c..ced15b9490 100644
--- a/spec/build/testsuites/validation/validation-intr.yml
+++ b/spec/build/testsuites/validation/validation-intr.yml
@@ -8,9 +8,11 @@ cxxflags: []
enabled-by: true
features: c cprogram
includes: []
-ldflags: []
+ldflags:
+- -Wl,--wrap=bsp_interrupt_handler_default
links: []
source:
+- testsuites/validation/tc-bsp-interrupt-spurious.c
- testsuites/validation/tc-intr-clear.c
- testsuites/validation/tc-intr-entry-install.c
- testsuites/validation/tc-intr-entry-remove.c
diff --git a/spec/build/testsuites/validation/validation-smp-only-0.yml
b/spec/build/testsuites/validation/validation-smp-only-0.yml
index fc4091b92e..7ed2f7c943 100644
--- a/spec/build/testsuites/validation/validation-smp-only-0.yml
+++ b/spec/build/testsuites/validation/validation-smp-only-0.yml
@@ -9,12 +9,10 @@ enabled-by: RTEMS_SMP
features: c cprogram
includes: []
ldflags:
-- -Wl,--wrap=bsp_interrupt_handler_default
- -Wl,--wrap=_Scheduler_EDF_SMP_Yield
links: []
source:
- testsuites/validation/tc-acfg-scheduler-edf-smp.c
-- testsuites/validation/tc-bsp-interrupt-spurious.c
- testsuites/validation/tc-intr-smp-only.c
- testsuites/validation/tc-scheduler-smp-only.c
- testsuites/validation/tc-sched-smp.c
diff --git a/testsuites/validation/tc-bsp-interrupt-spurious.c
b/testsuites/validation/tc-bsp-interrupt-spurious.c
index de139337da..0cb14f8f1a 100644
--- a/testsuites/validation/tc-bsp-interrupt-spurious.c
+++ b/testsuites/validation/tc-bsp-interrupt-spurious.c
@@ -63,7 +63,7 @@
* @defgroup RTEMSTestCaseBspReqInterruptSpurious \
* spec:/bsp/req/interrupt-spurious
*
- * @ingroup RTEMSTestSuiteTestsuitesValidationSmpOnly0
+ * @ingroup RTEMSTestSuiteTestsuitesValidationIntr
*
* @{
*/
@@ -416,28 +416,24 @@ static void BspReqInterruptSpurious_Action(
BspReqInterruptSpurious_Context *ctx
)
{
+ rtems_status_code sc;
+
ctx->interrupt_occurred = false;
ctx->entry_counter = 0;
ctx->fatal_counter = 0;
ctx->fatal_source = RTEMS_FATAL_SOURCE_LAST;
ctx->fatal_code = UINT32_MAX;
- if ( *ctx->first == NULL ) {
-rtems_status_code sc;
-
-(void) rtems_interrupt_vector_enable( ctx->test_vector );
-
-sc = rtems_interrupt_raise( ctx->test_vector );
-T_rsc_success( sc );
+ (void) rtems_interrupt_vector_enable( ctx->test_vector );
-while ( !ctx->interrupt_occurred ) {
- /* Wait */
-}
+ sc = rtems_interrupt_raise( ctx->test_vector );
+ T_rsc_success( sc );
-Disable( ctx );
- } else {
-bsp_interrupt_spurious( ctx->test_vector );
+ while ( !ctx->interrupt_occurred ) {
+/* Wait */
}
+
+ Disable( ctx );
}
static const BspReqInterruptSpurious_Entry
--
2.35.3
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[PATCH] validation: Test thread idle bodies
---
.../testsuites/validation/validation-0.yml| 1 +
.../tc-thread-idle-body-no-return.c | 194 ++
2 files changed, 195 insertions(+)
create mode 100644 testsuites/validation/tc-thread-idle-body-no-return.c
diff --git a/spec/build/testsuites/validation/validation-0.yml
b/spec/build/testsuites/validation/validation-0.yml
index 926b03240f..dffb1d0726 100644
--- a/spec/build/testsuites/validation/validation-0.yml
+++ b/spec/build/testsuites/validation/validation-0.yml
@@ -16,6 +16,7 @@ source:
- testsuites/validation/tc-mem-rtems-calloc.c
- testsuites/validation/tc-mem-rtems-malloc.c
- testsuites/validation/tc-mem-posix-memalign.c
+- testsuites/validation/tc-thread-idle-body-no-return.c
- testsuites/validation/tr-event-send-receive.c
- testsuites/validation/ts-validation-0.c
stlib: []
diff --git a/testsuites/validation/tc-thread-idle-body-no-return.c
b/testsuites/validation/tc-thread-idle-body-no-return.c
new file mode 100644
index 00..5234a460f9
--- /dev/null
+++ b/testsuites/validation/tc-thread-idle-body-no-return.c
@@ -0,0 +1,194 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSTestCaseScoreThreadValIdleBodyNoReturn
+ */
+
+/*
+ * Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+
+#include "tx-support.h"
+
+#include
+
+/**
+ * @defgroup RTEMSTestCaseScoreThreadValIdleBodyNoReturn \
+ * spec:/score/thread/val/idle-body-no-return
+ *
+ * @ingroup RTEMSTestSuiteTestsuitesValidation0
+ *
+ * @brief Tests thread idle body behaviour.
+ *
+ * This test case performs the following actions:
+ *
+ * - Create threads which execute an thread idle body. Check that the thread
+ * idle body does not return. If it would return, then an
+ * INTERNAL_ERROR_THREAD_EXITTED fatal error would occur.
+ *
+ * - Check that the CPU port thread idle body does not return.
+ *
+ * - Where the BSP provides an idle thread body, check that it does not
+ * return.
+ *
+ * - Clean up all used resources.
+ *
+ * @{
+ */
+
+/**
+ * @brief Test context for spec:/score/thread/val/idle-body-no-return test
+ * case.
+ */
+typedef struct {
+ /**
+ * @brief This member contains a counter.
+ */
+ uint32_t counter;;
+} ScoreThreadValIdleBodyNoReturn_Context;
+
+static ScoreThreadValIdleBodyNoReturn_Context
+ ScoreThreadValIdleBodyNoReturn_Instance;
+
+typedef ScoreThreadValIdleBodyNoReturn_Context Context;
+
+static void CheckIdleBody( Context *ctx, rtems_task_entry entry )
+{
+ rtems_id id;
+
+ ctx->counter = 0;
+ id = CreateTask( "WORK", PRIO_LOW );
+ StartTask( id, entry, ctx );
+
+ while ( ctx->counter == 0 ) {
+rtems_status_code sc;
+
+sc = rtems_task_wake_after( 1 );
+T_rsc_success( sc );
+ }
+
+ T_eq_u32( ctx->counter, 1 );
+ DeleteTask( id );
+}
+
+static void CPUThreadIdleBody( rtems_task_argument arg )
+{
+ Context *ctx;
+
+ ctx = (Context *) arg;
+ ++ctx->counter;
+
+ (void) _CPU_Thread_
Re: [tools] tester: Remove hard coded time limits for SIS
> On 5 Jul 2022, at 6:23 pm, Sebastian Huber > wrote: > > On 05/07/2022 10:21, Chris Johns wrote: >>> On 5/7/2022 4:29 pm, Sebastian Huber wrote: >>> On 05/07/2022 08:23, Chris Johns wrote: On 5/7/2022 4:02 pm, Sebastian Huber wrote: > On 05/07/2022 07:14, Chris Johns wrote: >> On 5/7/2022 2:58 pm, Sebastian Huber wrote: >>> On 05/07/2022 03:08, Chris Johns wrote: On 5/7/2022 9:44 am, Joel Sherrill wrote: > The limit removed in sis and tsim is the simulated cpu time used. If > not > using > that, the behavior of the tester is to let the simulator run for so > much > real > processor time. > > Replacing these with a command line argument is probably good but just > removing > these mean these simulators will just run much longer before being > killed. > > How best to capture the distinction between target run time and host > run > time? Thank you for the explanation. I was not sure how the option effected things and yes it does matter we have this set correctly. Options can be set in the $HOME/.rtemstesterrc is via the --user-config option. Maybe this can be used to control the time out for specific user tests? >>> I would not make this more complicated than necessary. We have a >>> --timeout >>> command line option and the default timeout value can be set by *.ini >>> files. The >>> simulator speed is just a detail similar to running a target at 100MHz >>> or >>> 1GHz. >> It is actually simpler to have this option and to measure time against >> the cpu >> time. The work loads on SMP hosts with qemu shows simulation timeouts are >> difficult to get right. > I don't know what is wrong with the patch. Overruling command line > options is > just bad. It does not work that way. When simulating the timeout in the tester is a catch all. It may triggered if the simulator locks up. With real hardware it is the timeout but that is a different use case. A simulator timeout is preferred when available. >>> >>> Ok, good. Who will fix this? >> I am sorry I am not following. The tests have valid times for the default >> optimisation. What is broken? > > What is broken is that the --timeout command line option doesn't work with > SIS because it uses hard coded values. The timeout option is correct and your understanding of it’s purpose is wrong. Joining them as you would like would break it. Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [tools] tester: Remove hard coded time limits for SIS
On 7/5/22 12:31, Chris Johns wrote: On 5 Jul 2022, at 6:23 pm, Sebastian Huber wrote: On 05/07/2022 10:21, Chris Johns wrote: On 5/7/2022 4:29 pm, Sebastian Huber wrote: On 05/07/2022 08:23, Chris Johns wrote: On 5/7/2022 4:02 pm, Sebastian Huber wrote: On 05/07/2022 07:14, Chris Johns wrote: On 5/7/2022 2:58 pm, Sebastian Huber wrote: On 05/07/2022 03:08, Chris Johns wrote: On 5/7/2022 9:44 am, Joel Sherrill wrote: The limit removed in sis and tsim is the simulated cpu time used. If not using that, the behavior of the tester is to let the simulator run for so much real processor time. Replacing these with a command line argument is probably good but just removing these mean these simulators will just run much longer before being killed. How best to capture the distinction between target run time and host run time? Thank you for the explanation. I was not sure how the option effected things and yes it does matter we have this set correctly. Options can be set in the $HOME/.rtemstesterrc is via the --user-config option. Maybe this can be used to control the time out for specific user tests? I would not make this more complicated than necessary. We have a --timeout command line option and the default timeout value can be set by *.ini files. The simulator speed is just a detail similar to running a target at 100MHz or 1GHz. It is actually simpler to have this option and to measure time against the cpu time. The work loads on SMP hosts with qemu shows simulation timeouts are difficult to get right. I don't know what is wrong with the patch. Overruling command line options is just bad. It does not work that way. When simulating the timeout in the tester is a catch all. It may triggered if the simulator locks up. With real hardware it is the timeout but that is a different use case. A simulator timeout is preferred when available. Ok, good. Who will fix this? I am sorry I am not following. The tests have valid times for the default optimisation. What is broken? What is broken is that the --timeout command line option doesn't work with SIS because it uses hard coded values. The timeout option is correct and your understanding of it’s purpose is wrong. Joining them as you would like would break it. I think that Sebastian has a point, a hard-coded value in the sis script prevents changing the time-out value from rtems-test. The timeout value in sis is in simulated CPU time, not host time. I am not sure how it works on the other simulators. If you would prefer host time time-outs, let me know and I will modify sis for this. Jiri. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [tools] tester: Remove hard coded time limits for SIS
On 05/07/2022 12:31, Chris Johns wrote: On 5 Jul 2022, at 6:23 pm, Sebastian Huber wrote: On 05/07/2022 10:21, Chris Johns wrote: On 5/7/2022 4:29 pm, Sebastian Huber wrote: On 05/07/2022 08:23, Chris Johns wrote: On 5/7/2022 4:02 pm, Sebastian Huber wrote: On 05/07/2022 07:14, Chris Johns wrote: On 5/7/2022 2:58 pm, Sebastian Huber wrote: On 05/07/2022 03:08, Chris Johns wrote: On 5/7/2022 9:44 am, Joel Sherrill wrote: The limit removed in sis and tsim is the simulated cpu time used. If not using that, the behavior of the tester is to let the simulator run for so much real processor time. Replacing these with a command line argument is probably good but just removing these mean these simulators will just run much longer before being killed. How best to capture the distinction between target run time and host run time? Thank you for the explanation. I was not sure how the option effected things and yes it does matter we have this set correctly. Options can be set in the $HOME/.rtemstesterrc is via the --user-config option. Maybe this can be used to control the time out for specific user tests? I would not make this more complicated than necessary. We have a --timeout command line option and the default timeout value can be set by *.ini files. The simulator speed is just a detail similar to running a target at 100MHz or 1GHz. It is actually simpler to have this option and to measure time against the cpu time. The work loads on SMP hosts with qemu shows simulation timeouts are difficult to get right. I don't know what is wrong with the patch. Overruling command line options is just bad. It does not work that way. When simulating the timeout in the tester is a catch all. It may triggered if the simulator locks up. With real hardware it is the timeout but that is a different use case. A simulator timeout is preferred when available. Ok, good. Who will fix this? I am sorry I am not following. The tests have valid times for the default optimisation. What is broken? What is broken is that the --timeout command line option doesn't work with SIS because it uses hard coded values. The timeout option is correct and your understanding of it’s purpose is wrong. Joining them as you would like would break it. It would be nice if someone could offer me a way to run tests which exceed the hard coded SIS timeout values? -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [tools] tester: Remove hard coded time limits for SIS
On 7/5/22 12:45, Sebastian Huber wrote: On 05/07/2022 12:31, Chris Johns wrote: On 5 Jul 2022, at 6:23 pm, Sebastian Huber wrote: On 05/07/2022 10:21, Chris Johns wrote: On 5/7/2022 4:29 pm, Sebastian Huber wrote: On 05/07/2022 08:23, Chris Johns wrote: On 5/7/2022 4:02 pm, Sebastian Huber wrote: On 05/07/2022 07:14, Chris Johns wrote: On 5/7/2022 2:58 pm, Sebastian Huber wrote: On 05/07/2022 03:08, Chris Johns wrote: On 5/7/2022 9:44 am, Joel Sherrill wrote: The limit removed in sis and tsim is the simulated cpu time used. If not using that, the behavior of the tester is to let the simulator run for so much real processor time. Replacing these with a command line argument is probably good but just removing these mean these simulators will just run much longer before being killed. How best to capture the distinction between target run time and host run time? Thank you for the explanation. I was not sure how the option effected things and yes it does matter we have this set correctly. Options can be set in the $HOME/.rtemstesterrc is via the --user-config option. Maybe this can be used to control the time out for specific user tests? I would not make this more complicated than necessary. We have a --timeout command line option and the default timeout value can be set by *.ini files. The simulator speed is just a detail similar to running a target at 100MHz or 1GHz. It is actually simpler to have this option and to measure time against the cpu time. The work loads on SMP hosts with qemu shows simulation timeouts are difficult to get right. I don't know what is wrong with the patch. Overruling command line options is just bad. It does not work that way. When simulating the timeout in the tester is a catch all. It may triggered if the simulator locks up. With real hardware it is the timeout but that is a different use case. A simulator timeout is preferred when available. Ok, good. Who will fix this? I am sorry I am not following. The tests have valid times for the default optimisation. What is broken? What is broken is that the --timeout command line option doesn't work with SIS because it uses hard coded values. The timeout option is correct and your understanding of it’s purpose is wrong. Joining them as you would like would break it. It would be nice if someone could offer me a way to run tests which exceed the hard coded SIS timeout values? sis accepts several -tlim options. The last one will be the active one. So rtems-test could add an extra -tlim option at the end of the sis parameters which would override the default one. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 0/4] Creating a new GPIO API and adding implementation for STM32F4 BSP
Hello, This patch adds a new GPIO API that aims at portability. GPIO of STM32F4 BSP has been implemented using this API. The sample application code can be found at https://github.com/dtbpkmte/GSoC-2022-RTEMS-Sample-Apps. Best, Duc Doan .gitignore | 1 + bsps/arm/include/cmsis_compiler.h | 266 + bsps/arm/include/cmsis_gcc.h | 1152 +- bsps/arm/include/cmsis_version.h |39 + bsps/arm/include/core_cm4.h| 4066 ++-- bsps/arm/include/core_cm7.h| 582 +- bsps/arm/include/legacy/cmsis_gcc.h| 1375 ++ bsps/arm/include/legacy/core_cm7.h | 2515 +++ bsps/arm/include/mpu_armv7.h | 270 + bsps/arm/stm32f4/gpio/gpio.c | 595 + bsps/arm/stm32f4/hal/Legacy/stm32f4xx_hal_can.c| 1679 ++ bsps/arm/stm32f4/hal/Legacy/stm32f4xx_hal_eth.c| 2307 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal.c | 615 + bsps/arm/stm32f4/hal/stm32f4xx_hal_adc.c | 2110 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_adc_ex.c| 1112 + bsps/arm/stm32f4/hal/stm32f4xx_hal_can.c | 2462 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cec.c | 996 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cortex.c| 502 + bsps/arm/stm32f4/hal/stm32f4xx_hal_crc.c | 328 + bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp.c | 7132 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_cryp_ex.c | 680 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dac.c | 1341 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dac_ex.c| 495 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi.c | 1161 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dcmi_ex.c | 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dfsdm.c | 4423 bsps/arm/stm32f4/hal/stm32f4xx_hal_dma.c | 1305 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dma2d.c | 2126 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_dma_ex.c| 313 + bsps/arm/stm32f4/hal/stm32f4xx_hal_dsi.c | 2760 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_eth.c | 3112 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_exti.c | 547 + bsps/arm/stm32f4/hal/stm32f4xx_hal_flash.c | 775 + bsps/arm/stm32f4/hal/stm32f4xx_hal_flash_ex.c | 1347 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_flash_ramfunc.c | 172 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpi2c.c| 6864 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpi2c_ex.c | 258 + bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpsmbus.c | 2749 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_fmpsmbus_ex.c | 145 + bsps/arm/stm32f4/hal/stm32f4xx_hal_gpio.c | 533 + bsps/arm/stm32f4/hal/stm32f4xx_hal_hash.c | 3514 bsps/arm/stm32f4/hal/stm32f4xx_hal_hash_ex.c | 1040 + bsps/arm/stm32f4/hal/stm32f4xx_hal_hcd.c | 1728 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c.c | 7524 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2c_ex.c| 182 + bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s.c | 2094 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_i2s_ex.c| 1135 + bsps/arm/stm32f4/hal/stm32f4xx_hal_irda.c | 2687 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_iwdg.c | 262 + bsps/arm/stm32f4/hal/stm32f4xx_hal_lptim.c | 2484 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc.c | 2215 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_ltdc_ex.c | 151 + bsps/arm/stm32f4/hal/stm32f4xx_hal_mmc.c | 3201 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_msp_template.c | 100 + bsps/arm/stm32f4/hal/stm32f4xx_hal_nand.c | 2405 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_nor.c | 1543 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pccard.c| 946 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd.c | 2387 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_pcd_ex.c| 341 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr.c | 571 + bsps/arm/stm32f4/hal/stm32f4xx_hal_pwr_ex.c| 600 + bsps/arm/stm32f4/hal/stm32f4xx_hal_qspi.c | 2915 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rcc.c | 1122 + bsps/arm/stm32f4/hal/stm32f4xx_hal_rcc_ex.c| 3784 bsps/arm/stm32f4/hal/stm32f4xx_hal_rng.c | 867 + bsps/arm/stm32f4/hal/stm32f4xx_hal_rtc.c | 1896 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_rtc_ex.c| 1878 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sai.c | 2554 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sai_ex.c| 310 + bsps/arm/stm32f4/hal/stm32f4xx_hal_sd.c| 3277 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_sdram.c | 1308 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_smartcard.c | 2364 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_smbus.c | 2784 +++ bsps/arm/stm32f4/hal/stm32f4xx_hal_spdifrx.c | 1627 ++ bsps/arm/stm32f4/hal/stm32f4xx_hal_spi.c | 3915 bsps/arm/stm32f4/hal/
[PATCH 3/4] GPIO API: Add GPIO API
---
bsps/include/bsp/gpio2.h| 538
bsps/shared/dev/gpio/gpio.c | 196 +
spec/build/bsps/obj.yml | 2 +-
3 files changed, 735 insertions(+), 1 deletion(-)
create mode 100644 bsps/include/bsp/gpio2.h
create mode 100644 bsps/shared/dev/gpio/gpio.c
diff --git a/bsps/include/bsp/gpio2.h b/bsps/include/bsp/gpio2.h
new file mode 100644
index 00..e99967cd47
--- /dev/null
+++ b/bsps/include/bsp/gpio2.h
@@ -0,0 +1,538 @@
+/**
+ * @file
+ *
+ * @ingroup rtems_gpio2
+ *
+ * @brief RTEMS GPIO new API definition.
+ */
+
+/*
+* Copyright (c) 2022 Duc Doan
+*
+* The license and distribution terms for this file may be
+* found in the file LICENSE in this distribution or at
+* http://www.rtems.org/license/LICENSE.
+*/
+
+#ifndef LIBBSP_BSP_GPIO2_H
+#define LIBBSP_BSP_GPIO2_H
+
+#include
+#include
+
+/**
+ * Configure the maximum number of GPIO controllers used in
+ * a application.
+ *
+ * The macro CONFIGURE_GPIO_MAXIMUM_CONTROLLERS can be
+ * defined in application code. If it is not defined,
+ * it will default to BSP_GPIO_NUM_CONTROLLERS. If BSP's
+ * number of controllers is not defined, it will default
+ * to 1.
+ */
+#ifndef CONFIGURE_GPIO_MAXIMUM_CONTROLLERS
+
+#ifndef BSP_GPIO_NUM_CONTROLLERS
+#define CONFIGURE_GPIO_MAXIMUM_CONTROLLERS 1
+#else
+#define CONFIGURE_GPIO_MAXIMUM_CONTROLLERS BSP_GPIO_NUM_CONTROLLERS
+#endif /* BSP_GPIO_NUM_CONTROLLERS */
+
+#endif /* CONFIGURE_GPIO_MAXIMUM_CONTROLLERS */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @name GPIO data structures
+ *
+ * @{
+ */
+
+/**
+ * @brief GPIO bit set and reset enumeration.
+ */
+typedef enum {
+RTEMS_GPIO_PIN_RESET = 0,
+RTEMS_GPIO_PIN_SET = 1
+} rtems_gpio_pin_state;
+
+/**
+ * @brief GPIO pin modes.
+ */
+typedef enum {
+RTEMS_GPIO_PINMODE_OUTPUT = 0,
+RTEMS_GPIO_PINMODE_OUTPUT_PP = 0,
+RTEMS_GPIO_PINMODE_OUTPUT_OD = 1,
+RTEMS_GPIO_PINMODE_INPUT = 2,
+RTEMS_GPIO_PINMODE_ANALOG = 3,
+RTEMS_GPIO_PINMODE_BSP_SPECIFIC = 4
+} rtems_gpio_pin_mode;
+
+/**
+ * @brief GPIO pull resistor configuration. Defines pull-up or
+ *pull-down activation.
+ */
+typedef enum {
+RTEMS_GPIO_NOPULL,
+RTEMS_GPIO_PULLUP,
+RTEMS_GPIO_PULLDOWN
+} rtems_gpio_pull;
+
+/**
+ * @brief Interrupt modes enumeration.
+ */
+typedef enum {
+RTEMS_GPIO_INT_TRIG_NONE = 0,
+RTEMS_GPIO_INT_TRIG_FALLING,
+RTEMS_GPIO_INT_TRIG_RISING,
+RTEMS_GPIO_INT_TRIG_BOTH_EDGES,
+RTEMS_GPIO_INT_TRIG_LOW,
+RTEMS_GPIO_INT_TRIG_HIGH
+} rtems_gpio_interrupt_trig;
+
+typedef struct rtems_gpio_handlers rtems_gpio_handlers;
+typedef struct rtems_gpio rtems_gpio;
+/**
+ * @brief Typedef of the function pointer of an ISR.
+ */
+typedef void (*rtems_gpio_isr)(void *);
+
+/**
+ * @brief Structure containing pointers to handlers of a
+ *BSP/driver. Each BSP/driver must define its own
+ *handlers and create an object of this structure
+ *with pointers to those handlers.
+ */
+struct rtems_gpio_handlers {
+/**
+ * @brief This member is the pointer to an initialize handler.
+ *
+ * This handler could be used to perform some set up steps for
+ * a GPIO object (which means a pin or a port).
+ */
+rtems_status_code (*init)(rtems_gpio *);
+
+/**
+ * @brief This member is the pointer to a deinitialize handler.
+ *
+ * This handler could be used to deinitialize a GPIO object.
+ */
+rtems_status_code (*deinit)(rtems_gpio *);
+
+/**
+ * @brief This member is the pointer to a handler for setting
+ *pin mode.
+ *
+ * Pin modes are from rtems_gpio_pin_mode enumeration.
+ */
+rtems_status_code (*set_pin_mode)(rtems_gpio *, rtems_gpio_pin_mode);
+
+/**
+ * @brief This member is the pointer to a handler for setting
+ *pull resistor mode.
+ *
+ * Pull resistor modes are from rtems_gpio_pull enumeration.
+ */
+rtems_status_code (*set_pull)(rtems_gpio *, rtems_gpio_pull);
+
+/**
+ * @brief This member is the pointer to a handler for configuring
+ *interrupt of a pin.
+ *
+ * This handler should register ISR and its argument, interrupt
+ * trigger mode, and pull resister mode for the pin.
+ *
+ * @note Enabling interrupt should be done in enable_interrupt()
+ * handler.
+ */
+rtems_status_code (*configure_interrupt)(rtems_gpio *, rtems_gpio_isr,
void *, rtems_gpio_interrupt_trig, rtems_gpio_pull);
+
+/**
+ * @brief This member is the pointer to a handler for removing
+ *interrupt settings of a pin.
+ *
+ * Interrupt settings can be ISR address, pin configuration, etc.
+ */
+rtems_status_code (*remove_interrupt)(rtems_gpio *);
+
+/**
+ * @brief This member is the pointer to a handler for enabling
+ *interrupt functional
[PATCH 4/4] STM32F4 GPIO: Add GPIO implementation for STM32F4
---
bsps/arm/stm32f4/gpio/gpio.c | 595 ++
bsps/arm/stm32f4/include/bsp.h| 4 -
bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h | 37 ++
bsps/arm/stm32f4/include/bsp/stm32f4_hal.h| 17 +
bsps/arm/stm32f4/start/bspstart.c | 11 +-
spec/build/bsps/arm/stm32f4/grp.yml | 4 +-
.../build/bsps/arm/stm32f4/optnumgpioctrl.yml | 16 +
7 files changed, 674 insertions(+), 10 deletions(-)
create mode 100644 bsps/arm/stm32f4/gpio/gpio.c
create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4_gpio.h
create mode 100644 bsps/arm/stm32f4/include/bsp/stm32f4_hal.h
create mode 100644 spec/build/bsps/arm/stm32f4/optnumgpioctrl.yml
diff --git a/bsps/arm/stm32f4/gpio/gpio.c b/bsps/arm/stm32f4/gpio/gpio.c
new file mode 100644
index 00..e971f91140
--- /dev/null
+++ b/bsps/arm/stm32f4/gpio/gpio.c
@@ -0,0 +1,595 @@
+/**
+ * @file
+ *
+ * @ingroup rtems_bsp/arm/stm32f4
+ *
+ * @brief RTEMS GPIO new API implementation for STM32F4.
+ *
+ * @note RTEMS_GPIO_PINMODE_BSP_SPECIFIC is Alternate mode for STM32F4 BSP
+ */
+
+/*
+ * Copyright (c) 2022 Duc Doan
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include
+#include
+#include
+#include
+
+/*** Helpers */
+static stm32f4_gpio *get_gpio_from_base(
+rtems_gpio *base
+);
+
+/*** GPIO API ***/
+static rtems_status_code stm32f4_gpio_get(
+uint32_t interm_pin,
+rtems_gpio **out
+);
+
+static rtems_status_code stm32f4_gpio_destroy(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_init(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_deinit(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_set_pin_mode(
+rtems_gpio *base,
+rtems_gpio_pin_mode mode
+);
+
+static rtems_status_code stm32f4_gpio_set_pull(
+rtems_gpio *base,
+rtems_gpio_pull pull
+);
+
+static rtems_status_code stm32f4_gpio_configure_interrupt(
+rtems_gpio *base,
+rtems_gpio_isr isr,
+void *arg,
+rtems_gpio_interrupt_trig trig,
+rtems_gpio_pull pull
+);
+
+static rtems_status_code stm32f4_gpio_remove_interrupt(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_enable_interrupt(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_disable_interrupt(
+rtems_gpio *base
+);
+
+static rtems_status_code stm32f4_gpio_read(
+rtems_gpio *base,
+rtems_gpio_pin_state *value
+);
+
+static rtems_status_code stm32f4_gpio_write(
+rtems_gpio *base,
+rtems_gpio_pin_state value
+);
+
+static rtems_status_code stm32f4_gpio_toggle(
+rtems_gpio *base
+);
+
+/*/
+
+/**
+ * @brief STM32F4 GPIO handlers
+ */
+static const rtems_gpio_handlers stm32f4_gpio_handlers = {
+.init = stm32f4_gpio_init,
+.deinit = stm32f4_gpio_deinit,
+.set_pin_mode = stm32f4_gpio_set_pin_mode,
+.set_pull = stm32f4_gpio_set_pull,
+.configure_interrupt = stm32f4_gpio_configure_interrupt,
+.remove_interrupt = stm32f4_gpio_remove_interrupt,
+.enable_interrupt = stm32f4_gpio_enable_interrupt,
+.disable_interrupt = stm32f4_gpio_disable_interrupt,
+.read = stm32f4_gpio_read,
+.write = stm32f4_gpio_write,
+.toggle = stm32f4_gpio_toggle
+};
+
+static GPIO_TypeDef *GPIOx[] = {
+GPIOA, GPIOB, GPIOC, GPIOD, GPIOE,
+GPIOF, GPIOG, GPIOH, GPIOI,
+#ifdef STM32F429X
+GPIOJ, GPIOK
+#endif /* STM32F429X */
+};
+
+static uint16_t GPIO_PIN_x[] = {
+GPIO_PIN_0,
+GPIO_PIN_1,
+GPIO_PIN_2,
+GPIO_PIN_3,
+GPIO_PIN_4,
+GPIO_PIN_5,
+GPIO_PIN_6,
+GPIO_PIN_7,
+GPIO_PIN_8,
+GPIO_PIN_9,
+GPIO_PIN_10,
+GPIO_PIN_11,
+GPIO_PIN_12,
+GPIO_PIN_13,
+GPIO_PIN_14,
+GPIO_PIN_15
+};
+
+static uint32_t LL_EXTI_LINE_x[] = {
+LL_EXTI_LINE_0,
+LL_EXTI_LINE_1,
+LL_EXTI_LINE_2,
+LL_EXTI_LINE_3,
+LL_EXTI_LINE_4,
+LL_EXTI_LINE_5,
+LL_EXTI_LINE_6,
+LL_EXTI_LINE_7,
+LL_EXTI_LINE_8,
+LL_EXTI_LINE_9,
+LL_EXTI_LINE_10,
+LL_EXTI_LINE_11,
+LL_EXTI_LINE_12,
+LL_EXTI_LINE_13,
+LL_EXTI_LINE_14,
+LL_EXTI_LINE_15
+};
+
+static unsigned int EXTIx_IRQn[] = {
+EXTI0_IRQn,
+EXTI1_IRQn,
+EXTI2_IRQn,
+EXTI3_IRQn,
+EXTI4_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI9_5_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn,
+EXTI15_10_IRQn
+};
+
+/**
+ * @brief Converts intermediate pin number to port pointer.
+ *
+ * Intermediate pin number is a way of numerically labeling
+ * pins. Pins are labeled incrementally across all ports.
+ * Pins 0-15 from port A are 0-15. Pins 0-15 from port B are
+ * 16-31. And so on.
+ *
+ * @param interm_pin is the int
Re: [PATCH 0/4] Creating a new GPIO API and adding implementation for STM32F4 BSP
Hello, Please find my patches here: PATCH 1/4: https://github.com/dtbpkmte/GSoC-2022-RTEMS/commit/df255bbc3ff80a596ff329964fe0673f0141a522 PATCH 2/4: https://github.com/dtbpkmte/GSoC-2022-RTEMS/commit/5a814d4e5f8af3f78ffcf62a7e7da331843f168a PATCH 3/4: https://github.com/dtbpkmte/GSoC-2022-RTEMS/commit/d226d07b8985da2f4135340dac9593089d64b49d PATCH 4/4: https://github.com/dtbpkmte/GSoC-2022-RTEMS/commit/f415cc0a2b58f0ae5f2219f2ef96ca7c429d66f6 They were too big that I could not send via email. Best, Duc Doan ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 4/4] STM32F4 GPIO: Add GPIO implementation for STM32F4
Hello,
Have you tried a tiny bit to optimize this code because at a quick
glance, it sounds like for critical routines, you choose some slow and
complicated ways to do simple things, see a few some example below:
+static uint16_t GPIO_PIN_x[] = {
+GPIO_PIN_0,
+GPIO_PIN_1,
+GPIO_PIN_2,
+GPIO_PIN_3,
+GPIO_PIN_4,
+GPIO_PIN_5,
+GPIO_PIN_6,
+GPIO_PIN_7,
+GPIO_PIN_8,
+GPIO_PIN_9,
+GPIO_PIN_10,
+GPIO_PIN_11,
+GPIO_PIN_12,
+GPIO_PIN_13,
+GPIO_PIN_14,
+GPIO_PIN_15
+};
[...]
+
+/**
+ * @brief Converts pin number from 0-15 to HAL pin mask.
+ * @param pin is the pin number from 0-15
+ */
+#define STM32F4_GET_HAL_GPIO_PIN(pin) (GPIO_PIN_x[( pin )])
So, one macro and one static array indirection to basically write "1<
+/**
+ * @note Warning: only one pin can be passed as argument
+ * @note If using interrupt mode, use rtems_gpio_configure_interrupt().
+ * @note If using alternate mode, use rtems_gpio_configure().
+ */
+rtems_status_code stm32f4_gpio_set_pin_mode(
+rtems_gpio *base,
+rtems_gpio_pin_mode mode
+)
+{
[...]
+LL_GPIO_SetPinMode(gpio->port, pin_mask, stm32f4_mode);
+if (stm32f4_mode == LL_GPIO_MODE_OUTPUT) {
+LL_GPIO_SetPinOutputType(gpio->port, pin_mask, stm32f4_output_type);
+}
+
+return RTEMS_SUCCESSFUL;
+}
Here I see that you're using the new, low level, API. That's very good.
RTEMS should really only use the Low Level API everywhere possible.
+rtems_status_code stm32f4_gpio_write(
+rtems_gpio *base,
+rtems_gpio_pin_state value
+)
+{
+stm32f4_gpio *gpio = get_gpio_from_base(base);
+uint32_t pin_mask = STM32F4_GET_HAL_GPIO_PIN(gpio->pin);
+
+HAL_GPIO_WritePin(gpio->port, pin_mask, value);
+return RTEMS_SUCCESSFUL;
+}
In particular here, this function should be fast, and you do 2 function
calls plus one unneeded array indirection.
Why not simply something like (totally untested):
rtems_status_code stm32f4_gpio_write(
rtems_gpio *base,
rtems_gpio_pin_state value
)
{
stm32f4_gpio *gpio = RTEMS_CONTAINER_OF(base, stm32f4_gpio, base);
if (value)
gpio->BSRR = 1 << gpio->pin;
// or LL_GPIO_SetOutputPin(gpio, 1 << gpio->pin)
else
gpio->BSRR = 1 << (gpio->pin + 16);
// or LL_GPIO_ResetOutputPin(gpio, 1 << gpio->pin)
}
As a general rule, I believe that RTEMS should stop using the HAL for
all simple devices.
The HAL is fine for complicated IPs like Ethernet, USB, memory controller.
For simple IPs (serial, CAN, gpio, DMA, everything else) the HAL is just
a huge fat pile of slow and unnecessary code.
ST was forced to develop the LL API after everyone complained about the HAL.
Thanks,
Cedric
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[PATCH] cpukit/aarch64: Remove _CPU_ISR_install_vector
This function was never actually used and is dead code.
---
cpukit/score/cpu/aarch64/cpu.c| 25 ---
.../cpu/aarch64/include/rtems/score/cpu.h | 6 -
2 files changed, 31 deletions(-)
diff --git a/cpukit/score/cpu/aarch64/cpu.c b/cpukit/score/cpu/aarch64/cpu.c
index f0062adf30..923f53da08 100644
--- a/cpukit/score/cpu/aarch64/cpu.c
+++ b/cpukit/score/cpu/aarch64/cpu.c
@@ -174,31 +174,6 @@ uint32_t _CPU_ISR_Get_level( void )
return ( level & AARCH64_PSTATE_I ) != 0;
}
-void _CPU_ISR_install_vector(
- uint32_t vector,
- CPU_ISR_handler new_handler,
- CPU_ISR_handler *old_handler
-)
-{
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Warray-bounds"
- /* Redirection table starts at the end of the vector table */
- CPU_ISR_handler *table = (CPU_ISR_handler *) (MAX_EXCEPTIONS * 4);
-
- CPU_ISR_handler current_handler = table [vector];
-
- /* The current handler is now the old one */
- if (old_handler != NULL) {
-*old_handler = current_handler;
- }
-
- /* Write only if necessary to avoid writes to a maybe read-only memory */
- if (current_handler != new_handler) {
-table [vector] = new_handler;
- }
-#pragma GCC diagnostic pop
-}
-
void _CPU_Initialize( void )
{
/* Do nothing */
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
index fdc0e3d929..47a8e97985 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
@@ -306,12 +306,6 @@ void _CPU_Initialize( void );
typedef void ( *CPU_ISR_handler )( void );
-void _CPU_ISR_install_vector(
- uint32_t vector,
- CPU_ISR_handler new_handler,
- CPU_ISR_handler *old_handler
-);
-
/**
* @brief CPU switch context.
*/
--
2.30.2
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[PATCH] bsps/aarch64: Use MMU pages appropriately
There were two bugs with MMU page use that were partially hiding each
other. The linker script page table section was 4x the size it needed to
be and the page table allocation routine was allocating pages PTRSIZE
times larger than it needed to. On ILP32, this resulted in incorrect but
functional allocation. On LP64, this resulted in allocation failures
earlier than expected.
---
bsps/aarch64/include/bsp/aarch64-mmu.h | 4 ++--
spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml | 6 +++---
spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml | 6 +++---
spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_ilp32.yml | 6 +++---
spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_lp64.yml | 6 +++---
5 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/bsps/aarch64/include/bsp/aarch64-mmu.h
b/bsps/aarch64/include/bsp/aarch64-mmu.h
index 6e589cd6cd..bca7e0ce8d 100644
--- a/bsps/aarch64/include/bsp/aarch64-mmu.h
+++ b/bsps/aarch64/include/bsp/aarch64-mmu.h
@@ -145,8 +145,8 @@ BSP_START_TEXT_SECTION static inline rtems_status_code
aarch64_mmu_page_table_alloc( uint64_t **page_table )
{
/* First page table is already in use as TTB0 */
- static uintptr_t *current_page_table =
-(uintptr_t *) bsp_translation_table_base;
+ static uintptr_t current_page_table =
+(uintptr_t) bsp_translation_table_base;
current_page_table += MMU_PAGE_SIZE;
*page_table = (uint64_t *) current_page_table;
diff --git a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml
b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml
index 3030fd0ae9..2d7a922495 100644
--- a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml
+++ b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml
@@ -29,9 +29,9 @@ content: |
*/
MEMORY {
-RAM : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} -
${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} -
(0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
-NOCACHE : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 *
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH},
LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
-RAM_MMU : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 *
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x4000 *
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
+RAM : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} -
${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} -
(0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
+NOCACHE : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 *
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH},
LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
+RAM_MMU : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 *
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x1000 *
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
}
REGION_ALIAS ("REGION_START", RAM);
diff --git a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml
b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml
index bd5d1f791b..76c0220f0e 100644
--- a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml
+++ b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml
@@ -29,9 +29,9 @@ content: |
*/
MEMORY {
-RAM : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} -
${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} -
(0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
-NOCACHE : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 *
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH},
LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
-RAM_MMU : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 *
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x4000 *
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
+RAM : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} -
${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} -
(0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
+NOCACHE : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 *
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH},
LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
+RAM_MMU : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 *
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x1000 *
${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
}
REGION_ALIAS ("REGION_START",
Re: [PATCH] cpukit/aarch64: Remove _CPU_ISR_install_vector
OK.
On Tue, Jul 5, 2022 at 2:36 PM Kinsey Moore
wrote:
> This function was never actually used and is dead code.
> ---
> cpukit/score/cpu/aarch64/cpu.c| 25 ---
> .../cpu/aarch64/include/rtems/score/cpu.h | 6 -
> 2 files changed, 31 deletions(-)
>
> diff --git a/cpukit/score/cpu/aarch64/cpu.c
> b/cpukit/score/cpu/aarch64/cpu.c
> index f0062adf30..923f53da08 100644
> --- a/cpukit/score/cpu/aarch64/cpu.c
> +++ b/cpukit/score/cpu/aarch64/cpu.c
> @@ -174,31 +174,6 @@ uint32_t _CPU_ISR_Get_level( void )
>return ( level & AARCH64_PSTATE_I ) != 0;
> }
>
> -void _CPU_ISR_install_vector(
> - uint32_t vector,
> - CPU_ISR_handler new_handler,
> - CPU_ISR_handler *old_handler
> -)
> -{
> -#pragma GCC diagnostic push
> -#pragma GCC diagnostic ignored "-Warray-bounds"
> - /* Redirection table starts at the end of the vector table */
> - CPU_ISR_handler *table = (CPU_ISR_handler *) (MAX_EXCEPTIONS * 4);
> -
> - CPU_ISR_handler current_handler = table [vector];
> -
> - /* The current handler is now the old one */
> - if (old_handler != NULL) {
> -*old_handler = current_handler;
> - }
> -
> - /* Write only if necessary to avoid writes to a maybe read-only memory
> */
> - if (current_handler != new_handler) {
> -table [vector] = new_handler;
> - }
> -#pragma GCC diagnostic pop
> -}
> -
> void _CPU_Initialize( void )
> {
>/* Do nothing */
> diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
> b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
> index fdc0e3d929..47a8e97985 100644
> --- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
> +++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
> @@ -306,12 +306,6 @@ void _CPU_Initialize( void );
>
> typedef void ( *CPU_ISR_handler )( void );
>
> -void _CPU_ISR_install_vector(
> - uint32_t vector,
> - CPU_ISR_handler new_handler,
> - CPU_ISR_handler *old_handler
> -);
> -
> /**
> * @brief CPU switch context.
> */
> --
> 2.30.2
>
> ___
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> devel@rtems.org
> http://lists.rtems.org/mailman/listinfo/devel
>
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Re: [PATCH] bsps/aarch64: Use MMU pages appropriately
I'm ok with this. But Chris should speak up about the Versal.
On Tue, Jul 5, 2022 at 2:36 PM Kinsey Moore
wrote:
> There were two bugs with MMU page use that were partially hiding each
> other. The linker script page table section was 4x the size it needed to
> be and the page table allocation routine was allocating pages PTRSIZE
> times larger than it needed to. On ILP32, this resulted in incorrect but
> functional allocation. On LP64, this resulted in allocation failures
> earlier than expected.
> ---
> bsps/aarch64/include/bsp/aarch64-mmu.h | 4 ++--
> spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml | 6 +++---
> spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml | 6 +++---
> spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_ilp32.yml | 6 +++---
> spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_lp64.yml | 6 +++---
> 5 files changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/bsps/aarch64/include/bsp/aarch64-mmu.h
> b/bsps/aarch64/include/bsp/aarch64-mmu.h
> index 6e589cd6cd..bca7e0ce8d 100644
> --- a/bsps/aarch64/include/bsp/aarch64-mmu.h
> +++ b/bsps/aarch64/include/bsp/aarch64-mmu.h
> @@ -145,8 +145,8 @@ BSP_START_TEXT_SECTION static inline rtems_status_code
> aarch64_mmu_page_table_alloc( uint64_t **page_table )
> {
>/* First page table is already in use as TTB0 */
> - static uintptr_t *current_page_table =
> -(uintptr_t *) bsp_translation_table_base;
> + static uintptr_t current_page_table =
> +(uintptr_t) bsp_translation_table_base;
>
>current_page_table += MMU_PAGE_SIZE;
>*page_table = (uint64_t *) current_page_table;
> diff --git a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml
> b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml
> index 3030fd0ae9..2d7a922495 100644
> --- a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml
> +++ b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml
> @@ -29,9 +29,9 @@ content: |
> */
>
>MEMORY {
> -RAM : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH}
> - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} -
> (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
> -NOCACHE : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 *
> ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) -
> ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH =
> ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
> -RAM_MMU : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 *
> ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x4000 *
> ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
> +RAM : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH}
> - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} -
> (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
> +NOCACHE : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 *
> ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) -
> ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH =
> ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
> +RAM_MMU : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 *
> ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x1000 *
> ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
>}
>
>REGION_ALIAS ("REGION_START", RAM);
> diff --git a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml
> b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml
> index bd5d1f791b..76c0220f0e 100644
> --- a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml
> +++ b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml
> @@ -29,9 +29,9 @@ content: |
> */
>
>MEMORY {
> -RAM : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH}
> - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} -
> (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
> -NOCACHE : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 *
> ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) -
> ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH =
> ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
> -RAM_MMU : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 *
> ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x4000 *
> ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
> +RAM : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH}
> - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} -
> (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
> +NOCACHE : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} +
> ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 *
> ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) -
> ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH =
> ${BSP_XILINX
[PATCH v3] gcc12/libstdc++: Fix lifetime bugs for non-TLS eh_globals
From: Chris Johns
- This is the fix from PR105880:
https://gcc.gnu.org/bugzilla/attachment.cgi?id=53103
Closes #4661
---
.../config/tools/rtems-gcc-12-newlib-head.cfg | 29 ++-
1 file changed, 21 insertions(+), 8 deletions(-)
diff --git a/rtems/config/tools/rtems-gcc-12-newlib-head.cfg
b/rtems/config/tools/rtems-gcc-12-newlib-head.cfg
index cec65a8..4a7654b 100644
--- a/rtems/config/tools/rtems-gcc-12-newlib-head.cfg
+++ b/rtems/config/tools/rtems-gcc-12-newlib-head.cfg
@@ -5,13 +5,21 @@
%define gcc_external 1
%define gcc_expand_name gnu-mirror-gcc-%{gcc_version}
%source set gcc --rsb-file=%{gcc_expand_name}.tar.gz
https://codeload.github.com/RTEMS/gnu-mirror-gcc/tar.gz/%{gcc_version}
-%hash sha512 %{gcc_expand_name}.tar.gz
829fcdbdbc684e28a74500e38a19c02fdc9b19cef7a52e20f18831e1c12651e9accc8a5dafd39d3c8e7983e5c2794d6cbf842b83917775a080524cd1046ffc76
+%hash sha512 %{gcc_expand_name}.tar.gz \
+
gp/NvbxoTiinRQDjihnAL9ybGc73pS4g8Ygx4cEmUemszIpdr9OdPI55g+XCeU1sv4Qrg5F3daCAUkzRBG/8dg==
+
+%patch add gcc -p1
--rsb-file=PR105880-libstdcxx-Fix-lifetime-bugs-for-non-TLS-eh_globals.patch \
+https://gcc.gnu.org/bugzilla/attachment.cgi?id=53103
+%hash sha512 PR105880-libstdcxx-Fix-lifetime-bugs-for-non-TLS-eh_globals.patch
\
+
4ueSYXR59fcp0tch/6p4ktay2srtx6h2hmREL4qtNr4TvglwurWUdqN3c9mIe38YDPcY/braF+83vHSCybg33Q==
%patch add gcc -p1
https://devel.rtems.org/raw-attachment/ticket/4196/0001-Back-port-v1-of-gcov-tool-merge-stream-to-GCC-12.patch
-%hash sha512 0001-Back-port-v1-of-gcov-tool-merge-stream-to-GCC-12.patch
413f14374856f8bfd2bb94a56f1860fff8fe9a936f33c96fdf6a5a0c5a30e2cf7d05026d0338e8b30015a93d80169a602397076b947c8292ac5b5cdc2237ec4e
+%hash sha512 0001-Back-port-v1-of-gcov-tool-merge-stream-to-GCC-12.patch \
+
QT8UN0hW+L/Su5Slbxhg//j+mpNvM8lv32paDFow4s99BQJtAzjoswAVqT2AFppgI5cHa5R8gpKsW1zcIjfsTg==
%patch add newlib -p1
https://devel.rtems.org/raw-attachment/ticket/4510/0001-aarch64-Add-ILP32-ABI-support-in-assembly-v2.patch
-%hash sha512 0001-aarch64-Add-ILP32-ABI-support-in-assembly-v2.patch
7ca237eabfd5b382713186e1fc290dfc999a353315795ecb8dd0d22fcd1ab7f5bf31f4329954adab91ad04c100dcac0e86d406fdbce8f82cf9dc23842c88caf6
+%hash sha512 0001-aarch64-Add-ILP32-ABI-support-in-assembly-v2.patch \
+
fKI36r/Vs4JxMYbh/CkN/JmaNTMVeV7LjdDSL80at/W/MfQymVStq5GtBMEA3KwOhtQG/bzo+Cz53COELIjK9g==
# Following patches are related to compilation on Apple M1/Darwin host
platform.
# They are here to workaround issues with ISL, MPFR and MPC libraries.
@@ -20,18 +28,23 @@
# The patches are solely for libisl 0.24, libmpfr 4.1.0 and libmpc 1.2.1
# See #4657 for more information.
%patch add isl -p1
https://devel.rtems.org/raw-attachment/ticket/4657/fix-mac-arm64-isl-config.patch
-%hash sha512 fix-mac-arm64-isl-config.patch
c07fdb605a6520d194358504731e63b540211ef680383f1ca4ec65b4ac43ae27687534fd7d8196a4dbe83a0ecf2c42a4254c71e609ee484a7614573bc499a2e8
+%hash sha512 fix-mac-arm64-isl-config.patch \
+
wH/bYFplINGUNYUEcx5jtUAhHvaAOD8cpOxltKxDridodTT9fYGWpNvoOg7PLEKkJUxx5gnuSEp2FFc7xJmi6A==
%patch add mpfr -p1
https://devel.rtems.org/raw-attachment/ticket/4657/fix-mac-arm64-mpfr-config.patch
-%hash sha512 fix-mac-arm64-mpfr-config.patch
dc5069df870bd02b7e78ed22c6ad9e9a2bb9ca372ce1a6b7e8fa5b7635dcef35c29f251fe5195c9c2a43513116c12cab1b0e96171cf34bd7fb7d0334c2c740fb
+%hash sha512 fix-mac-arm64-mpfr-config.patch \
+
3FBp34cL0Ct+eO0ixq2emiu5yjcs4aa36PpbdjXc7zXCnyUf5RlcnCpDUTEWwSyrGw6WFxzzS9f7fQM0wsdA+w==
%patch add mpc -p1
https://devel.rtems.org/raw-attachment/ticket/4657/fix-mac-arm64-mpc-config.patch
-%hash sha512 fix-mac-arm64-mpc-config.patch
2849b11e360ea98e0b4d708c67723ad2d6c7bac6d1e469673f408b0111cf0278429e8bc38fd2b7538dc2d5bb0cc430c646a0fa7f0b6b105a0482a5455fadc8b9
+%hash sha512 fix-mac-arm64-mpc-config.patch \
+
KEmxHjYOqY4LTXCMZ3I60tbHusbR5GlnP0CLARHPAnhCnovDj9K3U43C1bsMxDDGRqD6fwtrEFoEgqVFX63IuQ==
# Comment above related to #4657 and patches ends here
%define newlib_version 27fd806
%define newlib_external 1
%define newlib_expand_name sourceware-mirror-newlib-cygwin-%{newlib_version}
-%source set newlib --rsb-file=newlib-%{newlib_version}.tar.gz
https://codeload.github.com/RTEMS/sourceware-mirror-newlib-cygwin/tar.gz/%{newlib_version}
-%hash sha512 newlib-%{newlib_version}.tar.gz
02fc2a0ffc8bf581f3f98deab582469130cfd6e10983b2be69f9971a326bbc9abedd1e828f990ae69ea984fd5dcad0889345ccab37d83c2f025437f65c53dab6
+%source set newlib --rsb-file=newlib-%{newlib_version}.tar.gz \
+
https://codeload.github.com/RTEMS/sourceware-mirror-newlib-cygwin/tar.gz/%{newlib_version}
+%hash sha512 newlib-%{newlib_version}.tar.gz \
+
02fc2a0ffc8bf581f3f98deab582469130cfd6e10983b2be69f9971a326bbc9abedd1e828f990ae69ea984fd5dcad0889345ccab37d83c2f025437f65c53dab6
%define with_threads 1
%define with_plugin 0
--
2.24.1
___
devel mailing list
devel@rtems.org
http://lis
[PATCH] tester: Make the SIS time limit user configurable
From: Chris Johns
Let the user set the test time limit in a config file to
provide site specific overrides. Optimisation can effect
the time a test may take to run.
---
tester/rtems/testing/bsps/erc32-sis.ini | 5 +-
tester/rtems/testing/bsps/gr740-sis.ini | 5 +-
tester/rtems/testing/bsps/griscv-sis-cov.ini | 5 +-
tester/rtems/testing/bsps/griscv-sis.ini | 5 +-
tester/rtems/testing/bsps/leon2-sis.ini | 5 +-
tester/rtems/testing/bsps/leon3-run.ini | 3 +-
tester/rtems/testing/bsps/leon3-sis-cov.ini | 5 +-
tester/rtems/testing/bsps/leon3-sis.ini | 5 +-
tester/rtems/testing/bsps/sis-run.ini| 5 +-
tester/rtems/testing/sis.cfg | 72
10 files changed, 89 insertions(+), 26 deletions(-)
create mode 100644 tester/rtems/testing/sis.cfg
diff --git a/tester/rtems/testing/bsps/erc32-sis.ini
b/tester/rtems/testing/bsps/erc32-sis.ini
index fca2122..a025265 100644
--- a/tester/rtems/testing/bsps/erc32-sis.ini
+++ b/tester/rtems/testing/bsps/erc32-sis.ini
@@ -34,6 +34,5 @@
[erc32-sis]
bsp = erc32
arch = sparc
-tester = %{_rtscripts}/run.cfg
-bsp_run_cmd = %{rtems_tools}/%{bsp_arch}-rtems%{rtems_version}-sis
-bsp_run_opts = -nouartrx -r -tlim 600 s
+tester = %{_rtscripts}/sis.cfg
+bsp_run_opts =
diff --git a/tester/rtems/testing/bsps/gr740-sis.ini
b/tester/rtems/testing/bsps/gr740-sis.ini
index b71048c..c42d716 100644
--- a/tester/rtems/testing/bsps/gr740-sis.ini
+++ b/tester/rtems/testing/bsps/gr740-sis.ini
@@ -33,6 +33,5 @@
[gr740-sis]
bsp = gr740
arch = sparc
-tester = %{_rtscripts}/run.cfg
-bsp_run_cmd = %{rtems_tools}/%{bsp_arch}-rtems%{rtems_version}-sis
-bsp_run_opts = -gr740 -nouartrx -r -tlim 200 s -m 4
+tester = %{_rtscripts}/sis.cfg
+bsp_run_opts = -gr740 -m 4
diff --git a/tester/rtems/testing/bsps/griscv-sis-cov.ini
b/tester/rtems/testing/bsps/griscv-sis-cov.ini
index 9ab37a8..fa86b55 100644
--- a/tester/rtems/testing/bsps/griscv-sis-cov.ini
+++ b/tester/rtems/testing/bsps/griscv-sis-cov.ini
@@ -34,7 +34,6 @@
[griscv-sis-cov]
bsp= griscv-sis
arch = riscv
-tester = %{_rtscripts}/run.cfg
-bsp_run_cmd= %{rtems_tools}/%{bsp_arch}-rtems%{rtems_version}-sis
-bsp_run_opts = -nouartrx -r -tlim 300 s -m 4 -cov
+tester = %{_rtscripts}/sis.cfg
+bsp_run_opts = -m 4 -cov
bsp_covoar_cmd = -S %{bsp_symbol_path} -E %{cov_explanations} -f TSIM
diff --git a/tester/rtems/testing/bsps/griscv-sis.ini
b/tester/rtems/testing/bsps/griscv-sis.ini
index b21cba1..bf32851 100644
--- a/tester/rtems/testing/bsps/griscv-sis.ini
+++ b/tester/rtems/testing/bsps/griscv-sis.ini
@@ -34,6 +34,5 @@
[griscv-sis]
bsp = griscv
arch = riscv
-tester = %{_rtscripts}/run.cfg
-bsp_run_cmd = %{rtems_tools}/%{bsp_arch}-rtems%{rtems_version}-sis
-bsp_run_opts = -nouartrx -r -tlim 300 s -m 4
+tester = %{_rtscripts}/sis.cfg
+bsp_run_opts = -m 4
diff --git a/tester/rtems/testing/bsps/leon2-sis.ini
b/tester/rtems/testing/bsps/leon2-sis.ini
index 61205ad..810320c 100644
--- a/tester/rtems/testing/bsps/leon2-sis.ini
+++ b/tester/rtems/testing/bsps/leon2-sis.ini
@@ -34,6 +34,5 @@
[leon2-sis]
bsp = leon2
arch = sparc
-tester = %{_rtscripts}/run.cfg
-bsp_run_cmd = %{rtems_tools}/%{bsp_arch}-rtems%{rtems_version}-sis
-bsp_run_opts = -leon2 -nouartrx -r -tlim 200 s
+tester = %{_rtscripts}/sis.cfg
+bsp_run_opts = -leon2
diff --git a/tester/rtems/testing/bsps/leon3-run.ini
b/tester/rtems/testing/bsps/leon3-run.ini
index a8c97a6..99c391b 100644
--- a/tester/rtems/testing/bsps/leon3-run.ini
+++ b/tester/rtems/testing/bsps/leon3-run.ini
@@ -34,6 +34,5 @@
[leon3-run]
bsp = leon3
arch = sparc
-tester = %{_rtscripts}/run.cfg
-bsp_run_cmd = %{rtems_tools}/%{bsp_arch}-rtems%{rtems_version}-run
+tester = %{_rtscripts}/sis.cfg
bsp_run_opts = -a -leon3
diff --git a/tester/rtems/testing/bsps/leon3-sis-cov.ini
b/tester/rtems/testing/bsps/leon3-sis-cov.ini
index d8ffe28..7c6a279 100644
--- a/tester/rtems/testing/bsps/leon3-sis-cov.ini
+++ b/tester/rtems/testing/bsps/leon3-sis-cov.ini
@@ -34,7 +34,6 @@
[leon3-sis-cov]
bsp= leon3-sis
arch = sparc
-tester = %{_rtscripts}/run.cfg
-bsp_run_cmd= %{rtems_tools}/%{bsp_arch}-rtems%{rtems_version}-sis
-bsp_run_opts = -leon3 -nouartrx -r -tlim 200 s -cov
+tester = %{_rtscripts}/sis.cfg
+bsp_run_opts = -leon3 -cov
bsp_covoar_cmd = -S %{bsp_symbol_path} -E %{cov_explanations} -f TSIM
diff --git a/tester/rtems/testing/bsps/leon3-sis.ini
b/tester/rtems/testing/bsps/leon3-sis.ini
index 2f933a7..9035f48 100644
--- a/tester/rtems/testing/bsps/leon3-sis.ini
+++ b/tester/rtems/testing/bsps/leon3-sis.ini
@@ -34,6 +34,5 @@
[leon3-sis]
bsp = leon3
arch = sparc
-tester = %{_rtscripts}/run.cfg
-bsp_run_cmd = %{rtems_tools}/%{bsp_arch}-rtems%{rtems_version}-sis
-bsp_run_op
Re: [tools] tester: Remove hard coded time limits for SIS
On 5/7/2022 8:50 pm, Jiri Gaisler wrote: > > On 7/5/22 12:45, Sebastian Huber wrote: >> >> >> On 05/07/2022 12:31, Chris Johns wrote: >>> On 5 Jul 2022, at 6:23 pm, Sebastian Huber wrote: On 05/07/2022 10:21, Chris Johns wrote: >> On 5/7/2022 4:29 pm, Sebastian Huber wrote: >> On 05/07/2022 08:23, Chris Johns wrote: >>> On 5/7/2022 4:02 pm, Sebastian Huber wrote: On 05/07/2022 07:14, Chris Johns wrote: > On 5/7/2022 2:58 pm, Sebastian Huber wrote: >> On 05/07/2022 03:08, Chris Johns wrote: >>> On 5/7/2022 9:44 am, Joel Sherrill wrote: The limit removed in sis and tsim is the simulated cpu time used. If not using that, the behavior of the tester is to let the simulator run for so much real processor time. Replacing these with a command line argument is probably good but just removing these mean these simulators will just run much longer before being killed. How best to capture the distinction between target run time and host run time? >>> Thank you for the explanation. I was not sure how the option >>> effected >>> things >>> and >>> yes it does matter we have this set correctly. >>> >>> Options can be set in the $HOME/.rtemstesterrc is via the >>> --user-config >>> option. >>> Maybe this can be used to control the time out for specific user >>> tests? This is the only way we currently have and it works ok for hardware type testing with site specific overrides. I think we need an sis.cfg to test for a user defined time limit or use a default. >> I would not make this more complicated than necessary. We have a >> --timeout >> command line option and the default timeout value can be set by *.ini >> files. The >> simulator speed is just a detail similar to running a target at >> 100MHz or >> 1GHz. > It is actually simpler to have this option and to measure time against > the cpu > time. The work loads on SMP hosts with qemu shows simulation timeouts > are > difficult to get right. I don't know what is wrong with the patch. Overruling command line options is just bad. >>> It does not work that way. When simulating the timeout in the tester is >>> a >>> catch >>> all. It may triggered if the simulator locks up. With real hardware it >>> is >>> the >>> timeout but that is a different use case. A simulator timeout is >>> preferred when >>> available. >> Ok, good. Who will fix this? > I am sorry I am not following. The tests have valid times for the default > optimisation. What is broken? What is broken is that the --timeout command line option doesn't work with SIS because it uses hard coded values. >>> The timeout option is correct and your understanding of it’s purpose is >>> wrong. Joining them as you would like would break it. >> >> It would be nice if someone could offer me a way to run tests which exceed >> the >> hard coded SIS timeout values? I will post a patch. I have only tested the erc32-sis bsp. I think it is important we do not join the host's realtime clock to the simulated CPU's realtime clock if we can. The problem with the host's realtime clock controlling the simulated test's time limit is the performance of hosts users differ and what works for one person may not work for someone else. Using extra long timeouts on the host tends to skew the testing time by having the tester wait for the stuck tests to time out and be killed. Note, testing on hardware does not have this problem because the host's and hardware's realtime clocks are the same. > sis accepts several -tlim options. The last one will be the active one. So > rtems-test could add an extra -tlim option at the end of the sis parameters > which would override the default one. I think adding a `sis.cfg` and then letting the user pass the option via the $HOME/.rtemstesterrc or the --user-config option is the best approach. It provides an easy to manage site specific configuration. Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] tester: Make the SIS time limit user configurable
Optimization may affect the time but host speed is more likely
Ok to commit
On Tue, Jul 5, 2022, 6:51 PM wrote:
> From: Chris Johns
>
> Let the user set the test time limit in a config file to
> provide site specific overrides. Optimisation can effect
> the time a test may take to run.
> ---
> tester/rtems/testing/bsps/erc32-sis.ini | 5 +-
> tester/rtems/testing/bsps/gr740-sis.ini | 5 +-
> tester/rtems/testing/bsps/griscv-sis-cov.ini | 5 +-
> tester/rtems/testing/bsps/griscv-sis.ini | 5 +-
> tester/rtems/testing/bsps/leon2-sis.ini | 5 +-
> tester/rtems/testing/bsps/leon3-run.ini | 3 +-
> tester/rtems/testing/bsps/leon3-sis-cov.ini | 5 +-
> tester/rtems/testing/bsps/leon3-sis.ini | 5 +-
> tester/rtems/testing/bsps/sis-run.ini| 5 +-
> tester/rtems/testing/sis.cfg | 72
> 10 files changed, 89 insertions(+), 26 deletions(-)
> create mode 100644 tester/rtems/testing/sis.cfg
>
> diff --git a/tester/rtems/testing/bsps/erc32-sis.ini
> b/tester/rtems/testing/bsps/erc32-sis.ini
> index fca2122..a025265 100644
> --- a/tester/rtems/testing/bsps/erc32-sis.ini
> +++ b/tester/rtems/testing/bsps/erc32-sis.ini
> @@ -34,6 +34,5 @@
> [erc32-sis]
> bsp = erc32
> arch = sparc
> -tester = %{_rtscripts}/run.cfg
> -bsp_run_cmd = %{rtems_tools}/%{bsp_arch}-rtems%{rtems_version}-sis
> -bsp_run_opts = -nouartrx -r -tlim 600 s
> +tester = %{_rtscripts}/sis.cfg
> +bsp_run_opts =
> diff --git a/tester/rtems/testing/bsps/gr740-sis.ini
> b/tester/rtems/testing/bsps/gr740-sis.ini
> index b71048c..c42d716 100644
> --- a/tester/rtems/testing/bsps/gr740-sis.ini
> +++ b/tester/rtems/testing/bsps/gr740-sis.ini
> @@ -33,6 +33,5 @@
> [gr740-sis]
> bsp = gr740
> arch = sparc
> -tester = %{_rtscripts}/run.cfg
> -bsp_run_cmd = %{rtems_tools}/%{bsp_arch}-rtems%{rtems_version}-sis
> -bsp_run_opts = -gr740 -nouartrx -r -tlim 200 s -m 4
> +tester = %{_rtscripts}/sis.cfg
> +bsp_run_opts = -gr740 -m 4
> diff --git a/tester/rtems/testing/bsps/griscv-sis-cov.ini
> b/tester/rtems/testing/bsps/griscv-sis-cov.ini
> index 9ab37a8..fa86b55 100644
> --- a/tester/rtems/testing/bsps/griscv-sis-cov.ini
> +++ b/tester/rtems/testing/bsps/griscv-sis-cov.ini
> @@ -34,7 +34,6 @@
> [griscv-sis-cov]
> bsp= griscv-sis
> arch = riscv
> -tester = %{_rtscripts}/run.cfg
> -bsp_run_cmd= %{rtems_tools}/%{bsp_arch}-rtems%{rtems_version}-sis
> -bsp_run_opts = -nouartrx -r -tlim 300 s -m 4 -cov
> +tester = %{_rtscripts}/sis.cfg
> +bsp_run_opts = -m 4 -cov
> bsp_covoar_cmd = -S %{bsp_symbol_path} -E %{cov_explanations} -f TSIM
> diff --git a/tester/rtems/testing/bsps/griscv-sis.ini
> b/tester/rtems/testing/bsps/griscv-sis.ini
> index b21cba1..bf32851 100644
> --- a/tester/rtems/testing/bsps/griscv-sis.ini
> +++ b/tester/rtems/testing/bsps/griscv-sis.ini
> @@ -34,6 +34,5 @@
> [griscv-sis]
> bsp = griscv
> arch = riscv
> -tester = %{_rtscripts}/run.cfg
> -bsp_run_cmd = %{rtems_tools}/%{bsp_arch}-rtems%{rtems_version}-sis
> -bsp_run_opts = -nouartrx -r -tlim 300 s -m 4
> +tester = %{_rtscripts}/sis.cfg
> +bsp_run_opts = -m 4
> diff --git a/tester/rtems/testing/bsps/leon2-sis.ini
> b/tester/rtems/testing/bsps/leon2-sis.ini
> index 61205ad..810320c 100644
> --- a/tester/rtems/testing/bsps/leon2-sis.ini
> +++ b/tester/rtems/testing/bsps/leon2-sis.ini
> @@ -34,6 +34,5 @@
> [leon2-sis]
> bsp = leon2
> arch = sparc
> -tester = %{_rtscripts}/run.cfg
> -bsp_run_cmd = %{rtems_tools}/%{bsp_arch}-rtems%{rtems_version}-sis
> -bsp_run_opts = -leon2 -nouartrx -r -tlim 200 s
> +tester = %{_rtscripts}/sis.cfg
> +bsp_run_opts = -leon2
> diff --git a/tester/rtems/testing/bsps/leon3-run.ini
> b/tester/rtems/testing/bsps/leon3-run.ini
> index a8c97a6..99c391b 100644
> --- a/tester/rtems/testing/bsps/leon3-run.ini
> +++ b/tester/rtems/testing/bsps/leon3-run.ini
> @@ -34,6 +34,5 @@
> [leon3-run]
> bsp = leon3
> arch = sparc
> -tester = %{_rtscripts}/run.cfg
> -bsp_run_cmd = %{rtems_tools}/%{bsp_arch}-rtems%{rtems_version}-run
> +tester = %{_rtscripts}/sis.cfg
> bsp_run_opts = -a -leon3
> diff --git a/tester/rtems/testing/bsps/leon3-sis-cov.ini
> b/tester/rtems/testing/bsps/leon3-sis-cov.ini
> index d8ffe28..7c6a279 100644
> --- a/tester/rtems/testing/bsps/leon3-sis-cov.ini
> +++ b/tester/rtems/testing/bsps/leon3-sis-cov.ini
> @@ -34,7 +34,6 @@
> [leon3-sis-cov]
> bsp= leon3-sis
> arch = sparc
> -tester = %{_rtscripts}/run.cfg
> -bsp_run_cmd= %{rtems_tools}/%{bsp_arch}-rtems%{rtems_version}-sis
> -bsp_run_opts = -leon3 -nouartrx -r -tlim 200 s -cov
> +tester = %{_rtscripts}/sis.cfg
> +bsp_run_opts = -leon3 -cov
> bsp_covoar_cmd = -S %{bsp_symbol_path} -E %{cov_explanations} -f TSIM
> diff --git a/tester/rtems/testing/bsps/leon3-sis.ini
> b/tester/rt
Re: [PATCH] bsps/aarch64: Use MMU pages appropriately
On 6/7/2022 5:38 am, Joel Sherrill wrote: > I'm ok with this. But Chris should speak up about the Versal. OK to push. Tested on Versal hardware and it boots as before. I have not returned to see if I can get access to at least 4G of memory in the lower 32bits of the address space. That is in the queue. Thanks Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] tester: Make the SIS time limit user configurable
On 06/07/2022 01:51, chr...@rtems.org wrote:
+#
+# Timeout option. This is the default for timeout for the CPU realtime
+# clock
+
+%ifn %{defined sis_time_limit}
+ %define sis_time_limit -tlim 400 s
+%endif
Making this configurable is good, but why do you impose a limit by
default? Why can't the simulator run forever in the standard configuration?
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