[PATCH 2/2] tester/bsps: add stm32h7-stlink family configuration
Sponsored-By: Precidata
---
tester/rtems/testing/bsps/stm32h7-stlink.ini | 43
1 file changed, 43 insertions(+)
create mode 100644 tester/rtems/testing/bsps/stm32h7-stlink.ini
diff --git a/tester/rtems/testing/bsps/stm32h7-stlink.ini
b/tester/rtems/testing/bsps/stm32h7-stlink.ini
new file mode 100644
index 000..042ec7c
--- /dev/null
+++ b/tester/rtems/testing/bsps/stm32h7-stlink.ini
@@ -0,0 +1,43 @@
+#
+# RTEMS Tools Project (http://www.rtems.org/)
+# Copyright 2015 On-Line Applications Research Corporation (OAR).
+# All rights reserved.
+#
+# This file is part of the RTEMS Tools package in 'rtems-tools'.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+#
+# The stm32h7 BSP family
+#
+[stm32h7-stlink]
+bsp= stm32h7-stlink
+arch = arm
+tester = %{_rtscripts}/gdb.cfg
+jobs = 1
+gdb_script = bsp_gdb_script
+requires: bsp_tty_dev, bsp_gdb_script, target_pretest_command,
target_posttest_command
+bsp_gdb_script = target extended-remote :61234
+ load
+ cont
--
2.25.1
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[PATCH 1/2] tester/gdb: allow kill on the test end
Sponsored-By: Precidata
---
tester/rt/config.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/tester/rt/config.py b/tester/rt/config.py
index a7b9ee3..8a433af 100644
--- a/tester/rt/config.py
+++ b/tester/rt/config.py
@@ -258,6 +258,7 @@ class file(config.file):
script = self.expand('%%{%s}' % data[2])
if script:
script = [l.strip() for l in script.splitlines()]
+self.kill_on_end = True
if not self.in_error:
if self.console:
self.console.open()
--
2.25.1
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Re: [PATCH 2/2] tester/bsps: add stm32h7-stlink family configuration
On 30/5/2022 7:35 am, Karel Gardas wrote:
> Sponsored-By: Precidata
> ---
> tester/rtems/testing/bsps/stm32h7-stlink.ini | 43
> 1 file changed, 43 insertions(+)
> create mode 100644 tester/rtems/testing/bsps/stm32h7-stlink.ini
>
> diff --git a/tester/rtems/testing/bsps/stm32h7-stlink.ini
> b/tester/rtems/testing/bsps/stm32h7-stlink.ini
> new file mode 100644
> index 000..042ec7c
> --- /dev/null
> +++ b/tester/rtems/testing/bsps/stm32h7-stlink.ini
> @@ -0,0 +1,43 @@
> +#
> +# RTEMS Tools Project (http://www.rtems.org/)
> +# Copyright 2015 On-Line Applications Research Corporation (OAR).
> +# All rights reserved.
> +#
> +# This file is part of the RTEMS Tools package in 'rtems-tools'.
> +#
> +# Redistribution and use in source and binary forms, with or without
> +# modification, are permitted provided that the following conditions are met:
> +#
> +# 1. Redistributions of source code must retain the above copyright notice,
> +# this list of conditions and the following disclaimer.
> +#
> +# 2. Redistributions in binary form must reproduce the above copyright
> notice,
> +# this list of conditions and the following disclaimer in the documentation
> +# and/or other materials provided with the distribution.
> +#
> +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
> +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
> +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
> +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
> +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
> +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
> +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
> +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
> +# POSSIBILITY OF SUCH DAMAGE.
> +#
> +
> +#
> +# The stm32h7 BSP family
> +#
> +[stm32h7-stlink]
> +bsp= stm32h7-stlink
> +arch = arm
> +tester = %{_rtscripts}/gdb.cfg
> +jobs = 1
> +gdb_script = bsp_gdb_script
> +requires: bsp_tty_dev, bsp_gdb_script, target_pretest_command,
> target_posttest_command
Should this be `requires =`?
Chris
> +bsp_gdb_script = target extended-remote :61234
> + load
> + cont
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Re: [PATCH 2/2] tester/bsps: add stm32h7-stlink family configuration
On 5/30/22 00:52, Chris Johns wrote: +requires: bsp_tty_dev, bsp_gdb_script, target_pretest_command, target_posttest_command Should this be `requires =`? Indeed, very likely yes, but I'm wondering how it passed my testing. And IIRC I really tested it by modifying user ini file and it really complained about missing config bits... Anyway, I'll retest and resubmit. Thanks! Karel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 2/2] tester/bsps: add stm32h7-stlink family configuration
On 30/5/2022 9:07 am, Karel Gardas wrote: > On 5/30/22 00:52, Chris Johns wrote: >>> +requires: bsp_tty_dev, bsp_gdb_script, target_pretest_command, >>> target_posttest_command >> >> Should this be `requires =`? > > Indeed, very likely yes, but I'm wondering how it passed my testing. And IIRC > I > really tested it by modifying user ini file and it really complained about > missing config bits... Defaults? > Anyway, I'll retest and resubmit. OK to commit with the fix. Thanks Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 2/2] tester/bsps: add stm32h7-stlink family configuration
On 5/30/22 01:07, Karel Gardas wrote: On 5/30/22 00:52, Chris Johns wrote: +requires: bsp_tty_dev, bsp_gdb_script, target_pretest_command, target_posttest_command Should this be `requires =`? Indeed, very likely yes, but I'm wondering how it passed my testing. And IIRC I really tested it by modifying user ini file and it really complained about missing config bits... And I was right about it. I've deleted target_pretest_command from my user config file and tester immediate starts complain: error: user value missing, BSP stm32h7-stlink requires 'bsp_gdb_script, bsp_tty_dev, target_posttest_command, target_pretest_command': missing: target_pretest_command So I guess this works fine, but for the sake of being in harmony with others I'll surely change to requires = ... Karel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 1/7] bsps/arm: add CMSIS Cortex-M4 Core Peripheral Access Layer Header File
---
bsps/arm/include/core_cm4.h | 1937 +++
1 file changed, 1937 insertions(+)
create mode 100644 bsps/arm/include/core_cm4.h
diff --git a/bsps/arm/include/core_cm4.h b/bsps/arm/include/core_cm4.h
new file mode 100644
index 00..dc840ebf22
--- /dev/null
+++ b/bsps/arm/include/core_cm4.h
@@ -0,0 +1,1937 @@
+/**//**
+ * @file core_cm4.h
+ * @briefCMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+
**/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+
---*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA
check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type:
'{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/***
+ * CMSIS definitions
+
**/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (0x04U)
/*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x1EU)
/*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+__CM4_CMSIS_VERSION_SUB )
/*!< CMSIS HAL version number */
+
+#define __CORTEX_M(0x04U)
/*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM__asm /*!< asm
keyword for ARM Compiler */
+ #define __INLINE __inline /*!<
inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM__asm /*!< asm
keyword for ARM Compiler */
+ #define __INLINE __inline /*!<
inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM__asm /*!< asm
keyword for GNU Compiler */
+ #define __INLINE inline /*!<
inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+
[PATCH 3/7] bsps/stm32h7: move cache implementation from obj to BSPs own yml file
This is done in preparation for future Cortex-M4 based BSP variants which do not provide cache at all. Sponsored-By: Precidata --- spec/build/bsps/arm/stm32h7/bspnucleoh743zi.yml| 1 + spec/build/bsps/arm/stm32h7/bspstm32h7.yml | 1 + spec/build/bsps/arm/stm32h7/bspstm32h757i-eval.yml | 1 + spec/build/bsps/arm/stm32h7/bspstm32h7b3i-dk.yml | 1 + spec/build/bsps/arm/stm32h7/obj.yml| 1 - 5 files changed, 4 insertions(+), 1 deletion(-) diff --git a/spec/build/bsps/arm/stm32h7/bspnucleoh743zi.yml b/spec/build/bsps/arm/stm32h7/bspnucleoh743zi.yml index 1cad10b39d..9a3e556eda 100644 --- a/spec/build/bsps/arm/stm32h7/bspnucleoh743zi.yml +++ b/spec/build/bsps/arm/stm32h7/bspnucleoh743zi.yml @@ -19,4 +19,5 @@ source: - bsps/arm/stm32h7/boards/stm/nucleo-h743zi/stm32h7-config-per.c - bsps/arm/stm32h7/boards/stm/nucleo-h743zi/system_stm32h7xx.c - bsps/arm/stm32h7/boards/stm/nucleo-h743zi/ext-mem-ctl.c +- bsps/arm/shared/cache/cache-v7m.c type: build diff --git a/spec/build/bsps/arm/stm32h7/bspstm32h7.yml b/spec/build/bsps/arm/stm32h7/bspstm32h7.yml index 89ded74e05..52d47295d9 100644 --- a/spec/build/bsps/arm/stm32h7/bspstm32h7.yml +++ b/spec/build/bsps/arm/stm32h7/bspstm32h7.yml @@ -19,4 +19,5 @@ source: - bsps/arm/stm32h7/boards/stm/stm32h743i-eval/stm32h7-config-per.c - bsps/arm/stm32h7/boards/stm/stm32h743i-eval/system_stm32h7xx.c - bsps/arm/stm32h7/boards/stm/stm32h743i-eval/ext-mem-ctl.c +- bsps/arm/shared/cache/cache-v7m.c type: build diff --git a/spec/build/bsps/arm/stm32h7/bspstm32h757i-eval.yml b/spec/build/bsps/arm/stm32h7/bspstm32h757i-eval.yml index 541210952c..c8a4df954a 100644 --- a/spec/build/bsps/arm/stm32h7/bspstm32h757i-eval.yml +++ b/spec/build/bsps/arm/stm32h7/bspstm32h757i-eval.yml @@ -20,4 +20,5 @@ source: - bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-osc.c - bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-per.c - bsps/arm/stm32h7/boards/stm/stm32h757i-eval/system_stm32h7xx.c +- bsps/arm/shared/cache/cache-v7m.c type: build diff --git a/spec/build/bsps/arm/stm32h7/bspstm32h7b3i-dk.yml b/spec/build/bsps/arm/stm32h7/bspstm32h7b3i-dk.yml index f3456cacca..907c107a33 100644 --- a/spec/build/bsps/arm/stm32h7/bspstm32h7b3i-dk.yml +++ b/spec/build/bsps/arm/stm32h7/bspstm32h7b3i-dk.yml @@ -21,4 +21,5 @@ source: - bsps/arm/stm32h7/boards/stm/stm32h7b3i-dk/stm32h7-config-per.c - bsps/arm/stm32h7/boards/stm/stm32h7b3i-dk/system_stm32h7xx.c - bsps/arm/stm32h7/boards/stm/stm32h7b3i-dk/ext-mem-ctl.c +- bsps/arm/shared/cache/cache-v7m.c type: build diff --git a/spec/build/bsps/arm/stm32h7/obj.yml b/spec/build/bsps/arm/stm32h7/obj.yml index 93fa91f023..9b1cc62a22 100644 --- a/spec/build/bsps/arm/stm32h7/obj.yml +++ b/spec/build/bsps/arm/stm32h7/obj.yml @@ -171,7 +171,6 @@ install: - bsps/arm/stm32h7/include/stm32h7/mpu-config.h links: [] source: -- bsps/arm/shared/cache/cache-v7m.c - bsps/arm/shared/clock/clock-armv7m.c - bsps/arm/shared/cpucounter/cpucounter-armv7m.c - bsps/arm/shared/irq/irq-armv7m.c -- 2.25.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 2/7] bsps/stm32h7: enable cache and MPU only on Cortex-M7
Sponsored-By: Precidata
---
bsps/arm/stm32h7/start/bspstarthooks.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/bsps/arm/stm32h7/start/bspstarthooks.c
b/bsps/arm/stm32h7/start/bspstarthooks.c
index ef26af5eba..dd8f544e52 100644
--- a/bsps/arm/stm32h7/start/bspstarthooks.c
+++ b/bsps/arm/stm32h7/start/bspstarthooks.c
@@ -101,7 +101,7 @@ void bsp_start_hook_0(void)
HAL_Init();
SystemInit_ExtMemCtl();
}
-
+#if __CORTEX_M == 0x07U
if ((SCB->CCR & SCB_CCR_IC_Msk) == 0) {
SCB_EnableICache();
}
@@ -111,12 +111,15 @@ void bsp_start_hook_0(void)
}
_ARMV7M_MPU_Setup(stm32h7_config_mpu_region,
stm32h7_config_mpu_region_count);
+#endif
}
void bsp_start_hook_1(void)
{
bsp_start_copy_sections_compact();
+#if __CORTEX_M == 0x07U
SCB_CleanDCache();
SCB_InvalidateICache();
+#endif
bsp_start_clear_bss();
}
--
2.25.1
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[PATCH 4/7] bsps/stm32h7: include CMSIS Cortex-M4 header when required by configuration
Sponsored-By: Precidata --- bsps/arm/stm32h7/include/chip.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/bsps/arm/stm32h7/include/chip.h b/bsps/arm/stm32h7/include/chip.h index 26b067a3b7..ac579c0743 100644 --- a/bsps/arm/stm32h7/include/chip.h +++ b/bsps/arm/stm32h7/include/chip.h @@ -29,6 +29,13 @@ #define LIBBSP_ARM_STM32H7_CHIP_H #include +#if defined(CORE_CM7) || defined(BOOT_CORE_DEFINE_NOT_NEEDED) +/* M7 is a default core of the H7 family */ #include +#elif defined(CORE_CM4) +#include +#else +#error "Boot core definition missing!" +#endif #endif /* LIBBSP_ARM_STM32H7_CHIP_H */ -- 2.25.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 5/7] bsps/stm32h7: add configuration and enable build of stm32h757i-eval-m4 BSP
This is minimalist configuration for the stm32h757i-eval-m4 BSP provided
here. The only general enhancement worth mention is a flash origin address
configuration which is needed for simplification as M4 core boots
from second flash bank which starts at 0x810 by default. The boot
address of the core may be changed by using STM32CubeProgrammer. If done
so then also BSP configuration needs to be changed accordingly.
As the BSP variant is running on M4 core, there is also more configuration
changes required here. E.g. boot core and ABI (compilation flags)
in comparison with stm32h757i-eval BSP. On the other hand, C code is shared
completely with this BSP variant.
Sponsored-By: Precidata
---
spec/build/bsps/arm/stm32h7/abi.yml | 9 ++-
.../arm/stm32h7/bspstm32h757i-eval-m4.yml | 24 +++
spec/build/bsps/arm/stm32h7/grp.yml | 2 ++
.../build/bsps/arm/stm32h7/linkcmdsmemory.yml | 2 +-
spec/build/bsps/arm/stm32h7/optbootcore.yml | 3 +++
spec/build/bsps/arm/stm32h7/optlinkcmds.yml | 1 +
.../bsps/arm/stm32h7/optmemflashorigin.yml| 19 +++
spec/build/bsps/arm/stm32h7/optmemflashsz.yml | 6 -
spec/build/bsps/arm/stm32h7/optpwrsupply.yml | 1 +
.../bsps/arm/stm32h7/optusart1gpioregs.yml| 1 +
spec/build/bsps/arm/stm32h7/optvariant.yml| 1 +
11 files changed, 66 insertions(+), 3 deletions(-)
create mode 100644 spec/build/bsps/arm/stm32h7/bspstm32h757i-eval-m4.yml
create mode 100644 spec/build/bsps/arm/stm32h7/optmemflashorigin.yml
diff --git a/spec/build/bsps/arm/stm32h7/abi.yml
b/spec/build/bsps/arm/stm32h7/abi.yml
index 697220b1b1..dd751cb72e 100644
--- a/spec/build/bsps/arm/stm32h7/abi.yml
+++ b/spec/build/bsps/arm/stm32h7/abi.yml
@@ -8,7 +8,14 @@ default:
- -mcpu=cortex-m7
- -mfpu=fpv5-d16
- -mfloat-abi=hard
-default-by-variant: []
+default-by-variant:
+- value:
+ - -mthumb
+ - -mcpu=cortex-m4
+ - -mfpu=fpv4-sp-d16
+ - -mfloat-abi=hard
+ variants:
+ - arm/stm32h757i-eval-m4
enabled-by: true
links: []
name: ABI_FLAGS
diff --git a/spec/build/bsps/arm/stm32h7/bspstm32h757i-eval-m4.yml
b/spec/build/bsps/arm/stm32h7/bspstm32h757i-eval-m4.yml
new file mode 100644
index 00..4850396281
--- /dev/null
+++ b/spec/build/bsps/arm/stm32h7/bspstm32h757i-eval-m4.yml
@@ -0,0 +1,24 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: arm
+bsp: stm32h757i-eval-m4
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2022 Karel Gardas
+cppflags: []
+enabled-by: true
+family: stm32h7
+includes: []
+install: []
+links:
+- role: build-dependency
+ uid: grp
+- role: build-dependency
+ uid: tststm32h757i-eval
+source:
+- bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-clk.c
+- bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-osc.c
+- bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-per.c
+- bsps/arm/stm32h7/boards/stm/stm32h757i-eval/system_stm32h7xx.c
+- bsps/shared/cache/nocache.c
+type: build
diff --git a/spec/build/bsps/arm/stm32h7/grp.yml
b/spec/build/bsps/arm/stm32h7/grp.yml
index 6e7036b6aa..c056a2034b 100644
--- a/spec/build/bsps/arm/stm32h7/grp.yml
+++ b/spec/build/bsps/arm/stm32h7/grp.yml
@@ -51,6 +51,8 @@ links:
uid: optmemflashsz
- role: build-dependency
uid: optmemflashlatency
+- role: build-dependency
+ uid: optmemflashorigin
- role: build-dependency
uid: optmemitcmsz
- role: build-dependency
diff --git a/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml
b/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml
index 7ff7f3da5e..78f0308832 100644
--- a/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml
+++ b/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml
@@ -3,7 +3,7 @@ content: |
MEMORY {
NULL: ORIGIN = 0x, LENGTH =
${STM32H7_MEMORY_NULL_SIZE:#010x}
ITCM: ORIGIN = ${STM32H7_MEMORY_NULL_SIZE:#010x}, LENGTH =
${STM32H7_MEMORY_ITCM_SIZE:#010x}
-FLASH : ORIGIN = 0x0800, LENGTH =
${STM32H7_MEMORY_FLASH_SIZE:#010x}
+FLASH : ORIGIN = ${STM32H7_MEMORY_FLASH_ORIGIN:#010x}, LENGTH =
${STM32H7_MEMORY_FLASH_SIZE:#010x}
DTCM: ORIGIN = 0x2000, LENGTH =
${STM32H7_MEMORY_DTCM_SIZE:#010x}
SRAM_AXI: ORIGIN = 0x2400, LENGTH =
${STM32H7_MEMORY_SRAM_AXI_SIZE:#010x}
SRAM_1 : ORIGIN = 0x3000, LENGTH =
${STM32H7_MEMORY_SRAM_1_SIZE:#010x}
diff --git a/spec/build/bsps/arm/stm32h7/optbootcore.yml
b/spec/build/bsps/arm/stm32h7/optbootcore.yml
index 53ffb496cc..e6f52e8631 100644
--- a/spec/build/bsps/arm/stm32h7/optbootcore.yml
+++ b/spec/build/bsps/arm/stm32h7/optbootcore.yml
@@ -11,6 +11,9 @@ default-by-variant:
- value: CORE_CM7
variants:
- arm/stm32h757i-eval
+- value: CORE_CM4
+ variants:
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optlinkcmds.yml
b/spec/build/bsps/arm/stm32h7/optlinkcmds.yml
index 43af9c8613..c3c76f9496 100644
--- a/spec/build/bsps/arm/stm32h7/optlinkcmds.yml
+++ b/spec/build/
[PATCH 6/7] bsps/stm32h7: disable all U(S)ARTs except USART1 on stm32h757i-eval-m4 BSP
This patch disables all U(S)ARTs which are not supported by the board
itself and its provided connectors.
Sponsored-By: Precidata
---
spec/build/bsps/arm/stm32h7/optenuart4.yml | 1 +
spec/build/bsps/arm/stm32h7/optenuart5.yml | 1 +
spec/build/bsps/arm/stm32h7/optenuart7.yml | 1 +
spec/build/bsps/arm/stm32h7/optenuart8.yml | 1 +
spec/build/bsps/arm/stm32h7/optenuart9.yml | 1 +
spec/build/bsps/arm/stm32h7/optenusart10.yml | 1 +
spec/build/bsps/arm/stm32h7/optenusart2.yml | 1 +
spec/build/bsps/arm/stm32h7/optenusart3.yml | 1 +
spec/build/bsps/arm/stm32h7/optenusart6.yml | 1 +
9 files changed, 9 insertions(+)
diff --git a/spec/build/bsps/arm/stm32h7/optenuart4.yml
b/spec/build/bsps/arm/stm32h7/optenuart4.yml
index 8665f4c821..73c1ebef1c 100644
--- a/spec/build/bsps/arm/stm32h7/optenuart4.yml
+++ b/spec/build/bsps/arm/stm32h7/optenuart4.yml
@@ -7,6 +7,7 @@ default-by-variant:
- value: false
variants:
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenuart5.yml
b/spec/build/bsps/arm/stm32h7/optenuart5.yml
index f32f719f49..e445f2834f 100644
--- a/spec/build/bsps/arm/stm32h7/optenuart5.yml
+++ b/spec/build/bsps/arm/stm32h7/optenuart5.yml
@@ -8,6 +8,7 @@ default-by-variant:
variants:
- arm/stm32h7b3i-dk
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenuart7.yml
b/spec/build/bsps/arm/stm32h7/optenuart7.yml
index bd9ed8fe76..225c9efa22 100644
--- a/spec/build/bsps/arm/stm32h7/optenuart7.yml
+++ b/spec/build/bsps/arm/stm32h7/optenuart7.yml
@@ -8,6 +8,7 @@ default-by-variant:
variants:
- arm/stm32h7b3i-dk
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenuart8.yml
b/spec/build/bsps/arm/stm32h7/optenuart8.yml
index 74304e1256..96b869907d 100644
--- a/spec/build/bsps/arm/stm32h7/optenuart8.yml
+++ b/spec/build/bsps/arm/stm32h7/optenuart8.yml
@@ -8,6 +8,7 @@ default-by-variant:
variants:
- arm/stm32h7b3i-dk
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenuart9.yml
b/spec/build/bsps/arm/stm32h7/optenuart9.yml
index 76378c622d..864948fc91 100644
--- a/spec/build/bsps/arm/stm32h7/optenuart9.yml
+++ b/spec/build/bsps/arm/stm32h7/optenuart9.yml
@@ -8,6 +8,7 @@ default-by-variant:
variants:
- arm/stm32h7b3i-dk
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenusart10.yml
b/spec/build/bsps/arm/stm32h7/optenusart10.yml
index 1558bdb017..b60acf62a4 100644
--- a/spec/build/bsps/arm/stm32h7/optenusart10.yml
+++ b/spec/build/bsps/arm/stm32h7/optenusart10.yml
@@ -8,6 +8,7 @@ default-by-variant:
variants:
- arm/stm32h7b3i-dk
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenusart2.yml
b/spec/build/bsps/arm/stm32h7/optenusart2.yml
index 05f73df137..b49d3315e0 100644
--- a/spec/build/bsps/arm/stm32h7/optenusart2.yml
+++ b/spec/build/bsps/arm/stm32h7/optenusart2.yml
@@ -8,6 +8,7 @@ default-by-variant:
- value: false
variants:
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenusart3.yml
b/spec/build/bsps/arm/stm32h7/optenusart3.yml
index 1d676fdc3c..798aaed2a5 100644
--- a/spec/build/bsps/arm/stm32h7/optenusart3.yml
+++ b/spec/build/bsps/arm/stm32h7/optenusart3.yml
@@ -8,6 +8,7 @@ default-by-variant:
variants:
- arm/stm32h7b3i-dk
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenusart6.yml
b/spec/build/bsps/arm/stm32h7/optenusart6.yml
index 17761be7c3..a8ab30cba5 100644
--- a/spec/build/bsps/arm/stm32h7/optenusart6.yml
+++ b/spec/build/bsps/arm/stm32h7/optenusart6.yml
@@ -8,6 +8,7 @@ default-by-variant:
variants:
- arm/stm32h7b3i-dk
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{}'
links: []
--
2.25.1
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[PATCH 7/7] bsps/stm32h7: set default SDRAM x sizes on stm32h757i-eval-m4 BSP
This means:
SDRAM 1: 0
SDRAM 2: 32 MB
Sponsored-By: Precidata
---
spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml | 1 +
spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml | 1 +
2 files changed, 2 insertions(+)
diff --git a/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml
b/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml
index 4825a6446b..82267648a4 100644
--- a/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml
+++ b/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml
@@ -8,6 +8,7 @@ default-by-variant:
variants:
- arm/stm32h7b3i-dk
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{:#010x}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml
b/spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml
index dff8a772e4..9fa8accbf4 100644
--- a/spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml
+++ b/spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml
@@ -7,6 +7,7 @@ default-by-variant:
- value: 33554432
variants:
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{:#010x}'
links: []
--
2.25.1
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http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 2/7] bsps/arm: disable cache operations on Cortex-M4
On 5/23/22 14:45, Sebastian Huber wrote: On 16/05/2022 16:02, Karel Gardas wrote: --- bsps/arm/shared/cache/cache-v7m.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/bsps/arm/shared/cache/cache-v7m.c b/bsps/arm/shared/cache/cache-v7m.c index f5a9e208e5..100d38765f 100644 --- a/bsps/arm/shared/cache/cache-v7m.c +++ b/bsps/arm/shared/cache/cache-v7m.c @@ -9,21 +9,25 @@ #include #include +#if __CORTEX_M != 0x04U #define CPU_DATA_CACHE_ALIGNMENT 32 #define CPU_INSTRUCTION_CACHE_ALIGNMENT 32 #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS +#endif This is file for Cortex-M7. Maybe use __CORTEX_M == 0x07U. This is a misunderstanding on my side. I've thought this was for armv7m and not for cotex-m7 specifically. You can probably use a single #if with an #endif before the cachimpl.h include. Indeed, I took it even a bit further and use nochache.c for m4 variant. Also I took your advice and use __CORTEX_M comparison for disabling code enabling cache and MPU in bspstarthook.c Thanks for the review! Karel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
AW: AW: [PATCH 1/1] kern_tc.c: th_generation starts with 1 after overflow for single-core
> On 27.05.22 11:49, gabriel.moy...@dlr.de wrote: > >> On 27.05.22 10:51, Sebastian Huber wrote: > >>> Hello Gabriel, > >>> > >>> the uniprocessor version uses an optimization at the reader side: > >>> > >>> #if defined(RTEMS_SMP) > >>> } while (gen == 0 || gen != th->th_generation); #else > >>> } while (gen != th->th_generation); #endif > >>> > >>> This is possible since the windup happens with interrupts disabled. > >>> I guess you need this optimization somewhere in the PPS/NTP code. > > Yes, you are right that is for the PPS code. > > The value of th_generation is saved in pps_capture() and I shouldn't add a > > while waiting it to be different that 0 there. > > If its value is 0, then the pps_event() returns early. > > This is something that could happen in very particular circumstance (pps > > event happens when the th_generation is 0). > > In uniprocessor configurations, we don't need the 0 special value. It is only > required in SMP configurations since one processor may > observe a timecounter update which is in progress on another processor. Being that case, the easiest solution will be to not check if pps->capgen == 0 in pps_event() for uniprocessors configurations. /* If the timecounter was wound up underneath us, bail out. */ #if defined(RTEMS_SMP) if (pps->capgen == 0 || pps->capgen != #else if (pps->capgen != #endif atomic_load_acq_int(&pps->capth->th_generation)) return; what do you think? ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: AW: AW: [PATCH 1/1] kern_tc.c: th_generation starts with 1 after overflow for single-core
On 30/05/2022 08:29, gabriel.moy...@dlr.de wrote: On 27.05.22 11:49,gabriel.moy...@dlr.de wrote: On 27.05.22 10:51, Sebastian Huber wrote: Hello Gabriel, the uniprocessor version uses an optimization at the reader side: #if defined(RTEMS_SMP) } while (gen == 0 || gen != th->th_generation); #else } while (gen != th->th_generation); #endif This is possible since the windup happens with interrupts disabled. I guess you need this optimization somewhere in the PPS/NTP code. Yes, you are right that is for the PPS code. The value of th_generation is saved in pps_capture() and I shouldn't add a while waiting it to be different that 0 there. If its value is 0, then the pps_event() returns early. This is something that could happen in very particular circumstance (pps event happens when the th_generation is 0). In uniprocessor configurations, we don't need the 0 special value. It is only required in SMP configurations since one processor may observe a timecounter update which is in progress on another processor. Being that case, the easiest solution will be to not check if pps->capgen == 0 in pps_event() for uniprocessors configurations. /* If the timecounter was wound up underneath us, bail out. */ #if defined(RTEMS_SMP) if (pps->capgen == 0 || pps->capgen != #else if (pps->capgen != #endif atomic_load_acq_int(&pps->capth->th_generation)) return; what do you think? Sounds good if it makes your test case passing. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
