Re: [PATCH 8/8] bsp/stm32h7: remove system files from start directory
On 15/05/2022 22:10, Karel Gardas wrote: The files are already presented in boards directories and are not needed in start directory anymore. Thanks, the patch set is fine. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: riscv failures from bsp builder
On 15/05/2022 19:51, Joel Sherrill wrote: This doesn't appear to fail on FreeBSD based on https://lists.rtems.org/pipermail/build/2022-May/033521.html. Not sure what that means. I didn't observe failures on my machine. It would be good to get the log messages with the actual failure. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH v3 00/11] ENABLE PPS API in RTEMS6
Hello Gabriel, I get a test failure in spntp01 now using the sparc/gr740 and arm/xilinx_zynq_a9_qemu BSP: F:23:0:UI1:init.c:84:2 == 0 Did you observe this test failure also? -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
AW: [PATCH v3 00/11] ENABLE PPS API in RTEMS6
> Hello Gabriel, > > I get a test failure in spntp01 now using the sparc/gr740 and > arm/xilinx_zynq_a9_qemu BSP: > > F:23:0:UI1:init.c:84:2 == 0 > > Did you observe this test failure also? > Yes, thanks for noticing it. It is due the changes in [PATCH v3 09/11]. The default value for pps_shift is PPS_FAVG which is equals to 2. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] bsp/arm: allocate .rtemsstack on REGION_STACK instead of on REGION_WORK
Hello,
this one seems to slip through. Nobody reviewed it nor commented yet.
I've been running with this patch here for about a month on various
STM32h7 boards without a problem.
Thanks!
Karel
On 4/7/22 21:15, Karel Gardas wrote:
REGION_WORK may be backed by external RAM which may not be initialized
in a time we need stack to work well. E.g. code loaded in flash,
stack allocated on in-cpu SRAM and data (REGION_WORK) on external SDRAM.
Sponsored-By: Precidata
---
bsps/arm/shared/start/linkcmds.base | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/bsps/arm/shared/start/linkcmds.base
b/bsps/arm/shared/start/linkcmds.base
index ec6c4e4557..10d2c54028 100644
--- a/bsps/arm/shared/start/linkcmds.base
+++ b/bsps/arm/shared/start/linkcmds.base
@@ -329,7 +329,7 @@ SECTIONS {
bsp_section_rtemsstack_begin = .;
*(SORT_BY_ALIGNMENT (SORT_BY_NAME (.rtemsstack*)))
bsp_section_rtemsstack_end = .;
- } > REGION_WORK AT > REGION_WORK
+ } > REGION_STACK AT > REGION_STACK
bsp_section_rtemsstack_size = bsp_section_rtemsstack_end -
bsp_section_rtemsstack_begin;
.noinit (NOLOAD) : ALIGN_WITH_INPUT {
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[PATCH 1/7] bsps/stm32h7: add board C files for stm32h757i-eval BSP
Sponsored-By: Precidata
---
.../stm/stm32h757i-eval/stm32h7-config-clk.c | 45 +
.../stm/stm32h757i-eval/stm32h7-config-osc.c | 53 ++
.../stm/stm32h757i-eval/stm32h7-config-per.c | 39 +
.../stm/stm32h757i-eval/system_stm32h7xx.c| 794 ++
4 files changed, 931 insertions(+)
create mode 100644
bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-clk.c
create mode 100644
bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-osc.c
create mode 100644
bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-per.c
create mode 100644
bsps/arm/stm32h7/boards/stm/stm32h757i-eval/system_stm32h7xx.c
diff --git a/bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-clk.c
b/bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-clk.c
new file mode 100644
index 00..c4ea947c3c
--- /dev/null
+++ b/bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-clk.c
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2022 Karel Gardas
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+
+const RCC_ClkInitTypeDef stm32h7_config_clocks = {
+ .ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
+| RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1,
+ .SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK,
+ .SYSCLKDivider = RCC_SYSCLK_DIV1,
+ .AHBCLKDivider = RCC_HCLK_DIV2,
+ .APB3CLKDivider = RCC_APB3_DIV2,
+ .APB1CLKDivider = RCC_APB1_DIV2,
+ .APB2CLKDivider = RCC_APB2_DIV2,
+ .APB4CLKDivider = RCC_APB4_DIV2
+};
diff --git a/bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-osc.c
b/bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-osc.c
new file mode 100644
index 00..8f23508cbb
--- /dev/null
+++ b/bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-osc.c
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2022 Karel Gardas
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+
+const RCC_OscInitTypeDef stm32h7_config_oscillator = {
+ .OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE
+| RCC_OSCILLATORTYPE_HSI48,
+ .HSEState = RCC_HSE_ON,
+ .LSEState = RCC_LSE_OFF,
+ .HSIState = RCC_HSI_DIV1,
+ .HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT,
+ .HSI48Sta
[PATCH 2/7] bsps/stm32h7: add configuration and enable build of stm32h757i-eval BSP
This is minimalist configuration for the stm32h757i-eval BSP provided
here. The only general enhancement worth mention is boot core
configuration which is needed here as this is the first dual-core board
supported by stm32h7 BSP family and we need to choose boot core in order
to get C files compiling well.
Sponsored-By: Precidata
---
.../bsps/arm/stm32h7/bspstm32h757i-eval.yml | 21 +
spec/build/bsps/arm/stm32h7/grp.yml | 2 ++
spec/build/bsps/arm/stm32h7/optbootcore.yml | 23 +++
spec/build/bsps/arm/stm32h7/optlinkcmds.yml | 1 +
spec/build/bsps/arm/stm32h7/optpwrsupply.yml | 1 +
.../bsps/arm/stm32h7/optusart1gpioregs.yml| 3 +++
spec/build/bsps/arm/stm32h7/optvariant.yml| 3 +++
7 files changed, 54 insertions(+)
create mode 100644 spec/build/bsps/arm/stm32h7/bspstm32h757i-eval.yml
create mode 100644 spec/build/bsps/arm/stm32h7/optbootcore.yml
diff --git a/spec/build/bsps/arm/stm32h7/bspstm32h757i-eval.yml
b/spec/build/bsps/arm/stm32h7/bspstm32h757i-eval.yml
new file mode 100644
index 00..4ef5690a65
--- /dev/null
+++ b/spec/build/bsps/arm/stm32h7/bspstm32h757i-eval.yml
@@ -0,0 +1,21 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: arm
+bsp: stm32h757i-eval
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2022 Karel Gardas
+cppflags: []
+enabled-by: true
+family: stm32h7
+includes: []
+install: []
+links:
+- role: build-dependency
+ uid: grp
+source:
+- bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-clk.c
+- bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-osc.c
+- bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-per.c
+- bsps/arm/stm32h7/boards/stm/stm32h757i-eval/system_stm32h7xx.c
+type: build
diff --git a/spec/build/bsps/arm/stm32h7/grp.yml
b/spec/build/bsps/arm/stm32h7/grp.yml
index 7cb8f698cc..401b8b415a 100644
--- a/spec/build/bsps/arm/stm32h7/grp.yml
+++ b/spec/build/bsps/arm/stm32h7/grp.yml
@@ -83,6 +83,8 @@ links:
uid: optprintkinstance
- role: build-dependency
uid: optpwrsupply
+- role: build-dependency
+ uid: optbootcore
- role: build-dependency
uid: optusart1gpiopins
- role: build-dependency
diff --git a/spec/build/bsps/arm/stm32h7/optbootcore.yml
b/spec/build/bsps/arm/stm32h7/optbootcore.yml
new file mode 100644
index 00..53ffb496cc
--- /dev/null
+++ b/spec/build/bsps/arm/stm32h7/optbootcore.yml
@@ -0,0 +1,23 @@
+actions:
+- get-string: null
+- script: |
+ cores = ["CORE_CM7", "CORE_CM4", "BOOT_CORE_DEFINE_NOT_NEEDED"]
+ if value not in cores:
+ conf.fatal("STM32H7 boot core '{}' is not one of
{}".format(value, cores))
+ conf.define_cond(value, True)
+build-type: option
+default: BOOT_CORE_DEFINE_NOT_NEEDED
+default-by-variant:
+- value: CORE_CM7
+ variants:
+ - arm/stm32h757i-eval
+enabled-by: true
+format: '{}'
+links: []
+name: STM32H7_BOOT_CORE
+description: |
+ Select the boot core. Possible values are CORE_CM7 and CORE_CM4
+type: build
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2022 Karel Gardas
diff --git a/spec/build/bsps/arm/stm32h7/optlinkcmds.yml
b/spec/build/bsps/arm/stm32h7/optlinkcmds.yml
index 18a1983f63..a7281addd8 100644
--- a/spec/build/bsps/arm/stm32h7/optlinkcmds.yml
+++ b/spec/build/bsps/arm/stm32h7/optlinkcmds.yml
@@ -7,6 +7,7 @@ default-by-variant:
- value: linkcmds.flash
variants:
- arm/stm32h7b3i-dk
+ - arm/stm32h757i-eval
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optpwrsupply.yml
b/spec/build/bsps/arm/stm32h7/optpwrsupply.yml
index d7eeb63906..76888fc1ca 100644
--- a/spec/build/bsps/arm/stm32h7/optpwrsupply.yml
+++ b/spec/build/bsps/arm/stm32h7/optpwrsupply.yml
@@ -7,6 +7,7 @@ default-by-variant:
- value: PWR_DIRECT_SMPS_SUPPLY
variants:
- arm/stm32h7b3i-dk
+ - arm/stm32h757i-eval
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optusart1gpioregs.yml
b/spec/build/bsps/arm/stm32h7/optusart1gpioregs.yml
index 46d10616bb..e389efe6a9 100644
--- a/spec/build/bsps/arm/stm32h7/optusart1gpioregs.yml
+++ b/spec/build/bsps/arm/stm32h7/optusart1gpioregs.yml
@@ -7,6 +7,9 @@ default-by-variant:
- value: GPIOA
variants:
- arm/stm32h7b3i-dk
+- value: GPIOB
+ variants:
+ - arm/stm32h757i-eval
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optvariant.yml
b/spec/build/bsps/arm/stm32h7/optvariant.yml
index 5d77ece120..fd77d26f7f 100644
--- a/spec/build/bsps/arm/stm32h7/optvariant.yml
+++ b/spec/build/bsps/arm/stm32h7/optvariant.yml
@@ -17,6 +17,9 @@ default-by-variant:
- value: STM32H7B3xxQ
variants:
- arm/stm32h7b3i-dk
+- value: STM32H757xx
+ variants:
+- arm/stm32h757i-eval
enabled-by: true
format: '{}'
links: []
--
2.25.1
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[PATCH 3/7] bsps/stm32h7: disable all U(S)ARTs except USART1 on stm32h757i-eval BSP
This patch disables all U(S)ARTs which are not supported by the board
itself and its provided connectors.
Sponsored-By: Precidata
---
spec/build/bsps/arm/stm32h7/optenuart4.yml | 5 -
spec/build/bsps/arm/stm32h7/optenuart5.yml | 1 +
spec/build/bsps/arm/stm32h7/optenuart7.yml | 1 +
spec/build/bsps/arm/stm32h7/optenuart8.yml | 1 +
spec/build/bsps/arm/stm32h7/optenuart9.yml | 1 +
spec/build/bsps/arm/stm32h7/optenusart10.yml | 1 +
spec/build/bsps/arm/stm32h7/optenusart2.yml | 6 +-
spec/build/bsps/arm/stm32h7/optenusart3.yml | 1 +
spec/build/bsps/arm/stm32h7/optenusart6.yml | 1 +
9 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/spec/build/bsps/arm/stm32h7/optenuart4.yml
b/spec/build/bsps/arm/stm32h7/optenuart4.yml
index cd5fd31370..8665f4c821 100644
--- a/spec/build/bsps/arm/stm32h7/optenuart4.yml
+++ b/spec/build/bsps/arm/stm32h7/optenuart4.yml
@@ -3,7 +3,10 @@ actions:
- define-condition: null
build-type: option
default: true
-default-by-variant: []
+default-by-variant:
+- value: false
+ variants:
+ - arm/stm32h757i-eval
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenuart5.yml
b/spec/build/bsps/arm/stm32h7/optenuart5.yml
index 413f9447b8..f32f719f49 100644
--- a/spec/build/bsps/arm/stm32h7/optenuart5.yml
+++ b/spec/build/bsps/arm/stm32h7/optenuart5.yml
@@ -7,6 +7,7 @@ default-by-variant:
- value: false
variants:
- arm/stm32h7b3i-dk
+ - arm/stm32h757i-eval
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenuart7.yml
b/spec/build/bsps/arm/stm32h7/optenuart7.yml
index c9884fcb46..bd9ed8fe76 100644
--- a/spec/build/bsps/arm/stm32h7/optenuart7.yml
+++ b/spec/build/bsps/arm/stm32h7/optenuart7.yml
@@ -7,6 +7,7 @@ default-by-variant:
- value: false
variants:
- arm/stm32h7b3i-dk
+ - arm/stm32h757i-eval
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenuart8.yml
b/spec/build/bsps/arm/stm32h7/optenuart8.yml
index 593f736970..74304e1256 100644
--- a/spec/build/bsps/arm/stm32h7/optenuart8.yml
+++ b/spec/build/bsps/arm/stm32h7/optenuart8.yml
@@ -7,6 +7,7 @@ default-by-variant:
- value: false
variants:
- arm/stm32h7b3i-dk
+ - arm/stm32h757i-eval
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenuart9.yml
b/spec/build/bsps/arm/stm32h7/optenuart9.yml
index 596aae59ef..76378c622d 100644
--- a/spec/build/bsps/arm/stm32h7/optenuart9.yml
+++ b/spec/build/bsps/arm/stm32h7/optenuart9.yml
@@ -7,6 +7,7 @@ default-by-variant:
- value: false
variants:
- arm/stm32h7b3i-dk
+ - arm/stm32h757i-eval
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenusart10.yml
b/spec/build/bsps/arm/stm32h7/optenusart10.yml
index d5c5a1906e..1558bdb017 100644
--- a/spec/build/bsps/arm/stm32h7/optenusart10.yml
+++ b/spec/build/bsps/arm/stm32h7/optenusart10.yml
@@ -7,6 +7,7 @@ default-by-variant:
- value: false
variants:
- arm/stm32h7b3i-dk
+ - arm/stm32h757i-eval
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenusart2.yml
b/spec/build/bsps/arm/stm32h7/optenusart2.yml
index 0bbec65278..05f73df137 100644
--- a/spec/build/bsps/arm/stm32h7/optenusart2.yml
+++ b/spec/build/bsps/arm/stm32h7/optenusart2.yml
@@ -3,7 +3,11 @@ actions:
- define-condition: null
build-type: option
default: true
-default-by-variant: []
+default-by-variant:
+default-by-variant:
+- value: false
+ variants:
+ - arm/stm32h757i-eval
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenusart3.yml
b/spec/build/bsps/arm/stm32h7/optenusart3.yml
index f74ea31fa3..1d676fdc3c 100644
--- a/spec/build/bsps/arm/stm32h7/optenusart3.yml
+++ b/spec/build/bsps/arm/stm32h7/optenusart3.yml
@@ -7,6 +7,7 @@ default-by-variant:
- value: false
variants:
- arm/stm32h7b3i-dk
+ - arm/stm32h757i-eval
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenusart6.yml
b/spec/build/bsps/arm/stm32h7/optenusart6.yml
index 51791b56cd..17761be7c3 100644
--- a/spec/build/bsps/arm/stm32h7/optenusart6.yml
+++ b/spec/build/bsps/arm/stm32h7/optenusart6.yml
@@ -7,6 +7,7 @@ default-by-variant:
- value: false
variants:
- arm/stm32h7b3i-dk
+ - arm/stm32h757i-eval
enabled-by: true
format: '{}'
links: []
--
2.25.1
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[PATCH 4/7] bsps/stm32h7: add and enable test set exclusion for stm32h757i-eval BSP
Sponsored-By: Precidata --- .../bsps/arm/stm32h7/bspstm32h757i-eval.yml | 2 ++ .../bsps/arm/stm32h7/tststm32h757i-eval.yml | 19 +++ 2 files changed, 21 insertions(+) create mode 100644 spec/build/bsps/arm/stm32h7/tststm32h757i-eval.yml diff --git a/spec/build/bsps/arm/stm32h7/bspstm32h757i-eval.yml b/spec/build/bsps/arm/stm32h7/bspstm32h757i-eval.yml index 4ef5690a65..541210952c 100644 --- a/spec/build/bsps/arm/stm32h7/bspstm32h757i-eval.yml +++ b/spec/build/bsps/arm/stm32h7/bspstm32h757i-eval.yml @@ -13,6 +13,8 @@ install: [] links: - role: build-dependency uid: grp +- role: build-dependency + uid: tststm32h757i-eval source: - bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-clk.c - bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-osc.c diff --git a/spec/build/bsps/arm/stm32h7/tststm32h757i-eval.yml b/spec/build/bsps/arm/stm32h7/tststm32h757i-eval.yml new file mode 100644 index 00..656461c9aa --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/tststm32h757i-eval.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- set-test-state: +linpack: exclude +fsdosfsname01: exclude +record02: exclude +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +default: null +default-by-variant: [] +description: '' +enabled-by: true +links: +- role: build-dependency + uid: ../../tstnoiconv +- role: build-dependency + uid: ../../tstnolibdl +type: build -- 2.25.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 5/7] bsps/stm32h7: provide linkcmds for SRAM, FLASH+SDRAM and SRAM+SDRAM linking
Sponsored-By: Precidata
---
spec/build/bsps/arm/stm32h7/grp.yml | 6 +++
.../bsps/arm/stm32h7/linkcmdsflashsdram.yml | 49 +++
spec/build/bsps/arm/stm32h7/linkcmdssram.yml | 49 +++
.../bsps/arm/stm32h7/linkcmdssramsdram.yml| 49 +++
spec/build/bsps/arm/stm32h7/optlinkcmds.yml | 5 +-
5 files changed, 156 insertions(+), 2 deletions(-)
create mode 100644 spec/build/bsps/arm/stm32h7/linkcmdsflashsdram.yml
create mode 100644 spec/build/bsps/arm/stm32h7/linkcmdssram.yml
create mode 100644 spec/build/bsps/arm/stm32h7/linkcmdssramsdram.yml
diff --git a/spec/build/bsps/arm/stm32h7/grp.yml
b/spec/build/bsps/arm/stm32h7/grp.yml
index 401b8b415a..6e7036b6aa 100644
--- a/spec/build/bsps/arm/stm32h7/grp.yml
+++ b/spec/build/bsps/arm/stm32h7/grp.yml
@@ -117,6 +117,12 @@ links:
uid: linkcmds
- role: build-dependency
uid: linkcmdssdram
+- role: build-dependency
+ uid: linkcmdssram
+- role: build-dependency
+ uid: linkcmdssramsdram
+- role: build-dependency
+ uid: linkcmdsflashsdram
- role: build-dependency
uid: ../../bspopts
type: build
diff --git a/spec/build/bsps/arm/stm32h7/linkcmdsflashsdram.yml
b/spec/build/bsps/arm/stm32h7/linkcmdsflashsdram.yml
new file mode 100644
index 00..8b24c939bf
--- /dev/null
+++ b/spec/build/bsps/arm/stm32h7/linkcmdsflashsdram.yml
@@ -0,0 +1,49 @@
+build-type: script
+do-build: |
+ bld.install_as("${BSP_LIBDIR}/linkcmds.flash+sdram", "linkcmds.flash+sdram")
+do-configure: |
+ content = """INCLUDE linkcmds.memory
+
+ REGION_ALIAS ("REGION_START", FLASH);
+ REGION_ALIAS ("REGION_VECTOR", FLASH);
+ REGION_ALIAS ("REGION_TEXT", FLASH);
+ REGION_ALIAS ("REGION_TEXT_LOAD", FLASH);
+ REGION_ALIAS ("REGION_RODATA", FLASH);
+ REGION_ALIAS ("REGION_RODATA_LOAD", FLASH);
+ REGION_ALIAS ("REGION_DATA", SRAM_AXI);
+ REGION_ALIAS ("REGION_DATA_LOAD", FLASH);
+ REGION_ALIAS ("REGION_FAST_TEXT", ITCM);
+ REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ITCM);
+ REGION_ALIAS ("REGION_FAST_DATA", DTCM);
+ REGION_ALIAS ("REGION_FAST_DATA_LOAD", DTCM);
+ REGION_ALIAS ("REGION_BSS", SRAM_AXI);
+ REGION_ALIAS ("REGION_WORK", SDRAM_2);
+ REGION_ALIAS ("REGION_STACK", SRAM_AXI);
+ REGION_ALIAS ("REGION_NOCACHE", SRAM_1);
+ REGION_ALIAS ("REGION_NOCACHE_LOAD", FLASH);
+
+ bsp_vector_table_in_start_section = 1;
+ """
+
+ if conf.env.STM32H7_ENABLE_MPU_ALIGNMENT:
+ content += """
+ bsp_align_text_and_rodata_end_to_power_of_2 = 1;
+ """
+
+ content += """
+ INCLUDE linkcmds.armv7m
+ """
+ f = conf.bldnode.make_node(
+ conf.env.VARIANT + "/linkcmds.flash+sdram"
+ )
+ f.parent.mkdir()
+ f.write(content)
+ conf.env.append_value("cfg_files", f.abspath())
+enabled-by: true
+links: []
+prepare-build: null
+prepare-configure: null
+type: build
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
diff --git a/spec/build/bsps/arm/stm32h7/linkcmdssram.yml
b/spec/build/bsps/arm/stm32h7/linkcmdssram.yml
new file mode 100644
index 00..808bff3627
--- /dev/null
+++ b/spec/build/bsps/arm/stm32h7/linkcmdssram.yml
@@ -0,0 +1,49 @@
+build-type: script
+do-build: |
+ bld.install_as("${BSP_LIBDIR}/linkcmds.sram", "linkcmds.sram")
+do-configure: |
+ content = """INCLUDE linkcmds.memory
+
+ REGION_ALIAS ("REGION_START", SRAM_AXI);
+ REGION_ALIAS ("REGION_VECTOR", SRAM_AXI);
+ REGION_ALIAS ("REGION_TEXT", SRAM_AXI);
+ REGION_ALIAS ("REGION_TEXT_LOAD", SRAM_AXI);
+ REGION_ALIAS ("REGION_RODATA", SRAM_AXI);
+ REGION_ALIAS ("REGION_RODATA_LOAD", SRAM_AXI);
+ REGION_ALIAS ("REGION_DATA", SRAM_AXI);
+ REGION_ALIAS ("REGION_DATA_LOAD", SRAM_AXI);
+ REGION_ALIAS ("REGION_FAST_TEXT", ITCM);
+ REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ITCM);
+ REGION_ALIAS ("REGION_FAST_DATA", DTCM);
+ REGION_ALIAS ("REGION_FAST_DATA_LOAD", DTCM);
+ REGION_ALIAS ("REGION_BSS", SRAM_AXI);
+ REGION_ALIAS ("REGION_WORK", SRAM_AXI);
+ REGION_ALIAS ("REGION_STACK", SRAM_AXI);
+ REGION_ALIAS ("REGION_NOCACHE", SRAM_1);
+ REGION_ALIAS ("REGION_NOCACHE_LOAD", SRAM_AXI);
+
+ bsp_vector_table_in_start_section = 1;
+ """
+
+ if conf.env.STM32H7_ENABLE_MPU_ALIGNMENT:
+ content += """
+ bsp_align_text_and_rodata_end_to_power_of_2 = 1;
+ """
+
+ content += """
+ INCLUDE linkcmds.armv7m
+ """
+ f = conf.bldnode.make_node(
+ conf.env.VARIANT + "/linkcmds.sram"
+ )
+ f.parent.mkdir()
+ f.write(content)
+ conf.env.append_value("cfg_files", f.abspath())
+enabled-by: true
+links: []
+prepare-build: null
+prepare-configure: null
+type: build
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
diff --git a/spec/build/bsps/arm/stm32h7/linkcmdssramsdram.yml
b/spec/build/bsps/arm/stm32h7/linkcmdssramsdram.yml
new file mode 100644
index 00..a1122d6551
--- /dev/null
+++ b/spec/build/bsps/arm/stm32h7/linkcmdssramsdram.yml
@@ -0,0
[PATCH 6/7] bsps/stm32h7: enable SDRAM 2 MPU region
Sponsored-By: Precidata
---
bsps/arm/stm32h7/start/mpu-config.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/bsps/arm/stm32h7/start/mpu-config.c
b/bsps/arm/stm32h7/start/mpu-config.c
index 8140e73c37..ce3c92ccb0 100644
--- a/bsps/arm/stm32h7/start/mpu-config.c
+++ b/bsps/arm/stm32h7/start/mpu-config.c
@@ -44,6 +44,13 @@ const ARMV7M_MPU_Region_config stm32h7_config_mpu_region []
= {
| ARMV7M_MPU_RASR_AP(0x3)
| ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
| ARMV7M_MPU_RASR_ENABLE,
+}, {
+ .begin = stm32h7_memory_sdram_2_begin,
+ .end = stm32h7_memory_sdram_2_end,
+ .rasr = ARMV7M_MPU_RASR_XN
+| ARMV7M_MPU_RASR_AP(0x3)
+| ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
+| ARMV7M_MPU_RASR_ENABLE,
}, {
.begin = bsp_section_start_begin,
.end = bsp_section_text_end,
--
2.25.1
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[PATCH 7/7] bsps/stm32h7: set default SDRAM x sizes on stm32h757i-eval BSP
This means:
SDRAM 1: 0
SDRAM 2: 32 MB
Sponsored-By: Precidata
---
spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml | 1 +
spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml | 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml
b/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml
index b748d7d3f7..4825a6446b 100644
--- a/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml
+++ b/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml
@@ -7,6 +7,7 @@ default-by-variant:
- value: 0
variants:
- arm/stm32h7b3i-dk
+ - arm/stm32h757i-eval
enabled-by: true
format: '{:#010x}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml
b/spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml
index 5a1ffdcace..dff8a772e4 100644
--- a/spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml
+++ b/spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml
@@ -3,7 +3,10 @@ actions:
- env-assign: null
build-type: option
default: 0
-default-by-variant: []
+default-by-variant:
+- value: 33554432
+ variants:
+ - arm/stm32h757i-eval
enabled-by: true
format: '{:#010x}'
links: []
--
2.25.1
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[PATCH 1/7] bsps/arm: add CMSIS Cortex-M4 Core Peripheral Access Layer Header File
---
bsps/arm/include/core_cm4.h | 1937 +++
1 file changed, 1937 insertions(+)
create mode 100644 bsps/arm/include/core_cm4.h
diff --git a/bsps/arm/include/core_cm4.h b/bsps/arm/include/core_cm4.h
new file mode 100644
index 00..dc840ebf22
--- /dev/null
+++ b/bsps/arm/include/core_cm4.h
@@ -0,0 +1,1937 @@
+/**//**
+ * @file core_cm4.h
+ * @briefCMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+
**/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+
---*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA
check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type:
'{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/***
+ * CMSIS definitions
+
**/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (0x04U)
/*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x1EU)
/*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+__CM4_CMSIS_VERSION_SUB )
/*!< CMSIS HAL version number */
+
+#define __CORTEX_M(0x04U)
/*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM__asm /*!< asm
keyword for ARM Compiler */
+ #define __INLINE __inline /*!<
inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM__asm /*!< asm
keyword for ARM Compiler */
+ #define __INLINE __inline /*!<
inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM__asm /*!< asm
keyword for GNU Compiler */
+ #define __INLINE inline /*!<
inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+
[PATCH 3/7] bsps/stm32h7: enable cache and MPU only on Cortex-M7
Sponsored-By: Precidata
---
bsps/arm/stm32h7/start/bspstarthooks.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/bsps/arm/stm32h7/start/bspstarthooks.c
b/bsps/arm/stm32h7/start/bspstarthooks.c
index ef26af5eba..10ae2bf0d3 100644
--- a/bsps/arm/stm32h7/start/bspstarthooks.c
+++ b/bsps/arm/stm32h7/start/bspstarthooks.c
@@ -101,7 +101,7 @@ void bsp_start_hook_0(void)
HAL_Init();
SystemInit_ExtMemCtl();
}
-
+#if defined(CORE_CM7)
if ((SCB->CCR & SCB_CCR_IC_Msk) == 0) {
SCB_EnableICache();
}
@@ -111,12 +111,15 @@ void bsp_start_hook_0(void)
}
_ARMV7M_MPU_Setup(stm32h7_config_mpu_region,
stm32h7_config_mpu_region_count);
+#endif
}
void bsp_start_hook_1(void)
{
bsp_start_copy_sections_compact();
+#if defined(CORE_CM7)
SCB_CleanDCache();
SCB_InvalidateICache();
+#endif
bsp_start_clear_bss();
}
--
2.25.1
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[PATCH 2/7] bsps/arm: disable cache operations on Cortex-M4
---
bsps/arm/shared/cache/cache-v7m.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/bsps/arm/shared/cache/cache-v7m.c
b/bsps/arm/shared/cache/cache-v7m.c
index f5a9e208e5..100d38765f 100644
--- a/bsps/arm/shared/cache/cache-v7m.c
+++ b/bsps/arm/shared/cache/cache-v7m.c
@@ -9,21 +9,25 @@
#include
#include
+#if __CORTEX_M != 0x04U
#define CPU_DATA_CACHE_ALIGNMENT 32
#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
+#endif
static inline void _CPU_cache_flush_data_range(
const void *d_addr,
size_t n_bytes
)
{
+#if __CORTEX_M != 0x04U
SCB_CleanInvalidateDCache_by_Addr(
RTEMS_DECONST(uint32_t *, (const uint32_t *) d_addr),
n_bytes
);
+#endif
}
static inline void _CPU_cache_invalidate_data_range(
@@ -31,10 +35,12 @@ static inline void _CPU_cache_invalidate_data_range(
size_t n_bytes
)
{
+#if __CORTEX_M != 0x04U
SCB_InvalidateDCache_by_Addr(
RTEMS_DECONST(uint32_t *, (const uint32_t *) d_addr),
n_bytes
);
+#endif
}
static inline void _CPU_cache_freeze_data(void)
@@ -52,11 +58,13 @@ static inline void _CPU_cache_invalidate_instruction_range(
size_t n_bytes
)
{
+#if __CORTEX_M != 0x04U
rtems_interrupt_level level;
rtems_interrupt_disable(level);
SCB_InvalidateICache();
rtems_interrupt_enable(level);
+#endif
}
static inline void _CPU_cache_freeze_instruction(void)
@@ -71,65 +79,79 @@ static inline void _CPU_cache_unfreeze_instruction(void)
static inline void _CPU_cache_flush_entire_data(void)
{
+#if __CORTEX_M != 0x04U
rtems_interrupt_level level;
rtems_interrupt_disable(level);
SCB_CleanDCache();
rtems_interrupt_enable(level);
+#endif
}
static inline void _CPU_cache_invalidate_entire_data(void)
{
+#if __CORTEX_M != 0x04U
rtems_interrupt_level level;
rtems_interrupt_disable(level);
SCB_InvalidateDCache();
rtems_interrupt_enable(level);
+#endif
}
static inline void _CPU_cache_enable_data(void)
{
+#if __CORTEX_M != 0x04U
rtems_interrupt_level level;
rtems_interrupt_disable(level);
SCB_EnableDCache();
rtems_interrupt_enable(level);
+#endif
}
static inline void _CPU_cache_disable_data(void)
{
+#if __CORTEX_M != 0x04U
rtems_interrupt_level level;
rtems_interrupt_disable(level);
SCB_DisableDCache();
rtems_interrupt_enable(level);
+#endif
}
static inline void _CPU_cache_invalidate_entire_instruction(void)
{
+#if __CORTEX_M != 0x04U
rtems_interrupt_level level;
rtems_interrupt_disable(level);
SCB_InvalidateICache();
rtems_interrupt_enable(level);
+#endif
}
static inline void _CPU_cache_enable_instruction(void)
{
+#if __CORTEX_M != 0x04U
rtems_interrupt_level level;
rtems_interrupt_disable(level);
SCB_EnableICache();
rtems_interrupt_enable(level);
+#endif
}
static inline void _CPU_cache_disable_instruction(void)
{
+#if __CORTEX_M != 0x04U
rtems_interrupt_level level;
rtems_interrupt_disable(level);
SCB_DisableICache();
rtems_interrupt_enable(level);
+#endif
}
#include "../../shared/cache/cacheimpl.h"
--
2.25.1
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[PATCH 4/7] bsps/stm32h7: include CMSIS Cortex-M4 header when required by configuration
Sponsored-By: Precidata --- bsps/arm/stm32h7/include/chip.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/bsps/arm/stm32h7/include/chip.h b/bsps/arm/stm32h7/include/chip.h index 26b067a3b7..ac579c0743 100644 --- a/bsps/arm/stm32h7/include/chip.h +++ b/bsps/arm/stm32h7/include/chip.h @@ -29,6 +29,13 @@ #define LIBBSP_ARM_STM32H7_CHIP_H #include +#if defined(CORE_CM7) || defined(BOOT_CORE_DEFINE_NOT_NEEDED) +/* M7 is a default core of the H7 family */ #include +#elif defined(CORE_CM4) +#include +#else +#error "Boot core definition missing!" +#endif #endif /* LIBBSP_ARM_STM32H7_CHIP_H */ -- 2.25.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 5/7] bsps/stm32h7: add configuration and enable build of stm32h757i-eval-m4 BSP
This is minimalist configuration for the stm32h757i-eval-m4 BSP provided
here. The only general enhancement worth mention is a flash origin address
configuration which is needed for simplification as M4 core boots
from second flash bank which starts at 0x810 by default. The boot
address of the core may be changed by using STM32CubeProgrammer. If done
so then also BSP configuration needs to be changed accordingly.
As the BSP variant is running on M4 core, there is also more configuration
changes required here. E.g. boot core and ABI (compilation flags)
in comparison with stm32h757i-eval BSP. On the other hand, C code is shared
completely with this BSP variant.
Sponsored-By: Precidata
---
spec/build/bsps/arm/stm32h7/abi.yml | 9 +++-
.../arm/stm32h7/bspstm32h757i-eval-m4.yml | 23 +++
spec/build/bsps/arm/stm32h7/grp.yml | 2 ++
.../build/bsps/arm/stm32h7/linkcmdsmemory.yml | 2 +-
spec/build/bsps/arm/stm32h7/optbootcore.yml | 3 +++
spec/build/bsps/arm/stm32h7/optlinkcmds.yml | 1 +
.../bsps/arm/stm32h7/optmemflashorigin.yml| 19 +++
spec/build/bsps/arm/stm32h7/optmemflashsz.yml | 6 -
spec/build/bsps/arm/stm32h7/optpwrsupply.yml | 1 +
.../bsps/arm/stm32h7/optusart1gpioregs.yml| 1 +
spec/build/bsps/arm/stm32h7/optvariant.yml| 1 +
11 files changed, 65 insertions(+), 3 deletions(-)
create mode 100644 spec/build/bsps/arm/stm32h7/bspstm32h757i-eval-m4.yml
create mode 100644 spec/build/bsps/arm/stm32h7/optmemflashorigin.yml
diff --git a/spec/build/bsps/arm/stm32h7/abi.yml
b/spec/build/bsps/arm/stm32h7/abi.yml
index 697220b1b1..dd751cb72e 100644
--- a/spec/build/bsps/arm/stm32h7/abi.yml
+++ b/spec/build/bsps/arm/stm32h7/abi.yml
@@ -8,7 +8,14 @@ default:
- -mcpu=cortex-m7
- -mfpu=fpv5-d16
- -mfloat-abi=hard
-default-by-variant: []
+default-by-variant:
+- value:
+ - -mthumb
+ - -mcpu=cortex-m4
+ - -mfpu=fpv4-sp-d16
+ - -mfloat-abi=hard
+ variants:
+ - arm/stm32h757i-eval-m4
enabled-by: true
links: []
name: ABI_FLAGS
diff --git a/spec/build/bsps/arm/stm32h7/bspstm32h757i-eval-m4.yml
b/spec/build/bsps/arm/stm32h7/bspstm32h757i-eval-m4.yml
new file mode 100644
index 00..588b97f7c3
--- /dev/null
+++ b/spec/build/bsps/arm/stm32h7/bspstm32h757i-eval-m4.yml
@@ -0,0 +1,23 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: arm
+bsp: stm32h757i-eval-m4
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2022 Karel Gardas
+cppflags: []
+enabled-by: true
+family: stm32h7
+includes: []
+install: []
+links:
+- role: build-dependency
+ uid: grp
+- role: build-dependency
+ uid: tststm32h757i-eval
+source:
+- bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-clk.c
+- bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-osc.c
+- bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-config-per.c
+- bsps/arm/stm32h7/boards/stm/stm32h757i-eval/system_stm32h7xx.c
+type: build
diff --git a/spec/build/bsps/arm/stm32h7/grp.yml
b/spec/build/bsps/arm/stm32h7/grp.yml
index 6e7036b6aa..c056a2034b 100644
--- a/spec/build/bsps/arm/stm32h7/grp.yml
+++ b/spec/build/bsps/arm/stm32h7/grp.yml
@@ -51,6 +51,8 @@ links:
uid: optmemflashsz
- role: build-dependency
uid: optmemflashlatency
+- role: build-dependency
+ uid: optmemflashorigin
- role: build-dependency
uid: optmemitcmsz
- role: build-dependency
diff --git a/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml
b/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml
index 7ff7f3da5e..78f0308832 100644
--- a/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml
+++ b/spec/build/bsps/arm/stm32h7/linkcmdsmemory.yml
@@ -3,7 +3,7 @@ content: |
MEMORY {
NULL: ORIGIN = 0x, LENGTH =
${STM32H7_MEMORY_NULL_SIZE:#010x}
ITCM: ORIGIN = ${STM32H7_MEMORY_NULL_SIZE:#010x}, LENGTH =
${STM32H7_MEMORY_ITCM_SIZE:#010x}
-FLASH : ORIGIN = 0x0800, LENGTH =
${STM32H7_MEMORY_FLASH_SIZE:#010x}
+FLASH : ORIGIN = ${STM32H7_MEMORY_FLASH_ORIGIN:#010x}, LENGTH =
${STM32H7_MEMORY_FLASH_SIZE:#010x}
DTCM: ORIGIN = 0x2000, LENGTH =
${STM32H7_MEMORY_DTCM_SIZE:#010x}
SRAM_AXI: ORIGIN = 0x2400, LENGTH =
${STM32H7_MEMORY_SRAM_AXI_SIZE:#010x}
SRAM_1 : ORIGIN = 0x3000, LENGTH =
${STM32H7_MEMORY_SRAM_1_SIZE:#010x}
diff --git a/spec/build/bsps/arm/stm32h7/optbootcore.yml
b/spec/build/bsps/arm/stm32h7/optbootcore.yml
index 53ffb496cc..e6f52e8631 100644
--- a/spec/build/bsps/arm/stm32h7/optbootcore.yml
+++ b/spec/build/bsps/arm/stm32h7/optbootcore.yml
@@ -11,6 +11,9 @@ default-by-variant:
- value: CORE_CM7
variants:
- arm/stm32h757i-eval
+- value: CORE_CM4
+ variants:
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optlinkcmds.yml
b/spec/build/bsps/arm/stm32h7/optlinkcmds.yml
index d767ade48c..f6e50f31ae 100644
--- a/spec/build/bsps/arm/stm32h7/optlinkcmds.yml
+++ b/spec/build/bsps/arm/stm32h7/optlinkcmds.y
[PATCH 6/7] bsps/stm32h7: set default SDRAM x sizes on stm32h757i-eval-m4 BSP
This means:
SDRAM 1: 0
SDRAM 2: 32 MB
Sponsored-By: Precidata
---
spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml | 1 +
spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml | 1 +
2 files changed, 2 insertions(+)
diff --git a/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml
b/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml
index 4825a6446b..82267648a4 100644
--- a/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml
+++ b/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml
@@ -8,6 +8,7 @@ default-by-variant:
variants:
- arm/stm32h7b3i-dk
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{:#010x}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml
b/spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml
index dff8a772e4..9fa8accbf4 100644
--- a/spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml
+++ b/spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml
@@ -7,6 +7,7 @@ default-by-variant:
- value: 33554432
variants:
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{:#010x}'
links: []
--
2.25.1
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http://lists.rtems.org/mailman/listinfo/devel
[PATCH 7/7] bsps/stm32h7: disable all U(S)ARTs except USART1 on stm32h757i-eval-m4 BSP
This patch disables all U(S)ARTs which are not supported by the board
itself and its provided connectors.
Sponsored-By: Precidata
---
spec/build/bsps/arm/stm32h7/optenuart4.yml | 1 +
spec/build/bsps/arm/stm32h7/optenuart5.yml | 1 +
spec/build/bsps/arm/stm32h7/optenuart7.yml | 1 +
spec/build/bsps/arm/stm32h7/optenuart8.yml | 1 +
spec/build/bsps/arm/stm32h7/optenuart9.yml | 1 +
spec/build/bsps/arm/stm32h7/optenusart10.yml | 1 +
spec/build/bsps/arm/stm32h7/optenusart2.yml | 1 +
spec/build/bsps/arm/stm32h7/optenusart3.yml | 1 +
spec/build/bsps/arm/stm32h7/optenusart6.yml | 1 +
9 files changed, 9 insertions(+)
diff --git a/spec/build/bsps/arm/stm32h7/optenuart4.yml
b/spec/build/bsps/arm/stm32h7/optenuart4.yml
index 8665f4c821..73c1ebef1c 100644
--- a/spec/build/bsps/arm/stm32h7/optenuart4.yml
+++ b/spec/build/bsps/arm/stm32h7/optenuart4.yml
@@ -7,6 +7,7 @@ default-by-variant:
- value: false
variants:
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenuart5.yml
b/spec/build/bsps/arm/stm32h7/optenuart5.yml
index f32f719f49..e445f2834f 100644
--- a/spec/build/bsps/arm/stm32h7/optenuart5.yml
+++ b/spec/build/bsps/arm/stm32h7/optenuart5.yml
@@ -8,6 +8,7 @@ default-by-variant:
variants:
- arm/stm32h7b3i-dk
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenuart7.yml
b/spec/build/bsps/arm/stm32h7/optenuart7.yml
index bd9ed8fe76..225c9efa22 100644
--- a/spec/build/bsps/arm/stm32h7/optenuart7.yml
+++ b/spec/build/bsps/arm/stm32h7/optenuart7.yml
@@ -8,6 +8,7 @@ default-by-variant:
variants:
- arm/stm32h7b3i-dk
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenuart8.yml
b/spec/build/bsps/arm/stm32h7/optenuart8.yml
index 74304e1256..96b869907d 100644
--- a/spec/build/bsps/arm/stm32h7/optenuart8.yml
+++ b/spec/build/bsps/arm/stm32h7/optenuart8.yml
@@ -8,6 +8,7 @@ default-by-variant:
variants:
- arm/stm32h7b3i-dk
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenuart9.yml
b/spec/build/bsps/arm/stm32h7/optenuart9.yml
index 76378c622d..864948fc91 100644
--- a/spec/build/bsps/arm/stm32h7/optenuart9.yml
+++ b/spec/build/bsps/arm/stm32h7/optenuart9.yml
@@ -8,6 +8,7 @@ default-by-variant:
variants:
- arm/stm32h7b3i-dk
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenusart10.yml
b/spec/build/bsps/arm/stm32h7/optenusart10.yml
index 1558bdb017..b60acf62a4 100644
--- a/spec/build/bsps/arm/stm32h7/optenusart10.yml
+++ b/spec/build/bsps/arm/stm32h7/optenusart10.yml
@@ -8,6 +8,7 @@ default-by-variant:
variants:
- arm/stm32h7b3i-dk
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenusart2.yml
b/spec/build/bsps/arm/stm32h7/optenusart2.yml
index 05f73df137..b49d3315e0 100644
--- a/spec/build/bsps/arm/stm32h7/optenusart2.yml
+++ b/spec/build/bsps/arm/stm32h7/optenusart2.yml
@@ -8,6 +8,7 @@ default-by-variant:
- value: false
variants:
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenusart3.yml
b/spec/build/bsps/arm/stm32h7/optenusart3.yml
index 1d676fdc3c..798aaed2a5 100644
--- a/spec/build/bsps/arm/stm32h7/optenusart3.yml
+++ b/spec/build/bsps/arm/stm32h7/optenusart3.yml
@@ -8,6 +8,7 @@ default-by-variant:
variants:
- arm/stm32h7b3i-dk
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenusart6.yml
b/spec/build/bsps/arm/stm32h7/optenusart6.yml
index 17761be7c3..a8ab30cba5 100644
--- a/spec/build/bsps/arm/stm32h7/optenusart6.yml
+++ b/spec/build/bsps/arm/stm32h7/optenusart6.yml
@@ -8,6 +8,7 @@ default-by-variant:
variants:
- arm/stm32h7b3i-dk
- arm/stm32h757i-eval
+ - arm/stm32h757i-eval-m4
enabled-by: true
format: '{}'
links: []
--
2.25.1
___
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http://lists.rtems.org/mailman/listinfo/devel
Apple M1 compilation issue.
Hello, RTEMS community is using MPC as a part of GNU C compiler. Recently we have been hit by an issue of compiling GNU C compiler toolchain on the Apple M1 hardware. The issue is easily fixable by the patch below, but RTEMS community refuses to include the fix without a clear sign that upstream project (you) were contacted and asked either for patch acceptance or fixing the issue. Could you be so kind and in next release use latest available autotools to generate configure script and associated files? This way, problematic config.sub file is generated with the proper support for Apple M1 hardware and everything should be working again. Thanks! Karel Gardas --- mpc/build-aux/config.sub.orig 2022-05-11 09:20:51.0 +0200 +++ mpc/build-aux/config.sub2022-05-11 09:23:47.0 +0200 @@ -916,6 +916,10 @@ cpu=sparc vendor=`echo "$basic_machine" | sed 's/-.*//'` ;; + arm64-*) + cpu=aarch64 + vendor=`echo "$basic_machine" | sed 's/-.*//'` + ;; *-*) # shellcheck disable=SC2162 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: Apple M1 compilation issue.
On 5/16/22 17:33, Andreas Enge wrote: Hello Karel, Am Mon, May 16, 2022 at 04:33:42PM +0200 schrieb Karel Gardas: Could you be so kind and in next release use latest available autotools to generate configure script and associated files? This way, problematic config.sub file is generated with the proper support for Apple M1 hardware and everything should be working again. actually this is already part of our release process. I just tried with the latest release of autoconf, 2.71, and got the following: --- mpc/build-aux/config.sub.orig 2022-05-11 09:20:51.0 +0200 +++ mpc/build-aux/config.sub2022-05-11 09:23:47.0 +0200 @@ -916,6 +916,10 @@ + arm64-*) + cpu=aarch64 + vendor=`echo "$basic_machine" | sed 's/-.*//'` + ;; timestamp='2021-08-14' arm64-*) cpu=aarch64 ;; So there is no vendor part. Would that be enough for your purposes? I think so, but I don't have hardware here to test anymore. Thanks! Karel PS: I wonder where this is downloaded from. The git repository of autoconf itself has an older version of that file from 2021-01-08. Ah, here: git clone https://git.savannah.gnu.org/git/config.git shows a config.sub from 2022-01-03, which has the same arm64 line. Indeed! ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: Apple M1 compilation issue.
On 5/16/22 16:45, Paul Zimmermann wrote: Dear Karel, yes, we'll take care of that in the next release of MPC. Thanks for assurance. That's perfectly fine for us since now we may apply patch locally and schedule its removal on another MPC release. Perfect! Karel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] ISL, MPC, MPFR: fix configuration issues on ARM64/Darwin host
On 5/13/22 15:57, Joel Sherrill wrote: We do not put patches in RTEMS repos. File an rtems ticket, attach them, and reference them from there. If they are needed upstream, please submit them to the appropriate projects. Joel, based on the discussion I've created https://devel.rtems.org/ticket/4657 -- hopefully this will be enough to accept interim solution and fix M1 compilation issues. I'll follow the possible replies, links on their archives and link them as go into the ticket for your reference. Thanks, Karel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] ISL, MPC, MPFR: fix configuration issues on ARM64/Darwin host
On Mon, May 16, 2022, 12:33 PM Karel Gardas wrote: > On 5/13/22 15:57, Joel Sherrill wrote: > > We do not put patches in RTEMS repos. File an rtems ticket, attach them, > > and reference them from there. > > > > If they are needed upstream, please submit them to the appropriate > projects. > > Joel, > > based on the discussion I've created https://devel.rtems.org/ticket/4657 > -- hopefully this will be enough to accept interim solution and fix M1 > compilation issues. > I'll follow the possible replies, links on their archives and link them > as go into the ticket for your reference. > Perfect! Just use the raw attachment url for them. --joel > > Thanks, > Karel > > ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
