[PATCH v1 4/5] cpukit/microblaze: Clarify interrupt frame usage
Avoid use of magic numbers in favor of named constants and add MSR to the interrupt frame so that thread dispatch can occur on exceptions as well. --- .../microblaze_fpga/start/_interrupt_handler.S | 4 +++- cpukit/score/cpu/microblaze/cpu_asm.S| 16 .../cpu/microblaze/include/rtems/score/cpuimpl.h | 3 ++- 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S index b817503922..c24807c3e0 100644 --- a/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S +++ b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S @@ -31,6 +31,8 @@ */ +#include + .text .globl _interrupt_handler# Interrupt Handler Label .align 2 @@ -41,7 +43,7 @@ nop #else /* __rtems__ */ /* Subtract stack frame */ - addik r1, r1, -52 + addik r1, r1, -(CPU_INTERRUPT_FRAME_SIZE) swi r5, r1, 8 diff --git a/cpukit/score/cpu/microblaze/cpu_asm.S b/cpukit/score/cpu/microblaze/cpu_asm.S index bf5080d2e1..62bb8075bd 100644 --- a/cpukit/score/cpu/microblaze/cpu_asm.S +++ b/cpukit/score/cpu/microblaze/cpu_asm.S @@ -56,6 +56,8 @@ _ISR_Handler: swi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12 swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15 swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18 + mfs r3, rmsr + swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_MSR /* Disable dispatching */ lwi r3, r0, _Per_CPU_Information + 16 @@ -79,7 +81,7 @@ _ISR_Handler: switch_to_interrupt_stack: add r4, r0, r1 lwi r1, r0, _Per_CPU_Information + 4 - addik r1, r1, -52 + addik r1, r1, -(CPU_INTERRUPT_FRAME_SIZE) swi r4, r1, 0 on_interrupt_stack: @@ -123,6 +125,8 @@ after_stack_switch: quick_exit: /* Simple return from nested interrupt */ /* Restore registers */ + lwi r3, r1, MICROBLAZE_INTERRUPT_FRAME_MSR + mts rmsr, r3 lwi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3 lwi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4 lwi r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5 @@ -138,14 +142,14 @@ quick_exit: lwi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18 /* Remove stack frame */ - addik r1, r1, 52 + addik r1, r1, CPU_INTERRUPT_FRAME_SIZE rtid r14, 0 nop thread_dispatch: /* Reserve stack */ - addik r1, r1, -52 + addik r1, r1, -(CPU_INTERRUPT_FRAME_SIZE) /* Save scratch registers */ swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3 swi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4 @@ -160,11 +164,15 @@ thread_dispatch: swi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14 swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15 swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18 + mfs r3, rmsr + swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_RMS bralid r15, _Thread_Dispatch nop /* Restore scratch registers */ + lwi r3, r1, MICROBLAZE_INTERRUPT_FRAME_RMS + mts rmsr, r3 lwi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3 lwi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4 lwi r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5 @@ -179,7 +187,7 @@ thread_dispatch: lwi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15 lwi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18 /* Free stack space */ - addik r1, r1, 52 + addik r1, r1, CPU_INTERRUPT_FRAME_SIZE bri quick_exit diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h index 3d0167dd40..0573759d52 100644 --- a/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h @@ -49,7 +49,7 @@ */ #define CPU_PER_CPU_CONTROL_SIZE 0 -#define CPU_INTERRUPT_FRAME_SIZE 52 +#define CPU_INTERRUPT_FRAME_SIZE 56 #define MICROBLAZE_INTERRUPT_FRAME_R3 0 #define MICROBLAZE_INTERRUPT_FRAME_R4 4 @@ -64,6 +64,7 @@ #define MICROBLAZE_INTERRUPT_FRAME_R14 40 #define MICROBLAZE_INTERRUPT_FRAME_R15 44 #define MICROBLAZE_INTERRUPT_FRAME_R18 48 +#define MICROBLAZE_INTERRUPT_FRAME_MSR 52 #ifndef ASM -- 2.30.2 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 2/5] cpukit/microblaze: Add debug vector and handler
This patch adds a vector for debug events along with a hook similar to the exception framework. The debug vector generates an exception frame for use by libdebugger. --- .../start/_debug_sw_break_handler.S | 106 ++ bsps/microblaze/shared/start/start.S | 7 +- cpukit/score/cpu/microblaze/cpu.c | 26 + .../cpu/microblaze/include/rtems/score/cpu.h | 9 ++ .../bsps/microblaze/microblaze_fpga/obj.yml | 1 + 5 files changed, 148 insertions(+), 1 deletion(-) create mode 100644 bsps/microblaze/microblaze_fpga/start/_debug_sw_break_handler.S diff --git a/bsps/microblaze/microblaze_fpga/start/_debug_sw_break_handler.S b/bsps/microblaze/microblaze_fpga/start/_debug_sw_break_handler.S new file mode 100644 index 00..ebf69f6d53 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/_debug_sw_break_handler.S @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze debug trap handler implementation + */ + +/* + * Copyright (C) 2022 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + + .text + .globl _debug_sw_break_handler# HW Exception Handler Label + .extern _CPU_Debug_handle + .align 2 + + _debug_sw_break_handler: + /* The stack used here does not matter since debug cannot recurse */ + + /* Subtract exception frame */ + addik r1, r1, -(CPU_EXCEPTION_FRAME_SIZE) + + /* Store program state */ + swi r2, r1, MICROBLAZE_EXCEPTION_FRAME_R2 + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_R3 + swi r4, r1, MICROBLAZE_EXCEPTION_FRAME_R4 + swi r5, r1, MICROBLAZE_EXCEPTION_FRAME_R5 + swi r6, r1, MICROBLAZE_EXCEPTION_FRAME_R6 + swi r7, r1, MICROBLAZE_EXCEPTION_FRAME_R7 + swi r8, r1, MICROBLAZE_EXCEPTION_FRAME_R8 + swi r9, r1, MICROBLAZE_EXCEPTION_FRAME_R9 + swi r10, r1, MICROBLAZE_EXCEPTION_FRAME_R10 + swi r11, r1, MICROBLAZE_EXCEPTION_FRAME_R11 + swi r12, r1, MICROBLAZE_EXCEPTION_FRAME_R12 + swi r13, r1, MICROBLAZE_EXCEPTION_FRAME_R13 + swi r14, r1, MICROBLAZE_EXCEPTION_FRAME_R14 + swi r15, r1, MICROBLAZE_EXCEPTION_FRAME_R15 + swi r16, r1, MICROBLAZE_EXCEPTION_FRAME_R16 + swi r17, r1, MICROBLAZE_EXCEPTION_FRAME_R17 + swi r18, r1, MICROBLAZE_EXCEPTION_FRAME_R18 + swi r19, r1, MICROBLAZE_EXCEPTION_FRAME_R19 + swi r20, r1, MICROBLAZE_EXCEPTION_FRAME_R20 + swi r21, r1, MICROBLAZE_EXCEPTION_FRAME_R21 + swi r22, r1, MICROBLAZE_EXCEPTION_FRAME_R22 + swi r23, r1, MICROBLAZE_EXCEPTION_FRAME_R23 + swi r24, r1, MICROBLAZE_EXCEPTION_FRAME_R24 + swi r25, r1, MICROBLAZE_EXCEPTION_FRAME_R25 + swi r26, r1, MICROBLAZE_EXCEPTION_FRAME_R26 + swi r27, r1, MICROBLAZE_EXCEPTION_FRAME_R27 + swi r28, r1, MICROBLAZE_EXCEPTION_FRAME_R28 + swi r29, r1, MICROBLAZE_EXCEPTION_FRAME_R29 + swi r30, r1, MICROBLAZE_EXCEPTION_FRAME_R30 + swi r31, r1, MICROBLAZE_EXCEPTION_FRAME_R31 + + /* Retrieve and store MSR */ + mfs r3, rmsr + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_MSR + + /* Retrieve and store EAR */ + mfs r3, rear + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_EAR + + /* Retrieve and store ESR */ + mfs r3, resr + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_ESR + + /* Retrieve and store BTR */ + mfs r3, rbtr + swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_BTR + + /* Calculate and store original stack pointer */ + addik r3, r1, CPU_EXCEPTION_FRAME_SIZE + swi r3, r1, MICROBLAZE_EXCE
[PATCH v1 5/5] cpukit/microblaze: Simplify dispatch assembly
The dispatch code was unnecessarily saving and restoring an extra interrupt frame. This avoids the extra frame and folds the dispatch call into a fallthrough to the interrupt frame restoration code. --- cpukit/score/cpu/microblaze/cpu_asm.S | 48 ++- 1 file changed, 2 insertions(+), 46 deletions(-) diff --git a/cpukit/score/cpu/microblaze/cpu_asm.S b/cpukit/score/cpu/microblaze/cpu_asm.S index 62bb8075bd..e7861b5f91 100644 --- a/cpukit/score/cpu/microblaze/cpu_asm.S +++ b/cpukit/score/cpu/microblaze/cpu_asm.S @@ -118,9 +118,9 @@ after_stack_switch: beqi r3, quick_exit /* Return to interrupted thread and make it do a dispatch */ - addik r14, r0, thread_dispatch - rtid r14, 0 + bralid r15, _Thread_Dispatch nop + /* Fall through to quick exit */ quick_exit: /* Simple return from nested interrupt */ @@ -147,50 +147,6 @@ quick_exit: rtid r14, 0 nop -thread_dispatch: - /* Reserve stack */ - addik r1, r1, -(CPU_INTERRUPT_FRAME_SIZE) - /* Save scratch registers */ - swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3 - swi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4 - swi r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5 - swi r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6 - swi r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7 - swi r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8 - swi r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9 - swi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10 - swi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11 - swi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12 - swi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14 - swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15 - swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18 - mfs r3, rmsr - swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_RMS - - bralid r15, _Thread_Dispatch - nop - - /* Restore scratch registers */ - lwi r3, r1, MICROBLAZE_INTERRUPT_FRAME_RMS - mts rmsr, r3 - lwi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3 - lwi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4 - lwi r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5 - lwi r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6 - lwi r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7 - lwi r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8 - lwi r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9 - lwi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10 - lwi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11 - lwi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12 - lwi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14 - lwi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15 - lwi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18 - /* Free stack space */ - addik r1, r1, CPU_INTERRUPT_FRAME_SIZE - - bri quick_exit - _CPU_Exception_dispatch_and_resume: /* Subtract 1 from ISR_NEST_LEVEL */ lwi r3, r0, _Per_CPU_Information + 8 -- 2.30.2 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 1/5] cpukit/microblaze: Add exception framework
This patch updates the CPU_Exception_frame to include all necessary registers, combines hardware snd software exception handlers into a shared vector, provides an architecture-specific hook for taking control of exception handling, and moves exception handling over to actually using the CPU_Exception_frame instead of a minimal interrupt stack frame. As the significant contents of _exception_handler.S have been entirely rewritten, the copyright information on this file has been updated to reflect that. --- .../start/_exception_handler.S| 129 -- .../start/_hw_exception_handler.S | 52 --- bsps/microblaze/shared/start/start.S | 7 +- cpukit/score/cpu/microblaze/cpu.c | 85 cpukit/score/cpu/microblaze/cpu_asm.S | 13 -- .../cpu/microblaze/include/rtems/score/cpu.h | 106 +- .../bsps/microblaze/microblaze_fpga/obj.yml | 1 - 7 files changed, 283 insertions(+), 110 deletions(-) delete mode 100644 bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S diff --git a/bsps/microblaze/microblaze_fpga/start/_exception_handler.S b/bsps/microblaze/microblaze_fpga/start/_exception_handler.S index 1d96b694a7..25caf63d9c 100644 --- a/bsps/microblaze/microblaze_fpga/start/_exception_handler.S +++ b/bsps/microblaze/microblaze_fpga/start/_exception_handler.S @@ -1,52 +1,103 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ +/* SPDX-License-Identifier: BSD-2-Clause */ -/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze exception handler implementation + */ - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are - met: +/* + * Copyright (C) 2022 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ - 1. Redistributions source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - 3. Neither the name of Xilinx nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS - IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*/ +#include .text .globl _exception_handler# Exception Handler Label .align 2 _exception_handler: -#ifndef __rtems__ - rtsdr17, 0 - nop -#else /* __rtems__ */ - /* Subtract stack frame */ - addik r1, r1, -52 + /* Subtract exception frame */ + addik r1, r1, -(CPU_EXCEPTION_FRAME_SIZE) + + /* Store program state */ +
[PATCH v1 3/5] cpukit/microblaze: Add exception extensions
Add the functions necessary to support RTEMS_EXCEPTION_EXTENSIONS and
mark this functionality as available on MicroBlaze.
---
cpukit/score/cpu/microblaze/cpu.c | 133 +
cpukit/score/cpu/microblaze/cpu_asm.S | 137 ++
.../cpu/microblaze/include/rtems/score/cpu.h | 38 +
spec/build/cpukit/optexceptionextensions.yml | 1 +
4 files changed, 309 insertions(+)
diff --git a/cpukit/score/cpu/microblaze/cpu.c
b/cpukit/score/cpu/microblaze/cpu.c
index c75aa0f147..009d93793f 100644
--- a/cpukit/score/cpu/microblaze/cpu.c
+++ b/cpukit/score/cpu/microblaze/cpu.c
@@ -43,6 +43,7 @@
#include
#include
#include
+#include
#include
#include
@@ -230,3 +231,135 @@ void _CPU_Debug_handle( CPU_Exception_frame *ef )
rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) ef );
}
+
+RTEMS_NO_RETURN void _CPU_Exception_resume( CPU_Exception_frame *frame )
+{
+ /* Break in progress */
+ if ( ( frame->msr & MICROBLAZE_MSR_BIP ) != 0 ) {
+_CPU_Exception_resume_from_break( frame );
+ }
+
+ /* Exception in progress */
+ if ( ( frame->msr & MICROBLAZE_MSR_EIP ) != 0 ) {
+_CPU_Exception_resume_from_exception( frame );
+ }
+
+ /* Execution should never reach this point */
+ rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) frame );
+}
+
+void _CPU_Exception_disable_thread_dispatch( void )
+{
+ Per_CPU_Control *cpu_self = _Per_CPU_Get();
+
+ /* Increment interrupt nest and thread dispatch disable level */
+ ++cpu_self->thread_dispatch_disable_level;
+ ++cpu_self->isr_nest_level;
+}
+
+/* -1 means not mappable/recoverable */
+int _CPU_Exception_frame_get_signal( CPU_Exception_frame *ef )
+{
+ uint32_t EC = ef->esr & MICROBLAZE_ESR_EC_MASK;
+
+ /* Break in progress */
+ if ( ( ef->msr & MICROBLAZE_MSR_BIP ) != 0 ) {
+return -1;
+ }
+
+ switch ( EC ) {
+ case 0x0: /* Stream */
+ case 0x7: /* Privileged or Stack Protection */
+ return -1;
+
+ case 0x5: /* Divide */
+ case 0x6: /* FPU */
+ return SIGFPE;
+
+ case 0x3: /* Instruction Abort */
+ case 0x4: /* Data Abort */
+ return SIGSEGV;
+
+ case 0x1: /* Unaligned access */
+ case 0x2: /* Illegal op-code */
+ default:
+ return SIGILL;
+ }
+}
+
+void _CPU_Exception_frame_set_resume( CPU_Exception_frame *ef, void *address )
+{
+ /* Break in progress */
+ if ( ( ef->msr & MICROBLAZE_MSR_BIP ) != 0 ) {
+ef->r16 = address;
+return;
+ }
+
+ /* Exception in progress */
+ if ( ( ef->msr & MICROBLAZE_MSR_EIP ) != 0 ) {
+ef->r17 = address;
+return;
+ }
+
+ Per_CPU_Control *cpu_self = _Per_CPU_Get();
+
+ /* Interrupt in progress must be determined by stack pointer location */
+ if (
+ef->r1 >= (uint32_t) cpu_self->interrupt_stack_low
+&& ef->r1 < (uint32_t) cpu_self->interrupt_stack_high
+ ) {
+ef->r14 = address;
+return;
+ }
+
+ /* Default to normal link register */
+ ef->r15 = address;
+}
+
+/*
+ * This returns the target return address, not necessarily the address of the
+ * instruction that caused exception. These are the same if it's a MMU
exception
+ * and the BTR overrides the return address if the exception occurred in a
delay
+ * slot. */
+uint32_t *_MicroBlaze_Get_return_address( CPU_Exception_frame *ef )
+{
+ /* Break in progress */
+ if ( ( ef->msr & MICROBLAZE_MSR_BIP ) != 0 ) {
+return ef->r16;
+ }
+
+ /* Exception in progress */
+ if ( ( ef->msr & MICROBLAZE_MSR_EIP ) != 0 ) {
+if ( ( ef->esr & MICROBLAZE_ESR_DS ) != 0 ) {
+ return ef->btr;
+}
+
+return ef->r17;
+ }
+
+ Per_CPU_Control *cpu_self = _Per_CPU_Get();
+
+ /* Interrupt in progress must be determined by stack pointer location */
+ if (
+ef->r1 >= (uint32_t) cpu_self->interrupt_stack_low
+&& ef->r1 < (uint32_t) cpu_self->interrupt_stack_high
+ ) {
+return ef->r14;
+ }
+
+ /* Default to normal link register */
+ return ef->r15;
+}
+
+/*
+ * This can only change the resume address in the case of an exception in a
+ * branch delay slot instruction.
+ */
+void _CPU_Exception_frame_make_resume_next_instruction(
+ CPU_Exception_frame *ef
+)
+{
+ uintptr_t ret_addr = (uintptr_t) _MicroBlaze_Get_return_address( ef );
+
+ _CPU_Exception_frame_set_resume( ef, (uint32_t *) ret_addr );
+}
diff --git a/cpukit/score/cpu/microblaze/cpu_asm.S
b/cpukit/score/cpu/microblaze/cpu_asm.S
index 92cf15e901..bf5080d2e1 100644
--- a/cpukit/score/cpu/microblaze/cpu_asm.S
+++ b/cpukit/score/cpu/microblaze/cpu_asm.S
@@ -38,6 +38,9 @@
.text
.globl _ISR_Handler
+.globl _CPU_Exception_dispatch_and_resume
+.globl _CPU_Exception_resume_from_exception
+.globl _CPU_Exception_resume_from_break
.align 2
_ISR_Handler:
@@ -179,3 +182,137 @@ thread_dispatch:
addik r1, r1, 52
bri quick_exit
+
+_CPU_Exception_dispatch_and_resume:
+ /* Subtract 1 from ISR_NEST_LEVEL */
+ lwi r3, r0, _Per_CPU_Information + 8
+ addik r3, r3, -
Re: [PATCH v1 1/5] cpukit/microblaze: Add exception framework
Hello Kinsey, could you please use the _CPU_* and CPU_* prefixes only for items which are defined by the CPU port interface: cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h Architecture-specific interfaces should have an architecture-specific prefix, for example _Microblaze_* and MICROBLAZE_*. The code for the optional exception resume should be in a separate file and not in cpu.c. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
