[PATCH] score: Add _IO_Relax()
This function may be used to burn a couple of processor cycles with
minimum impact on the system bus. It may be used in busy wait loops.
Since it is a global function, it is possible to wrap it in device
driver test code.
---
cpukit/include/rtems/score/io.h | 8 +
cpukit/score/src/iorelax.c| 53 +++
spec/build/cpukit/librtemscpu.yml | 1 +
3 files changed, 62 insertions(+)
create mode 100644 cpukit/score/src/iorelax.c
diff --git a/cpukit/include/rtems/score/io.h b/cpukit/include/rtems/score/io.h
index f7b576fddd..5cc946bba8 100644
--- a/cpukit/include/rtems/score/io.h
+++ b/cpukit/include/rtems/score/io.h
@@ -120,6 +120,14 @@ int _IO_Base64url(
int wordlen
);
+/**
+ * @brief Issues a couple of no-operation instructions.
+ *
+ * This function may be used to burn a couple of processor cycles with minimum
+ * impact on the system bus. It may be used in busy wait loops.
+ */
+void _IO_Relax( void );
+
/** @} */
#ifdef __cplusplus
diff --git a/cpukit/score/src/iorelax.c b/cpukit/score/src/iorelax.c
new file mode 100644
index 00..f37d848605
--- /dev/null
+++ b/cpukit/score/src/iorelax.c
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreIO
+ *
+ * @brief This source file contains the implementation of _IO_Relax().
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include
+#include
+
+void _IO_Relax( void )
+{
+ _CPU_Instruction_no_operation();
+ _CPU_Instruction_no_operation();
+ _CPU_Instruction_no_operation();
+ _CPU_Instruction_no_operation();
+ _CPU_Instruction_no_operation();
+ _CPU_Instruction_no_operation();
+ _CPU_Instruction_no_operation();
+ _CPU_Instruction_no_operation();
+}
diff --git a/spec/build/cpukit/librtemscpu.yml
b/spec/build/cpukit/librtemscpu.yml
index 423974502c..f8594a7784 100644
--- a/spec/build/cpukit/librtemscpu.yml
+++ b/spec/build/cpukit/librtemscpu.yml
@@ -1421,6 +1421,7 @@ source:
- cpukit/score/src/interr.c
- cpukit/score/src/iobase64.c
- cpukit/score/src/ioprintf.c
+- cpukit/score/src/iorelax.c
- cpukit/score/src/iovprintf.c
- cpukit/score/src/isr.c
- cpukit/score/src/isrisinprogress.c
--
2.31.1
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[PATCH 2/4] bsp/leon3: Use interrupt entry for the SMP support
Using rtems_interrupt_entry_install() instead of
rtems_interrupt_handler_install() avoids a dependency on the dynamic memory
allocation.
---
bsps/sparc/leon3/start/bspsmp.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/bsps/sparc/leon3/start/bspsmp.c b/bsps/sparc/leon3/start/bspsmp.c
index a556da1e09..74f9df5404 100644
--- a/bsps/sparc/leon3/start/bspsmp.c
+++ b/bsps/sparc/leon3/start/bspsmp.c
@@ -51,6 +51,13 @@ void bsp_start_on_secondary_processor(Per_CPU_Control
*cpu_self)
_SMP_Start_multitasking_on_secondary_processor(cpu_self);
}
+static rtems_interrupt_entry leon3_inter_processor_interrupt_entry =
+ RTEMS_INTERRUPT_ENTRY_INITIALIZER(
+bsp_inter_processor_interrupt,
+NULL,
+"IPI"
+ );
+
static void leon3_install_inter_processor_interrupt( void )
{
rtems_status_code sc;
@@ -60,12 +67,10 @@ static void leon3_install_inter_processor_interrupt( void )
bsp_interrupt_set_affinity( irq, _SMP_Get_online_processors() );
- sc = rtems_interrupt_handler_install(
+ sc = rtems_interrupt_entry_install(
irq,
-"IPI",
RTEMS_INTERRUPT_SHARED,
-bsp_inter_processor_interrupt,
-NULL
+&leon3_inter_processor_interrupt_entry
);
_Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL );
}
--
2.26.2
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[PATCH 1/4] bsp/leon3: Use interrupt entry for Clock Driver
Using rtems_interrupt_entry_install() instead of
rtems_interrupt_handler_install() avoids a dependency on the dynamic memory
allocation.
---
bsps/sparc/leon3/clock/ckinit.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/bsps/sparc/leon3/clock/ckinit.c b/bsps/sparc/leon3/clock/ckinit.c
index 4d30e0fd64..69afb25f3c 100644
--- a/bsps/sparc/leon3/clock/ckinit.c
+++ b/bsps/sparc/leon3/clock/ckinit.c
@@ -133,16 +133,22 @@ static void leon3_tc_do_tick(void)
#define Clock_driver_support_install_isr(isr) \
bsp_clock_handler_install(isr)
+static rtems_interrupt_entry leon3_clock_interrupt_entry;
+
static void bsp_clock_handler_install(rtems_interrupt_handler isr)
{
rtems_status_code sc;
- sc = rtems_interrupt_handler_install(
+ rtems_interrupt_entry_initialize(
+&leon3_clock_interrupt_entry,
+isr,
+NULL,
+"Clock"
+ );
+ sc = rtems_interrupt_entry_install(
clkirq,
-"Clock",
RTEMS_INTERRUPT_UNIQUE,
-isr,
-NULL
+&leon3_clock_interrupt_entry
);
if (sc != RTEMS_SUCCESSFUL) {
rtems_fatal(RTEMS_FATAL_SOURCE_BSP, LEON3_FATAL_CLOCK_INITIALIZATION);
--
2.26.2
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[PATCH 3/4] bsp/leon3: Use interrupt entry for tm27 support
Using rtems_interrupt_entry_install() instead of
rtems_interrupt_handler_install() avoids a dependency on the dynamic memory
allocation.
Use Interrupt Manager directives instead of a BSP-specific API. Use inline
functions. In SMP configurations, set an affinity to all online processors and
raise the interrupt on the current processor.
---
bsps/sparc/leon3/include/tm27.h | 75 -
1 file changed, 55 insertions(+), 20 deletions(-)
diff --git a/bsps/sparc/leon3/include/tm27.h b/bsps/sparc/leon3/include/tm27.h
index dda21f558f..7635d9b070 100644
--- a/bsps/sparc/leon3/include/tm27.h
+++ b/bsps/sparc/leon3/include/tm27.h
@@ -21,7 +21,11 @@
#define __tm27_h
#include
-#include
+#include
+
+#if defined(RTEMS_SMP)
+#include
+#endif
/*
* Define the interrupt mechanism for Time Test 27
@@ -59,40 +63,71 @@
#else /* use a regular asynchronous trap */
-#define TEST_INTERRUPT_SOURCE LEON_INTERRUPT_EXTERNAL_1
-#define TEST_INTERRUPT_SOURCE2 LEON_INTERRUPT_EXTERNAL_1+1
+#define TEST_INTERRUPT_SOURCE 5
+#define TEST_INTERRUPT_SOURCE2 6
#define MUST_WAIT_FOR_INTERRUPT 1
static inline void Install_tm27_vector(
void ( *handler )( rtems_vector_number )
)
{
- (void) rtems_interrupt_handler_install(
+ static rtems_interrupt_entry entry_low;
+ static rtems_interrupt_entry entry_high;
+
+#if defined(RTEMS_SMP)
+ bsp_interrupt_set_affinity(
+TEST_INTERRUPT_SOURCE,
+_SMP_Get_online_processors()
+ );
+ bsp_interrupt_set_affinity(
+TEST_INTERRUPT_SOURCE2,
+_SMP_Get_online_processors()
+ );
+#endif
+
+ rtems_interrupt_entry_initialize(
+&entry_low,
+(rtems_interrupt_handler) handler,
+NULL,
+"tm27 low"
+ );
+ (void) rtems_interrupt_entry_install(
TEST_INTERRUPT_SOURCE,
-"tm27 low",
RTEMS_INTERRUPT_SHARED,
+&entry_low
+ );
+ rtems_interrupt_entry_initialize(
+&entry_high,
(rtems_interrupt_handler) handler,
-NULL
+NULL,
+"tm27 high"
);
- (void) rtems_interrupt_handler_install(
+ (void) rtems_interrupt_entry_install(
TEST_INTERRUPT_SOURCE2,
-"tm27 high",
RTEMS_INTERRUPT_SHARED,
-(rtems_interrupt_handler) handler,
-NULL
+&entry_high
);
}
-#define Cause_tm27_intr() \
- do { \
-LEON_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1)); \
-nop(); \
-nop(); \
-nop(); \
- } while (0)
-
-#define Clear_tm27_intr() \
- LEON_Clear_interrupt( TEST_INTERRUPT_SOURCE )
+static inline void Cause_tm27_intr( void )
+{
+ rtems_vector_number vector;
+
+ vector = TEST_INTERRUPT_SOURCE + ( Interrupt_nest >> 1 );
+#if defined(RTEMS_SMP)
+ (void) rtems_interrupt_raise_on( vector, rtems_scheduler_get_processor() );
+#else
+ (void) rtems_interrupt_raise( vector );
+#endif
+ nop();
+ nop();
+ nop();
+}
+
+static inline void Clear_tm27_intr( void )
+{
+ (void) rtems_interrupt_clear( TEST_INTERRUPT_SOURCE );
+}
#define Lower_tm27_intr() /* empty */
--
2.26.2
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[PATCH 4/4] bsp/leon3: Do not invalidate cache in SMP start
Since the trap table is now statically initialized, there is no need to
invalidate the instruction cache.
---
bsps/sparc/leon3/start/bspsmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/bsps/sparc/leon3/start/bspsmp.c b/bsps/sparc/leon3/start/bspsmp.c
index 74f9df5404..acd932843a 100644
--- a/bsps/sparc/leon3/start/bspsmp.c
+++ b/bsps/sparc/leon3/start/bspsmp.c
@@ -105,7 +105,7 @@ void _CPU_SMP_Finalize_initialization( uint32_t cpu_count )
void _CPU_SMP_Prepare_start_multitasking( void )
{
- rtems_cache_invalidate_entire_instruction();
+ /* Do nothing */
}
void _CPU_SMP_Send_interrupt(uint32_t target_processor_index)
--
2.26.2
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[PATCH] bsps/aarch64: Remove erroneous cache feature
The AArch64 cache implementation does not define rtems_cache_disable_data(), but declares that it does via CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA. The existing implementation of _CPU_cache_disable_data() is sufficient to enable this functionality without the erroneous cache feature flag. Closes #4569 --- bsps/aarch64/shared/cache/cache.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/bsps/aarch64/shared/cache/cache.c b/bsps/aarch64/shared/cache/cache.c index 9e7446a077..fc1766c2b9 100644 --- a/bsps/aarch64/shared/cache/cache.c +++ b/bsps/aarch64/shared/cache/cache.c @@ -47,8 +47,6 @@ #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS -#define CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA - #define AARCH64_CACHE_L1_CPU_DATA_ALIGNMENT ( (size_t) 64 ) #define AARCH64_CACHE_PREPARE_MVA(mva) (const void *) \ RTEMS_ALIGN_DOWN ( (size_t) mva, AARCH64_CACHE_L1_CPU_DATA_ALIGNMENT ) -- 2.30.2 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] bsps/aarch64: Remove erroneous cache feature
On 10/12/2021 16:49, Kinsey Moore wrote: The AArch64 cache implementation does not define rtems_cache_disable_data(), but declares that it does via CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA. The existing implementation of _CPU_cache_disable_data() is sufficient to enable this functionality without the erroneous cache feature flag. Closes #4569 Thanks, please check it in. At least for ARMv7 we have an assembler implementation for this function: bsps/arm/shared/cache/cache-v7ar-disable-data.S -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [rtems commit] untar: Make behavior similar to GNU or BSD tar
On 10/12/21 6:20 pm, Christian MAUDERER wrote: > Am 09.12.21 um 22:09 schrieb Chris Johns: >> On 9/12/21 6:47 pm, Christian MAUDERER wrote: >> >> Given it is in maybe we let it sit and it there is feedback we come back and >> take another look? > > No problem with that. I will try to be extra sensitive for problems with Untar > that appear on the list in the next months. > Thanks. There is no easy or clear guideline with this as a number of factors effect this. Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
