[PATCH] GcovData.cc: Remove ampersands where not needed
Removed some ampersands that were left in on accident.
---
tester/covoar/GcovData.cc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tester/covoar/GcovData.cc b/tester/covoar/GcovData.cc
index 44928a9..59412a6 100644
--- a/tester/covoar/GcovData.cc
+++ b/tester/covoar/GcovData.cc
@@ -404,7 +404,7 @@ namespace Gcov {
// Read the gcov preamble and make sure it is the right length and has the
// magic number
-gcovFile.read( (char *) &preamble, sizeof( gcov_preamble ) );
+gcovFile.read( (char *) preamble, sizeof( gcov_preamble ) );
if ( gcovFile.gcount() != sizeof( gcov_preamble ) ) {
std::cerr << "Error while reading file preamble" << std::endl;
return -1;
@@ -429,7 +429,7 @@ namespace Gcov {
char buffer[512];
char intBuffer[16384];
-gcovFile.read( (char *) &intBuffer, 8 );
+gcovFile.read( (char *) intBuffer, 8 );
if ( gcovFile.gcount() != 8 ) {
std::cerr << "ERROR: Unable to read Function ID & checksum" << std::endl;
return false;
@@ -443,7 +443,7 @@ namespace Gcov {
function->setFunctionName( buffer, symbolsToAnalyze_m );
header.length -= readString( buffer, gcovFile );
function->setFileName( buffer );
-gcovFile.read( (char*) &intBuffer, 4 * header.length );
+gcovFile.read( (char*) intBuffer, 4 * header.length );
if (gcovFile.gcount() != 4 * header.length ) {
std::cerr << "ERROR: Unable to read Function starting line number"
<< std::endl;
--
1.8.3.1
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] GcovData.cc: Remove ampersands where not needed
ok
On Mon, Aug 23, 2021 at 9:49 AM Ryan Long wrote:
>
> Removed some ampersands that were left in on accident.
> ---
> tester/covoar/GcovData.cc | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/tester/covoar/GcovData.cc b/tester/covoar/GcovData.cc
> index 44928a9..59412a6 100644
> --- a/tester/covoar/GcovData.cc
> +++ b/tester/covoar/GcovData.cc
> @@ -404,7 +404,7 @@ namespace Gcov {
>
> // Read the gcov preamble and make sure it is the right length and has
> the
> // magic number
> -gcovFile.read( (char *) &preamble, sizeof( gcov_preamble ) );
> +gcovFile.read( (char *) preamble, sizeof( gcov_preamble ) );
> if ( gcovFile.gcount() != sizeof( gcov_preamble ) ) {
>std::cerr << "Error while reading file preamble" << std::endl;
>return -1;
> @@ -429,7 +429,7 @@ namespace Gcov {
> char buffer[512];
> char intBuffer[16384];
>
> -gcovFile.read( (char *) &intBuffer, 8 );
> +gcovFile.read( (char *) intBuffer, 8 );
> if ( gcovFile.gcount() != 8 ) {
>std::cerr << "ERROR: Unable to read Function ID & checksum" <<
> std::endl;
>return false;
> @@ -443,7 +443,7 @@ namespace Gcov {
> function->setFunctionName( buffer, symbolsToAnalyze_m );
> header.length -= readString( buffer, gcovFile );
> function->setFileName( buffer );
> -gcovFile.read( (char*) &intBuffer, 4 * header.length );
> +gcovFile.read( (char*) intBuffer, 4 * header.length );
> if (gcovFile.gcount() != 4 * header.length ) {
>std::cerr << "ERROR: Unable to read Function starting line number"
> << std::endl;
> --
> 1.8.3.1
>
> ___
> devel mailing list
> devel@rtems.org
> http://lists.rtems.org/mailman/listinfo/devel
___
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devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH] tester: Add MicroBlaze KCU105 QEMU BSP
---
tester/rtems/testing/bsps/kcu105.dtb | Bin 0 -> 15256 bytes
tester/rtems/testing/bsps/kcu105_qemu.ini | 38 ++
2 files changed, 38 insertions(+)
create mode 100644 tester/rtems/testing/bsps/kcu105.dtb
create mode 100644 tester/rtems/testing/bsps/kcu105_qemu.ini
diff --git a/tester/rtems/testing/bsps/kcu105.dtb
b/tester/rtems/testing/bsps/kcu105.dtb
new file mode 100644
index
..998e8c03b74d8d9ddc82b5f6fa53242415abbd84
GIT binary patch
literal 15256
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zbe}YXXVEv9whpc*+4|u$4$FLy1g8X5DEl%zSKS#Wakk#Sjoh0J7y4l_sVInM?6Pm{
za@@lX=D2LsU7AyUqq{&l9)pkXe)iXtF!(m~cW8VW{<}W=^Ycfv$wue)(-1^6HpD;B
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z;ODyW=uLswZ~48;(YNN(b7J2+0e;VtzXN?XZNGOn`ZoUqnrHZ*pfDQoUWk54BK60}
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zSWWcRs$5TkOw9R30;QCpm-ABO`ORd!f*6S`9>8SdI8sjEpXzn^;ZKSJiKc{
zZ#}Le+v6U>?=t4yg=dM*80jU0pvv7L`CEiaSJiD^j@8%!&eS+V0_*i|v9F6BDJsV;
z5lt{M5im{-d8<)&ZHkeS4p?QFc)_mAR=TqanV{objwYtI*Ja!t$s%ANhTUg?@uP6$
z4dY?14pSyhXrFNEUc|?q`2;cN;UmMGr$1$IIm}No@_m2%&vpd1Bd{HT
i?Fei~U^@ca5!jBvb_BK~upNQz2y91SI|Bcw5%?!f%5Pf$
literal 0
HcmV?d1
diff --git a/tester/rtems/testing/bsps/kcu105_qemu.ini
b/tester/rtems/testing/bsps/kcu105_qemu.ini
new file mode 100644
index 000..42d90ab
--- /dev/null
+++ b/tester/rtems/testing/bsps/kcu105_qemu.ini
@@ -0,0 +1,38 @@
+#
+# RTEMS Tools Project (http://www.rtems.org/)
+# Copyright 2021 On-Line Applications Research Corporation (OAR).
+# All rights reserved.
+#
+# This file is part of the RTEMS Tools package in 'rtems-tools'.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT,
[PATCH rtems v1 2/2] bsps/zynqmp: Added I2C support for ZynqMP
Added I2C drivers for ZynqMP and updated build system accordingly.
---
bsps/aarch64/xilinx-zynqmp/include/bsp.h | 4 ++
bsps/aarch64/xilinx-zynqmp/include/bsp/i2c.h | 63 +++
bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h | 2 +
bsps/aarch64/xilinx-zynqmp/start/bspstart.c | 10 +++
spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml | 4 ++
.../bsps/aarch64/xilinx-zynqmp/grp_zu3eg.yml | 2 +
.../aarch64/xilinx-zynqmp/objcadencei2c.yml | 19 ++
.../bsps/aarch64/xilinx-zynqmp/optclki2c0.yml | 19 ++
.../bsps/aarch64/xilinx-zynqmp/optclki2c1.yml | 19 ++
9 files changed, 142 insertions(+)
create mode 100644 bsps/aarch64/xilinx-zynqmp/include/bsp/i2c.h
create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/objcadencei2c.yml
create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/optclki2c0.yml
create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/optclki2c1.yml
diff --git a/bsps/aarch64/xilinx-zynqmp/include/bsp.h
b/bsps/aarch64/xilinx-zynqmp/include/bsp.h
index 83f2e2f4e4..6d49b9ad2a 100644
--- a/bsps/aarch64/xilinx-zynqmp/include/bsp.h
+++ b/bsps/aarch64/xilinx-zynqmp/include/bsp.h
@@ -70,6 +70,10 @@ BSP_START_TEXT_SECTION void zynqmp_setup_mmu_and_cache(void);
void zynqmp_debug_console_flush(void);
+uint32_t zynqmp_clock_i2c0(void);
+
+uint32_t zynqmp_clock_i2c1(void);
+
#ifdef __cplusplus
}
#endif /* __cplusplus */
diff --git a/bsps/aarch64/xilinx-zynqmp/include/bsp/i2c.h
b/bsps/aarch64/xilinx-zynqmp/include/bsp/i2c.h
new file mode 100644
index 00..e09747d414
--- /dev/null
+++ b/bsps/aarch64/xilinx-zynqmp/include/bsp/i2c.h
@@ -0,0 +1,63 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2021 On-Line Applications Research (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_ZYNQ_I2C_H
+#define LIBBSP_ARM_XILINX_ZYNQ_I2C_H
+
+#include
+#include
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+static inline int zynqmp_register_i2c_0(void)
+{
+ return i2c_bus_register_cadence(
+"/dev/i2c-0",
+0x00FF02,
+zynqmp_clock_i2c0(),
+ZYNQMP_IRQ_I2C_0
+ );
+}
+
+static inline int zynqmp_register_i2c_1(void)
+{
+ return i2c_bus_register_cadence(
+"/dev/i2c-1",
+0x00FF03,
+zynqmp_clock_i2c1(),
+ZYNQMP_IRQ_I2C_1
+ );
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_XILINX_ZYNQ_I2C_H */
diff --git a/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h
b/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h
index b67d7d0f8e..9af41643bd 100644
--- a/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h
+++ b/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h
@@ -53,6 +53,8 @@ extern "C" {
/* Interrupts vectors */
#define BSP_TIMER_VIRT_PPI 27
#define BSP_TIMER_PHYS_NS_PPI 30
+#define ZYNQMP_IRQ_I2C_0 49
+#define ZYNQMP_IRQ_I2C_1 50
#define ZYNQMP_IRQ_UART_0 54
#define ZYNQMP_IRQ_UART_1 53
#define ZYNQMP_IRQ_ETHERNET_0 89
diff --git a/bsps/aarch64/xilinx-zynqmp/start/bspstart.c
b/bsps/aarch64/xilinx-zynqmp/start/bspstart.c
index 36194a337d..d75e5a1620 100644
--- a/bsps/aarch64/xilinx-zynqmp/start/bspstart.c
+++ b/bsps/aarch64/xilinx-zynqmp/start/bspstart.c
@@ -39,6 +39,16 @@
#include
#include
+__attribute__ ((weak)) uint32_t zynqmp_clock_i2c0(void)
+{
+ return ZYNQMP_CLOCK_I2C0;
+}
+
+__attribute__ ((weak)) uint32_t zynqmp_clock_i2c1(void)
+{
+ return ZYNQMP_CLOCK_I2C1;
+}
+
void bsp_start( void )
{
bsp_interrupt_initialize();
diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
b/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
index 03ccdbbc8b..1a356903cd 100644
--- a/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
+++ b/spec/build/bsps/aarch64/xilinx-zynqmp/grp.
[PATCH rtems v1 1/2] bsps/zynq: Moved general i2c files to shared directories
Certain files related to the Zynq BSP's I2C driver are useable by the ZynqMP
BSP as well.
Moved these files to shared directory in anticipation of I2C support for ZynqMP.
---
.../include/bsp => include/dev/i2c}/cadence-i2c-regs.h | 0
.../include/bsp => include/dev/i2c}/cadence-i2c.h | 0
bsps/{arm/xilinx-zynq => shared/dev}/i2c/cadence-i2c.c | 4 ++--
spec/build/bsps/arm/xilinx-zynq/obj.yml | 6 +++---
4 files changed, 5 insertions(+), 5 deletions(-)
rename bsps/{arm/xilinx-zynq/include/bsp =>
include/dev/i2c}/cadence-i2c-regs.h (100%)
rename bsps/{arm/xilinx-zynq/include/bsp => include/dev/i2c}/cadence-i2c.h
(100%)
rename bsps/{arm/xilinx-zynq => shared/dev}/i2c/cadence-i2c.c (99%)
diff --git a/bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h
b/bsps/include/dev/i2c/cadence-i2c-regs.h
similarity index 100%
rename from bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h
rename to bsps/include/dev/i2c/cadence-i2c-regs.h
diff --git a/bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h
b/bsps/include/dev/i2c/cadence-i2c.h
similarity index 100%
rename from bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h
rename to bsps/include/dev/i2c/cadence-i2c.h
diff --git a/bsps/arm/xilinx-zynq/i2c/cadence-i2c.c
b/bsps/shared/dev/i2c/cadence-i2c.c
similarity index 99%
rename from bsps/arm/xilinx-zynq/i2c/cadence-i2c.c
rename to bsps/shared/dev/i2c/cadence-i2c.c
index 07379992ce..91774fb926 100644
--- a/bsps/arm/xilinx-zynq/i2c/cadence-i2c.c
+++ b/bsps/shared/dev/i2c/cadence-i2c.c
@@ -25,8 +25,8 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include
-#include
+#include
+#include
#include
#include
diff --git a/spec/build/bsps/arm/xilinx-zynq/obj.yml
b/spec/build/bsps/arm/xilinx-zynq/obj.yml
index e81decaa3d..8a11a45dd3 100644
--- a/spec/build/bsps/arm/xilinx-zynq/obj.yml
+++ b/spec/build/bsps/arm/xilinx-zynq/obj.yml
@@ -14,8 +14,8 @@ install:
- bsps/arm/xilinx-zynq/include/tm27.h
- destination: ${BSP_INCLUDEDIR}/bsp
source:
- - bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h
- - bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h
+ - bsps/include/dev/i2c/cadence-i2c-regs.h
+ - bsps/include/dev/i2c/cadence-i2c.h
- bsps/arm/xilinx-zynq/include/bsp/i2c.h
- bsps/arm/xilinx-zynq/include/bsp/irq.h
links: []
@@ -28,7 +28,7 @@ source:
- bsps/arm/xilinx-zynq/console/console-config.c
- bsps/arm/xilinx-zynq/console/console-init.c
- bsps/arm/xilinx-zynq/console/debug-console.c
-- bsps/arm/xilinx-zynq/i2c/cadence-i2c.c
+- bsps/shared/dev/i2c/cadence-i2c.c
- bsps/arm/xilinx-zynq/start/bspreset.c
- bsps/arm/xilinx-zynq/start/bspstart.c
- bsps/arm/xilinx-zynq/start/bspstarthooks.c
--
2.27.0
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH 0/5] Preliminary Exception Manager Work
This patch set contains the result of the Exception Manager work I proposed a while back to manage handling of machine exceptions along with a general feature for mapping exceptions to POSIX signals without delving into the CPU Port-specific details. This is a pretty basic initial implementation, but it can easily be expanded with mutators for the CPU_Exception_frame for additional capabilities. Also included is a test that demonstrates usage of the Exception Manager and exception to signal mapping functionality. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 1/5] cpukit/aarch64: Use correct interrupt level types
All other architectures use uint32_t for interrupt levels and there is
no reason not to do so on AArch64.
---
cpukit/score/cpu/aarch64/cpu.c | 4 ++--
cpukit/score/cpu/aarch64/include/rtems/score/cpu.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/cpukit/score/cpu/aarch64/cpu.c b/cpukit/score/cpu/aarch64/cpu.c
index d09403a349..b36f55ae17 100644
--- a/cpukit/score/cpu/aarch64/cpu.c
+++ b/cpukit/score/cpu/aarch64/cpu.c
@@ -146,7 +146,7 @@ void _CPU_Context_Initialize(
}
}
-void _CPU_ISR_Set_level( uint64_t level )
+void _CPU_ISR_Set_level( uint32_t level )
{
/* Set the mask bit if interrupts are disabled */
level = level ? AARCH64_PSTATE_I : 0;
@@ -156,7 +156,7 @@ void _CPU_ISR_Set_level( uint64_t level )
);
}
-uint64_t _CPU_ISR_Get_level( void )
+uint32_t _CPU_ISR_Get_level( void )
{
uint64_t level;
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
index dacc18638e..5db1eb395e 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
@@ -204,9 +204,9 @@ static inline void
_AARCH64_Instruction_synchronization_barrier( void )
__asm__ volatile ( "isb" : : : "memory" );
}
-void _CPU_ISR_Set_level( uint64_t level );
+void _CPU_ISR_Set_level( uint32_t level );
-uint64_t _CPU_ISR_Get_level( void );
+uint32_t _CPU_ISR_Get_level( void );
#if defined(AARCH64_DISABLE_INLINE_ISR_DISABLE_ENABLE)
uint64_t AArch64_interrupt_disable( void );
--
2.20.1
___
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http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 2/5] cpukit: Add Exception Manager
This adds the framework necessary to allow more generic handling of
machine exceptions. This initial patch offers the ability to get the
class of exception from the CPU_Exception_frame provided. Future
extensions of the Exception Manager could include the ability to get
the address of the exception if applicable or to resume execution at
the next instruction or an arbitrary location.
---
cpukit/include/rtems/exception.h | 159 ++
cpukit/include/rtems/score/userext.h | 18 +++
cpukit/include/rtems/score/userextimpl.h | 41 ++
cpukit/score/src/userextiterate.c | 18 ++-
spec/build/cpukit/cpuopts.yml | 2 +
spec/build/cpukit/librtemscpu.yml | 1 +
spec/build/cpukit/optexceptionmanager.yml | 17 +++
7 files changed, 255 insertions(+), 1 deletion(-)
create mode 100644 cpukit/include/rtems/exception.h
create mode 100644 spec/build/cpukit/optexceptionmanager.yml
diff --git a/cpukit/include/rtems/exception.h b/cpukit/include/rtems/exception.h
new file mode 100644
index 00..dea1712409
--- /dev/null
+++ b/cpukit/include/rtems/exception.h
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @brief This header file defines the Exception Manager API.
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated. If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual. The manual is provided as a part of
+ * a release. For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+/* Generated from spec:/rtems/fatal/if/header */
+
+#ifndef _RTEMS_EXCEPTION_H
+#define _RTEMS_EXCEPTION_H
+
+#include
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Generated from spec:/rtems/fatal/if/group */
+
+/**
+ * @defgroup RTEMSAPIClassicException Exception Manager
+ *
+ * @ingroup RTEMSAPIClassic
+ *
+ * @brief The Exception Manager processes all machine exceptions and passes
+ * any unhandled exceptions to the Fatal Error Manager.
+ */
+
+/**
+ * @ingroup RTEMSAPIClassicException
+ *
+ * @brief Invokes the fatal error handler.
+ *
+ * @param exception_frame is the CPU_Exception_frame describing the exception.
+ *
+ * @return Returns whether the exception was handled with finality.
+ *
+ * This directive processes non-irq exceptions.
+ *
+ * @par Constraints
+ * @parblock
+ * The following constraints apply to this directive:
+ *
+ * * The directive must only be called from the CPU exception context.
+ *
+ * * The directive invokes the Exception Manager extensions in extension
+ * forward order.
+ *
+ * * The directive invokes the Fatal Error Manager if no exception handlers
+ *
+ * * The directive must only be called with interrupts disabled.
+ * handle the exception.
+ * @endparblock
+ */
+static inline bool rtems_exception_manage(
+ rtems_exception_frame *exception_frame
+)
+{
+ return _User_extensions_Exception( exception_frame );
+}
+
+/**
+ * The following lists the generic exception classes supported by the
Exception
+ * Management API.
+ */
+typedef enum {
+ EXCEPTION_UNKNOWN,
+ EXCEPTION_FPU,
+ EXCEPTION_TAGGED_OVERFLOW,
+ EXCEPTION_DIV_ZERO,
+ EXCEPTION_DATA_ABORT_READ,
+ EXCEPTION_DATA_ABORT_WR
[PATCH v1 3/5] cpukit/aarch64: Add Exception Manager support
This adds the call and support functions necessary to add Exception
Manager support to AArch64.
---
.../cpu/aarch64/aarch64-exception-default.S | 50 +
.../cpu/aarch64/aarch64-exception-default.c | 55 ++-
.../cpu/aarch64/aarch64-exception-interrupt.S | 18 --
spec/build/cpukit/optexceptionmanager.yml | 4 ++
4 files changed, 110 insertions(+), 17 deletions(-)
diff --git a/cpukit/score/cpu/aarch64/aarch64-exception-default.S
b/cpukit/score/cpu/aarch64/aarch64-exception-default.S
index 2a4ddbcc61..0065cf9e87 100644
--- a/cpukit/score/cpu/aarch64/aarch64-exception-default.S
+++ b/cpukit/score/cpu/aarch64/aarch64-exception-default.S
@@ -44,6 +44,8 @@
#include
.extern _AArch64_Exception_default
+.extern _AArch64_Wrap_Dispatch
+.extern _AArch64_Perform_Thread_Dispatch
.globl bsp_start_vector_table_begin
.globl bsp_start_vector_table_end
@@ -203,22 +205,34 @@ curr_el_spx_sync_get_pc: /* The current
PC is now in LR */
/* Store the vector */
str lr, [sp, #AARCH64_EXCEPTION_FRAME_REGISTER_VECTOR_OFFSET]
mov x0, sp
- blr x1
+/* x1 contains the branch target to be wrapped, x0 contains the argument to x1
*/
+ bl _AArch64_Wrap_Dispatch
+/* Save off x0 for later cmp */
+ mov x22, x0
+/*
+ * It is now safe to assume that the source of the exception has been resolved.
+ * Copy the exception frame to the thread stack to be compatible with thread
+ * dispatch. This may arbitrarily clobber corruptible registers.
+ */
+ bl .move_exception_frame_and_switch_to_thread_stack
+/*
+ * Check thread dispatch necessary, ISR dispatch disable and thread dispatch
+ * disable level.
+ */
+ cmp x22, #0
+ bne .Lno_need_thread_dispatch
+ bl _AArch64_Perform_Thread_Dispatch
+.Lno_need_thread_dispatch:
/* bl to CEF restore routine (doesn't restore lr) */
bl .pop_exception_context
ldr lr, [sp, #AARCH64_EXCEPTION_FRAME_REGISTER_LR_OFFSET] /* get
lr from CEF */
/* drop space reserved for CEF and clear exclusive */
add sp, sp, #AARCH64_EXCEPTION_FRAME_SIZE
- msr spsel, #1 /* switch to thread stack */
eret/* exception return */
nop
nop
nop
nop
- nop
- nop
- nop
- nop
/* Takes up the space of 2 instructions */
#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
.word _AArch64_Exception_default
@@ -527,12 +541,8 @@ twiddle:
ldp x24, x25, [sp, #0xc0]
ldp x26, x27, [sp, #0xd0]
ldp x28, x29, [sp, #0xe0]
-/* Pop sp and ELR */
- ldp x0, x1, [sp, #AARCH64_EXCEPTION_FRAME_REGISTER_SP_OFFSET]
-/* Restore thread SP */
- msr spsel, #1
- mov sp, x0
- msr spsel, #0
+/* Pop ELR, SP already popped */
+ ldr x1, [sp, #(AARCH64_EXCEPTION_FRAME_REGISTER_SP_OFFSET + 0x8)]
/* Restore exception LR */
msr ELR_EL1, x1
ldp x0, x1, [sp, #0x00]
@@ -541,3 +551,19 @@ twiddle:
clrex
ret
+
+/* Assumes sp currently points to the EF on the exception stack and SPSel is 0
*/
+.move_exception_frame_and_switch_to_thread_stack:
+ mov x1, sp /* Set
x1 to the current exception frame */
+ msr spsel, #1 /*
switch to thread stack */
+ ldr x0, [x1, #AARCH64_EXCEPTION_FRAME_REGISTER_SP_OFFSET] /* Get
thread SP from exception frame since it may have been updated */
+ mov sp, x0
+ sub sp, sp, #AARCH64_EXCEPTION_FRAME_SIZE /*
reserve space for CEF */
+ mov x0, sp /* Set
x0 to the new exception frame */
+ mov x19, lr /* Save
LR */
+ bl Exception_Manager_Copy_CPU_Exception_frame /* Copy
exception frame to reserved thread stack space */
+ mov lr, x19 /*
Restore LR */
+ msr spsel, #0 /*
switch to exception stack */
+ add sp, sp, #AARCH64_EXCEPTION_FRAME_SIZE /*
release space for CEF on exception stack */
+ msr spsel, #1 /*
switch to thread stack */
+ ret
diff --git a/cpukit/score/cpu/aarch64/aarch64-exception-default.c
b/cpukit/score/cpu/aarch64/aarch64-exception-default.c
index 2ebb3dee9f..e51e9453e1 100644
--- a/cpukit/score/cpu/aarch64/aarch64-exception-default.c
+++ b/cpukit/score/cpu/aarch64/aarch64-exception-default.c
@@ -43,8 +43,61 @@
#include
#include
+#include
void _AArch64_Exception_default( CPU_Exception_frame *frame )
{
- rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) frame );
+ if ( rtems_exception_manage( frame ) == false ) {
+rtems_fatal( RTEMS_FATAL_SOURCE
[PATCH v1 4/5] cpukit: Add signal mapping support
This adds a confdef option allowing an application to request mapping
machine exceptions to POSIX signals. This is required for some languages
such as Ada.
---
cpukit/doxygen/appl-config.h | 25 +-
cpukit/include/rtems/confdefs/extensions.h | 7 ++
cpukit/include/rtems/exception.h | 8 ++
cpukit/score/src/exceptionmapping.c| 93 ++
spec/build/cpukit/librtemscpu.yml | 2 +
spec/build/cpukit/objexceptionmapping.yml | 15
6 files changed, 149 insertions(+), 1 deletion(-)
create mode 100644 cpukit/score/src/exceptionmapping.c
create mode 100644 spec/build/cpukit/objexceptionmapping.yml
diff --git a/cpukit/doxygen/appl-config.h b/cpukit/doxygen/appl-config.h
index bbeb438bec..8ad3a3c70e 100644
--- a/cpukit/doxygen/appl-config.h
+++ b/cpukit/doxygen/appl-config.h
@@ -3,7 +3,7 @@
/*
* Copyright (C) 2019, 2021 embedded brains GmbH
(http://www.embedded-brains.de)
* Copyright (C) 2010 Gedare Bloom
- * Copyright (C) 1988, 2008 On-Line Applications Research Corporation (OAR)
+ * Copyright (C) 1988, 2021 On-Line Applications Research Corporation (OAR)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -1773,6 +1773,29 @@
*/
#define CONFIGURE_ATA_DRIVER_TASK_PRIORITY
+/* Generated from spec:/acfg/if/exception-to-signal-mapping */
+
+/**
+ * @brief This configuration option is a boolean feature define.
+ *
+ * In case this configuration option is defined, then the machine exception to
+ * POSIX signal mapping is configured during system initialization.
+ *
+ * @par Default Configuration
+ * If this configuration option is undefined, then the described feature is not
+ * enabled.
+ *
+ * @par Notes
+ * @parblock
+ * This device driver is responsible for setting up a mapping from machine
+ * exceptions to POSIX signals so that applications may consume them and alter
+ * task execution as necessary.
+ *
+ * This is especially useful for applications written in Ada or C++.
+ * @endparblock
+ */
+#define CONFIGURE_EXCEPTION_TO_SIGNAL_MAPPING
+
/* Generated from spec:/acfg/if/max-drivers */
/**
diff --git a/cpukit/include/rtems/confdefs/extensions.h
b/cpukit/include/rtems/confdefs/extensions.h
index 83d690d50a..e7185aa9d1 100644
--- a/cpukit/include/rtems/confdefs/extensions.h
+++ b/cpukit/include/rtems/confdefs/extensions.h
@@ -93,6 +93,10 @@
#include
#endif
+#ifdef CONFIGURE_EXCEPTION_TO_SIGNAL_MAPPING
+ #include
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -139,6 +143,9 @@ extern "C" {
#ifdef CONFIGURE_INITIAL_EXTENSIONS
CONFIGURE_INITIAL_EXTENSIONS,
#endif
+#ifdef CONFIGURE_EXCEPTION_TO_SIGNAL_MAPPING
+ { .exception = _Exception_map_signal },
+#endif
#ifdef BSP_INITIAL_EXTENSION
BSP_INITIAL_EXTENSION
#endif
diff --git a/cpukit/include/rtems/exception.h b/cpukit/include/rtems/exception.h
index dea1712409..5bf11127e7 100644
--- a/cpukit/include/rtems/exception.h
+++ b/cpukit/include/rtems/exception.h
@@ -152,6 +152,14 @@ void Exception_Manager_Copy_CPU_Exception_frame(
CPU_Exception_frame *old_ef
);
+/**
+ * @brief Handle an exception frame for mapping signals
+ *
+ * See CONFIGURE_EXCEPTION_TO_SIGNAL_MAPPING documentation in the
+ * "RTEMS Classic API Guide".
+ */
+void _Exception_map_signal( CPU_Exception_frame *ef, bool *handled );
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/src/exceptionmapping.c
b/cpukit/score/src/exceptionmapping.c
new file mode 100644
index 00..ef88feadfe
--- /dev/null
+++ b/cpukit/score/src/exceptionmapping.c
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreExceptionMapping
+ *
+ * @brief AArch64 machine exception to POSIX signal mapping.
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DA
[PATCH v1 5/5] testsuite: Add machine exception signal map test
Add a test to verify that mapping of machine exceptions to POSIX signals
operates properly when the application requests it.
---
spec/build/testsuites/psxtests/grp.yml| 2 +
.../build/testsuites/psxtests/psxsignal09.yml | 22 ++
testsuites/psxtests/psxsignal09/init.c| 73 +++
.../psxtests/psxsignal09/psxsignal09.doc | 7 ++
.../psxtests/psxsignal09/psxsignal09.scn | 3 +
testsuites/psxtests/psxsignal09/system.h | 55 ++
6 files changed, 162 insertions(+)
create mode 100644 spec/build/testsuites/psxtests/psxsignal09.yml
create mode 100644 testsuites/psxtests/psxsignal09/init.c
create mode 100644 testsuites/psxtests/psxsignal09/psxsignal09.doc
create mode 100644 testsuites/psxtests/psxsignal09/psxsignal09.scn
create mode 100644 testsuites/psxtests/psxsignal09/system.h
diff --git a/spec/build/testsuites/psxtests/grp.yml
b/spec/build/testsuites/psxtests/grp.yml
index fb7ce465ae..f61f45dbe9 100644
--- a/spec/build/testsuites/psxtests/grp.yml
+++ b/spec/build/testsuites/psxtests/grp.yml
@@ -205,6 +205,8 @@ links:
uid: psxsignal07
- role: build-dependency
uid: psxsignal08
+- role: build-dependency
+ uid: psxsignal09
- role: build-dependency
uid: psxspin01
- role: build-dependency
diff --git a/spec/build/testsuites/psxtests/psxsignal09.yml
b/spec/build/testsuites/psxtests/psxsignal09.yml
new file mode 100644
index 00..b09e2d62ce
--- /dev/null
+++ b/spec/build/testsuites/psxtests/psxsignal09.yml
@@ -0,0 +1,22 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: test-program
+cflags: []
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research (OAR)
+cppflags: []
+cxxflags: []
+enabled-by:
+- and:
+ - RTEMS_EXCEPTION_MANAGER
+ - RTEMS_POSIX_API
+features: c cprogram
+includes: []
+ldflags: []
+links: []
+source:
+- testsuites/psxtests/psxsignal09/init.c
+stlib: []
+target: testsuites/psxtests/psxsignal09.exe
+type: build
+use-after: []
+use-before: []
diff --git a/testsuites/psxtests/psxsignal09/init.c
b/testsuites/psxtests/psxsignal09/init.c
new file mode 100644
index 00..12883cc28c
--- /dev/null
+++ b/testsuites/psxtests/psxsignal09/init.c
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup psxtests
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#define CONFIGURE_INIT
+#include "system.h"
+#include
+#include
+#include
+
+const char rtems_test_name[] = "PSXSIGNAL 9";
+
+static void Handler_1( int signo )
+{
+ TEST_END();
+ rtems_test_exit(0);
+}
+
+void *POSIX_Init( void *argument )
+{
+ int status;
+ struct sigaction act;
+
+ TEST_BEGIN();
+
+ /* Hook signals that can be generated from machine exceptions */
+ act.sa_handler = Handler_1;
+ act.sa_flags = 0;
+ status = sigaction( SIGFPE, &act, NULL );
+ rtems_test_assert( !status );
+ status = sigaction( SIGILL, &act, NULL );
+ rtems_test_assert( !status );
+ status = sigaction( SIGSEGV, &act, NULL );
+ rtems_test_assert( !status );
+
+ /* Generate machine exception */
+ _CPU_Instruction_illegal();
+
+ return NULL;
+}
diff --git a/testsuites/psxtests/psxsignal09/psxsignal09.doc
b/testsuites/psxtests/psxsignal09/psxsignal09.doc
new file mode 100644
index 00..5375ee6c20
--- /dev/null
+++ b/testsuites/psxtests/psxsignal09/psxsignal09.doc
@@ -0,0 +1,7 @@
+# COPYRIGHT (c) 2021.
+# On-Line Applications Research Corporation (OAR).
+#
+# SPDX-License-Identifier: BSD-2-Clause
+
+This test ensures that machine exceptions are mapped to POSIX signals when
+required
Re: [PATCH] tester: Add MicroBlaze KCU105 QEMU BSP
Hi, Could you please explain this file? Where is the source? Why would we allow a binay blob into the tester like this? This seems specific to a set up or a BSP and not the tester. I am not comfortable with this approach. Have alternative approaches have you considered? Chris On 24/8/21 4:46 am, Alex White wrote: > --- > tester/rtems/testing/bsps/kcu105.dtb | Bin 0 -> 15256 bytes > tester/rtems/testing/bsps/kcu105_qemu.ini | 38 ++ > 2 files changed, 38 insertions(+) > create mode 100644 tester/rtems/testing/bsps/kcu105.dtb > create mode 100644 tester/rtems/testing/bsps/kcu105_qemu.ini > > diff --git a/tester/rtems/testing/bsps/kcu105.dtb > b/tester/rtems/testing/bsps/kcu105.dtb > new file mode 100644 > index > ..998e8c03b74d8d9ddc82b5f6fa53242415abbd84 > GIT binary patch > literal 15256 > Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH rtems v1 2/2] bsps/zynqmp: Added I2C support for ZynqMP
On 24/8/21 8:24 am, Stephen Clark wrote:
> Added I2C drivers for ZynqMP and updated build system accordingly.
> ---
> bsps/aarch64/xilinx-zynqmp/include/bsp.h | 4 ++
> bsps/aarch64/xilinx-zynqmp/include/bsp/i2c.h | 63 +++
> bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h | 2 +
> bsps/aarch64/xilinx-zynqmp/start/bspstart.c | 10 +++
> spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml | 4 ++
> .../bsps/aarch64/xilinx-zynqmp/grp_zu3eg.yml | 2 +
> .../aarch64/xilinx-zynqmp/objcadencei2c.yml | 19 ++
> .../bsps/aarch64/xilinx-zynqmp/optclki2c0.yml | 19 ++
> .../bsps/aarch64/xilinx-zynqmp/optclki2c1.yml | 19 ++
> 9 files changed, 142 insertions(+)
> create mode 100644 bsps/aarch64/xilinx-zynqmp/include/bsp/i2c.h
> create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/objcadencei2c.yml
> create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/optclki2c0.yml
> create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/optclki2c1.yml
>
> diff --git a/bsps/aarch64/xilinx-zynqmp/include/bsp.h
> b/bsps/aarch64/xilinx-zynqmp/include/bsp.h
> index 83f2e2f4e4..6d49b9ad2a 100644
> --- a/bsps/aarch64/xilinx-zynqmp/include/bsp.h
> +++ b/bsps/aarch64/xilinx-zynqmp/include/bsp.h
> @@ -70,6 +70,10 @@ BSP_START_TEXT_SECTION void
> zynqmp_setup_mmu_and_cache(void);
>
> void zynqmp_debug_console_flush(void);
>
> +uint32_t zynqmp_clock_i2c0(void);
> +
> +uint32_t zynqmp_clock_i2c1(void);
> +
> #ifdef __cplusplus
> }
> #endif /* __cplusplus */
> diff --git a/bsps/aarch64/xilinx-zynqmp/include/bsp/i2c.h
> b/bsps/aarch64/xilinx-zynqmp/include/bsp/i2c.h
> new file mode 100644
> index 00..e09747d414
> --- /dev/null
> +++ b/bsps/aarch64/xilinx-zynqmp/include/bsp/i2c.h
> @@ -0,0 +1,63 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (C) 2021 On-Line Applications Research (OAR)
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *notice, this list of conditions and the following disclaimer in the
> + *documentation and/or other materials provided with the distribution.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
> IS"
> + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
> + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
> + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
> + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
> + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
> + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
> + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
> + * POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +#ifndef LIBBSP_ARM_XILINX_ZYNQ_I2C_H
> +#define LIBBSP_ARM_XILINX_ZYNQ_I2C_H
> +
> +#include
> +#include
> +#include
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif /* __cplusplus */
> +
> +static inline int zynqmp_register_i2c_0(void)
> +{
> + return i2c_bus_register_cadence(
> +"/dev/i2c-0",
> +0x00FF02,
> +zynqmp_clock_i2c0(),
> +ZYNQMP_IRQ_I2C_0
> + );
> +}
> +
> +static inline int zynqmp_register_i2c_1(void)
> +{
> + return i2c_bus_register_cadence(
> +"/dev/i2c-1",
> +0x00FF03,
> +zynqmp_clock_i2c1(),
> +ZYNQMP_IRQ_I2C_1
> + );
I know these are currently inlined but I do not know why they are. It is the
only BSP that does this. Should they be moved to a .c file seem they are being
touched?
Chris
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Re: [PATCH 0/5] Preliminary Exception Manager Work
On 24/8/21 9:50 am, Kinsey Moore wrote: > This patch set contains the result of the Exception Manager work I > proposed a while back to manage handling of machine exceptions along > with a general feature for mapping exceptions to POSIX signals without > delving into the CPU Port-specific details. This is a pretty basic > initial implementation, but it can easily be expanded with mutators for > the CPU_Exception_frame for additional capabilities. Also included is a > test that demonstrates usage of the Exception Manager and exception to > signal mapping functionality. Could you please provide a link to the previous discussion? I have some concerns on how this interface and libdebugger are to work? Thanks Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
