RE: [PATCH v2 2/3] bsps/xilinx_zynq: Add SPI driver to waf

2021-02-14 Thread Jan.Sommer 
Yes, my bad.
When changing that compared to version 1 of the patch, I wanted to remove the 
references to cadence-spi, but instead removed the ones to cadence-i2c :-/

I will send in a new patchset.

Best regards,

   Jan

> -Original Message-
> From: Kinsey Moore 
> Sent: Saturday, February 13, 2021 6:16 PM
> To: Sommer, Jan ; devel@rtems.org
> Subject: RE: [PATCH v2 2/3] bsps/xilinx_zynq: Add SPI driver to waf
> 
> The header locations in spec/build/bsps/arm/xilinx-zynq/obj.yml don't look
> correct due to the relocation and should probably be removed entirely since
> they're now broken out into spec/build/bsps/objdevspizynq.yml, instead.
> 
> Kinsey
> 
> -Original Message-
> From: devel  On Behalf Of Jan Sommer
> Sent: Saturday, February 13, 2021 08:19
> To: devel@rtems.org
> Subject: [PATCH v2 2/3] bsps/xilinx_zynq: Add SPI driver to waf
> 
> ---
>  spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml  |  2 ++
>  spec/build/bsps/arm/xilinx-zynq/grp.yml|  2 ++
>  spec/build/bsps/arm/xilinx-zynq/obj.yml|  4 ++--
>  .../bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml |  2 ++
>  spec/build/bsps/objdevspizynq.yml  | 18 ++
>  5 files changed, 26 insertions(+), 2 deletions(-)  create mode 100644
> spec/build/bsps/objdevspizynq.yml
> 
> diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
> b/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
> index 552723c61c..c952b4f59e 100644
> --- a/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
> +++ b/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
> @@ -33,6 +33,8 @@ links:
>uid: ../../objirq
>  - role: build-dependency
>uid: ../../objdevserialzynq
> +- role: build-dependency
> +  uid: ../../objdevspizynq
>  - role: build-dependency
>uid: ../../optcachedata
>  - role: build-dependency
> diff --git a/spec/build/bsps/arm/xilinx-zynq/grp.yml
> b/spec/build/bsps/arm/xilinx-zynq/grp.yml
> index 74adbd7fa7..0bbee1922c 100644
> --- a/spec/build/bsps/arm/xilinx-zynq/grp.yml
> +++ b/spec/build/bsps/arm/xilinx-zynq/grp.yml
> @@ -57,6 +57,8 @@ links:
>uid: ../../objirq
>  - role: build-dependency
>uid: ../../objdevserialzynq
> +- role: build-dependency
> +  uid: ../../objdevspizynq
>  - role: build-dependency
>uid: linkcmds
>  - role: build-dependency
> diff --git a/spec/build/bsps/arm/xilinx-zynq/obj.yml
> b/spec/build/bsps/arm/xilinx-zynq/obj.yml
> index 6602b20a03..8b7e65ed40 100644
> --- a/spec/build/bsps/arm/xilinx-zynq/obj.yml
> +++ b/spec/build/bsps/arm/xilinx-zynq/obj.yml
> @@ -14,9 +14,9 @@ install:
>- bsps/arm/xilinx-zynq/include/tm27.h
>  - destination: ${BSP_INCLUDEDIR}/bsp
>source:
> -  - bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h
> -  - bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h
>- bsps/arm/xilinx-zynq/include/bsp/i2c.h
> +  - bsps/arm/xilinx-zynq/include/bsp/cadence-spi.h
> +  - bsps/arm/xilinx-zynq/include/bsp/cadence-spi-regs.h
>- bsps/arm/xilinx-zynq/include/bsp/irq.h
>  links: []
>  source:
> diff --git a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
> b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
> index 51d3268e99..d4e8cbc1ce 100644
> --- a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
> +++ b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
> @@ -69,6 +69,8 @@ links:
>uid: ../../objirq
>  - role: build-dependency
>uid: ../../objdevserialzynq
> +- role: build-dependency
> +  uid: ../../objdevspizynq
>  - role: build-dependency
>uid: ../../opto2
>  - role: build-dependency
> diff --git a/spec/build/bsps/objdevspizynq.yml
> b/spec/build/bsps/objdevspizynq.yml
> new file mode 100644
> index 00..b778e756e1
> --- /dev/null
> +++ b/spec/build/bsps/objdevspizynq.yml
> @@ -0,0 +1,18 @@
> +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
> +build-type: objects
> +cflags: []
> +copyrights:
> +- Copyright (C) 2021 German Aerospace Center (DLR)
> +cppflags: []
> +cxxflags: []
> +enabled-by: true
> +includes: []
> +install:
> +- destination: ${BSP_INCLUDEDIR}/dev/spi
> +  source:
> +  - bsps/include/dev/spi/cadence-spi-regs.h
> +  - bsps/include/dev/spi/cadence-spi.h
> +links: []
> +source:
> +- bsps/shared/dev/spi/cadence-spi.c
> +type: build
> --
> 2.17.1
> 
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[PATCH v3 2/3] bsps/xilinx_zynq: Add SPI driver to waf

2021-02-14 Thread Jan Sommer 
---
 spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml  |  2 ++
 spec/build/bsps/arm/xilinx-zynq/grp.yml|  2 ++
 .../bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml |  2 ++
 spec/build/bsps/objdevspizynq.yml  | 18 ++
 4 files changed, 24 insertions(+)
 create mode 100644 spec/build/bsps/objdevspizynq.yml

diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml 
b/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
index 552723c61c..c952b4f59e 100644
--- a/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
+++ b/spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml
@@ -33,6 +33,8 @@ links:
   uid: ../../objirq
 - role: build-dependency
   uid: ../../objdevserialzynq
+- role: build-dependency
+  uid: ../../objdevspizynq
 - role: build-dependency
   uid: ../../optcachedata
 - role: build-dependency
diff --git a/spec/build/bsps/arm/xilinx-zynq/grp.yml 
b/spec/build/bsps/arm/xilinx-zynq/grp.yml
index 74adbd7fa7..0bbee1922c 100644
--- a/spec/build/bsps/arm/xilinx-zynq/grp.yml
+++ b/spec/build/bsps/arm/xilinx-zynq/grp.yml
@@ -57,6 +57,8 @@ links:
   uid: ../../objirq
 - role: build-dependency
   uid: ../../objdevserialzynq
+- role: build-dependency
+  uid: ../../objdevspizynq
 - role: build-dependency
   uid: linkcmds
 - role: build-dependency
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml 
b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
index 51d3268e99..d4e8cbc1ce 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
@@ -69,6 +69,8 @@ links:
   uid: ../../objirq
 - role: build-dependency
   uid: ../../objdevserialzynq
+- role: build-dependency
+  uid: ../../objdevspizynq
 - role: build-dependency
   uid: ../../opto2
 - role: build-dependency
diff --git a/spec/build/bsps/objdevspizynq.yml 
b/spec/build/bsps/objdevspizynq.yml
new file mode 100644
index 00..b778e756e1
--- /dev/null
+++ b/spec/build/bsps/objdevspizynq.yml
@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: objects
+cflags: []
+copyrights:
+- Copyright (C) 2021 German Aerospace Center (DLR)
+cppflags: []
+cxxflags: []
+enabled-by: true
+includes: []
+install:
+- destination: ${BSP_INCLUDEDIR}/dev/spi
+  source:
+  - bsps/include/dev/spi/cadence-spi-regs.h
+  - bsps/include/dev/spi/cadence-spi.h
+links: []
+source:
+- bsps/shared/dev/spi/cadence-spi.c
+type: build
-- 
2.17.1

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[PATCH v3 0/3] Add cadence-SPI driver

2021-02-14 Thread Jan Sommer 
v3:
- Fix wrong changes to spec/build/bsps/arm/xilinx-zynq/obj.yml

v2:
- Moved source file to bsps/shared/dev/spi
- Moved include files to bsps/include/dev/spi
- Enabled build in aarch64 BSPs

v1:

This patchset implements a driver for the cadence-spi device of the Xilinx 
Zynq-7000 based SoCs  using the spidev API.


Jan Sommer (3):
  bsps/xilinx_zynq: Add SPI driver for cadence-spi
  bsps/xilinx_zynq: Add SPI driver to waf
  bsps/xilinx_zynq: Add SPI driver to autotools build

 bsps/headers.am   |   5 +
 bsps/include/dev/spi/cadence-spi-regs.h   |  84 
 bsps/include/dev/spi/cadence-spi.h|  48 ++
 bsps/shared/dev/spi/cadence-spi.c | 437 ++
 c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am  |   3 +
 .../lib/libbsp/arm/xilinx-zynqmp/Makefile.am  |   3 +
 spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml |   2 +
 spec/build/bsps/arm/xilinx-zynq/grp.yml   |   2 +
 .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml |   2 +
 spec/build/bsps/objdevspizynq.yml |  18 +
 10 files changed, 604 insertions(+)
 create mode 100644 bsps/include/dev/spi/cadence-spi-regs.h
 create mode 100644 bsps/include/dev/spi/cadence-spi.h
 create mode 100644 bsps/shared/dev/spi/cadence-spi.c
 create mode 100644 spec/build/bsps/objdevspizynq.yml

-- 
2.17.1

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[PATCH v3 1/3] bsps/xilinx_zynq: Add SPI driver for cadence-spi

2021-02-14 Thread Jan Sommer 
---
 bsps/include/dev/spi/cadence-spi-regs.h |  84 +
 bsps/include/dev/spi/cadence-spi.h  |  48 +++
 bsps/shared/dev/spi/cadence-spi.c   | 437 
 3 files changed, 569 insertions(+)
 create mode 100644 bsps/include/dev/spi/cadence-spi-regs.h
 create mode 100644 bsps/include/dev/spi/cadence-spi.h
 create mode 100644 bsps/shared/dev/spi/cadence-spi.c

diff --git a/bsps/include/dev/spi/cadence-spi-regs.h 
b/bsps/include/dev/spi/cadence-spi-regs.h
new file mode 100644
index 00..2851c88df1
--- /dev/null
+++ b/bsps/include/dev/spi/cadence-spi-regs.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 Jan Sommer, Deutsches Zentrum für Luft- und Raumfahrt e. 
V. (DLR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H
+#define LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H
+
+#include 
+
+typedef struct {
+uint32_t config;
+#define CADENCE_SPI_CONFIG_MODEFAIL_EN BSP_BIT32(17)
+#define CADENCE_SPI_CONFIG_MANSTRT BSP_BIT32(16)
+#define CADENCE_SPI_CONFIG_MANSTRT_EN BSP_BIT32(15)
+#define CADENCE_SPI_CONFIG_MANUAL_CS BSP_BIT32(14)
+#define CADENCE_SPI_CONFIG_CS(val) BSP_FLD32(val, 10, 13)
+#define CADENCE_SPI_CONFIG_CS_GET(reg) BSP_FLD32GET(reg, 10, 13)
+#define CADENCE_SPI_CONFIG_CS_SET(reg, val) BSP_FLD32SET(reg, val, 10, 13)
+#define CADENCE_SPI_CONFIG_PERI_SEL BSP_BIT32(9)
+#define CADENCE_SPI_CONFIG_REF_CLK BSP_BIT32(8)
+#define CADENCE_SPI_CONFIG_BAUD_DIV(val) BSP_FLD32(val, 3, 5)
+#define CADENCE_SPI_CONFIG_BAUD_DIV_GET(reg) BSP_FLD32GET(reg, 3, 5)
+#define CADENCE_SPI_CONFIG_BAUD_DIV_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
+#define CADENCE_SPI_CONFIG_CLK_PH BSP_BIT32(2)
+#define CADENCE_SPI_CONFIG_CLK_POL BSP_BIT32(1)
+#define CADENCE_SPI_CONFIG_MSTREN BSP_BIT32(0)
+   uint32_t irqstatus;
+   uint32_t irqenable;
+   uint32_t irqdisable;
+   uint32_t irqmask;
+#define CADENCE_SPI_IXR_TXUF BSP_BIT32(6)
+#define CADENCE_SPI_IXR_RXFULL BSP_BIT32(5)
+#define CADENCE_SPI_IXR_RXNEMPTY BSP_BIT32(4)
+#define CADENCE_SPI_IXR_TXFULL BSP_BIT32(3)
+#define CADENCE_SPI_IXR_TXOW BSP_BIT32(2)
+#define CADENCE_SPI_IXR_MODF BSP_BIT32(1)
+#define CADENCE_SPI_IXR_RXOVR BSP_BIT32(0)
+uint32_t spienable;
+#define CADENCE_SPI_EN BSP_BIT32(0)
+uint32_t delay;
+#define CADENCE_SPI_DELAY_DNSS(val) BSP_FLD32(val, 24, 31)
+#define CADENCE_SPI_DELAY_DNSS_GET(reg) BSP_FLD32GET(reg, 24, 31)
+#define CADENCE_SPI_DELAY_DNSS_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
+#define CADENCE_SPI_DELAY_DBTWN(val) BSP_FLD32(val, 16, 23)
+#define CADENCE_SPI_DELAY_DBTWN_GET(reg) BSP_FLD32GET(reg, 16, 23)
+#define CADENCE_SPI_DELAY_DBTWN_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
+#define CADENCE_SPI_DELAY_DAFTER(val) BSP_FLD32(val, 8, 15)
+#define CADENCE_SPI_DELAY_DAFTER_GET(reg) BSP_FLD32GET(reg, 8, 15)
+#define CADENCE_SPI_DELAY_DAFTER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
+#define CADENCE_SPI_DELAY_DINT(val) BSP_FLD32(val, 0, 7)
+#define CADENCE_SPI_DELAY_DINT_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define CADENCE_SPI_DELAY_DINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+   uint32_t txdata;
+   uint32_t rxdata;
+   uint32_t slave_idle_count;
+   uint32_t txthreshold;
+   uint32_t rxthreshold;
+   uint32_t moduleid;
+} cadence_spi;
+
+#endif /* LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H */
diff --git a/bsps/include/dev/spi/cadence-spi.h 
b/bsps/include/dev/spi/cadence-spi.h
new file mode 100644
index 00..7d7ecd3885
--- /dev/null
+++ b/bsps/include/dev/spi/cadence-spi.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 Jan Sommer, Deutsches Zentrum für Luft- und R

[PATCH v3 3/3] bsps/xilinx_zynq: Add SPI driver to autotools build

2021-02-14 Thread Jan Sommer 
---
 bsps/headers.am| 5 +
 c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am   | 3 +++
 c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am | 3 +++
 3 files changed, 11 insertions(+)

diff --git a/bsps/headers.am b/bsps/headers.am
index 1b82382db8..37ce6d6c73 100644
--- a/bsps/headers.am
+++ b/bsps/headers.am
@@ -39,6 +39,11 @@ include_dev_serial_HEADERS += 
../../bsps/include/dev/serial/arm-pl011.h
 include_dev_serial_HEADERS += ../../bsps/include/dev/serial/zynq-uart-regs.h
 include_dev_serial_HEADERS += ../../bsps/include/dev/serial/zynq-uart.h
 
+include_dev_spidir = $(includedir)/dev/spi
+include_dev_spi_HEADERS =
+include_dev_spi_HEADERS += ../../bsps/include/dev/spi/cadence-spi-regs.h
+include_dev_spi_HEADERS += ../../bsps/include/dev/spi/cadence-spi.h
+
 include_grlibdir = $(includedir)/grlib
 include_grlib_HEADERS =
 include_grlib_HEADERS += ../../bsps/include/grlib/ahbstat.h
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am 
b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am
index 8804dc40da..11749acc1b 100644
--- a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am
@@ -71,6 +71,9 @@ librtemsbsp_a_SOURCES += 
../../../../../../bsps/arm/shared/clock/clock-a9mpcore.
 # I2C
 librtemsbsp_a_SOURCES += 
../../../../../../bsps/arm/xilinx-zynq/i2c/cadence-i2c.c
 
+# SPI
+librtemsbsp_a_SOURCES +=  ../../../../../../bsps/shared/dev/spi/cadence-spi.c
+
 # Cache
 librtemsbsp_a_SOURCES += 
../../../../../../bsps/arm/shared/cache/cache-l2c-310.c
 
diff --git a/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am 
b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am
index 21db56a0ea..2d8ccf07cd 100644
--- a/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am
+++ b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am
@@ -67,6 +67,9 @@ librtemsbsp_a_SOURCES += 
../../../../../../bsps/shared/dev/serial/zynq-uart-poll
 librtemsbsp_a_SOURCES += 
../../../../../../bsps/shared/dev/clock/arm-generic-timer.c
 librtemsbsp_a_SOURCES += 
../../../../../../bsps/arm/shared/clock/arm-generic-timer-aarch32.c
 
+# SPI
+librtemsbsp_a_SOURCES +=  ../../../../../../bsps/shared/dev/spi/cadence-spi.c
+
 # Cache
 librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c
 
-- 
2.17.1

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gensh1 issues

2021-02-14 Thread Joel Sherrill 
Hi

I thought I would start checking in on some of the secondary target BSPs
that run on gdb. Something is broken in the waf build for this.

1) gensh1/start/start.s is not in the build but start.o is referenced in
linkcmds.

2) When I look at an executable, the start code is not from start.o but
addr2line says it is from crtstuff.o. Not sure where that comes from.

Since it doesn't have the right start file, it won't run. The address range
looks OK but the start code (whether it is from), doesn't end up very near
the base of RAM as I would expect.

I added start.S to the waf build but it didn't change the resulting
executables.

Any pointers would be appreciated.

Thanks.

--joel
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Re: [PATCH v3 1/3] bsps/xilinx_zynq: Add SPI driver for cadence-spi

2021-02-14 Thread Chris Johns 
Hi Jan,

Thank you for the changes. I have one question inlined below ...

On 14/2/21 10:30 pm, Jan Sommer wrote:
> ---
>  bsps/include/dev/spi/cadence-spi-regs.h |  84 +
>  bsps/include/dev/spi/cadence-spi.h  |  48 +++
>  bsps/shared/dev/spi/cadence-spi.c   | 437 
>  3 files changed, 569 insertions(+)
>  create mode 100644 bsps/include/dev/spi/cadence-spi-regs.h
>  create mode 100644 bsps/include/dev/spi/cadence-spi.h
>  create mode 100644 bsps/shared/dev/spi/cadence-spi.c
> 
> diff --git a/bsps/include/dev/spi/cadence-spi-regs.h 
> b/bsps/include/dev/spi/cadence-spi-regs.h
> new file mode 100644
> index 00..2851c88df1
> --- /dev/null
> +++ b/bsps/include/dev/spi/cadence-spi-regs.h
> @@ -0,0 +1,84 @@
> +/* SPDX-License-Identifier: BSD-2-Clause */
> +
> +/*
> + * Copyright (C) 2020 Jan Sommer, Deutsches Zentrum für Luft- und Raumfahrt 
> e. V. 

Is there a unicode character in this line? I cannot see anything in our coding
standard about unicode characters in source and I am not sure what the actual
policy is. I seem to remember some have been removed in the past. I thought I
would ask on the list now before we push these changes.

Chris
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Re: Requests Patches to be Applied to 4.10

2021-02-14 Thread Chris Johns 


On 12/2/21 6:52 am, Joel Sherrill wrote:
> 
> 
> On Thu, Feb 11, 2021 at 1:47 PM Gedare Bloom  > wrote:
> 
> Hi Joel,
> 
> On Thu, Feb 11, 2021 at 12:30 PM Joel Sherrill  > wrote:
> >
> > Hi
> >
> > Phillip Smith pinged me at the FSW via Slack about this set of patches 
> he
> proposed be added to the 4.10 branch.
> >
> > https://lists.rtems.org/pipermail/devel/2019-April/025610.html
> 
> >
> > I assume this matches what their project requires. Given that 4.10 is 
> the
> last unirprocessor version and we appear to be recommending 5 over 4.11, I
> suggest we consider applying the patches and discuss the possibility of
> another release. [1]
> >
> > I've previously suggested treating 4.10 as a long-term version since it 
> is
> the last uniprocessor version and a good baseline for behavior, 
> performance,
> and size.
> >
> I've agreed with that view, and in fact we do have several (20+?)
> patches that have been pushed on top of 4.10.2 (including some that
> broke internal APIs such as my PIP improvements). So, these patches
> can be considered for sure for a 4.10.3 cut. But we need to marshal
> time and resources to make it happen. I'm willing to contribute as I
> am able to do so.
> 
> 
> I'm thinking initially just evaluate the patches Phillip's project used and
> if they backport cleanly. If they don't, perhaps just file a ticket. If they 
> are
> low hanging, just push them. And run tests on say leon3 and psim.

All the patches listed in the link would need to be reviewed and tested so there
would need to be some sort of test plan. The 4.10 branch has sort of switched to
the RBS and release scripts. See the 4.10.3-rc2 package on ftp.rtems.org.

> > [1] Yes I know release cutting is thankless unpaid work. First step is
> just applying patches.
> 
> If I remember the discussion right, we came to the conclusion that
> maintaining 4.10 would require more resources than we have available
> to commit. I would suggest we identify what the costs may be
> (hardware, labor) for a long-term stable 4.10 version, and target some
> fundraising toward users that would benefit from it. I guess there may
> be at least some space and EPICS users that might be interested.

Yes this is my understanding. I am reluctant to move away from this plan and
make an exception. I have 4.11 in production in a number of systems and a 4.11
release is also needed.

> Cutting a release does involve thankless work and fixing a patch which
> doesn't backport very cleanly is also engineering.
> 
> I'm not disagreeing particularly on any point. We have finite resources 
> and funding core developers is the way to make something a priority.
> I can definitively state that a user's sponsorship of a code developer 
> got the 5 series over the hump and 5.1 out the door. It was greatly
> appreciated. 

Yes it was and I thank you for raising 5 because it is important we convey to
our users they can make a difference in these areas. It is great that Philip has
raised this but time only makes the problem harder.

A 4.10 release needs to deal with all hosts and all architectures and this makes
it complex given the host OSs have changed. To cut a 4.10.3 release I would need
to update the RSB to include a lot of recent changes to handle the python
version mix and then the built tools would need to be checked against the 4.10.2
build. I am not sure this happened. All of this takes many hours.

Chris
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rtems6 RSB tool build failures (lots)

2021-02-14 Thread Joel Sherrill 
Hi

Looks like most of the targets failed to build on CentOS over the weekend
and ended with this:

/home/joel/rtems-
 cron-6/tools/6/powerpc-rtems6/sys-include
configure: error: in `/home/joel/rtems-cron-6/rtems-source-builder/rtems/
build/powerpc-rtems6-gcc-eb15f76-newlib-d4a756f-x86_64-
linux-gnu-1/build/powerpc-rtems6/libgcc':
configure: error: cannot compute suffix of object files: cannot compile
See `config.log' for more details

I saw that on sparc, x86_64, and powerpc. Didn't look at them all.

Is anyone else seeing this? Any ideas?

--joel
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