Re: Oddity with address recorded for gcc instrumentation on ARM

[Peter Dufault]

> On Dec 18, 2020, at 17:52 , Joel Sherrill  wrote:
> 
> > Can someone explain this?
> These are link register values. The least significant bit determines if
> a bx instruction continues in ARM or Thumb mode.
> 
> I guess I've never had to look that close. Thanks Sebastian.
> 

It had me confused at first when I started working with ARM.

Peter
-
Peter Dufault
HD Associates, Inc.  Software and System Engineering

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[PATCH v1] zynq: Add support for SDHCI devices

[Kinsey Moore]

---
 libbsd.py |   1 +
 rtemsbsd/include/bsp/nexus-devices.h  |   3 +
 .../include/machine/rtems-bsd-nexus-bus.h |  29 ++
 rtemsbsd/sys/dev/sdhci/arasan_sdhci.c | 343 ++
 4 files changed, 376 insertions(+)
 create mode 100644 rtemsbsd/sys/dev/sdhci/arasan_sdhci.c

diff --git a/libbsd.py b/libbsd.py
index 909c0037..8bcb779d 100644
--- a/libbsd.py
+++ b/libbsd.py
@@ -226,6 +226,7 @@ class rtems(builder.Module):
 'sys/dev/ffec/if_ffec_mcf548x.c',
 'sys/dev/ffec/if_ffec_mpc8xx.c',
 'sys/dev/input/touchscreen/tsc_lpc32xx.c',
+'sys/dev/sdhci/arasan_sdhci.c',
 'sys/dev/smc/if_smc_nexus.c',
 'sys/dev/stmac/if_stmac.c',
 'sys/dev/tsec/if_tsec_nexus.c',
diff --git a/rtemsbsd/include/bsp/nexus-devices.h 
b/rtemsbsd/include/bsp/nexus-devices.h
index 51bca3aa..c3c43dc9 100644
--- a/rtemsbsd/include/bsp/nexus-devices.h
+++ b/rtemsbsd/include/bsp/nexus-devices.h
@@ -97,8 +97,11 @@ RTEMS_BSD_DRIVER_FEC;
 #include 
 
 RTEMS_BSD_DRIVER_XILINX_ZYNQ_SLCR;
+RTEMS_BSD_DRIVER_XILINX_ZYNQ_SDHCI0;
+RTEMS_BSD_DRIVER_XILINX_ZYNQ_SDHCI1;
 RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM0(ZYNQ_IRQ_ETHERNET_0);
 RTEMS_BSD_DRIVER_E1000PHY;
+RTEMS_BSD_DRIVER_MMC;
 
 #elif defined(LIBBSP_AARCH64_XILINX_ZYNQMP_BSP_H)
 
diff --git a/rtemsbsd/include/machine/rtems-bsd-nexus-bus.h 
b/rtemsbsd/include/machine/rtems-bsd-nexus-bus.h
index f1ca66d7..5c95d2c3 100644
--- a/rtemsbsd/include/machine/rtems-bsd-nexus-bus.h
+++ b/rtemsbsd/include/machine/rtems-bsd-nexus-bus.h
@@ -117,6 +117,35 @@ extern "C" {
   &zy7_slcr_res[0])
 #endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQ_SLCR */
 
+/*
+ * Xilinx Zynq Arasan SDIO Driver.
+ */
+#if !defined(RTEMS_BSD_DRIVER_XILINX_ZYNQ_SDHCI)
+  #define RTEMS_BSD_DRIVER_XILINX_ZYNQ_SDHCI(_num, _base, _irq)
 \
+static const rtems_bsd_device_resource arasan_sdhci ## _num ## _res[] = {  
 \
+  {
 \
+.type = RTEMS_BSD_RES_MEMORY,  
 \
+.start_request = 0,
 \
+.start_actual = (_base)
 \
+  }, { 
 \
+.type = RTEMS_BSD_RES_IRQ, 
 \
+.start_request = 0,
 \
+.start_actual = (_irq) 
 \
+  }
 \
+}; 
 \
+RTEMS_BSD_DEFINE_NEXUS_DEVICE(arasan_sdhci, _num,  
 \
+  RTEMS_ARRAY_SIZE(arasan_sdhci ## _num ## 
_res),  \
+  &arasan_sdhci ## _num ## _res[0])
+#endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQ_SDHCI */
+#if !defined(RTEMS_BSD_DRIVER_XILINX_ZYNQ_SDHCI0)
+  #define RTEMS_BSD_DRIVER_XILINX_ZYNQ_SDHCI0\
+RTEMS_BSD_DRIVER_XILINX_ZYNQ_SDHCI(0, 0xE010, 56)
+#endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQ_SDHCI0 */
+#if !defined(RTEMS_BSD_DRIVER_XILINX_ZYNQ_SDHCI1)
+  #define RTEMS_BSD_DRIVER_XILINX_ZYNQ_SDHCI1\
+RTEMS_BSD_DRIVER_XILINX_ZYNQ_SDHCI(1, 0xE0101000, 79)
+#endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQ_SDHCI1 */
+
 /*
  * LPC32XX Power Control (PWR).
  */
diff --git a/rtemsbsd/sys/dev/sdhci/arasan_sdhci.c 
b/rtemsbsd/sys/dev/sdhci/arasan_sdhci.c
new file mode 100644
index ..42574f16
--- /dev/null
+++ b/rtemsbsd/sys/dev/sdhci/arasan_sdhci.c
@@ -0,0 +1,343 @@
+#include 
+
+/*-
+ * Copyright (c) 2019 Navigation Technology Associates Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOO

Re: Oddity with address recorded for gcc instrumentation on ARM

[Chris Johns]

On 19/12/20 7:56 am, Sebastian Huber wrote:
> If you build the RTEMS tools with the LLVM development package you get the
> function name and line information in the trace.

Is there a wrote up or walk through on how to do this?

Thanks
Chris
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[PATCH] user: Mention use of LLVM

[Sebastian Huber]

---
 user/tracing/eventrecording.rst | 4 
 1 file changed, 4 insertions(+)

diff --git a/user/tracing/eventrecording.rst b/user/tracing/eventrecording.rst
index 27e929c..4867db8 100644
--- a/user/tracing/eventrecording.rst
+++ b/user/tracing/eventrecording.rst
@@ -179,6 +179,10 @@ extra support for the
 `Linux Trace Toolkit Next Generation (LTTng) `_.  This
 format can be analysed using `babeltrace `_ or
 `Eclipse Trace Compass `_.
+The command line tool :file:`rtems-record-lttng` optionally uses
+`LLVM `_ to translate target addresses to functions and
+source file locations.  Make sure you have the LLVM development package
+installed when you build the RTEMS Tools to enable this feature.
 
 For example, to get the event records from the record server running on the
 target use:
-- 
2.26.2

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