date:20201003

Re: [PATCH v4] cpukit/librcxx: Add a C++ thread interface with attributes

2020-10-03 Thread Joel Sherrill

Will this show up in documentation somewhere?

It does seem like we should say something about C++ threads and this.

What about C11 threads?

Test doesn't appear to cover much.

More interspersed


On Sat, Oct 3, 2020, 1:23 AM  wrote:

> From: Chris Johns 
>
> ---
>  cpukit/include/rtems/c++/error|  65 +++
>  cpukit/include/rtems/c++/thread   | 469 ++
>  cpukit/librtemscxx/error.cc   |  76 
>  cpukit/librtemscxx/thread.cc  | 416 +++
>  spec/build/cpukit/grp.yml |   2 +
>  spec/build/cpukit/librtemscxx.yml |  21 +
>  spec/build/testsuites/libtests/grp.yml|   2 +
>  spec/build/testsuites/libtests/rcxx01.yml |  22 +
>  testsuites/libtests/rcxx01/init.c |  69 
>  testsuites/libtests/rcxx01/rcxx01.doc |  16 +
>  testsuites/libtests/rcxx01/rcxx01.scn |  13 +
>  testsuites/libtests/rcxx01/thread.cc  |  90 +
>  12 files changed, 1261 insertions(+)
>  create mode 100644 cpukit/include/rtems/c++/error
>  create mode 100644 cpukit/include/rtems/c++/thread
>  create mode 100644 cpukit/librtemscxx/error.cc
>  create mode 100644 cpukit/librtemscxx/thread.cc
>  create mode 100644 spec/build/cpukit/librtemscxx.yml
>  create mode 100644 spec/build/testsuites/libtests/rcxx01.yml
>  create mode 100644 testsuites/libtests/rcxx01/init.c
>  create mode 100644 testsuites/libtests/rcxx01/rcxx01.doc
>  create mode 100644 testsuites/libtests/rcxx01/rcxx01.scn
>  create mode 100644 testsuites/libtests/rcxx01/thread.cc
>
> diff --git a/cpukit/include/rtems/c++/error
> b/cpukit/include/rtems/c++/error
> new file mode 100644
> index 00..8b9d875e0f
> --- /dev/null
> +++ b/cpukit/include/rtems/c++/error
> @@ -0,0 +1,65 @@
> +/* -*- C++ -*-
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (C) 2020 Chris Johns (http://contemporary.software)
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *notice, this list of conditions and the following disclaimer in the
> + *documentation and/or other materials provided with the distribution.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
> "AS IS"
> + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
> THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
> PURPOSE
> + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
> BE
> + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
> + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
> + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
> BUSINESS
> + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
> + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
> + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
> THE
> + * POSSIBILITY OF SUCH DAMAGE.
> + */
> +/**
> + * @file
> + *
> + * @ingroup RTEMSC++
> + *
> + * RTEMS Error exception.
> + */
> +
> +#if !defined(RTEMS_CXX_ERROR)
> +#define RTEMS_CXX_ERROR

+
> +#include 
> +#include 
> +
> +#include 
> +
> +namespace rtems
> +{
> +  class runtime_error :
> +public std::runtime_error
> +  {
> +const rtems_status_code sc;
> +  public:
> +runtime_error (const rtems_status_code sc);
> +runtime_error (const rtems_status_code sc, const std::string& what);
> +runtime_error (const rtems_status_code sc, const char* what);
> +~runtime_error ();
> +  };
> +
> +  /**
> +   * Throw a rtems::runtime_error exception if the RTEMS status code is
> +   * not RTEMS_SUCCESSFUL.
> +   */
> +  void runtime_error_check (const rtems_status_code sc);
> +  void runtime_error_check (const rtems_status_code sc, const
> std::string& what);
> +  void runtime_error_check (const rtems_status_code sc, const char* what);
> +};
> +
> +#endif
> diff --git a/cpukit/include/rtems/c++/thread
> b/cpukit/include/rtems/c++/thread
> new file mode 100644
> index 00..c3f18ab3cf
> --- /dev/null
> +++ b/cpukit/include/rtems/c++/thread
> @@ -0,0 +1,469 @@
> +/* -*- C++ -*-
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (C) 2020 Chris Johns (http://contemporary.software)
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *notice, this list of

Re: Interest in Virtual RTEMS Workshop

2020-10-03 Thread Richi Dubey

Hi,

This sounds great! I'd love to learn more about RTEMS through the workshop.

On Sat, Oct 3, 2020 at 1:32 AM Joel Sherrill  wrote:

> Hi
>
> In the past, we have internally discussed an RTEMS Workshop but always got
> hung up on the basic logistics. There had to be a host site which usually
> means cost. Although OAR now has access to a facility that could host about
> 40-50. Travel required to all be in a central location would be burdensome
> based on time and cost. Remember the core developers are spread across
> three continents.
>
> The pandemic has made it clear that virtual meetings, conferences,
> birthday parties, etc. are possible. Based on ideas from other open source
> projects, I am curious if there would be interest in having a virtual
> workshop.
>
> One thought is that given the time zones, it might be nice to do it as a
> TBD number of 2-3 hour sessions which vary in time across 2-3 days. That
> should let different people participate. One open source project did a 24
> hour event which spanned the world. I do not want to do that. :)
>
> I think recording the presentations beforehand and making them available
> afterwards would be ideal. I have seen formal setups where questions are
> restricted to the end of the presentation but like the idea of the
> presenter able to chat while their presentation is going.
>
> In my perfect world, most presentations would be from people using RTEMS,
> although I expect core developer presentations would add depth to what they
> are working on and the goals.
>
> Is there interest? Would you be willing to present? participate? Advice?
>
> Thanks.
>
> --joel
> ___
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> devel@rtems.org
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Re: Interest in Virtual RTEMS Workshop

2020-10-03 Thread Thomas Doerfler

Hi Joel,

you know I thought about a workshop/conference/meeting some years ago,
but the reasons you list in your message exactly hit the problems. So I
think such a virtual workshop would be a good idea (wow, thank you,
corona! (at least for this)).

Presenting what RTEMS is used for, how certain problems got solved,
where RTEMS is traveling to... would be interesting.

Having some open talks about what the users like (and dislike) at RTEMS,
how the future should look... would somehow round it up.

And getting/completing a world map, where RTEMS users are located would
be nice to see too.

wkr,

Thomas.

Am 02.10.20 um 22:02 schrieb Joel Sherrill:
> Hi
> 
> In the past, we have internally discussed an RTEMS Workshop but always
> got hung up on the basic logistics. There had to be a host site which
> usually means cost. Although OAR now has access to a facility that could
> host about 40-50. Travel required to all be in a central location would
> be burdensome based on time and cost. Remember the core developers are
> spread across three continents. 
> 
> The pandemic has made it clear that virtual meetings, conferences,
> birthday parties, etc. are possible. Based on ideas from other open
> source projects, I am curious if there would be interest in having a
> virtual workshop.
> 
> One thought is that given the time zones, it might be nice to do it as a
> TBD number of 2-3 hour sessions which vary in time across 2-3 days. That
> should let different people participate. One open source project did a
> 24 hour event which spanned the world. I do not want to do that. :)
> 
> I think recording the presentations beforehand and making them available
> afterwards would be ideal. I have seen formal setups where questions are
> restricted to the end of the presentation but like the idea of the
> presenter able to chat while their presentation is going. 
> 
> In my perfect world, most presentations would be from people using
> RTEMS, although I expect core developer presentations would add depth to
> what they are working on and the goals. 
> 
> Is there interest? Would you be willing to present? participate? Advice?
> 
> Thanks.
> 
> --joel
> 
> ___
> devel mailing list
> devel@rtems.org
> http://lists.rtems.org/mailman/listinfo/devel
> 

-- 

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Thomas Doerfler
Dornierstr. 4
D-82178 Puchheim
Germany
email: thomas.doerf...@embedded-brains.de
Phone: +49-89-18 94 741-12
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Re: Interest in Virtual RTEMS Workshop

2020-10-03 Thread groups

Hi Joel,

About two weeks ago, a lady from Seattle organized a kite makers workshop, but 
virtual, over Google Meet. 3 sessions Friday afternoon, 8 Saturday, and 8 on 
Sunday.

With very little fore notice, she managed to get people from Germany, England, 
Australia, Columbia, Argentina, as well as Canada and the US. It was awesome.

The general format was that the guest speaker gave a talk on some topic that 
was a bit off of the mainstream, where a more hands on approach would be 
helpful, but nothing to niche. After their intro/video the floor was opened for 
questions to cover the details that were missed and so forth.

The biggest issue was getting the various watchers to mute their mics when not 
talking, and Google Meet tended to screw up  for the presenter, even though it 
had been working perfectly for the previous two days. It’s like there was a 
maximum possible aggravation sensor got installed that was able to detect who 
was going to present at the next session.

Yes, I’m very interested.

Andrei (from The Great White North)

-
Andrei Chichak

Systems Developer
CBF Systems Inc.
Suite 225 
8215 112 St NW
EDMONTON, ALBERTA
T6G 2C8
CANADA

Phone: 780-628-2072
Skype: andrei.chichak










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[PATCH v3 02/10] spec: Add missing spintrcritical24 definition

2020-10-03 Thread Kinsey Moore

---
 spec/build/bsps/tstnointrcrit.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/spec/build/bsps/tstnointrcrit.yml 
b/spec/build/bsps/tstnointrcrit.yml
index 0460aaabb3..46f7d974c8 100644
--- a/spec/build/bsps/tstnointrcrit.yml
+++ b/spec/build/bsps/tstnointrcrit.yml
@@ -24,6 +24,7 @@ actions:
 spintrcritical21: exclude
 spintrcritical22: exclude
 spintrcritical23: exclude
+spintrcritical24: exclude
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-- 
2.20.1

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[PATCH v3 03/10] bsps: Break out AArch32 portions of GPT driver

2020-10-03 Thread Kinsey Moore

This breaks AArch32-specific portions of the ARM GPT driver into their
own file so that the generic code can be moved for reuse by other
architectures.
---
 bsps/arm/imx/headers.am   |  4 +
 bsps/arm/imx/include/bsp.h|  2 -
 bsps/arm/imx/start/bspstart.c |  3 +-
 .../shared/clock/arm-generic-timer-aarch32.c  | 76 +++
 bsps/arm/xen/headers.am   |  4 +
 bsps/arm/xen/include/bsp.h|  2 -
 bsps/arm/xen/start/bspstart.c |  3 +-
 bsps/arm/xilinx-zynqmp/headers.am |  4 +
 bsps/arm/xilinx-zynqmp/include/bsp.h  |  2 -
 bsps/arm/xilinx-zynqmp/start/bspstart.c   |  3 +-
 bsps/include/dev/clock/arm-generic-timer.h| 76 +++
 .../dev/clock/arm-generic-timer.c}| 65 
 c/src/lib/libbsp/arm/imx/Makefile.am  |  3 +-
 c/src/lib/libbsp/arm/xen/Makefile.am  |  3 +-
 .../lib/libbsp/arm/xilinx-zynqmp/Makefile.am  |  3 +-
 spec/build/bsps/arm/imx/bspimx.yml|  6 +-
 spec/build/bsps/arm/xen/bspxen.yml|  6 +-
 .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml |  6 +-
 18 files changed, 205 insertions(+), 66 deletions(-)
 create mode 100644 bsps/arm/shared/clock/arm-generic-timer-aarch32.c
 create mode 100644 bsps/include/dev/clock/arm-generic-timer.h
 rename bsps/{arm/shared/clock/clock-generic-timer.c => 
shared/dev/clock/arm-generic-timer.c} (71%)

diff --git a/bsps/arm/imx/headers.am b/bsps/arm/imx/headers.am
index 3a093b1698..9863f34300 100644
--- a/bsps/arm/imx/headers.am
+++ b/bsps/arm/imx/headers.am
@@ -21,3 +21,7 @@ include_bspdir = $(includedir)/bsp
 include_bsp_HEADERS =
 include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/imx-gpio.h
 include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/irq.h
+
+include_dev_clockdir = $(includedir)/dev/clock
+include_dev_clock_HEADERS =
+include_dev_clock_HEADERS += 
../../../../../../bsps/include/dev/clock/arm-generic-timer.h
diff --git a/bsps/arm/imx/include/bsp.h b/bsps/arm/imx/include/bsp.h
index 134b3fd858..99b7a0d1d7 100644
--- a/bsps/arm/imx/include/bsp.h
+++ b/bsps/arm/imx/include/bsp.h
@@ -57,8 +57,6 @@ extern uintptr_t imx_gic_dist_base;
 
 #define BSP_ARM_A9MPCORE_SCU_BASE 0
 
-void arm_generic_timer_get_config(uint32_t *frequency, uint32_t *irq);
-
 void *imx_get_reg_of_node(const void *fdt, int node);
 
 int imx_iomux_configure_pins(const void *fdt, uint32_t phandle);
diff --git a/bsps/arm/imx/start/bspstart.c b/bsps/arm/imx/start/bspstart.c
index 5fb07bf60a..ff4b204790 100644
--- a/bsps/arm/imx/start/bspstart.c
+++ b/bsps/arm/imx/start/bspstart.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -58,7 +59,7 @@ uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
   return intr[1] + MAGIC_IRQ_OFFSET;
 }
 
-void arm_generic_timer_get_config(
+void aarch_generic_timer_get_config(
   uint32_t *frequency,
   uint32_t *irq
 )
diff --git a/bsps/arm/shared/clock/arm-generic-timer-aarch32.c 
b/bsps/arm/shared/clock/arm-generic-timer-aarch32.c
new file mode 100644
index 00..8ce65ee5ad
--- /dev/null
+++ b/bsps/arm/shared/clock/arm-generic-timer-aarch32.c
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMShared
+ *
+ * @brief ARM-specific clock driver functions.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+uint64_t aarch_gt_clock_get_compare_value(void)
+{
+#ifdef ARM_GENERIC_TIMER_USE_VIRTUAL
+  return arm_cp15_get_counter_pl1_virtu

[PATCH v3 01/10] Move ARM PL011 UART driver

2020-10-03 Thread Kinsey Moore

This UART driver is now needed for BSPs other than ARM.
---
 bsps/arm/headers.am  | 2 --
 bsps/arm/raspberrypi/console/console-config.c| 2 +-
 bsps/arm/realview-pbx-a9/include/bsp/console.h   | 2 +-
 bsps/arm/xen/console/console.c   | 2 +-
 bsps/headers.am  | 5 +
 .../{arm/include/bsp => include/dev/serial}/arm-pl011-regs.h | 0
 bsps/{arm/include/bsp => include/dev/serial}/arm-pl011.h | 2 +-
 bsps/{arm/shared => shared/dev}/serial/arm-pl011.c   | 2 +-
 c/src/lib/libbsp/arm/raspberrypi/Makefile.am | 2 +-
 c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am | 2 +-
 c/src/lib/libbsp/arm/xen/Makefile.am | 2 +-
 spec/build/bsps/arm/grp.yml  | 2 --
 spec/build/bsps/arm/raspberrypi/obj.yml  | 1 -
 spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml | 1 -
 spec/build/bsps/arm/xen/bspxen.yml   | 1 -
 spec/build/bsps/obj.yml  | 5 +
 16 files changed, 18 insertions(+), 15 deletions(-)
 rename bsps/{arm/include/bsp => include/dev/serial}/arm-pl011-regs.h (100%)
 rename bsps/{arm/include/bsp => include/dev/serial}/arm-pl011.h (96%)
 rename bsps/{arm/shared => shared/dev}/serial/arm-pl011.c (98%)

diff --git a/bsps/arm/headers.am b/bsps/arm/headers.am
index 3d2b09effa..f0d498c8f4 100644
--- a/bsps/arm/headers.am
+++ b/bsps/arm/headers.am
@@ -21,8 +21,6 @@ include_bsp_HEADERS += 
../../../../../bsps/arm/include/bsp/arm-gic-irq.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-tm27.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011-regs.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl111-fb.h
diff --git a/bsps/arm/raspberrypi/console/console-config.c 
b/bsps/arm/raspberrypi/console/console-config.c
index bb0b596019..6b8eb80aa4 100644
--- a/bsps/arm/raspberrypi/console/console-config.c
+++ b/bsps/arm/raspberrypi/console/console-config.c
@@ -25,13 +25,13 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
diff --git a/bsps/arm/realview-pbx-a9/include/bsp/console.h 
b/bsps/arm/realview-pbx-a9/include/bsp/console.h
index da2e4099e2..2019fc2509 100644
--- a/bsps/arm/realview-pbx-a9/include/bsp/console.h
+++ b/bsps/arm/realview-pbx-a9/include/bsp/console.h
@@ -15,7 +15,7 @@
 #ifndef LIBBSP_ARM_REALVIEW_PBX_A9_BSP_CONSOLE_H
 #define LIBBSP_ARM_REALVIEW_PBX_A9_BSP_CONSOLE_H
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xen/console/console.c b/bsps/arm/xen/console/console.c
index 786b98f3ba..05eceae438 100644
--- a/bsps/arm/xen/console/console.c
+++ b/bsps/arm/xen/console/console.c
@@ -29,7 +29,7 @@
 #include 
 
 #include 
-#include 
+#include 
 #include 
 #include 
 
diff --git a/bsps/headers.am b/bsps/headers.am
index 5af7e43b4a..aaf13284bd 100644
--- a/bsps/headers.am
+++ b/bsps/headers.am
@@ -21,6 +21,11 @@ include_bsp_HEADERS += ../../bsps/include/bsp/u-boot.h
 include_bsp_HEADERS += ../../bsps/include/bsp/uart-output-char.h
 include_bsp_HEADERS += ../../bsps/include/bsp/utility.h
 
+include_dev_serialdir = $(includedir)/dev/serial
+include_dev_serial_HEADERS =
+include_dev_serial_HEADERS += ../../bsps/include/dev/serial/arm-pl011-regs.h
+include_dev_serial_HEADERS += ../../bsps/include/dev/serial/arm-pl011.h
+
 include_grlibdir = $(includedir)/grlib
 include_grlib_HEADERS =
 include_grlib_HEADERS += ../../bsps/include/grlib/ahbstat.h
diff --git a/bsps/arm/include/bsp/arm-pl011-regs.h 
b/bsps/include/dev/serial/arm-pl011-regs.h
similarity index 100%
rename from bsps/arm/include/bsp/arm-pl011-regs.h
rename to bsps/include/dev/serial/arm-pl011-regs.h
diff --git a/bsps/arm/include/bsp/arm-pl011.h 
b/bsps/include/dev/serial/arm-pl011.h
similarity index 96%
rename from bsps/arm/include/bsp/arm-pl011.h
rename to bsps/include/dev/serial/arm-pl011.h
index 49ff413581..c7e65656a3 100644
--- a/bsps/arm/include/bsp/arm-pl011.h
+++ b/bsps/include/dev/serial/arm-pl011.h
@@ -25,7 +25,7 @@
 
 #include 
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/shared/serial/arm-pl011.c 
b/bsps/shared/dev/serial/arm-pl011.c
similarity index 98%
rename from bsps/arm/shared/serial/arm-pl011.c
rename to bsps/shared/dev/serial/arm-pl011.c
index 44a409e551..c3cbab6f3e 100644
--- a/bsps/arm/shared/serial/arm-pl011.c
+++ b/bsps/shared/dev/serial/arm-pl011

[PATCH v3 04/10] bsps: Break out AArch32 GICv3 support

2020-10-03 Thread Kinsey Moore

This breaks out AArch32-specific code so that the shared GICv3 code can
be reused by other architectures.
---
 bsps/arm/altera-cyclone-v/include/bsp/irq.h   |   2 +-
 bsps/arm/altera-cyclone-v/include/tm27.h  |   2 +-
 bsps/arm/headers.am   |   4 -
 bsps/arm/imx/include/bsp/irq.h|   2 +-
 bsps/arm/imx/include/tm27.h   |   2 +-
 bsps/arm/include/bsp/arm-a9mpcore-start.h |   2 +-
 bsps/arm/realview-pbx-a9/include/bsp/irq.h|   2 +-
 bsps/arm/realview-pbx-a9/include/tm27.h   |   2 +-
 bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c   |  61 +
 bsps/arm/shared/irq/irq-gic.c |   2 +-
 bsps/arm/xen/include/bsp/irq.h|   2 +-
 bsps/arm/xen/include/tm27.h   |   2 +-
 bsps/arm/xilinx-zynq/include/bsp/irq.h|   2 +-
 bsps/arm/xilinx-zynq/include/tm27.h   |   2 +-
 bsps/arm/xilinx-zynqmp/include/bsp/irq.h  |   2 +-
 bsps/arm/xilinx-zynqmp/include/tm27.h |   2 +-
 bsps/headers.am   |   7 +
 .../bsp => include/dev/irq}/arm-gic-irq.h |  21 ++-
 .../bsp => include/dev/irq}/arm-gic-regs.h|   0
 .../bsp => include/dev/irq}/arm-gic-tm27.h|   0
 .../include/bsp => include/dev/irq}/arm-gic.h |   2 +-
 .../dev/irq/arm-gicv3.c}  | 123 +++---
 spec/build/bsps/arm/grp.yml   |  10 +-
 23 files changed, 183 insertions(+), 73 deletions(-)
 create mode 100644 bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c
 rename bsps/{arm/include/bsp => include/dev/irq}/arm-gic-irq.h (82%)
 rename bsps/{arm/include/bsp => include/dev/irq}/arm-gic-regs.h (100%)
 rename bsps/{arm/include/bsp => include/dev/irq}/arm-gic-tm27.h (100%)
 rename bsps/{arm/include/bsp => include/dev/irq}/arm-gic.h (99%)
 rename bsps/{arm/shared/irq/irq-gicv3.c => shared/dev/irq/arm-gicv3.c} (86%)

diff --git a/bsps/arm/altera-cyclone-v/include/bsp/irq.h 
b/bsps/arm/altera-cyclone-v/include/bsp/irq.h
index 4247d01747..bd2bba4caa 100644
--- a/bsps/arm/altera-cyclone-v/include/bsp/irq.h
+++ b/bsps/arm/altera-cyclone-v/include/bsp/irq.h
@@ -27,7 +27,7 @@
 #include 
 
 #include 
-#include 
+#include 
 #include 
 
 #ifdef __cplusplus
diff --git a/bsps/arm/altera-cyclone-v/include/tm27.h 
b/bsps/arm/altera-cyclone-v/include/tm27.h
index 23019a539a..00d7883f38 100644
--- a/bsps/arm/altera-cyclone-v/include/tm27.h
+++ b/bsps/arm/altera-cyclone-v/include/tm27.h
@@ -33,7 +33,7 @@
  * @brief Intel Cyclone V TM27 Support.
  */
 
-#include 
+#include 
 
 /** @} */
 
diff --git a/bsps/arm/headers.am b/bsps/arm/headers.am
index f0d498c8f4..bff9a16fc8 100644
--- a/bsps/arm/headers.am
+++ b/bsps/arm/headers.am
@@ -17,10 +17,6 @@ include_bsp_HEADERS += 
../../../../../bsps/arm/include/bsp/arm-a9mpcore-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-a9mpcore-start.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-cp15-start.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-errata.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-irq.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-regs.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-tm27.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl111-fb.h
diff --git a/bsps/arm/imx/include/bsp/irq.h b/bsps/arm/imx/include/bsp/irq.h
index 78b48e1613..1eea075bdc 100644
--- a/bsps/arm/imx/include/bsp/irq.h
+++ b/bsps/arm/imx/include/bsp/irq.h
@@ -20,7 +20,7 @@
 #include 
 #include 
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/imx/include/tm27.h b/bsps/arm/imx/include/tm27.h
index c17c0107b4..982ea594be 100644
--- a/bsps/arm/imx/include/tm27.h
+++ b/bsps/arm/imx/include/tm27.h
@@ -19,6 +19,6 @@
 #ifndef __tm27_h
 #define __tm27_h
 
-#include 
+#include 
 
 #endif /* __tm27_h */
diff --git a/bsps/arm/include/bsp/arm-a9mpcore-start.h 
b/bsps/arm/include/bsp/arm-a9mpcore-start.h
index 8423e64e9d..a03bc8fb33 100644
--- a/bsps/arm/include/bsp/arm-a9mpcore-start.h
+++ b/bsps/arm/include/bsp/arm-a9mpcore-start.h
@@ -31,7 +31,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/realview-pbx-a9/include/bsp/irq.h 
b/bsps/arm/realview-pbx-a9/include/bsp/irq.h
index e66bf41df4..270ecd33ae 100644
--- a/bsps/arm/realview-pbx-a9/include/bsp/irq.h
+++ b/bsps/arm/realview-pbx-a9/include/bsp/irq.h
@@ -29,7 +29,7 @@
 #include 
 
 #include 
-#include 
+#include 
 
 /**
  * @defgroup realview-pbx-a9_interrupt Interrrupt Support
diff --git a/bsps/arm/realview-pbx-a9/include/tm27.h 
b/bsps/arm/realview-pbx-a9/include/tm27.h
index ae148aacdd..ecc0dc4c32 100644
--- a/bsps/arm/realview-pbx-a9/include/tm27.h

[PATCH v3 06/10] bsps/arm: Break out linker script for AArch64

2020-10-03 Thread Kinsey Moore

This breaks out the common section of the ARM linker script that is
usable by AArch64 BSPs to avoid duplication of the vast majority. To do
so, it was necessary to add a new linker path at bsps/shared/start.
---
 bsps/arm/shared/start/linkcmds.base  | 381 +---
 bsps/shared/start/linkcmds-aarch.base| 420 +++
 spec/build/bsps/arm/grp.yml  |   1 +
 spec/build/bsps/optldflagsbsp.yml|   1 +
 testsuites/aclocal/rtems-bsp-linkcmds.m4 |   2 +
 testsuites/automake/compile.am   |   1 +
 6 files changed, 426 insertions(+), 380 deletions(-)
 create mode 100644 bsps/shared/start/linkcmds-aarch.base

diff --git a/bsps/arm/shared/start/linkcmds.base 
b/bsps/arm/shared/start/linkcmds.base
index 1f5f1ef959..d0c88f50d8 100644
--- a/bsps/arm/shared/start/linkcmds.base
+++ b/bsps/arm/shared/start/linkcmds.base
@@ -24,19 +24,10 @@ OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", 
"elf32-littlearm")
 
 OUTPUT_ARCH (arm)
 
-ENTRY (_start)
-STARTUP (start.o)
-
 /*
  * Global symbols that may be defined externally
  */
 
-bsp_vector_table_size = DEFINED (bsp_vector_table_size) ? 
bsp_vector_table_size : 64;
-
-bsp_section_xbarrier_align = DEFINED (bsp_section_xbarrier_align) ? 
bsp_section_xbarrier_align : 1;
-bsp_section_robarrier_align = DEFINED (bsp_section_robarrier_align) ? 
bsp_section_robarrier_align : 1;
-bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? 
bsp_section_rwbarrier_align : 1;
-
 bsp_stack_align = DEFINED (bsp_stack_align) ? bsp_stack_align : 8;
 
 bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 0;
@@ -48,374 +39,4 @@ bsp_stack_fiq_size = ALIGN (bsp_stack_fiq_size, 
bsp_stack_align);
 bsp_stack_und_size = DEFINED (bsp_stack_und_size) ? bsp_stack_und_size : 0;
 bsp_stack_und_size = ALIGN (bsp_stack_und_size, bsp_stack_align);
 
-bsp_stack_hyp_size = DEFINED (bsp_stack_hyp_size) ? bsp_stack_hyp_size : 0;
-bsp_stack_hyp_size = ALIGN (bsp_stack_hyp_size, bsp_stack_align);
-
-MEMORY {
-   UNEXPECTED_SECTIONS : ORIGIN = 0x, LENGTH = 0
-}
-
-SECTIONS {
-   .start : ALIGN_WITH_INPUT {
-   bsp_section_start_begin = .;
-   KEEP (*(.bsp_start_text))
-   KEEP (*(.bsp_start_data))
-   bsp_section_start_end = .;
-   } > REGION_START AT > REGION_START
-   bsp_section_start_size = bsp_section_start_end - 
bsp_section_start_begin;
-
-   .xbarrier : ALIGN_WITH_INPUT {
-   . = ALIGN (bsp_section_xbarrier_align);
-   } > REGION_VECTOR AT > REGION_VECTOR
-
-   .text : ALIGN_WITH_INPUT {
-   bsp_section_text_begin = .;
-   *(.text.unlikely .text.*_unlikely)
-   *(.text .stub .text.* .gnu.linkonce.t.*)
-   /* .gnu.warning sections are handled specially by elf32.em.  */
-   *(.gnu.warning)
-   *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)
-   } > REGION_TEXT AT > REGION_TEXT_LOAD
-   .init : ALIGN_WITH_INPUT {
-   KEEP (*(.init))
-   } > REGION_TEXT AT > REGION_TEXT_LOAD
-   .fini : ALIGN_WITH_INPUT {
-   KEEP (*(.fini))
-   bsp_section_text_end = .;
-   } > REGION_TEXT AT > REGION_TEXT_LOAD
-   bsp_section_text_size = bsp_section_text_end - bsp_section_text_begin;
-   bsp_section_text_load_begin = LOADADDR (.text);
-   bsp_section_text_load_end = bsp_section_text_load_begin + 
bsp_section_text_size;
-
-   .robarrier : ALIGN_WITH_INPUT {
-   . = ALIGN (bsp_section_robarrier_align);
-   } > REGION_RODATA AT > REGION_RODATA
-
-   .rodata : ALIGN_WITH_INPUT {
-   bsp_section_rodata_begin = .;
-   *(.rodata .rodata.* .gnu.linkonce.r.*)
-   } > REGION_RODATA AT > REGION_RODATA_LOAD
-   .rodata1 : ALIGN_WITH_INPUT {
-   *(.rodata1)
-   } > REGION_RODATA AT > REGION_RODATA_LOAD
-   .ARM.extab : ALIGN_WITH_INPUT {
-   *(.ARM.extab* .gnu.linkonce.armextab.*)
-   } > REGION_RODATA AT > REGION_RODATA_LOAD
-   .ARM.exidx : ALIGN_WITH_INPUT {
-   __exidx_start = .;
-   *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-   __exidx_end = .;
-   } > REGION_RODATA AT > REGION_RODATA_LOAD
-   .eh_frame : ALIGN_WITH_INPUT {
-   KEEP (*(.eh_frame))
-   } > REGION_RODATA AT > REGION_RODATA_LOAD
-   .gcc_except_table : ALIGN_WITH_INPUT {
-   *(.gcc_except_table .gcc_except_table.*)
-   } > REGION_RODATA AT > REGION_RODATA_LOAD
-   .tdata : ALIGN_WITH_INPUT {
-   _TLS_Data_begin = .;
-   *(.tdata .tdata.* .gnu.linkonce.td.*)
-   _TLS_Data_end = .;
-   } > REGION_RODATA AT > REGION_RODATA_LOAD
-   .tbss : ALIGN_WITH_INPUT {
-   _TLS_BSS_begin = .;
-   *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
-   _TLS_BSS_end = .;
-   } > REGION_RODATA AT > REGION_RODAT

[PATCH v3 08/10] score: Add AArch64 port

2020-10-03 Thread Kinsey Moore

This adds a CPU port for AArch64(ARMv8) with support for exceptions and
interrupts.
---
 cpukit/include/rtems/score/tls.h  |   6 +-
 .../cpu/aarch64/aarch64-context-validate.S| 305 ++
 .../aarch64-context-volatile-clobber.S| 100 
 .../cpu/aarch64/aarch64-exception-default.S   | 490 
 .../cpu/aarch64/aarch64-exception-default.c   |  50 ++
 .../aarch64/aarch64-exception-frame-print.c   | 108 
 .../cpu/aarch64/aarch64-exception-interrupt.S | 322 ++
 .../score/cpu/aarch64/aarch64-thread-idle.c   |  47 ++
 cpukit/score/cpu/aarch64/cpu.c| 197 +++
 cpukit/score/cpu/aarch64/cpu_asm.S| 134 +
 .../cpu/aarch64/include/libcpu/vectors.h  | 100 
 cpukit/score/cpu/aarch64/include/rtems/asm.h  |  89 +++
 .../cpu/aarch64/include/rtems/score/aarch64.h |  83 +++
 .../cpu/aarch64/include/rtems/score/cpu.h | 554 ++
 .../cpu/aarch64/include/rtems/score/cpu_irq.h |  50 ++
 .../aarch64/include/rtems/score/cpuatomic.h   |  42 ++
 .../cpu/aarch64/include/rtems/score/cpuimpl.h |  83 +++
 spec/build/cpukit/cpuaarch64.yml  |  36 ++
 spec/build/cpukit/librtemscpu.yml |   2 +
 19 files changed, 2797 insertions(+), 1 deletion(-)
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-context-validate.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-context-volatile-clobber.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-default.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-default.c
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-interrupt.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-thread-idle.c
 create mode 100644 cpukit/score/cpu/aarch64/cpu.c
 create mode 100644 cpukit/score/cpu/aarch64/cpu_asm.S
 create mode 100644 cpukit/score/cpu/aarch64/include/libcpu/vectors.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/asm.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/aarch64.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpu_irq.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpuatomic.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
 create mode 100644 spec/build/cpukit/cpuaarch64.yml

diff --git a/cpukit/include/rtems/score/tls.h b/cpukit/include/rtems/score/tls.h
index 65a49d87be..57063990e7 100644
--- a/cpukit/include/rtems/score/tls.h
+++ b/cpukit/include/rtems/score/tls.h
@@ -85,7 +85,11 @@ typedef struct TLS_Thread_control_block {
   struct TLS_Thread_control_block *tcb;
 #else /* !__i386__ */
   TLS_Dynamic_thread_vector *dtv;
-#if CPU_SIZEOF_POINTER == 4
+/*
+ * GCC under AArch64/LP64 expects a 16 byte TCB at the beginning of the TLS
+ * data segment and indexes into it accordingly for TLS variable addresses.
+ */
+#if CPU_SIZEOF_POINTER == 4 || defined(AARCH64_MULTILIB_ARCH_V8)
   uintptr_t reserved;
 #endif
 #endif /* __i386__ */
diff --git a/cpukit/score/cpu/aarch64/aarch64-context-validate.S 
b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
new file mode 100644
index 00..31c8d5571c
--- /dev/null
+++ b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUAArch64
+ *
+ * @brief Implementation of _CPU_Context_validate
+ *
+ * This file implements _CPU_Context_validate for use in spcontext01.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF A

[PATCH v3 05/10] bsps/shared: Add PSCI-based bspreset implementation

2020-10-03 Thread Kinsey Moore

This adds a bsp_reset implementation based on the ARM PSCI
specification often present in ARMv8 systems.
---
 bsps/shared/start/bspreset-arm-psci.c | 56 +++
 1 file changed, 56 insertions(+)
 create mode 100644 bsps/shared/start/bspreset-arm-psci.c

diff --git a/bsps/shared/start/bspreset-arm-psci.c 
b/bsps/shared/start/bspreset-arm-psci.c
new file mode 100644
index 00..215be5c9b5
--- /dev/null
+++ b/bsps/shared/start/bspreset-arm-psci.c
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsShared
+ *
+ * @brief PSCI-based BSP reset hook.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+void bsp_reset(void)
+{
+   uint32_t PSCI_FN_SYSTEM_RESET = 0x8409;
+   __asm__ volatile(
+#if defined(AARCH64_MULTILIB_ARCH_V8) || 
defined(AARCH64_MULTILIB_ARCH_V8_ILP32)
+   "mov x0, %0\n"
+#else
+   "mov r0, %0\n"
+#endif
+#ifdef BSP_RESET_SMC
+   "smc #0\n"
+#else
+   "hvc #0\n"
+#endif
+   : : "r" (PSCI_FN_SYSTEM_RESET)
+   );
+}
-- 
2.20.1

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[PATCH v3 10/10] bsps: Add Cortex-A53 ILP32 BSP variant

2020-10-03 Thread Kinsey Moore

This adds an AArch64 ILP32 BSP variant based on Qemu's Cortex-A53
emulation with interrupt support using GICv3 and clock support using
the ARM GPT.
---
 bsps/aarch64/shared/start/start.S | 16 +
 spec/build/bsps/aarch64/a53/abi.yml   |  7 +-
 .../bsps/aarch64/a53/bspa53ilp32qemu.yml  | 19 +
 .../build/bsps/aarch64/a53/linkcmds_ilp32.yml | 71 +++
 4 files changed, 112 insertions(+), 1 deletion(-)
 create mode 100644 spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml
 create mode 100644 spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml

diff --git a/bsps/aarch64/shared/start/start.S 
b/bsps/aarch64/shared/start/start.S
index f60e840137..f4c62b2b6c 100644
--- a/bsps/aarch64/shared/start/start.S
+++ b/bsps/aarch64/shared/start/start.S
@@ -101,19 +101,31 @@ _start:
  * Get current per-CPU control and store it in PL1 only Thread ID
  * Register (TPIDRPRW).
  */
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w1, =_Per_CPU_Information
+#else
ldr x1, =_Per_CPU_Information
+#endif
add x1, x1, x7, asl #PER_CPU_CONTROL_SIZE_LOG2
mcr p15, 0, x1, c13, c0, 4
 
 #endif
 
/* Calculate interrupt stack area end for current processor */
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w1, =_ISR_Stack_size
+#else
ldr x1, =_ISR_Stack_size
+#endif
 #ifdef RTEMS_SMP
add x3, x7, #1
mul x1, x1, x3
 #endif
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w2, =_ISR_Stack_area_begin
+#else
ldr x2, =_ISR_Stack_area_begin
+#endif
add x3, x1, x2
 
/* Save original DAIF value */
@@ -135,7 +147,11 @@ _start:
 * Normal operation for RTEMS on AArch64 uses SPx and runs on EL1
 * Exception operation (synchronous errors, IRQ, FIQ, System Errors) 
uses SP0
*/
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w1, =bsp_stack_exception_size
+#else
ldr x1, =bsp_stack_exception_size
+#endif
/* Switch to SP0 and set exception stack */
msr spsel, #0
mov sp, x3
diff --git a/spec/build/bsps/aarch64/a53/abi.yml 
b/spec/build/bsps/aarch64/a53/abi.yml
index 894839aa24..b65c10981e 100644
--- a/spec/build/bsps/aarch64/a53/abi.yml
+++ b/spec/build/bsps/aarch64/a53/abi.yml
@@ -8,7 +8,12 @@ copyrights:
 - Copyright (C) 2020 On-Line Applications Research (OAR)
 default:
 - -mcpu=cortex-a53
-default-by-variant: []
+default-by-variant:
+- value:
+  - -mcpu=cortex-a53
+  - -mabi=ilp32
+  variants:
+  - aarch64/a53_ilp32_qemu
 enabled-by: true
 links: []
 name: ABI_FLAGS
diff --git a/spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml 
b/spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml
new file mode 100644
index 00..019e97fcb3
--- /dev/null
+++ b/spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: aarch64
+bsp: a53_ilp32_qemu
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2020 On-Line Applications Research (OAR)
+cppflags: []
+enabled-by: true
+family: a53
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: grp
+- role: build-dependency
+  uid: linkcmds_ilp32
+source: []
+type: build
diff --git a/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml 
b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
new file mode 100644
index 00..ed585f1950
--- /dev/null
+++ b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
@@ -0,0 +1,71 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: config-file
+content: |
+  /*
+   * SPDX-License-Identifier: BSD-2-Clause
+   *
+   * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+   * Written by Kinsey Moore 
+   *
+   * Redistribution and use in source and binary forms, with or without
+   * modification, are permitted provided that the following conditions
+   * are met:
+   * 1. Redistributions of source code must retain the above copyright
+   *notice, this list of conditions and the following disclaimer.
+   * 2. Redistributions in binary form must reproduce the above copyright
+   *notice, this list of conditions and the following disclaimer in the
+   *documentation and/or other materials provided with the distribution.
+   *
+   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
IS"
+   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE

[PATCH v3 09/10] bsps: Add Cortex-A53 LP64 basic BSP

2020-10-03 Thread Kinsey Moore

This adds an AArch64 basic BSP based on Qemu's Cortex-A53 emulation with
interrupt support using GICv3 and clock support using the ARM GPT.
---
 bsps/aarch64/a53/console/console.c|  69 ++
 bsps/aarch64/a53/include/bsp.h|  74 +++
 bsps/aarch64/a53/include/bsp/irq.h|  67 ++
 bsps/aarch64/a53/include/tm27.h   |  46 ++
 bsps/aarch64/a53/start/bspstart.c |  49 ++
 bsps/aarch64/a53/start/bspstarthooks.c|  50 ++
 bsps/aarch64/include/bsp/linker-symbols.h | 161 +
 bsps/aarch64/include/bsp/start.h  | 189 ++
 bsps/aarch64/shared/cache/cache.c | 616 ++
 .../shared/clock/arm-generic-timer-aarch64.c  | 110 
 .../shared/irq/irq-arm-gicv3-aarch64.c|  64 ++
 bsps/aarch64/shared/start/linkcmds.base   |  46 ++
 bsps/aarch64/shared/start/start.S | 219 +++
 spec/build/bsps/aarch64/a53/abi.yml   |  17 +
 .../build/bsps/aarch64/a53/bspa53lp64qemu.yml |  19 +
 spec/build/bsps/aarch64/a53/grp.yml   |  42 ++
 spec/build/bsps/aarch64/a53/linkcmds_lp64.yml |  71 ++
 spec/build/bsps/aarch64/a53/obj.yml   |  37 ++
 spec/build/bsps/aarch64/a53/optloadoff.yml|  18 +
 spec/build/bsps/aarch64/a53/optnocachelen.yml |  18 +
 spec/build/bsps/aarch64/a53/optramlen.yml |  18 +
 spec/build/bsps/aarch64/a53/optramori.yml |  18 +
 spec/build/bsps/aarch64/a53/tsta53.yml|  44 ++
 spec/build/bsps/aarch64/grp.yml   |  25 +
 spec/build/bsps/aarch64/start.yml |  14 +
 25 files changed, 2101 insertions(+)
 create mode 100644 bsps/aarch64/a53/console/console.c
 create mode 100644 bsps/aarch64/a53/include/bsp.h
 create mode 100644 bsps/aarch64/a53/include/bsp/irq.h
 create mode 100644 bsps/aarch64/a53/include/tm27.h
 create mode 100644 bsps/aarch64/a53/start/bspstart.c
 create mode 100644 bsps/aarch64/a53/start/bspstarthooks.c
 create mode 100644 bsps/aarch64/include/bsp/linker-symbols.h
 create mode 100644 bsps/aarch64/include/bsp/start.h
 create mode 100644 bsps/aarch64/shared/cache/cache.c
 create mode 100644 bsps/aarch64/shared/clock/arm-generic-timer-aarch64.c
 create mode 100644 bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c
 create mode 100644 bsps/aarch64/shared/start/linkcmds.base
 create mode 100644 bsps/aarch64/shared/start/start.S
 create mode 100644 spec/build/bsps/aarch64/a53/abi.yml
 create mode 100644 spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
 create mode 100644 spec/build/bsps/aarch64/a53/grp.yml
 create mode 100644 spec/build/bsps/aarch64/a53/linkcmds_lp64.yml
 create mode 100644 spec/build/bsps/aarch64/a53/obj.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optloadoff.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optnocachelen.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optramlen.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optramori.yml
 create mode 100644 spec/build/bsps/aarch64/a53/tsta53.yml
 create mode 100644 spec/build/bsps/aarch64/grp.yml
 create mode 100644 spec/build/bsps/aarch64/start.yml

diff --git a/bsps/aarch64/a53/console/console.c 
b/bsps/aarch64/a53/console/console.c
new file mode 100644
index 00..1854909c98
--- /dev/null
+++ b/bsps/aarch64/a53/console/console.c
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64A53
+ *
+ * @brief Console Configuration
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+arm_pl011_context a53_qemu_vpl011_context = {
+  .base = RTEMS_TERMIOS_DEV

[PATCH v3 07/10] spmsgq_err01: Use correct max values and fix 64bit

2020-10-03 Thread Kinsey Moore

Fix spmsgq_err01 on systems with 64-bit pointers and correct max value
mismatches and inaccuracies that are more noticable on 64-bit systems.
---
 testsuites/sptests/spmsgq_err01/init.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/testsuites/sptests/spmsgq_err01/init.c 
b/testsuites/sptests/spmsgq_err01/init.c
index c68d30da16..9a6a8855be 100644
--- a/testsuites/sptests/spmsgq_err01/init.c
+++ b/testsuites/sptests/spmsgq_err01/init.c
@@ -101,7 +101,7 @@ rtems_task Init(
   /* not enough memory for messages */
   status = rtems_message_queue_create(
 Queue_name[ 1 ],
-SIZE_MAX / ( sizeof( uintptr_t ) + sizeof( CORE_message_queue_Buffer ) ),
+UINT_MAX / ( sizeof( uintptr_t ) + sizeof( CORE_message_queue_Buffer ) ),
 1,
 RTEMS_DEFAULT_ATTRIBUTES,
 &Queue_id[ 1 ]
@@ -116,8 +116,8 @@ rtems_task Init(
   /* too large a request for messages */
   status = rtems_message_queue_create(
 Queue_name[ 1 ],
-INT_MAX,
-INT_MAX,
+UINT_MAX,
+SIZE_MAX - sizeof( uintptr_t ) + 1 - sizeof( CORE_message_queue_Buffer ),
 RTEMS_DEFAULT_ATTRIBUTES,
 &Queue_id[ 1 ]
   );
-- 
2.20.1

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[PATCH v3 2/2] Add AArch64 documentation

2020-10-03 Thread Kinsey Moore

---
 cpu-supplement/aarch64.rst | 134 +
 user/bsps/aarch64/a53.rst  |  26 +++
 user/bsps/bsps-aarch64.rst |   2 +-
 3 files changed, 161 insertions(+), 1 deletion(-)
 create mode 100644 cpu-supplement/aarch64.rst
 create mode 100644 user/bsps/aarch64/a53.rst

diff --git a/cpu-supplement/aarch64.rst b/cpu-supplement/aarch64.rst
new file mode 100644
index 000..178ea10
--- /dev/null
+++ b/cpu-supplement/aarch64.rst
@@ -0,0 +1,134 @@
+.. SPDX-License-Identifier: CC-BY-SA-4.0
+
+.. Copyright (C) 1988, 2020 On-Line Applications Research Corporation (OAR)
+
+AArch64 Specific Information
+
+
+This chapter discusses the dependencies of the
+*ARM AArch64 architecture*
+(https://en.wikipedia.org/wiki/ARM_architecture#AArch64_features) in this port
+of RTEMS.  The ARMv8-A versions are supported by RTEMS.  Processors with a MMU
+use a static configuration which is set up during system start.  SMP is not
+supported.
+
+**Architecture Documents**
+
+For information on the ARM AArch64 architecture refer to the *ARM Infocenter*
+(http://infocenter.arm.com/).
+
+CPU Model Dependent Features
+
+
+This section presents the set of features which vary across ARM AArch64
+implementations and are of importance to RTEMS.  The set of CPU model feature
+macros are defined in the file 
:file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
+based upon the particular CPU model flags specified on the compilation command
+line.
+
+CPU Model Name
+--
+
+The macro ``CPU_MODEL_NAME`` is a string which designates the architectural
+level of this CPU model.  See in 
:file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
+for the values.
+
+Floating Point Unit and SIMD
+
+
+The Advanced SIMD (NEON) and Floating-point instruction set extension is
+supported and expected to be present since all ARMv8-A CPUs are expected to
+support it as per the *ARMv8-A Programmer's Guide Chapter 7 introduction*
+(https://developer.arm.com/docs/den0024/a/aarch64-floating-point-and-neon). As
+such, ``CPU_HARDWARE_FP`` will always be set to ``TRUE``.
+
+Multilibs
+=
+
+The following multilib variants are available:
+
+#. ``ILP32``: AArch64 instruction set and registers using 32bit long int and 
pointers
+
+#. ``LP64``: AArch64 instruction set and registers using 64bit long int and 
pointers
+
+Use for example the following GCC options:
+
+.. code-block:: shell
+
+-mcpu=cortex-a53 -mabi=ilp32
+
+to build an application or BSP for the ARMv8-A architecture and tune the code
+for a Cortex-A53 processor.  It is important to select the correct ABI.
+
+Calling Conventions
+===
+
+Please refer to the *Procedure Call Standard for the ARM 64-bit Architecture*
+(https://github.com/ARM-software/abi-aa/releases/download/2019Q4/aapcs64.pdf).
+
+Memory Model
+
+
+A flat 64-bit or 32-bit memory model is supported depending on the selected 
multilib
+variant.  All AArch64 CPU variants support a built-in MMU for which basic 
initialization
+for a flat memory model is handled.
+
+Interrupt Processing
+
+
+The Reset Vector is determined using RVBAR and is Read-Only. RVBAR is set using
+configuration signals only sampled at reset.  The ARMv8 architecture has four
+exception types: 
+
+- Synchronous Exception
+
+- Interrupt (IRQ)
+
+- Fast Interrupt (FIQ)
+
+- System Error Exception
+
+Of these types only the synchronous and IRQ exceptions have explicit operating
+system support.  It is intentional that the FIQ is not supported by the 
operating
+system.  Without operating system support for the FIQ it is not necessary to
+disable them during critical sections of the system.
+
+Interrupt Levels
+
+
+There are exactly two interrupt levels on ARMv8 with respect to RTEMS.  Level
+zero corresponds to interrupts enabled.  Level one corresponds to interrupts
+disabled.
+
+Interrupt Stack
+---
+
+The board support package must initialize the interrupt stack. The memory for
+the stacks is usually reserved in the linker script.
+
+Default Fatal Error Processing
+==
+
+The default fatal error handler for this architecture performs the following
+actions:
+
+- disables operating system supported interrupts (IRQ),
+
+- places the error code in ``x0``, and
+
+- executes an infinite loop to simulate a halt processor instruction.
+
+Symmetric Multiprocessing
+=
+
+SMP is not currently supported on ARMv8-A.
+
+Thread-Local Storage
+
+
+Thread-local storage (TLS) is supported. AArch64 uses unmodified TLS variant I
+which is not explcitly stated, but can be inferred from the behavior of GCC and
+*Addenda to, and Errata in, the ABI for the Arm® Architecture*
+(https://developer.arm.com/documentation/ihi0045/g). This alters expectations
+for the size of the TLS Thread Control Block (TCB) such that, under the LP64

[PATCH v3 1/2] cpu-supplement: Fix formatting and missing words

2020-10-03 Thread Kinsey Moore

---
 cpu-supplement/arm.rst | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/cpu-supplement/arm.rst b/cpu-supplement/arm.rst
index 63aa532..ac9e8c6 100644
--- a/cpu-supplement/arm.rst
+++ b/cpu-supplement/arm.rst
@@ -34,10 +34,10 @@ for the values.
 Count Leading Zeroes Instruction
 
 
-The ARMv5 and later has the count leading zeroes ``clz`` instruction which
-could be used to speed up the find first bit operation.  The use of this
-instruction should significantly speed up the scheduling associated with a
-thread blocking.  This is currently not used.
+The ARMv5 and later instruction sets have the count leading zeroes ``clz``
+instruction which could be used to speed up the find first bit operation. The
+use of this instruction should significantly speed up the scheduling associated
+with a thread blocking.  This is currently not used.
 
 Floating Point Unit
 ---
@@ -130,7 +130,7 @@ Memory Model
 
 
 A flat 32-bit memory model is supported.  The board support package must take
-care about the MMU if necessary.
+care of initializing the MMU if necessary.
 
 Interrupt Processing
 
@@ -194,13 +194,13 @@ actions:
 Symmetric Multiprocessing
 =
 
-SMP is supported on ARMv7-A.  Available platforms are
+SMP is supported on ARMv7-A.  Available platforms are:
 
-- Altera Cyclone V,
+- Altera Cyclone V
 
-- NXP i.MX 7, and
+- NXP i.MX 7
 
-- Xilinx Zynq.
+- Xilinx Zynq
 
 Thread-Local Storage
 
-- 
2.20.1

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Re: [PATCH v4] cpukit/librcxx: Add a C++ thread interface with attributes

Re: Interest in Virtual RTEMS Workshop

Re: Interest in Virtual RTEMS Workshop

Re: Interest in Virtual RTEMS Workshop

[PATCH v3 02/10] spec: Add missing spintrcritical24 definition

[PATCH v3 03/10] bsps: Break out AArch32 portions of GPT driver

[PATCH v3 01/10] Move ARM PL011 UART driver

[PATCH v3 04/10] bsps: Break out AArch32 GICv3 support

[PATCH v3 06/10] bsps/arm: Break out linker script for AArch64

[PATCH v3 08/10] score: Add AArch64 port

[PATCH v3 05/10] bsps/shared: Add PSCI-based bspreset implementation

[PATCH v3 10/10] bsps: Add Cortex-A53 ILP32 BSP variant

[PATCH v3 09/10] bsps: Add Cortex-A53 LP64 basic BSP

[PATCH v3 07/10] spmsgq_err01: Use correct max values and fix 64bit

[PATCH v3 2/2] Add AArch64 documentation

[PATCH v3 1/2] cpu-supplement: Fix formatting and missing words

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