Re: [PATCH v3] doc/raspberrypi: Added instructions for raspberrypi
On Wed, Jan 22, 2020 at 6:27 AM Niteesh wrote:
> On Wed, Jan 22, 2020 at 2:30 AM Christian Mauderer
> wrote:
>
>> Hello Niteesh,
>>
>> you had two different "v3" patches. Therefore I missed this one. I
>> thought there was still a review comment from Gedare pending (which he
>> added at the v2 patch but after the first v3 has been sent).
>
>
> I have added instruction about installing QEMU from RSB as he said.
>
>
>
> On 12/01/2020 19:47, G S Niteesh wrote:
>> > Added instructions to run examples on raspberrypi.
>> > ---
>> > user/bsps/arm/raspberrypi.rst | 85 ++-
>> > 1 file changed, 84 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/user/bsps/arm/raspberrypi.rst
>> b/user/bsps/arm/raspberrypi.rst
>> > index 4ef75bd..8e4b38c 100644
>> > --- a/user/bsps/arm/raspberrypi.rst
>> > +++ b/user/bsps/arm/raspberrypi.rst
>> > @@ -5,4 +5,87 @@
>> > raspberrypi
>> > ===
>> >
>> > -TODO.
>> > +This BSP supports `Raspberry Pi 1` and `Raspberry Pi 2` currently.
>> > +The support for `Raspberry Pi 3` is work under progress.
>> > +The default bootloader on the Raspberry Pi which is used to boot
>> Raspbian
>> > +or other OS can be also used to boot RTEMS. U-boot can also be used.
>> > +
>> > +Setup SD card
>> > +
>> > +
>> > +The Raspberry Pis have an unconventional booting mechanism. The GPU
>> > +boots first, initializes itself, runs the bootloader and starts the
>> CPU.
>> > +The bootloader looks for a kernel image, by default the kernel images
>> must
>> > +have a name of the form ``kernel*.img`` but this can be changed by
>> adding
>> > +`kernel=` to ``config.txt``.
>> > +
>> > +You must provide the required files for the GPU to proceed. These files
>> > +can be downloaded from
>> > +`the Raspberry Pi Firmware Repository <
>> https://github.com/raspberrypi/firmware/tree/master/boot>`_.
>> > +You can remove the ``kernel*.img`` files if you want too, but don't
>> touch the other files.
>>
>> This line seems a bit long. Please break at 80 chars. The link above it
>> is OK to violate that rule because it would most likely not work with a
>> line break.
>>
>> > +
>> > +Copy these files in to a SD card with FAT filesystem.
>> > +
>> > +Kernel image
>> > +
>> > +
>> > +The following steps show how to run ``hello.exe`` on a Raspberry Pi 2.
>> > +The same instructions can be applied to Raspberry Pi 1 also.
>> > +Other executables can be processed in a similar way.
>> > +
>> > +To create the kernel image:
>> > +
>> > +.. code-block:: none
>> > +
>> > + arm-rtems5-objcopy -Obinary hello.exe kernel.img
>> > +
>> > +Copy the kernel image to the SD card.
>> > +
>> > +Make sure you have these lines below, in your ``config.txt``.
>> > +
>> > +.. code-block:: none
>> > +
>> > + enable-uart=1
>> > + kernel_address=0x20
>> > + kernel=kernel.img
>> > +
>> > +Testing using QEMU
>> > +--
>> > +
>> > +QEMU can be built using RSB. Navigate to ``/rtems``
>> > +and run this command.
>> > +
>> > +.. code-block:: none
>> > +
>> > + ../source-builder/sb-set-builder --prefix=
>> devel/qemu4.bset
>> > +
>> > +**Note**: Replace and
>> with the correct
>> > +path of the directories. For example, if you used quick-start section
>> as your reference, these
>> > +two will be ``$HOME/quick-start/src/rsb`` and
>> ``$HOME/quick-start/rtems/5`` respectively,
>>
>> Again: Please use a 80 char limit (except for the code block).
>>
>> > +
>> > +QEMU along with GDB can be used for debugging, but it only supports
>> > +Raspberry Pi 2 and the emulation is also incomplete. So some of the
>> > +features might not work as expected.
>> > +
>> > +Make sure your version of QEMU > v2.6, because older ones don't support
>>
>> "...of QEMU is newer than v2.6 ..."
>>
>> For most readers it's much faster to read a text without cryptic
>> abbreviations.
>>
>> > +Raspberry Pi's.
>>
>> I have to be honest: I'm not sure here. As far as I know the apostroph
>> (') is a sign that you left something out. I'm not sure whether there
>> are cases in English where you use it other than that case. But I would
>> say that you didn't leave anything out in "Pi's" and therefore the
>> plural should be "Pis" even if it looks odd.
>
> Some comment from a native speaker?
>
>
Any update on this? As I have said, I added instructions for passing DTB
file, I will
send the patch once this issue is resolved.
>
>
> And we also have to add instructions for including the DTB file. I'll make
> the
> changes you mentioned and also add instructions for including DTB.
> I'll send in the patch, once we get a confirmation from a native speaker,
> anyhow
> I googled, and I think it should be Pis. The *'s *symbolizes
> possessiveness.
>
>>
>> > +
>> > +.. code-block:: none
>> > +
>> > + qemu-system-arm -M raspi2 -m 1G -kernel hello.exe -serial
>> mon:stdio -nographic -S -s
>> > +
>> > +This starts QEMU and creates a socket at port ``localhost:1234`` for
>> GDB to
>> > +connect
Re: [PATCH v3] doc/raspberrypi: Added instructions for raspberrypi
On 23/01/2020 14:41, Niteesh wrote:
> > +Raspberry Pi's.
>
> I have to be honest: I'm not sure here. As far as I know the
> apostroph
> (') is a sign that you left something out. I'm not sure whether
> there
> are cases in English where you use it other than that case. But
> I would
> say that you didn't leave anything out in "Pi's" and therefore the
> plural should be "Pis" even if it looks odd.
>
> Some comment from a native speaker?
>
>
> Any update on this? As I have said, I added instructions for passing DTB
> file, I will
> send the patch once this issue is resolved.
Let's solve it with another method:
https://www.raspberrypi.org/blog/teaching-pinet/
The official homepage for the RPi uses "Raspberry Pis".
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Herr Christian Mauderer
Dornierstr. 4
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Germany
email: christian.maude...@embedded-brains.de
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[PATCH] bsps/arm: Update GICv3 to use newer affinity interface
The GICv3 implementation uses the GICD_ITARGETSR register to configure
interrupt affinity. The GIC uses this register only when affinity
routing is disabled, which is called legacy operation mode. However,
affinity routing is being enabled, by setting the ARE_NS bit in the
GICD_CTLR register; therefore GICD_ITARGETSR will be ignored.
While affinity routing could be disabled, this legacy operation mode is
optional for a GIC implementation - it should be avoided.
This change uses the newer affinity register GICD_IROUTER. The register
is 64 bits wide, so any access would need to be performed with two store
operations on a 32 bit RTEMS build. This had to be done with assembly
code, as the compiler optimizer will try to use the 64 bit floating
point store operation VSTM to write to the register. This does not work
with virtual GICD registers on the Xen hypervisor, as the VSTM
instruction data abort does not provide syndrome information.
Affinity routing allows for hierarchical routing of interrupts. To take
advantage of this feature, it would require an understanding of the
processor/core hierarchy. RTEMS specifies the desired processor affinity
with a mask, which does not provide this information. For now, assume
a simple single level routing hierarchy.
Signed-off-by: Jeff Kubascik
---
bsps/arm/include/bsp/arm-gic-regs.h | 15 +++
bsps/arm/shared/irq/irq-gicv3.c | 26 +++---
2 files changed, 38 insertions(+), 3 deletions(-)
diff --git a/bsps/arm/include/bsp/arm-gic-regs.h
b/bsps/arm/include/bsp/arm-gic-regs.h
index 8a65294b6f..13b715a3b1 100644
--- a/bsps/arm/include/bsp/arm-gic-regs.h
+++ b/bsps/arm/include/bsp/arm-gic-regs.h
@@ -151,6 +151,21 @@ typedef struct {
#define GIC_DIST_ICDSGIR_SGIINTID(val) BSP_FLD32(val, 0, 3)
#define GIC_DIST_ICDSGIR_SGIINTID_GET(reg) BSP_FLD32GET(reg, 0, 3)
#define GIC_DIST_ICDSGIR_SGIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
+ uint32_t reserved_f04[5247];
+ uint64_t icdirr[988];
+#define GIC_DIST_ICDIRR_AFF3(val) BSP_FLD64(val, 32, 39)
+#define GIC_DIST_ICDIRR_AFF3_GET(reg) BSP_FLD64GET(val, 32, 39)
+#define GIC_DIST_ICDIRR_AFF3_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39)
+#define GIC_DIST_ICDIRR_INTERRUPT_ROUTING_MODE BSP_BIT64(31)
+#define GIC_DIST_ICDIRR_AFF2(val) BSP_FLD64(val, 16, 23)
+#define GIC_DIST_ICDIRR_AFF2_GET(reg) BSP_FLD64GET(val, 16, 23)
+#define GIC_DIST_ICDIRR_AFF2_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)
+#define GIC_DIST_ICDIRR_AFF1(val) BSP_FLD64(val, 8, 15)
+#define GIC_DIST_ICDIRR_AFF1_GET(reg) BSP_FLD64GET(val, 8, 15)
+#define GIC_DIST_ICDIRR_AFF1_SET(reg, val) BSP_FLD64SET(reg, val, 8, 15)
+#define GIC_DIST_ICDIRR_AFF0(val) BSP_FLD64(val, 0, 7)
+#define GIC_DIST_ICDIRR_AFF0_GET(reg) BSP_FLD64GET(val, 0, 7)
+#define GIC_DIST_ICDIRR_AFF0_SET(reg, val) BSP_FLD64SET(reg, val, 0, 7)
} gic_dist;
/* GICv3 only */
diff --git a/bsps/arm/shared/irq/irq-gicv3.c b/bsps/arm/shared/irq/irq-gicv3.c
index 138b565b9b..1b127fb4a1 100644
--- a/bsps/arm/shared/irq/irq-gicv3.c
+++ b/bsps/arm/shared/irq/irq-gicv3.c
@@ -107,6 +107,12 @@
#define WRITE64_SR(SR_NAME, VALUE) \
__asm__ volatile("mcrr" SR_NAME " \n" : : "r" (VALUE) );
+#define WRITE64_REG(ADDR, VALUE) \
+({ \
+ __asm__ volatile("str %0, [%1, #0]"::"r"(VALUE), "r"(ADDR)); \
+ __asm__ volatile("str %0, [%1, #4]"::"r"(VALUE >> 32), "r"(ADDR)); \
+})
+
#define ARM_GIC_REDIST ((volatile gic_redist *) BSP_ARM_GIC_REDIST_BASE)
#define ARM_GIC_SGI_PPI (((volatile gic_sgi_ppi *)
((char*)BSP_ARM_GIC_REDIST_BASE + (1 << 16
@@ -166,6 +172,16 @@ static inline uint32_t get_id_count(volatile gic_dist
*dist)
return id_count;
}
+static uint64_t cpu_to_affinity(uint32_t cpu)
+{
+ /* CPU logical mapping is not present - keep it simple with a single level
+ routing hierarchy */
+ return (GIC_DIST_ICDIRR_AFF3(0) |
+ GIC_DIST_ICDIRR_AFF2(0) |
+ GIC_DIST_ICDIRR_AFF1(0) |
+ GIC_DIST_ICDIRR_AFF0(cpu));
+}
+
static void init_cpu_interface(void)
{
uint32_t sre_value = 0x7;
@@ -222,7 +238,7 @@ rtems_status_code bsp_interrupt_facility_initialize(void)
}
for (id = 32; id < id_count; ++id) {
-gic_id_set_targets(dist, id, 0x01);
+WRITE64_REG(&dist->icdirr[id-32], cpu_to_affinity(0));
}
init_cpu_interface();
@@ -293,9 +309,13 @@ void bsp_interrupt_set_affinity(
)
{
volatile gic_dist *dist = ARM_GIC_DIST;
- uint8_t targets = (uint8_t) _Processor_mask_To_uint32_t(affinity, 0);
+ uint32_t cpu = _Processor_mask_Find_last_set(affinity);
- gic_id_set_targets(dist, vector, targets);
+ if (vector < 32) {
+/* Affinity doesn't apply to SGIs/PPIs */
+ } else {
+WRITE64_REG(&dist->icdirr[vector-32], cpu_to_affinity(cpu));
+ }
}
void bsp_interrupt_get_affinity(
--
2.17.1
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[PATCH 1/2] bsp/xen: Rename xen_virtual target to xen_gicv2
Rename the xen_virtual target to xen_gicv2, to reflect that this target
is using the GICv2 interrupt controller driver. A RTEMS virtual machine
may be required to use a different interrupt controller driver,
depending on the underlying platform.
---
bsps/arm/xen/config/{xen_virtual.cfg => xen_gicv2.cfg} | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
rename bsps/arm/xen/config/{xen_virtual.cfg => xen_gicv2.cfg} (82%)
diff --git a/bsps/arm/xen/config/xen_virtual.cfg
b/bsps/arm/xen/config/xen_gicv2.cfg
similarity index 82%
rename from bsps/arm/xen/config/xen_virtual.cfg
rename to bsps/arm/xen/config/xen_gicv2.cfg
index 1b5031c3f0..ebb6131693 100644
--- a/bsps/arm/xen/config/xen_virtual.cfg
+++ b/bsps/arm/xen/config/xen_gicv2.cfg
@@ -1,5 +1,5 @@
#
-# Configuration file for the "xen_virtual" target
+# Configuration file for the "xen_gicv2" target
#
include $(RTEMS_ROOT)/make/custom/default.cfg
--
2.17.1
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[PATCH 2/2] bsp/xen: Add xen_gicv3 target
Implement the xen_gicv3 target that uses the GICv3 interrupt controller
driver. This is required for platforms where the underlying processor is
using GICv3 with no legacy operation support.
---
bsps/arm/xen/config/xen_gicv3.cfg | 14 ++
bsps/arm/xen/include/bsp.h| 10 ++
bsps/arm/xen/start/bspstartmmu.c | 14 ++
c/src/lib/libbsp/arm/xen/Makefile.am | 5 +
c/src/lib/libbsp/arm/xen/configure.ac | 10 ++
5 files changed, 53 insertions(+)
create mode 100644 bsps/arm/xen/config/xen_gicv3.cfg
diff --git a/bsps/arm/xen/config/xen_gicv3.cfg
b/bsps/arm/xen/config/xen_gicv3.cfg
new file mode 100644
index 00..d5ca72b43d
--- /dev/null
+++ b/bsps/arm/xen/config/xen_gicv3.cfg
@@ -0,0 +1,14 @@
+#
+# Configuration file for the "xen_gicv3" target
+#
+
+include $(RTEMS_ROOT)/make/custom/default.cfg
+
+RTEMS_CPU = arm
+
+CPU_CFLAGS = -march=armv7-a -mthumb -mfpu=neon -mfloat-abi=hard
+
+CFLAGS_OPTIMIZE_V += -O2 -g
+CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections
+
+LDFLAGS = -Wl,--gc-sections
diff --git a/bsps/arm/xen/include/bsp.h b/bsps/arm/xen/include/bsp.h
index e5b23a902e..13b7592f1e 100644
--- a/bsps/arm/xen/include/bsp.h
+++ b/bsps/arm/xen/include/bsp.h
@@ -58,11 +58,21 @@
extern "C" {
#endif /* __cplusplus */
+#if USE_IRQ_GICV2
#define BSP_ARM_GIC_CPUIF_BASE 0x03002000
#define BSP_ARM_GIC_CPUIF_LENGTH 0x1000
#define BSP_ARM_GIC_DIST_BASE 0x03001000
#define BSP_ARM_GIC_DIST_LENGTH 0x1000
+#endif /* USE_IRQ_GICV2 */
+
+#if USE_IRQ_GICV3
+#define BSP_ARM_GIC_DIST_BASE 0x03001000
+#define BSP_ARM_GIC_DIST_LENGTH 0x1
+
+#define BSP_ARM_GIC_REDIST_BASE 0x0302
+#define BSP_ARM_GIC_REDIST_LENGTH 0x100
+#endif /* USE_IRQ_GICV3 */
#define BSP_ARM_A9MPCORE_SCU_BASE 0
diff --git a/bsps/arm/xen/start/bspstartmmu.c b/bsps/arm/xen/start/bspstartmmu.c
index b24af89d41..6310c37ff1 100644
--- a/bsps/arm/xen/start/bspstartmmu.c
+++ b/bsps/arm/xen/start/bspstartmmu.c
@@ -36,6 +36,7 @@
BSP_START_DATA_SECTION static const arm_cp15_start_section_config
xen_bsp_mmu_config_table[] = {
ARMV7_CP15_START_DEFAULT_SECTIONS,
+#if USE_IRQ_GICV2
{
.begin = BSP_ARM_GIC_DIST_BASE,
.end = BSP_ARM_GIC_DIST_BASE + BSP_ARM_GIC_DIST_LENGTH,
@@ -44,7 +45,20 @@ xen_bsp_mmu_config_table[] = {
.begin = BSP_ARM_GIC_CPUIF_BASE,
.end = BSP_ARM_GIC_CPUIF_BASE + BSP_ARM_GIC_CPUIF_LENGTH,
.flags = ARMV7_MMU_DEVICE
+ },
+#endif /* USE_IRQ_GICV2 */
+#if USE_IRQ_GICV3
+ {
+.begin = BSP_ARM_GIC_DIST_BASE,
+.end = BSP_ARM_GIC_DIST_BASE + BSP_ARM_GIC_DIST_LENGTH,
+.flags = ARMV7_MMU_DEVICE
}, {
+.begin = BSP_ARM_GIC_REDIST_BASE,
+.end = BSP_ARM_GIC_REDIST_BASE + BSP_ARM_GIC_REDIST_LENGTH,
+.flags = ARMV7_MMU_DEVICE
+ },
+#endif /* USE_IRQ_GICV3 */
+ {
.begin = BSP_XEN_VPL011_BASE,
.end = BSP_XEN_VPL011_BASE + BSP_XEN_VPL011_LENGTH,
.flags = ARMV7_MMU_DEVICE
diff --git a/c/src/lib/libbsp/arm/xen/Makefile.am
b/c/src/lib/libbsp/arm/xen/Makefile.am
index fecb665af4..4db0b78649 100644
--- a/c/src/lib/libbsp/arm/xen/Makefile.am
+++ b/c/src/lib/libbsp/arm/xen/Makefile.am
@@ -34,7 +34,12 @@ librtemsbsp_a_SOURCES +=
../../../../../../bsps/arm/shared/clock/clock-generic-t
librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c
# irq
librtemsbsp_a_SOURCES +=
../../../../../../bsps/shared/irq/irq-default-handler.c
+if USE_IRQ_GICV2
librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-gic.c
+endif
+if USE_IRQ_GICV3
+librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-gicv3.c
+endif
# console
librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xen/console/console.c
librtemsbsp_a_SOURCES +=
../../../../../../bsps/shared/dev/serial/console-termios.c
diff --git a/c/src/lib/libbsp/arm/xen/configure.ac
b/c/src/lib/libbsp/arm/xen/configure.ac
index 86ec0033ef..edeaba4e20 100644
--- a/c/src/lib/libbsp/arm/xen/configure.ac
+++ b/c/src/lib/libbsp/arm/xen/configure.ac
@@ -26,6 +26,16 @@ RTEMS_BSPOPTS_HELP([ARM_GENERIC_TIMER_USE_VIRTUAL],[use
virtual ARM generic time
RTEMS_BSPOPTS_SET([ARM_GENERIC_TIMER_UNMASK_AT_TICK],[*],[1])
RTEMS_BSPOPTS_HELP([ARM_GENERIC_TIMER_UNMASK_AT_TICK],[unmask the timer in the
tick handler, since Xen will mask the virtual timer before injecting the
interrupt to the guest])
+RTEMS_BSPOPTS_SET([USE_IRQ_GICV2],[xen_gicv2],[1])
+RTEMS_BSPOPTS_SET([USE_IRQ_GICV2],[*],[0])
+RTEMS_BSPOPTS_HELP([USE_IRQ_GICV2],[use the GICv2 interrupt controller driver])
+AM_CONDITIONAL(USE_IRQ_GICV2,test "$USE_IRQ_GICV2" = "1")
+
+RTEMS_BSPOPTS_SET([USE_IRQ_GICV3],[xen_gicv3],[1])
+RTEMS_BSPOPTS_SET([USE_IRQ_GICV3],[*],[0])
+RTEMS_BSPOPTS_HELP([USE_IRQ_GICV3],[use the GICv3 interrupt controller driver])
+AM_CONDITIONAL(USE_IRQ_GICV3,test "$USE_IRQ_GICV3" = "1")
+
RTEMS_BSPOPTS_SET([BSP_START_ZIMAGE_HEADER],[*],[1])
RTEMS_BSPOPTS_HELP([BSP_START_ZIMAGE_HEADER],[include zImage boot header])
--
2.17.1
__
[PATCH 0/2] Add new Xen BSP target using GICv3 driver
This patch set renames the "xen_virtual" target to "xen_gicv2", and adds a new
"xen_gicv3" target that uses the GICv3 driver. This is the only hardware
dependency I have identified that a RTEMS virtual machine has with Xen on ARMv8.
The "xen_gicv3" target has been confirmed to work with Xen and ARMv8 QEMU. This
required 3 patches to QEMU, which have been submitted to QEMU devel. As of now,
all 3 patches were accepted into master.
Jeff Kubascik (2):
bsp/xen: Rename xen_virtual target to xen_gicv2
bsp/xen: Add xen_gicv3 target
.../xen/config/{xen_virtual.cfg => xen_gicv2.cfg} | 2 +-
bsps/arm/xen/config/xen_gicv3.cfg | 14 ++
bsps/arm/xen/include/bsp.h | 10 ++
bsps/arm/xen/start/bspstartmmu.c | 14 ++
c/src/lib/libbsp/arm/xen/Makefile.am | 5 +
c/src/lib/libbsp/arm/xen/configure.ac | 10 ++
6 files changed, 54 insertions(+), 1 deletion(-)
rename bsps/arm/xen/config/{xen_virtual.cfg => xen_gicv2.cfg} (82%)
create mode 100644 bsps/arm/xen/config/xen_gicv3.cfg
--
2.17.1
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