Re: [GSoC - x86_64] Interrupt manager and and port-specific glue - was Re: [GSoC - x86_64 - automake] Limit CFLAGS to specific source for librtemsbsp.a

[Amaan Cheval]

Hi everyone!

Good news! The APIC timer _does_ work now (after implementing 1GiB
pages)! I see Clock_isr_ticks increasing steadily, though I don't have
tc_get_timecount implemented yet - I've yet to figure out the
specifics of the clock driver (how
rtems_configuration_get_microseconds_per_tick influences the
counter_ticks, specifically).

I suspect we'll barely just make ticker.exe work by EOD tomorrow,
leaving just the weekend for me to clean the patches up and Monday to
actually merge them.

Would someone be willing to have a meeting on Hangouts (or whatever)
with me to speed up the process of (1) upstreaming my patches and (2)
checking that my "work package" looks good enough at any convenient
time on Monday?

(I'm a bit busy on Monday, so I'd really prefer to have this whole
thing done by EOD Monday for me.)

On Thu, Aug 9, 2018 at 7:03 AM, Gedare Bloom  wrote:
> On Wed, Aug 8, 2018 at 12:21 PM, Amaan Cheval  wrote:
>> Status update: The code is at a point where the APIC timer _should_
>> work, but doesn't (it never starts ticking away, so when calibrating
>> with the PIT, and later starting the APIC timer to generate IRQs,
>> pretty much nothing happens).
>>
>> I suspect the cause being the APIC base relocation not working (the
>> APIC is located at 0xfee0 in physical memory by default, and in
>> the code we write to an MSR to relocate it, because the page-mapping
>> scheme FreeBSD setup doesn't let us access such high physical memory -
>> only the first 1GiB of physical memory).
>>
>> On QEMU, the MSR accepts our write for the relocation and happily
>> spits it back out when read, but given the unresponsiveness of the
>> APIC timer despite enabling all the right bits, I suspect it's just a
>> "fake" in that regard (QEMU's "info lapic" doesn't reflect any of our
>> changes to the APIC configuration either, supporting this theory).
>> QEMU _does_ reflect changes to the APIC by other operating systems
>> which don't relocate it, so I don't suspect its emulation being a
>> problem.
>>
>> On VirtualBox, the MSR simply silently swallows the write, and upon a
>> read, returns the original 0xfee0 value again. This means that if
>> we can't relocate it, we can't access it at the moment either.
>>
>> The only real way to work around this is to have a paging scheme that
>> lets us access physical address 0xfee0 - in that case, we could
>> support page-faults and dynamically map pages in, _or_ have static
>> pages that are absurdly large (such as 1GiB), letting the virtual
>> address do the heavy-lifting in terms of finding the
>> virtual-to-physical mapping.
>>
>
> I recommend a few static super pages to get it working. It is simple
> and fits the prevailing RTEMS model.
>
>> Either way, I think this issue this close to the deadline basically
>> means the APIC timer won't be functional and make it upstream.
>>
>> I'll clean things up and send patches tomorrow for everything so far,
>> including all the stub-code which will become usable once our paging
>> scheme works fine.
>>
>> If anyone has any last-minute swooping ideas on how to save the APIC
>> timer, let me know! (Interrupts aren't masked, and as far as I can
>> tell, changing the "-cpu" flag on QEMU doesn't make a difference. I
>> don't have any ideas as to what else the problem could be.)
>>
>> In my final report, I'll make sure I document what's remaining in
>> clearer terms than I have in this email, so it's easier for other
>> contributors to pick it up too, if any are interested.
>>
>> 
>>
>> On Tue, Aug 7, 2018 at 6:03 AM, Chris Johns  wrote:
>>> On 07/08/2018 09:27, Joel Sherrill wrote:
 On Mon, Aug 6, 2018 at 8:13 AM, Amaan Cheval >>> > wrote:

 Thanks for all the help! I have a simple test using the RTEMS
 interrupt manager working successfully (tested by calling
 rtems_interrupt_handler_install for vector 0, and then triggering a
 divide-by-0 exception).

 Yeah!

 Could someone shed any light on why the i386 only hooks the first 17
 vectors as "RTEMS interrupts"?

 You are making me feel very old especially since I have the real
 IBM manual in my office which corresponds to the answer.
>>>
>>> Grandchildren, grey hair or Sebastian posting he is feeling old do not make 
>>> you
>>> feel old? Interesting! ;) :)
>>>
> I feel old, too.
>
 It is dated Sept 1985. In fairness, I saved it from the garbage heap
 years later when someone was cleaning out their office. :)
>>>
>>> Ah the good old days before the internet and search engines!!
>>>
 The x86 architecture is really vectored and the original i386
 port actually used simple direct vectoring since the first BSP wasn't
 a PC. Imagine that!  Another board using an i386 which didn't
 look like a PC at all.

 For better or worse, the PC/AT (286) and later used two i8259 PICs
 in a master and slave configuration. The slave PIC cascaded off the
>

Re: [GSoC - x86_64] Interrupt manager and and port-specific glue - was Re: [GSoC - x86_64 - automake] Limit CFLAGS to specific source for librtemsbsp.a

[Amaan Cheval]

Addition to status: it doesn't seem like the RTEMS Interrupt's call to
_Thread_Dispatch functions either - ticker.exe has outputs like the
following (yeah, the counter is running too quickly right now):

*** BEGIN OF TEST CLOCK TICK ***
*** TEST VERSION: 5.0.0.2f10634899719c2857e2c8dd5088fb93a425fc83-modified
*** TEST STATE: EXPECTED-PASS
*** TEST BUILD: RTEMS_NETWORKING RTEMS_POSIX_API
*** TEST TOOLS: 7.3.0 20180125 (RTEMS 5, RSB
25f4db09c85a52fb1640a29f9bdc2de8c2768988, Newlib 3.0.0)
TA1  - rtems_clock_get_tod - 11:34:12   05/12/1990
TA2  - rtems_clock_get_tod - 11:34:12   05/12/1990
TA3  - rtems_clock_get_tod - 11:34:12   05/12/1990

(And then the _Thread_Idle_body is never preempted due to the
interrupt dispatching a new thread - not sure if it just thinks it's
"too late" to even bother or if simply never even tries. I'll keep
investigating.)

On Thu, Aug 9, 2018 at 6:03 PM, Amaan Cheval  wrote:
> Hi everyone!
>
> Good news! The APIC timer _does_ work now (after implementing 1GiB
> pages)! I see Clock_isr_ticks increasing steadily, though I don't have
> tc_get_timecount implemented yet - I've yet to figure out the
> specifics of the clock driver (how
> rtems_configuration_get_microseconds_per_tick influences the
> counter_ticks, specifically).
>
> I suspect we'll barely just make ticker.exe work by EOD tomorrow,
> leaving just the weekend for me to clean the patches up and Monday to
> actually merge them.
>
> Would someone be willing to have a meeting on Hangouts (or whatever)
> with me to speed up the process of (1) upstreaming my patches and (2)
> checking that my "work package" looks good enough at any convenient
> time on Monday?
>
> (I'm a bit busy on Monday, so I'd really prefer to have this whole
> thing done by EOD Monday for me.)
>
> On Thu, Aug 9, 2018 at 7:03 AM, Gedare Bloom  wrote:
>> On Wed, Aug 8, 2018 at 12:21 PM, Amaan Cheval  wrote:
>>> Status update: The code is at a point where the APIC timer _should_
>>> work, but doesn't (it never starts ticking away, so when calibrating
>>> with the PIT, and later starting the APIC timer to generate IRQs,
>>> pretty much nothing happens).
>>>
>>> I suspect the cause being the APIC base relocation not working (the
>>> APIC is located at 0xfee0 in physical memory by default, and in
>>> the code we write to an MSR to relocate it, because the page-mapping
>>> scheme FreeBSD setup doesn't let us access such high physical memory -
>>> only the first 1GiB of physical memory).
>>>
>>> On QEMU, the MSR accepts our write for the relocation and happily
>>> spits it back out when read, but given the unresponsiveness of the
>>> APIC timer despite enabling all the right bits, I suspect it's just a
>>> "fake" in that regard (QEMU's "info lapic" doesn't reflect any of our
>>> changes to the APIC configuration either, supporting this theory).
>>> QEMU _does_ reflect changes to the APIC by other operating systems
>>> which don't relocate it, so I don't suspect its emulation being a
>>> problem.
>>>
>>> On VirtualBox, the MSR simply silently swallows the write, and upon a
>>> read, returns the original 0xfee0 value again. This means that if
>>> we can't relocate it, we can't access it at the moment either.
>>>
>>> The only real way to work around this is to have a paging scheme that
>>> lets us access physical address 0xfee0 - in that case, we could
>>> support page-faults and dynamically map pages in, _or_ have static
>>> pages that are absurdly large (such as 1GiB), letting the virtual
>>> address do the heavy-lifting in terms of finding the
>>> virtual-to-physical mapping.
>>>
>>
>> I recommend a few static super pages to get it working. It is simple
>> and fits the prevailing RTEMS model.
>>
>>> Either way, I think this issue this close to the deadline basically
>>> means the APIC timer won't be functional and make it upstream.
>>>
>>> I'll clean things up and send patches tomorrow for everything so far,
>>> including all the stub-code which will become usable once our paging
>>> scheme works fine.
>>>
>>> If anyone has any last-minute swooping ideas on how to save the APIC
>>> timer, let me know! (Interrupts aren't masked, and as far as I can
>>> tell, changing the "-cpu" flag on QEMU doesn't make a difference. I
>>> don't have any ideas as to what else the problem could be.)
>>>
>>> In my final report, I'll make sure I document what's remaining in
>>> clearer terms than I have in this email, so it's easier for other
>>> contributors to pick it up too, if any are interested.
>>>
>>> 
>>>
>>> On Tue, Aug 7, 2018 at 6:03 AM, Chris Johns  wrote:
 On 07/08/2018 09:27, Joel Sherrill wrote:
> On Mon, Aug 6, 2018 at 8:13 AM, Amaan Cheval  > wrote:
>
> Thanks for all the help! I have a simple test using the RTEMS
> interrupt manager working successfully (tested by calling
> rtems_interrupt_handler_install for vector 0, and then triggering a
> divide-by-0 exception).
>
> 

Re: [GSoC - x86_64] Interrupt manager and and port-specific glue - was Re: [GSoC - x86_64 - automake] Limit CFLAGS to specific source for librtemsbsp.a

[Joel Sherrill]

On Thu, Aug 9, 2018 at 7:43 AM, Amaan Cheval  wrote:

> Addition to status: it doesn't seem like the RTEMS Interrupt's call to
> _Thread_Dispatch functions either - ticker.exe has outputs like the
> following (yeah, the counter is running too quickly right now):
>
> *** BEGIN OF TEST CLOCK TICK ***
> *** TEST VERSION: 5.0.0.2f10634899719c2857e2c8dd5088fb93a425fc83-modified
> *** TEST STATE: EXPECTED-PASS
> *** TEST BUILD: RTEMS_NETWORKING RTEMS_POSIX_API
> *** TEST TOOLS: 7.3.0 20180125 (RTEMS 5, RSB
> 25f4db09c85a52fb1640a29f9bdc2de8c2768988, Newlib 3.0.0)
> TA1  - rtems_clock_get_tod - 11:34:12   05/12/1990
> TA2  - rtems_clock_get_tod - 11:34:12   05/12/1990
> TA3  - rtems_clock_get_tod - 11:34:12   05/12/1990
>

Congratulations! But why is the date 5/12/1990? I think it is supposed
to be 12/31/1989. :)

>
> (And then the _Thread_Idle_body is never preempted due to the
> interrupt dispatching a new thread - not sure if it just thinks it's
> "too late" to even bother or if simply never even tries. I'll keep
> investigating.)
>

This means your "outer" assembly language _ISR_Handler does not
yet deal with "needs dispatch". On the 5 second tick, a task is unblocked
and set up to preempt. The end of the ISR path has to be right to
make this work.

--joel

>
> On Thu, Aug 9, 2018 at 6:03 PM, Amaan Cheval 
> wrote:
> > Hi everyone!
> >
> > Good news! The APIC timer _does_ work now (after implementing 1GiB
> > pages)! I see Clock_isr_ticks increasing steadily, though I don't have
> > tc_get_timecount implemented yet - I've yet to figure out the
> > specifics of the clock driver (how
> > rtems_configuration_get_microseconds_per_tick influences the
> > counter_ticks, specifically).
> >
> > I suspect we'll barely just make ticker.exe work by EOD tomorrow,
> > leaving just the weekend for me to clean the patches up and Monday to
> > actually merge them.
> >
> > Would someone be willing to have a meeting on Hangouts (or whatever)
> > with me to speed up the process of (1) upstreaming my patches and (2)
> > checking that my "work package" looks good enough at any convenient
> > time on Monday?
> >
> > (I'm a bit busy on Monday, so I'd really prefer to have this whole
> > thing done by EOD Monday for me.)
> >
> > On Thu, Aug 9, 2018 at 7:03 AM, Gedare Bloom  wrote:
> >> On Wed, Aug 8, 2018 at 12:21 PM, Amaan Cheval 
> wrote:
> >>> Status update: The code is at a point where the APIC timer _should_
> >>> work, but doesn't (it never starts ticking away, so when calibrating
> >>> with the PIT, and later starting the APIC timer to generate IRQs,
> >>> pretty much nothing happens).
> >>>
> >>> I suspect the cause being the APIC base relocation not working (the
> >>> APIC is located at 0xfee0 in physical memory by default, and in
> >>> the code we write to an MSR to relocate it, because the page-mapping
> >>> scheme FreeBSD setup doesn't let us access such high physical memory -
> >>> only the first 1GiB of physical memory).
> >>>
> >>> On QEMU, the MSR accepts our write for the relocation and happily
> >>> spits it back out when read, but given the unresponsiveness of the
> >>> APIC timer despite enabling all the right bits, I suspect it's just a
> >>> "fake" in that regard (QEMU's "info lapic" doesn't reflect any of our
> >>> changes to the APIC configuration either, supporting this theory).
> >>> QEMU _does_ reflect changes to the APIC by other operating systems
> >>> which don't relocate it, so I don't suspect its emulation being a
> >>> problem.
> >>>
> >>> On VirtualBox, the MSR simply silently swallows the write, and upon a
> >>> read, returns the original 0xfee0 value again. This means that if
> >>> we can't relocate it, we can't access it at the moment either.
> >>>
> >>> The only real way to work around this is to have a paging scheme that
> >>> lets us access physical address 0xfee0 - in that case, we could
> >>> support page-faults and dynamically map pages in, _or_ have static
> >>> pages that are absurdly large (such as 1GiB), letting the virtual
> >>> address do the heavy-lifting in terms of finding the
> >>> virtual-to-physical mapping.
> >>>
> >>
> >> I recommend a few static super pages to get it working. It is simple
> >> and fits the prevailing RTEMS model.
> >>
> >>> Either way, I think this issue this close to the deadline basically
> >>> means the APIC timer won't be functional and make it upstream.
> >>>
> >>> I'll clean things up and send patches tomorrow for everything so far,
> >>> including all the stub-code which will become usable once our paging
> >>> scheme works fine.
> >>>
> >>> If anyone has any last-minute swooping ideas on how to save the APIC
> >>> timer, let me know! (Interrupts aren't masked, and as far as I can
> >>> tell, changing the "-cpu" flag on QEMU doesn't make a difference. I
> >>> don't have any ideas as to what else the problem could be.)
> >>>
> >>> In my final report, I'll make sure I document what's remaining in
> >>> clearer terms than I have in this email,

Re: Inlined code

[Sebastian Huber]

- Am 6. Aug 2018 um 21:14 schrieb joel j...@rtems.org:
[...]
> We looked at a lot of generated assembly. Sometimes we would see
> large methods being inlined multiple times. This would increase the overall
> size of an RTEMS application. But size is not the only impact of inlining.
> If an inlined method has one or more if's in it, then the branch paths
> it includes are introduced EVERYWHERE it is inlined. When we
> had _Thread_Dispatch_enable, I recall it was used > 100 times and
> includes a branch in it. There was a build option to not inline this
> routine to avoid needing to add over 100 test cases.
[...]

I had a look at the _Thread_Dispatch_enable() code and was a bit surprised that 
GCC generates a stack frame in this function.  This turned out as a bug in the 
function. Do you find it? I will fix it tomorrow.

Before we start to turn inline functions into non-inline functions we should 
create a benchmark program (or more). We should look at the overall code size 
changes and the local code changes.
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Re: [GSoC - x86_64] Interrupt manager and and port-specific glue - was Re: [GSoC - x86_64 - automake] Limit CFLAGS to specific source for librtemsbsp.a

[Amaan Cheval]

Haha, my tc_frequency was set all wrong, causing the date to be wonky.

The dispatching issue turned out to be a (potential) QEMU bug where
"decq" wouldn't set the ZF in EFLAGS even if it resulted in a 0 value,
causing the "jne" to always be taken.

Anyway, here's where we're at now:

Start @ 0x1027f9 ...
EFI framebuffer information:
addr, size 0x8000, 0x1d4c00
dimensions 800 x 600
stride 800
masks  0x00ff, 0xff00, 0x00ff, 0xff00
Filling 512 page tables
1gib pages not supported!
maxphysaddr = 48
sidt = ff f a8 39 34 0 0 0 0 0
us_per_tick = 1
Desired frequency = 100 irqs/sec
APIC was at fee0
APIC is now at fee0
APIC ID at *fee00020=0
APIC spurious vector register *fee000f0=10f
APIC spurious vector register *fee000f0=1ff
CPU frequency: 0x57c60
APIC ticks/sec: 0x57c6qemu-system-x86_64: warning: I/O thread spun for
1000 iterations


*** BEGIN OF TEST CLOCK TICK ***
*** TEST VERSION: 5.0.0.2f10634899719c2857e2c8dd5088fb93a425fc83-modified
*** TEST STATE: EXPECTED-PASS
*** TEST BUILD: RTEMS_NETWORKING RTEMS_POSIX_API
*** TEST TOOLS: 7.3.0 20180125 (RTEMS 5, RSB
25f4db09c85a52fb1640a29f9bdc2de8c2768988, Newlib 3.0.0)
TA1  - rtems_clock_get_tod - 09:00:00   12/31/1988
TA2  - rtems_clock_get_tod - 09:00:00   12/31/1988
TA3  - rtems_clock_get_tod - 09:00:00   12/31/1988
TA1  - rtems_clock_get_tod - 09:00:05   12/31/1988
TA2  - rtems_clock_get_tod - 09:00:10   12/31/1988
TA1  - rtems_clock_get_tod - 09:00:10   12/31/1988
TA3  - rtems_clock_get_tod - 09:00:15   12/31/1988
TA1  - rtems_clock_get_tod - 09:00:15   12/31/1988
TA2  - rtems_clock_get_tod - 09:00:20   12/31/1988
TA1  - rtems_clock_get_tod - 09:00:20   12/31/1988
TA1  - rtems_clock_get_tod - 09:00:25   12/31/1988
TA3  - rtems_clock_get_tod - 09:00:30   12/31/1988
TA2  - rtems_clock_get_tod - 09:00:30   12/31/1988
TA1  - rtems_clock_get_tod - 09:00:30   12/31/1988

*** END OF TEST CLOCK TICK ***


*** FATAL ***
fatal source: 5 (RTEMS_FATAL_SOURCE_EXIT)
fatal code: 0 (0x)
RTEMS version: 5.0.0.2f10634899719c2857e2c8dd5088fb93a425fc83-modified
RTEMS tools: 7.3.0 20180125 (RTEMS 5, RSB
25f4db09c85a52fb1640a29f9bdc2de8c2768988, Newlib 3.0.0)
executing thread ID: 0x08a010002
executing thread name: TA1
qemu-system-x86_64: terminating on signal 2

-

2 issues:
- It isn't reliably this way - sometimes it may start at 9:00:01 (and
then the rest are 6, 11, etc.). I'm using a very naive timecounter
(number of IRQs occurred so far) right now - I'll have it account for
the ticks since the last IRQ too, which I imagine may help with this?
- It is much slower than IRL time - I'm not sure if this is just due
to QEMU or perhaps from ISRs piling over each other due to the handler
taking too long. I'm not quite sure how to find out either.

Let me know if you have any suggestions!

Patches incoming soon too, so I'd appreciate reviews! :)

On Thu, Aug 9, 2018 at 8:12 PM, Joel Sherrill  wrote:
>
>
> On Thu, Aug 9, 2018 at 7:43 AM, Amaan Cheval  wrote:
>>
>> Addition to status: it doesn't seem like the RTEMS Interrupt's call to
>> _Thread_Dispatch functions either - ticker.exe has outputs like the
>> following (yeah, the counter is running too quickly right now):
>>
>> *** BEGIN OF TEST CLOCK TICK ***
>> *** TEST VERSION: 5.0.0.2f10634899719c2857e2c8dd5088fb93a425fc83-modified
>> *** TEST STATE: EXPECTED-PASS
>> *** TEST BUILD: RTEMS_NETWORKING RTEMS_POSIX_API
>> *** TEST TOOLS: 7.3.0 20180125 (RTEMS 5, RSB
>> 25f4db09c85a52fb1640a29f9bdc2de8c2768988, Newlib 3.0.0)
>> TA1  - rtems_clock_get_tod - 11:34:12   05/12/1990
>> TA2  - rtems_clock_get_tod - 11:34:12   05/12/1990
>> TA3  - rtems_clock_get_tod - 11:34:12   05/12/1990
>
>
> Congratulations! But why is the date 5/12/1990? I think it is supposed
> to be 12/31/1989. :)
>>
>>
>> (And then the _Thread_Idle_body is never preempted due to the
>> interrupt dispatching a new thread - not sure if it just thinks it's
>> "too late" to even bother or if simply never even tries. I'll keep
>> investigating.)
>
>
> This means your "outer" assembly language _ISR_Handler does not
> yet deal with "needs dispatch". On the 5 second tick, a task is unblocked
> and set up to preempt. The end of the ISR path has to be right to
> make this work.
>
> --joel
>>
>>
>> On Thu, Aug 9, 2018 at 6:03 PM, Amaan Cheval 
>> wrote:
>> > Hi everyone!
>> >
>> > Good news! The APIC timer _does_ work now (after implementing 1GiB
>> > pages)! I see Clock_isr_ticks increasing steadily, though I don't have
>> > tc_get_timecount implemented yet - I've yet to figure out the
>> > specifics of the clock driver (how
>> > rtems_configuration_get_microseconds_per_tick influences the
>> > counter_ticks, specifically).
>> >
>> > I suspect we'll barely just make ticker.exe work by EOD tomorrow,
>> > leaving just the weekend for me to clean the patches up and Monday to
>> > actually merge them.
>> >
>> > Would someone be willing to have a meeting on Hango

Fwd: gcov questions

[Joel Sherrill]

Thought this was interesting. At least this info is now in the RTEMS
archives.

-- Forwarded message -
From: Jim Wilson 
Date: Thu, Aug 9, 2018, 1:26 PM
Subject: Re: gcov questions
To: daro...@o2.pl , g...@gcc.gnu.org 


On 08/09/2018 02:38 AM, daro...@o2.pl wrote:
> Hello,   I wanted to ask what model for
> branch coverage does gcov use?

There is a comment at the start of gcc/profile.c that gives some details
on how it works.  It is computing execution counts for edges in the
control flow graph.  As for which edges get instrumented, basically, you
construct a control flow graph, create a minimal spanning tree to cover
the graph, and then you only need to instrument the edges not on the
spanning tree, plus the function entry point.  You can compute the rest
of the edge counts from that.  Then there are some tricks to improve
efficiency by putting frequently executed edges on the minimal spanning
tree, so that infrequently edges get instrumented.

Gcov was originally written in 1990, based on an idea that came from
Knuth's Art of Computer Programming.  Ball & Larus wrote a nice paper in
1994 that does a good job of covering the methods used, though they may
not have been aware of gcov at the time as it hadn't been accepted into
GCC yet.  This is "Optimally Profiling and Tracing Programs" TOPLAS July
1994.  I don't know if there are free copies of that available.  There
may be better references available now, as these techniques are pretty
widely known nowadays

Jim
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Re: Inlined code

[Joel Sherrill]

On Thu, Aug 9, 2018, 11:50 AM Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:

> - Am 6. Aug 2018 um 21:14 schrieb joel j...@rtems.org:
> [...]
> > We looked at a lot of generated assembly. Sometimes we would see
> > large methods being inlined multiple times. This would increase the
> overall
> > size of an RTEMS application. But size is not the only impact of
> inlining.
> > If an inlined method has one or more if's in it, then the branch paths
> > it includes are introduced EVERYWHERE it is inlined. When we
> > had _Thread_Dispatch_enable, I recall it was used > 100 times and
> > includes a branch in it. There was a build option to not inline this
> > routine to avoid needing to add over 100 test cases.
> [...]
>
> I had a look at the _Thread_Dispatch_enable() code and was a bit surprised
> that GCC generates a stack frame in this function.  This turned out as a
> bug in the function. Do you find it? I will fix it tomorrow.
>

Chris and I were just counting instructions and branch paths. But I do
recall seeing ret and restore. That's a hint it is really too big to inline.

Perhaps the check for yes/no to dispatch should be inlined and the rest in
a method. This is how it was historically.

  If (--dispatch disable level)
Call thread dispatch

But this only avoided the call on non-interrupt cases so not inlining at
all really wasn't a hit. I suspect the same now. Nearly all the time it
calls a subroutine anyway and 3K of code is added uselessly.

Look at it holistically. What is executed when it is a different is not
inlined?


> Before we start to turn inline functions into non-inline functions we
> should create a benchmark program (or more). We should look at the overall
> code size changes and the local code changes.
>

We were relying on checking size and our benchmarks before.

One metric was the size of the code we were analysing for coverage. That's
directly in the coverage reports.

Another metric when a lot of branch paths have been inlined is the number
of uncovered ranges. When you investigate and realize they are from an
inlineethod used in N places, it is clearly something to.look at.

>
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Re: [GSoC - x86_64] Interrupt manager and and port-specific glue - was Re: [GSoC - x86_64 - automake] Limit CFLAGS to specific source for librtemsbsp.a

[Joel Sherrill]

On Thu, Aug 9, 2018 at 1:13 PM, Amaan Cheval  wrote:

> Haha, my tc_frequency was set all wrong, causing the date to be wonky.
>
> The dispatching issue turned out to be a (potential) QEMU bug where
> "decq" wouldn't set the ZF in EFLAGS even if it resulted in a 0 value,
> causing the "jne" to always be taken.
>
> Anyway, here's where we're at now:
>
> Start @ 0x1027f9 ...
> EFI framebuffer information:
> addr, size 0x8000, 0x1d4c00
> dimensions 800 x 600
> stride 800
> masks  0x00ff, 0xff00, 0x00ff, 0xff00
> Filling 512 page tables
> 1gib pages not supported!
> maxphysaddr = 48
> sidt = ff f a8 39 34 0 0 0 0 0
> us_per_tick = 1
> Desired frequency = 100 irqs/sec
> APIC was at fee0
> APIC is now at fee0
> APIC ID at *fee00020=0
> APIC spurious vector register *fee000f0=10f
> APIC spurious vector register *fee000f0=1ff
> CPU frequency: 0x57c60
> APIC ticks/sec: 0x57c6qemu-system-x86_64: warning: I/O thread spun for
> 1000 iterations
>
>
> *** BEGIN OF TEST CLOCK TICK ***
> *** TEST VERSION: 5.0.0.2f10634899719c2857e2c8dd5088fb93a425fc83-modified
> *** TEST STATE: EXPECTED-PASS
> *** TEST BUILD: RTEMS_NETWORKING RTEMS_POSIX_API
> *** TEST TOOLS: 7.3.0 20180125 (RTEMS 5, RSB
> 25f4db09c85a52fb1640a29f9bdc2de8c2768988, Newlib 3.0.0)
> TA1  - rtems_clock_get_tod - 09:00:00   12/31/1988
> TA2  - rtems_clock_get_tod - 09:00:00   12/31/1988
> TA3  - rtems_clock_get_tod - 09:00:00   12/31/1988
> TA1  - rtems_clock_get_tod - 09:00:05   12/31/1988
> TA2  - rtems_clock_get_tod - 09:00:10   12/31/1988
> TA1  - rtems_clock_get_tod - 09:00:10   12/31/1988
> TA3  - rtems_clock_get_tod - 09:00:15   12/31/1988
> TA1  - rtems_clock_get_tod - 09:00:15   12/31/1988
> TA2  - rtems_clock_get_tod - 09:00:20   12/31/1988
> TA1  - rtems_clock_get_tod - 09:00:20   12/31/1988
> TA1  - rtems_clock_get_tod - 09:00:25   12/31/1988
> TA3  - rtems_clock_get_tod - 09:00:30   12/31/1988
> TA2  - rtems_clock_get_tod - 09:00:30   12/31/1988
> TA1  - rtems_clock_get_tod - 09:00:30   12/31/1988
>
> *** END OF TEST CLOCK TICK ***
>
>
+1

>
> *** FATAL ***
> fatal source: 5 (RTEMS_FATAL_SOURCE_EXIT)
> fatal code: 0 (0x)
> RTEMS version: 5.0.0.2f10634899719c2857e2c8dd5088fb93a425fc83-modified
> RTEMS tools: 7.3.0 20180125 (RTEMS 5, RSB
> 25f4db09c85a52fb1640a29f9bdc2de8c2768988, Newlib 3.0.0)
> executing thread ID: 0x08a010002
> executing thread name: TA1
> qemu-system-x86_64: terminating on signal 2
>
> -
>
> 2 issues:
> - It isn't reliably this way - sometimes it may start at 9:00:01 (and
> then the rest are 6, 11, etc.). I'm using a very naive timecounter
> (number of IRQs occurred so far) right now - I'll have it account for
> the ticks since the last IRQ too, which I imagine may help with this?
>

Some of the simulators are odd this way. But I would expect this to
behave better. It is probably a calibration issue. There should be more
than enough time to do the prints and handle the tick ISRs. On some
simulators, it isn't that way.

The initialization should program it to get an interrupt based on the
configured microseconds per tick. You need the calibration or truth
speed to do this. I assume that calibration that would work on real
HW would work on qemu.


> - It is much slower than IRL time - I'm not sure if this is just due
> to QEMU or perhaps from ISRs piling over each other due to the handler
> taking too long. I'm not quite sure how to find out either.
>

This is expected. I recall it is ~2x IRL time for pc386 ticker.


>
> Let me know if you have any suggestions!
>
> Patches incoming soon too, so I'd appreciate reviews! :)
>

Nearly working is a great sign!


>
> On Thu, Aug 9, 2018 at 8:12 PM, Joel Sherrill  wrote:
> >
> >
> > On Thu, Aug 9, 2018 at 7:43 AM, Amaan Cheval 
> wrote:
> >>
> >> Addition to status: it doesn't seem like the RTEMS Interrupt's call to
> >> _Thread_Dispatch functions either - ticker.exe has outputs like the
> >> following (yeah, the counter is running too quickly right now):
> >>
> >> *** BEGIN OF TEST CLOCK TICK ***
> >> *** TEST VERSION: 5.0.0.2f10634899719c2857e2c8dd5088fb
> 93a425fc83-modified
> >> *** TEST STATE: EXPECTED-PASS
> >> *** TEST BUILD: RTEMS_NETWORKING RTEMS_POSIX_API
> >> *** TEST TOOLS: 7.3.0 20180125 (RTEMS 5, RSB
> >> 25f4db09c85a52fb1640a29f9bdc2de8c2768988, Newlib 3.0.0)
> >> TA1  - rtems_clock_get_tod - 11:34:12   05/12/1990
> >> TA2  - rtems_clock_get_tod - 11:34:12   05/12/1990
> >> TA3  - rtems_clock_get_tod - 11:34:12   05/12/1990
> >
> >
> > Congratulations! But why is the date 5/12/1990? I think it is supposed
> > to be 12/31/1989. :)
> >>
> >>
> >> (And then the _Thread_Idle_body is never preempted due to the
> >> interrupt dispatching a new thread - not sure if it just thinks it's
> >> "too late" to even bother or if simply never even tries. I'll keep
> >> investigating.)
> >
> >
> > This means your "outer" assembly language _ISR_Handler does not
> >

Re: [PATCH] rfs: Remove erroneous call of rtems_disk_release()

[Chris Johns]

On 07/08/2018 15:33, Chris Johns wrote:
> 
> I will ping Amar tomorrow. I do not touch the Trac install.
> 

Amar has installed the clone tool (Thank you). There is now a Clone button on
the tickets besides the Reply and Delete buttons.

Chris
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Re: [PATCH] rfs: Remove erroneous call of rtems_disk_release()

[Sebastian Huber]

On 10/08/18 01:44, Chris Johns wrote:

On 07/08/2018 15:33, Chris Johns wrote:

I will ping Amar tomorrow. I do not touch the Trac install.


Amar has installed the clone tool (Thank you). There is now a Clone button on
the tickets besides the Reply and Delete buttons.


Thanks, this makes it easier. I back ported the patch to 4.11 and 4.10.

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Fax : +49 89 189 47 41-09
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Tickets: Milestone vs. Version

[Sebastian Huber]

Hello,

we want a ticket for each milestone in which it is resolved. What is now 
the meaning of the version field?


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Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone   : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail  : sebastian.hu...@embedded-brains.de
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[PATCH] score: Fix ISR enable in _Thread_Dispatch_enable()

[Sebastian Huber]

This bug had probably no effect since the interrupt enable is idempotent
on all CPU ports.

Close #3496.
---
 cpukit/include/rtems/score/threaddispatch.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/cpukit/include/rtems/score/threaddispatch.h 
b/cpukit/include/rtems/score/threaddispatch.h
index 63eb4c6fb4..69696f4044 100644
--- a/cpukit/include/rtems/score/threaddispatch.h
+++ b/cpukit/include/rtems/score/threaddispatch.h
@@ -228,9 +228,8 @@ RTEMS_INLINE_ROUTINE void _Thread_Dispatch_enable( 
Per_CPU_Control *cpu_self )
 } else {
   cpu_self->thread_dispatch_disable_level = 0;
   _Profiling_Thread_dispatch_enable( cpu_self, 0 );
+  _ISR_Local_enable( level );
 }
-
-_ISR_Local_enable( level );
   } else {
 _Assert( disable_level > 0 );
 cpu_self->thread_dispatch_disable_level = disable_level - 1;
-- 
2.13.7

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Re: Tickets: Milestone vs. Version

[Chris Johns]

On 10/08/2018 15:03, Sebastian Huber wrote:
> 
> we want a ticket for each milestone in which it is resolved. What is now the
> meaning of the version field?
> 

A ticket may be assigned to a branch but not a milestone. Milestones lets us
select which tickets we fix on branch. Once all tickets on a milestone are
closed the release can be made.

We do not work that way at the moment. I use the milestones when making releases
to move tickets scheduled for a release that are not closed to the next release.

Chris
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Re: Tickets: Milestone vs. Version

[Sebastian Huber]

On 10/08/18 07:38, Chris Johns wrote:

On 10/08/2018 15:03, Sebastian Huber wrote:

we want a ticket for each milestone in which it is resolved. What is now the
meaning of the version field?


A ticket may be assigned to a branch but not a milestone. Milestones lets us
select which tickets we fix on branch. Once all tickets on a milestone are
closed the release can be made.

We do not work that way at the moment. I use the milestones when making releases
to move tickets scheduled for a release that are not closed to the next release.


This doesn't explain the version field. Is version the same as branch 
from your point of view?


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Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone   : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail  : sebastian.hu...@embedded-brains.de
PGP : Public key available on request.

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Re: Tickets: Milestone vs. Version

[Chris Johns]

On 10/08/2018 15:41, Sebastian Huber wrote:
> On 10/08/18 07:38, Chris Johns wrote:
>> On 10/08/2018 15:03, Sebastian Huber wrote:
>>> we want a ticket for each milestone in which it is resolved. What is now the
>>> meaning of the version field?
>>>
>> A ticket may be assigned to a branch but not a milestone. Milestones lets us
>> select which tickets we fix on branch. Once all tickets on a milestone are
>> closed the release can be made.
>>
>> We do not work that way at the moment. I use the milestones when making 
>> releases
>> to move tickets scheduled for a release that are not closed to the next 
>> release.
> 
> This doesn't explain the version field. Is version the same as branch from 
> your
> point of view?
> 

The branch is the version of RTEMS released from that branch. In trac it is
called version, ie 4.11, 4.10, 5 etc. The term version is more accurate, the use
of branch is actually a VC implementation detail.

I think https://devel.rtems.org/wiki/Developer/Release could do with some work.
May be the following from
https://devel.rtems.org/wiki/Developer/Release#ReleaseTerminology should be ...

Release Terminology

- A release is the creation of any generated files and their packaging together
with the source in a repository that makes the package available as a file.
- A release branch is a git branch pushed to the repositories used to create
release. There is a release branch for each version of RTEMS.
- A release is a git tag on a release branch with the tags pushed to the
repositories.

?

Chris
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[PATCH] score: Do not inline _Thread_Dispatch_enable()

[Sebastian Huber]

This function is slighly too complex for inlining with two if
statements.  The caller already needs a stack frame due to the potential
call to _Thread_Do_dispatch().  In _Thread_Dispatch_enable() the call to
_Thread_Do_dispatch() can be optimized to a tail call.

A text size comparision

  (text size after patch - text size before patch)
   / text size before patch

on sparc/erc32 with SMP enabled showed these results:

  Minimum -0.000697892 (fsdosfsname01.exe)
  Median -0.00745021 (psxtimes01.exe)
  Maximum -0.0233032 (spscheduler01.exe)

A text size comparision

  text size after patch - text size before patch

on sparc/erc32 with SMP enabled showed these results:

  Minimum -3312 (ada_sp09.exe)
  Median -1024 (tm15.exe)
  Maximum -592 (spglobalcon01.exe)
---
 cpukit/include/rtems/score/threaddispatch.h | 29 ++---
 cpukit/score/src/threaddispatch.c   | 27 +++
 2 files changed, 29 insertions(+), 27 deletions(-)

diff --git a/cpukit/include/rtems/score/threaddispatch.h 
b/cpukit/include/rtems/score/threaddispatch.h
index 69696f4044..f5d5c48035 100644
--- a/cpukit/include/rtems/score/threaddispatch.h
+++ b/cpukit/include/rtems/score/threaddispatch.h
@@ -205,36 +205,11 @@ RTEMS_INLINE_ROUTINE Per_CPU_Control 
*_Thread_Dispatch_disable( void )
 /**
  * @brief Enables thread dispatching.
  *
- * May perfrom a thread dispatch if necessary as a side-effect.
+ * May perform a thread dispatch if necessary as a side-effect.
  *
  * @param[in] cpu_self The current processor.
  */
-RTEMS_INLINE_ROUTINE void _Thread_Dispatch_enable( Per_CPU_Control *cpu_self )
-{
-  uint32_t disable_level = cpu_self->thread_dispatch_disable_level;
-
-  if ( disable_level == 1 ) {
-ISR_Level level;
-
-_ISR_Local_disable( level );
-
-if (
-  cpu_self->dispatch_necessary
-#if defined(RTEMS_SCORE_ROBUST_THREAD_DISPATCH)
-|| !_ISR_Is_enabled( level )
-#endif
-) {
-  _Thread_Do_dispatch( cpu_self, level );
-} else {
-  cpu_self->thread_dispatch_disable_level = 0;
-  _Profiling_Thread_dispatch_enable( cpu_self, 0 );
-  _ISR_Local_enable( level );
-}
-  } else {
-_Assert( disable_level > 0 );
-cpu_self->thread_dispatch_disable_level = disable_level - 1;
-  }
-}
+void _Thread_Dispatch_enable( Per_CPU_Control *cpu_self );
 
 /**
  * @brief Unnests thread dispatching.
diff --git a/cpukit/score/src/threaddispatch.c 
b/cpukit/score/src/threaddispatch.c
index 9cd1e294ed..d6207bc898 100644
--- a/cpukit/score/src/threaddispatch.c
+++ b/cpukit/score/src/threaddispatch.c
@@ -267,3 +267,30 @@ void _Thread_Dispatch_direct( Per_CPU_Control *cpu_self )
   _ISR_Local_disable( level );
   _Thread_Do_dispatch( cpu_self, level );
 }
+
+void _Thread_Dispatch_enable( Per_CPU_Control *cpu_self )
+{
+  uint32_t disable_level = cpu_self->thread_dispatch_disable_level;
+
+  if ( disable_level == 1 ) {
+ISR_Level level;
+
+_ISR_Local_disable( level );
+
+if (
+  cpu_self->dispatch_necessary
+#if defined(RTEMS_SCORE_ROBUST_THREAD_DISPATCH)
+|| !_ISR_Is_enabled( level )
+#endif
+) {
+  _Thread_Do_dispatch( cpu_self, level );
+} else {
+  cpu_self->thread_dispatch_disable_level = 0;
+  _Profiling_Thread_dispatch_enable( cpu_self, 0 );
+  _ISR_Local_enable( level );
+}
+  } else {
+_Assert( disable_level > 0 );
+cpu_self->thread_dispatch_disable_level = disable_level - 1;
+  }
+}
-- 
2.13.7

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