RISC-V interrupts in HiFive1
Hello all, at the end of the GSoC I've found out that interrupts in my BSP weren't properly enabled/disabled globally. This happens because my work is based on the Hesham's BSP for RISC-V and it was done for the previous version of ISA. Thus, the Hesham's interrupt enabling/disabling instructions did nothing in my version of ISA. I've tried to fix this issue, but without much of success. -- Regards, Denis Obrezkov ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Global configure options
Hello all, since my target board has a small amount of memory, where should I put the option CONFIGURE_UNIFIED_WORKSPACE to make it applied by default to all executives using my BSP? -- Regards, Denis Obrezkov ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: Global configure options
On Mon, Aug 14, 2017 at 11:32 AM, Denis Obrezkov wrote: > Hello all, > since my target board has a small amount of memory, > where should I put the option > CONFIGURE_UNIFIED_WORKSPACE > to make it applied by default to all executives using my BSP? > > Define BSP_DEFAULT_UNIFIED_WORK_AREAS in bsp.h > -- > Regards, Denis Obrezkov > > ___ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel > ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: Global configure options
2017-08-14 18:38 GMT+02:00 Joel Sherrill : > > > On Mon, Aug 14, 2017 at 11:32 AM, Denis Obrezkov > wrote: > >> Hello all, >> since my target board has a small amount of memory, >> where should I put the option >> CONFIGURE_UNIFIED_WORKSPACE >> to make it applied by default to all executives using my BSP? >> >> > Define BSP_DEFAULT_UNIFIED_WORK_AREAS in bsp.h > > >> -- >> Regards, Denis Obrezkov >> >> ___ >> devel mailing list >> devel@rtems.org >> http://lists.rtems.org/mailman/listinfo/devel >> > > Thank you! -- Regards, Denis Obrezkov ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
New lower ticker clock driver issue
Hello all, I am preparing my code for working without any modifications with examples-v2. Now I have an issue with a lower ticker example, this is my output: *** LOW MEMORY CLOCK TICK TEST *** TA1 - rtems_clock_get_tod - 09:00:00 12/31/1988 TA2 - rtems_clock_get_tod - 09:00:00 12/31/1988 TA3 - rtems_clock_get_tod - 09:00:00 12/31/1988 TA1 - rtems_clock_get_tod - 09:00:04 12/31/1988 TA2 - rtems_clock_get_tod - 09:00:09 12/31/1988 TA1 - rtems_clock_get_tod - 09:00:09 12/31/1988 and that's all, no errors. It seems that on some stage my interrupts aren't switched back on. I think this happens during a context switch. Could you Hasham, check my context switch and interrupt handling routine? My work branch: https://github.com/embeddedden/rtems-riscv/tree/hifive1 -- Regards, Denis Obrezkov ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: RISC-V interrupts in HiFive1
Hi Denis, You just need to modify riscv_interrupt_disable(). Read the priv-spec manual for your RISC-V version, and determine which bit should be cleared (it's called MIE in priv-1.10, but you mentioned you work with priv-1.9). Cheers, Hesham On Mon, Aug 14, 2017 at 6:10 PM, Denis Obrezkov wrote: > Hello all, > > at the end of the GSoC I've found out that interrupts in my BSP > weren't properly enabled/disabled globally. > This happens because my work is based on the Hesham's > BSP for RISC-V and it was done for the previous version of ISA. > Thus, the Hesham's interrupt enabling/disabling instructions did > nothing in my version of ISA. > I've tried to fix this issue, but without much of success. > > -- > Regards, Denis Obrezkov > > ___ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel -- Hesham ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
