This commit causes an error when running realview_pbx_a9_qemu in the
gem5 simulator. I have only been able to identify that this is the
problematic commit. I have not been able to debug further.
On Tue, Mar 28, 2017 at 4:34 AM, Sebastian Huber wrote:
> Module:rtems
> Branch:master
> Commit:cd3d74793a4e2ec93cefdddb855d4536d44c7e64
> Changeset:
> http://git.rtems.org/rtems/commit/?id=cd3d74793a4e2ec93cefdddb855d4536d44c7e64
>
> Author:Sebastian Huber
> Date: Mon Mar 27 08:01:38 2017 +0200
>
> arm: Optimize context switch
>
> Set CPU_ENABLE_ROBUST_THREAD_DISPATCH to TRUE. In this case the
> interrupts are always enabled during a context switch even after
> interrupt processing (see #2751). Remove the CPSR from the context
> control since it contains only volatile bits.
>
> Close #2954.
>
> ---
>
> c/src/lib/libbsp/arm/tms570/startup/bspstart.c | 12 --
> cpukit/score/cpu/arm/cpu.c | 33 --
> cpukit/score/cpu/arm/cpu_asm.S | 41 ++
> cpukit/score/cpu/arm/rtems/score/cpu.h | 59
> ++
> 4 files changed, 55 insertions(+), 90 deletions(-)
>
> diff --git a/c/src/lib/libbsp/arm/tms570/startup/bspstart.c
> b/c/src/lib/libbsp/arm/tms570/startup/bspstart.c
> index 7c1e9a1..025bb74 100644
> --- a/c/src/lib/libbsp/arm/tms570/startup/bspstart.c
> +++ b/c/src/lib/libbsp/arm/tms570/startup/bspstart.c
> @@ -35,18 +35,6 @@ void bsp_start( void )
>void *need_remap_ptr;
>unsigned int need_remap_int;
>
> - #if BYTE_ORDER == BIG_ENDIAN
> -/*
> - * If CPU is big endian (TMS570 family variant)
> - * set the CPU mode to supervisor and big endian.
> - * Do not set mode if CPU is little endian
> - * (RM48 family variant) for which default mode 0x13
> - * defined in cpukit/score/cpu/arm/cpu.c
> - * is right.
> - */
> -arm_cpu_mode = 0x213;
> - #endif
> -
>tms570_initialize_and_clear();
>
>/*
> diff --git a/cpukit/score/cpu/arm/cpu.c b/cpukit/score/cpu/arm/cpu.c
> index b5738b1..01a43b3 100644
> --- a/cpukit/score/cpu/arm/cpu.c
> +++ b/cpukit/score/cpu/arm/cpu.c
> @@ -15,7 +15,7 @@
> *
> * Copyright (c) 2007 Ray xu
> *
> - * Copyright (c) 2009, 2016 embedded brains GmbH
> + * Copyright (c) 2009, 2017 embedded brains GmbH
> *
> * The license and distribution terms for this file may be
> * found in the file LICENSE in this distribution or at
> @@ -26,14 +26,10 @@
> #include "config.h"
> #endif
>
> -#include
> -#include
> -#include
> -#include
> -#include
> +#include
> +#include
> #include
> #include
> -#include
>
> #ifdef ARM_MULTILIB_VFP
>RTEMS_STATIC_ASSERT(
> @@ -89,12 +85,6 @@ RTEMS_STATIC_ASSERT(
>
> #ifdef ARM_MULTILIB_ARCH_V4
>
> -/*
> - * This variable can be used to change the running mode of the execution
> - * contexts.
> - */
> -uint32_t arm_cpu_mode = 0x13;
> -
> void _CPU_Context_Initialize(
>Context_Control *the_context,
>void *stack_area_begin,
> @@ -105,10 +95,10 @@ void _CPU_Context_Initialize(
>void *tls_area
> )
> {
> + (void) new_level;
> +
>the_context->register_sp = (uint32_t) stack_area_begin + stack_area_size;
>the_context->register_lr = (uint32_t) entry_point;
> - the_context->register_cpsr = ( ( new_level != 0 ) ? ARM_PSR_I : 0 )
> -| arm_cpu_mode;
>the_context->isr_dispatch_disable = 0;
>
> #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
> @@ -120,25 +110,20 @@ void _CPU_Context_Initialize(
>}
> }
>
> -/* Preprocessor magic for stringification of x */
> -#define _CPU_ISR_LEVEL_DO_STRINGOF( x) #x
> -#define _CPU_ISR_LEVEL_STRINGOF( x) _CPU_ISR_LEVEL_DO_STRINGOF( x)
> -
> void _CPU_ISR_Set_level( uint32_t level )
> {
>uint32_t arm_switch_reg;
>
> - level = ( level != 0 ) ? ARM_PSR_I : 0;
> + /* Ignore the level parameter and just enable interrupts */
> + (void) level;
>
>__asm__ volatile (
> ARM_SWITCH_TO_ARM
> "mrs %[arm_switch_reg], cpsr\n"
> -"bic %[arm_switch_reg], #" _CPU_ISR_LEVEL_STRINGOF( ARM_PSR_I ) "\n"
> -"orr %[arm_switch_reg], %[level]\n"
> +"bic %[arm_switch_reg], #" RTEMS_XSTRING( ARM_PSR_I ) "\n"
> "msr cpsr, %0\n"
> ARM_SWITCH_BACK
> : [arm_switch_reg] "=&r" (arm_switch_reg)
> -: [level] "r" (level)
>);
> }
>
> @@ -150,7 +135,7 @@ uint32_t _CPU_ISR_Get_level( void )
>__asm__ volatile (
> ARM_SWITCH_TO_ARM
> "mrs %[level], cpsr\n"
> -"and %[level], #" _CPU_ISR_LEVEL_STRINGOF( ARM_PSR_I ) "\n"
> +"and %[level], #" RTEMS_XSTRING( ARM_PSR_I ) "\n"
> ARM_SWITCH_BACK
> : [level] "=&r" (level) ARM_SWITCH_ADDITIONAL_OUTPUT
>);
> diff --git a/cpukit/score/cpu/arm/cpu_asm.S b/cpukit/score/cpu/arm/cpu_asm.S
> index f10cd90..52ea77a 100644
> --- a/cpukit/score/cpu/arm/cpu_asm.S
> +++ b/cpukit/score/cpu/arm/cpu_asm.S
> @@ -19,7 +19,7 @@
> * COPYRIGHT (c) 2000 Canon Research Centre France SA.
> * Emmanuel Raguet, mailto:rag...@crf.canon.fr
> *
> - * Copyrig
