Re: Addressing git.dpdk.org downtime
On Thu, May 22, 2025 at 11:06 AM Bruce Richardson wrote: > > On Thu, May 22, 2025 at 08:36:28AM +, Ali Alnubani wrote: > > Hello everyone, > > > > We’re aware that https://git.dpdk.org has been experiencing availability > > issues lately, largely due to abusive bots and crawlers overloading the > > servers and ignoring traditional controls like robots.txt. > > > > To address this, we're preparing to deploy Anubis, a traffic-challenging > > tool, to help ensure reliable and continued access for the community, > > starting with our cgit instance. This approach has been adopted by several > > other open-source projects recently to reduce disruptive automated traffic. > > > > Please reach out if you have questions or encounter issues. > > > > See: https://github.com/TecharoHQ/anubis > > > > Thanks, > > Ali > > Thanks Ali, (and others involved) for taking action on this. > > To everyone else in the community, just a reminder that, rather than > accessing dpdk.org site directly, you can use > "https://github.com/DPDK/dpdk"; as a source for getting and browsing the > DPDK source code. The github mirror is always in sync with the main tree, > and, as an added convenience, also has the various "next" trees mirrored to > it too. This means that you don't need to clone multiple trees to get e.g. > next-net tree as well as main tree. To add on top of this, we discussed some additional mirroring during the techboard in Prague to ease life for (lazy?) maintainers and users who are not confortable with manipulating different git repositories. One request was to add mirroring of the stable branches and tags in a single repository with the main DPDK branch, and the DPDK/dpdk github repository seemed like the best location. I have just set up this mirroring down to 20.11 branch. The DPDK/dpdk github repository now contains most (if not all) of the active branches and tags. -- David Marchand
[PATCH v3 5/7] net/ena: fix unhandled interrupt config failure
Fixed the device initialization routine to correctly handle
failure during the registration or enabling of interrupts
when operating in control path interrupt mode.
Fixes: ca1dfa85f0d3 ("net/ena: add control path pure polling mode")
Cc: sta...@dpdk.org
Signed-off-by: Shai Brandes
Reviewed-by: Amit Bernstein
Reviewed-by: Yosef Raisman
---
doc/guides/rel_notes/release_25_07.rst | 2 ++
drivers/net/ena/ena_ethdev.c | 20 ++--
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/doc/guides/rel_notes/release_25_07.rst
b/doc/guides/rel_notes/release_25_07.rst
index 07b5feabc4..e7fecace4f 100644
--- a/doc/guides/rel_notes/release_25_07.rst
+++ b/doc/guides/rel_notes/release_25_07.rst
@@ -59,6 +59,8 @@ New Features
* Added support for enabling fragment bypass mode for egress packets.
This mode bypasses the PPS limit enforced by EC2 for fragmented egress
packets on every ENI.
+ * Fixed the device initialization routine to correctly handle failure during
the registration
+or enabling of interrupts when operating in control path interrupt mode.
* **Added Mucse rnp net driver.**
diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c
index 4caad9006e..f26f08ca85 100644
--- a/drivers/net/ena/ena_ethdev.c
+++ b/drivers/net/ena/ena_ethdev.c
@@ -2465,8 +2465,16 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
if (!adapter->control_path_poll_interval) {
/* Control path interrupt mode */
- rte_intr_callback_register(intr_handle,
ena_control_path_handler, eth_dev);
- rte_intr_enable(intr_handle);
+ rc = rte_intr_callback_register(intr_handle,
ena_control_path_handler, eth_dev);
+ if (unlikely(rc < 0)) {
+ PMD_DRV_LOG_LINE(ERR, "Failed to register control path
interrupt");
+ goto err_stats_destroy;
+ }
+ rc = rte_intr_enable(intr_handle);
+ if (unlikely(rc < 0)) {
+ PMD_DRV_LOG_LINE(ERR, "Failed to enable control path
interrupt");
+ goto err_control_path_destroy;
+ }
ena_com_set_admin_polling_mode(ena_dev, false);
} else {
/* Control path polling mode */
@@ -2485,6 +2493,14 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
return 0;
err_control_path_destroy:
+ if (!adapter->control_path_poll_interval) {
+ rc = rte_intr_callback_unregister_sync(intr_handle,
+ ena_control_path_handler,
+ eth_dev);
+ if (unlikely(rc < 0))
+ PMD_INIT_LOG_LINE(ERR, "Failed to unregister interrupt
handler");
+ }
+err_stats_destroy:
rte_free(adapter->drv_stats);
err_indirect_table_destroy:
ena_indirect_table_release(adapter);
--
2.17.1
[PATCH v3 7/7] net/ena: upgrade driver version to 2.13.0
Upgraded the driver version to 2.13.0. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein Reviewed-by: Yosef Raisman --- drivers/net/ena/ena_ethdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 182e063bf4..55b8d35285 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -22,7 +22,7 @@ #include #define DRV_MODULE_VER_MAJOR 2 -#define DRV_MODULE_VER_MINOR 12 +#define DRV_MODULE_VER_MINOR 13 #define DRV_MODULE_VER_SUBMINOR0 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l) -- 2.17.1
[PATCH v3 4/7] net/ena: support fragment bypass mode
Introduce devarg `enable_frag_bypass` to toggle the fragment bypass
mode for egress packets.
When enabled, this feature bypasses the PPS limit enforced by EC2 for
fragmented egress packets on every ENI. Note that enabling this might
negatively impact network performance.
By default, this feature is disabled. To enable it set
`enable_frag_bypass=1`. If it cannot be enabled, a warning will be
printed, but driver initialization will proceed as normal.
Signed-off-by: Yosef Raisman
Signed-off-by: Shai Brandes
Reviewed-by: Amit Bernstein
---
doc/guides/nics/ena.rst | 9
doc/guides/rel_notes/release_25_07.rst| 5 ++
drivers/net/ena/base/ena_com.c| 33 +
drivers/net/ena/base/ena_com.h| 8
.../net/ena/base/ena_defs/ena_admin_defs.h| 15 ++
drivers/net/ena/ena_ethdev.c | 46 +++
drivers/net/ena/ena_ethdev.h | 2 +
7 files changed, 118 insertions(+)
diff --git a/doc/guides/nics/ena.rst b/doc/guides/nics/ena.rst
index a34575dc9b..a42deccd81 100644
--- a/doc/guides/nics/ena.rst
+++ b/doc/guides/nics/ena.rst
@@ -141,6 +141,15 @@ Runtime Configuration
**A non-zero value for this devarg is mandatory for control path
functionality
when binding ports to uio_pci_generic kernel module which lacks interrupt
support.**
+ * **enable_frag_bypass** (default 0)
+
+ Enable fragment bypass mode for egress packets. This mode bypasses the PPS
+ limit enforced by EC2 for fragmented egress packets on every ENI. Note
that
+ enabling it might negatively impact network performance.
+
+ 0 - Disabled (Default).
+
+ 1 - Enabled.
ENA Configuration Parameters
diff --git a/doc/guides/rel_notes/release_25_07.rst
b/doc/guides/rel_notes/release_25_07.rst
index 467536fe05..07b5feabc4 100644
--- a/doc/guides/rel_notes/release_25_07.rst
+++ b/doc/guides/rel_notes/release_25_07.rst
@@ -55,6 +55,11 @@ New Features
Also, make sure to start the actual text at the margin.
===
+* **Updated Amazon ENA (Elastic Network Adapter) net driver.**
+
+ * Added support for enabling fragment bypass mode for egress packets.
+This mode bypasses the PPS limit enforced by EC2 for fragmented egress
packets on every ENI.
+
* **Added Mucse rnp net driver.**
Added a new network PMD which supports Mucse 10 Gigabit Ethernet NICs.
diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c
index 588dc61387..9715a627c1 100644
--- a/drivers/net/ena/base/ena_com.c
+++ b/drivers/net/ena/base/ena_com.c
@@ -3459,3 +3459,36 @@ int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
return 0;
}
+int ena_com_set_frag_bypass(struct ena_com_dev *ena_dev, bool enable)
+{
+ struct ena_admin_set_feat_resp set_feat_resp;
+ struct ena_com_admin_queue *admin_queue;
+ struct ena_admin_set_feat_cmd cmd;
+ int ret;
+
+ if (!ena_com_check_supported_feature_id(ena_dev,
ENA_ADMIN_FRAG_BYPASS)) {
+ ena_trc_dbg(ena_dev, "Feature %d isn't supported\n",
+ ENA_ADMIN_FRAG_BYPASS);
+ return ENA_COM_UNSUPPORTED;
+ }
+
+ memset(&cmd, 0x0, sizeof(cmd));
+ admin_queue = &ena_dev->admin_queue;
+
+ cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
+ cmd.aq_common_descriptor.flags = 0;
+ cmd.feat_common.feature_id = ENA_ADMIN_FRAG_BYPASS;
+ cmd.feat_common.feature_version =
ENA_ADMIN_FRAG_BYPASS_FEATURE_VERSION_0;
+ cmd.u.frag_bypass.enable = (u8)enable;
+
+ ret = ena_com_execute_admin_command(admin_queue,
+ (struct ena_admin_aq_entry *)&cmd,
+ sizeof(cmd),
+ (struct ena_admin_acq_entry
*)&set_feat_resp,
+ sizeof(set_feat_resp));
+
+ if (unlikely(ret))
+ ena_trc_err(ena_dev, "Failed to enable frag bypass. error:
%d\n", ret);
+
+ return ret;
+}
diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h
index b2aede1be1..f064095fd1 100644
--- a/drivers/net/ena/base/ena_com.h
+++ b/drivers/net/ena/base/ena_com.h
@@ -1109,6 +1109,14 @@ static inline bool
ena_com_get_missing_admin_interrupt(struct ena_com_dev *ena_d
return ena_dev->admin_queue.is_missing_admin_interrupt;
}
+/* ena_com_set_frag_bypass - set fragment bypass
+ * @ena_dev: ENA communication layer struct
+ * @enable: true if fragment bypass is enabled, false otherwise.
+ *
+ * @return - 0 on success, negative value on failure.
+ */
+int ena_com_set_frag_bypass(struct ena_com_dev *ena_dev, bool enable);
+
/* ena_com_io_sq_to_ena_dev - Extract ena_com_dev using contained field io_sq.
* @io_sq: IO submit queue struct
*
diff --git a/drivers/net/ena/base/ena_defs/en
Re: Addressing git.dpdk.org downtime
On 5/22/25 11:36 AM, Ali Alnubani wrote: Hello everyone, We’re aware that https://git.dpdk.org has been experiencing availability issues lately, largely due to abusive bots and crawlers overloading the servers and ignoring traditional controls like robots.txt. To address this, we're preparing to deploy Anubis, a traffic-challenging tool, to help ensure reliable and continued access for the community, starting with our cgit instance. This approach has been adopted by several other open-source projects recently to reduce disruptive automated traffic. Please reach out if you have questions or encounter issues. See: https://github.com/TecharoHQ/anubis Thanks, Ali The new service is now live on git.dpdk.org. Regular browsing and git operations should work as usual. HTTP traffic is now forcefully redirected to HTTPS as part of this change. Thanks for your understanding and support, Regards, Ali
[PATCH v3 6/7] net/ena: fix aenq timeout with low poll interval
The driver can work in polling-based functionality of the admin
queue, eliminating the need for interrupts in the control-path.
This mode is mandatory when using the uio_pci_generic driver,
which lacks interrupt support.
The control_path_poll_interval devarg is being set within the range
[1..1000]. A value of 0 disables the polling mechanism.
This value defines the interval in milliseconds at which the driver
checks for asynchronous notifications from the device.
Testing revealed that setting this interval below 500 milliseconds
might lead to false detection of device unresponsiveness.
This patch clamps the user-defined value to the updated valid range
[500..1000] that ensures reliable aenq monitoring.
Fixes: ca1dfa85f0d3 ("net/ena: add control path pure polling mode")
Cc: sta...@dpdk.org
Signed-off-by: Shai Brandes
Reviewed-by: Amit Bernstein
Reviewed-by: Yosef Raisman
---
doc/guides/nics/ena.rst| 4 +++-
doc/guides/rel_notes/release_25_07.rst | 2 ++
drivers/net/ena/ena_ethdev.c | 24 ++--
drivers/net/ena/ena_ethdev.h | 3 ++-
4 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/doc/guides/nics/ena.rst b/doc/guides/nics/ena.rst
index a42deccd81..decb6be766 100644
--- a/doc/guides/nics/ena.rst
+++ b/doc/guides/nics/ena.rst
@@ -136,7 +136,9 @@ Runtime Configuration
0 - Disable (Admin queue will work in interrupt mode).
- [1..1000] - Number of milliseconds to wait between periodic inspection of
the admin queues.
+ [500..1000] – Time in milliseconds to wait between periodic checks of the
admin queues.
+ If a value outside this range is specified, the driver will automatically
adjust it to
+ fit within the valid range.
**A non-zero value for this devarg is mandatory for control path
functionality
when binding ports to uio_pci_generic kernel module which lacks interrupt
support.**
diff --git a/doc/guides/rel_notes/release_25_07.rst
b/doc/guides/rel_notes/release_25_07.rst
index e7fecace4f..662b0db49e 100644
--- a/doc/guides/rel_notes/release_25_07.rst
+++ b/doc/guides/rel_notes/release_25_07.rst
@@ -61,6 +61,8 @@ New Features
This mode bypasses the PPS limit enforced by EC2 for fragmented egress
packets on every ENI.
* Fixed the device initialization routine to correctly handle failure during
the registration
or enabling of interrupts when operating in control path interrupt mode.
+ * Fixed an issue where the device might be incorrectly reported as
unresponsive when using
+polling-based admin queue functionality with a poll interval of less than
500 milliseconds.
* **Added Mucse rnp net driver.**
diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c
index f26f08ca85..182e063bf4 100644
--- a/drivers/net/ena/ena_ethdev.c
+++ b/drivers/net/ena/ena_ethdev.c
@@ -30,6 +30,8 @@
#define GET_L4_HDR_LEN(mbuf) \
((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \
mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
+#define CLAMP_VAL(val, min, max) \
+ (RTE_MIN(RTE_MAX((val), (typeof(val))(min)), (typeof(val))(max)))
#define ETH_GSTRING_LEN32
@@ -3756,25 +3758,19 @@ static int ena_process_uint_devarg(const char *key,
uint64_value * rte_get_timer_hz();
}
} else if (strcmp(key, ENA_DEVARG_CONTROL_PATH_POLL_INTERVAL) == 0) {
- if (uint64_value > ENA_MAX_CONTROL_PATH_POLL_INTERVAL_MSEC) {
- PMD_INIT_LOG_LINE(ERR,
- "Control path polling interval is too long: %"
PRIu64 " msecs. "
- "Maximum allowed: %d msecs.",
- uint64_value,
ENA_MAX_CONTROL_PATH_POLL_INTERVAL_MSEC);
- return -EINVAL;
- } else if (uint64_value == 0) {
+ if (uint64_value == 0) {
PMD_INIT_LOG_LINE(INFO,
- "Control path polling interval is set to zero.
Operating in "
- "interrupt mode.");
- adapter->control_path_poll_interval = 0;
+ "Control path polling is disabled - Operating
in interrupt mode");
} else {
+ uint64_value = CLAMP_VAL(uint64_value,
+ ENA_MIN_CONTROL_PATH_POLL_INTERVAL_MSEC,
+ ENA_MAX_CONTROL_PATH_POLL_INTERVAL_MSEC);
PMD_INIT_LOG_LINE(INFO,
- "Control path polling interval is set to %"
PRIu64 " msecs.",
+ "Control path polling interval is %" PRIu64 "
msec",
uint64_value);
- adapter->control_path_poll_interval =
uint64_value * USEC_PER_MSEC;
[PATCH v2 1/7] net/ena/base: avoid recalculating desc per entry
desc_per_entry is precomputed in ena_com_config_llq_info() using desc_stride_ctrl and desc_list_entry_size, which remain unchanged after device negotiation. Reuse the existing value instead of recalculating it in the fast path. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein Reviewed-by: Yosef Raisman --- drivers/net/ena/base/ena_eth_com.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/net/ena/base/ena_eth_com.c b/drivers/net/ena/base/ena_eth_com.c index 90dd85c7ff..c6668238e5 100644 --- a/drivers/net/ena/base/ena_eth_com.c +++ b/drivers/net/ena/base/ena_eth_com.c @@ -248,11 +248,7 @@ static int ena_com_sq_update_llq_tail(struct ena_com_io_sq *io_sq) 0x0, llq_info->desc_list_entry_size); pkt_ctrl->idx = 0; - if (unlikely(llq_info->desc_stride_ctrl == ENA_ADMIN_SINGLE_DESC_PER_ENTRY)) - pkt_ctrl->descs_left_in_line = 1; - else - pkt_ctrl->descs_left_in_line = - llq_info->desc_list_entry_size / io_sq->desc_entry_size; + pkt_ctrl->descs_left_in_line = llq_info->descs_per_entry; } return ENA_COM_OK; -- 2.17.1
Re: [PATCH 1/2] ci: bump tested distributions in GHA
Hello Luca, Xueming,
On Wed, Jan 31, 2024 at 6:44 PM David Marchand
wrote:
>
> Fedora 37 has reached end of life in December 2023.
> Ubuntu 20.04 is getting quite old.
>
> Switch to more recent versions.
>
> With this move, some packages provided by those distributions are now
> recent enough to extend our build coverage.
> Install additional dependencies like ipsec-mb, isal and other
> libbpf/libxdp devel packages.
>
> Signed-off-by: David Marchand
The Ubuntu 20.04 image has been removed from GHA which means that GHA
testing in github is KO for 22.11 and 23.11 branches.
If you do care about GHA, I suggest backporting this current patch to
those LTS branches (+ fix ef2535d022b9 ("ci: fix ccache for Ubuntu
22.04")).
It should apply cleanly (or at least easily), but I can help otherwise.
--
David Marchand
[PATCH v2 7/7] net/ena: upgrade driver version to 2.13.0
Upgraded the driver version to 2.13.0. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein Reviewed-by: Yosef Raisman --- drivers/net/ena/ena_ethdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 182e063bf4..55b8d35285 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -22,7 +22,7 @@ #include #define DRV_MODULE_VER_MAJOR 2 -#define DRV_MODULE_VER_MINOR 12 +#define DRV_MODULE_VER_MINOR 13 #define DRV_MODULE_VER_SUBMINOR0 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l) -- 2.17.1
[PATCH v2 4/7] net/ena: support fragment bypass mode
Introduce devarg `enable_frag_bypass` to toggle the fragment bypass
mode for egress packets.
When enabled, this feature bypasses the PPS limit enforced by EC2 for
fragmented egress packets on every ENI. Note that enabling this might
negatively impact network performance.
By default, this feature is disabled. To enable it set
`enable_frag_bypass=1`. If it cannot be enabled, a warning will be
printed, but driver initialization will proceed as normal.
Signed-off-by: Yosef Raisman
Signed-off-by: Shai Brandes
Reviewed-by: Amit Bernstein
---
doc/guides/nics/ena.rst | 9
doc/guides/rel_notes/release_25_07.rst| 5 ++
drivers/net/ena/base/ena_com.c| 33 +
drivers/net/ena/base/ena_com.h| 8
.../net/ena/base/ena_defs/ena_admin_defs.h| 15 ++
drivers/net/ena/ena_ethdev.c | 46 +++
drivers/net/ena/ena_ethdev.h | 2 +
7 files changed, 118 insertions(+)
diff --git a/doc/guides/nics/ena.rst b/doc/guides/nics/ena.rst
index a34575dc9b..a42deccd81 100644
--- a/doc/guides/nics/ena.rst
+++ b/doc/guides/nics/ena.rst
@@ -141,6 +141,15 @@ Runtime Configuration
**A non-zero value for this devarg is mandatory for control path
functionality
when binding ports to uio_pci_generic kernel module which lacks interrupt
support.**
+ * **enable_frag_bypass** (default 0)
+
+ Enable fragment bypass mode for egress packets. This mode bypasses the PPS
+ limit enforced by EC2 for fragmented egress packets on every ENI. Note
that
+ enabling it might negatively impact network performance.
+
+ 0 - Disabled (Default).
+
+ 1 - Enabled.
ENA Configuration Parameters
diff --git a/doc/guides/rel_notes/release_25_07.rst
b/doc/guides/rel_notes/release_25_07.rst
index 467536fe05..07b5feabc4 100644
--- a/doc/guides/rel_notes/release_25_07.rst
+++ b/doc/guides/rel_notes/release_25_07.rst
@@ -55,6 +55,11 @@ New Features
Also, make sure to start the actual text at the margin.
===
+* **Updated Amazon ENA (Elastic Network Adapter) net driver.**
+
+ * Added support for enabling fragment bypass mode for egress packets.
+This mode bypasses the PPS limit enforced by EC2 for fragmented egress
packets on every ENI.
+
* **Added Mucse rnp net driver.**
Added a new network PMD which supports Mucse 10 Gigabit Ethernet NICs.
diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c
index 588dc61387..9715a627c1 100644
--- a/drivers/net/ena/base/ena_com.c
+++ b/drivers/net/ena/base/ena_com.c
@@ -3459,3 +3459,36 @@ int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
return 0;
}
+int ena_com_set_frag_bypass(struct ena_com_dev *ena_dev, bool enable)
+{
+ struct ena_admin_set_feat_resp set_feat_resp;
+ struct ena_com_admin_queue *admin_queue;
+ struct ena_admin_set_feat_cmd cmd;
+ int ret;
+
+ if (!ena_com_check_supported_feature_id(ena_dev,
ENA_ADMIN_FRAG_BYPASS)) {
+ ena_trc_dbg(ena_dev, "Feature %d isn't supported\n",
+ ENA_ADMIN_FRAG_BYPASS);
+ return ENA_COM_UNSUPPORTED;
+ }
+
+ memset(&cmd, 0x0, sizeof(cmd));
+ admin_queue = &ena_dev->admin_queue;
+
+ cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
+ cmd.aq_common_descriptor.flags = 0;
+ cmd.feat_common.feature_id = ENA_ADMIN_FRAG_BYPASS;
+ cmd.feat_common.feature_version =
ENA_ADMIN_FRAG_BYPASS_FEATURE_VERSION_0;
+ cmd.u.frag_bypass.enable = (u8)enable;
+
+ ret = ena_com_execute_admin_command(admin_queue,
+ (struct ena_admin_aq_entry *)&cmd,
+ sizeof(cmd),
+ (struct ena_admin_acq_entry
*)&set_feat_resp,
+ sizeof(set_feat_resp));
+
+ if (unlikely(ret))
+ ena_trc_err(ena_dev, "Failed to enable frag bypass. error:
%d\n", ret);
+
+ return ret;
+}
diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h
index b2aede1be1..f064095fd1 100644
--- a/drivers/net/ena/base/ena_com.h
+++ b/drivers/net/ena/base/ena_com.h
@@ -1109,6 +1109,14 @@ static inline bool
ena_com_get_missing_admin_interrupt(struct ena_com_dev *ena_d
return ena_dev->admin_queue.is_missing_admin_interrupt;
}
+/* ena_com_set_frag_bypass - set fragment bypass
+ * @ena_dev: ENA communication layer struct
+ * @enable: true if fragment bypass is enabled, false otherwise.
+ *
+ * @return - 0 on success, negative value on failure.
+ */
+int ena_com_set_frag_bypass(struct ena_com_dev *ena_dev, bool enable);
+
/* ena_com_io_sq_to_ena_dev - Extract ena_com_dev using contained field io_sq.
* @io_sq: IO submit queue struct
*
diff --git a/drivers/net/ena/base/ena_defs/en
[PATCH v3 0/7] net/ena: release 2.13.0
This patchset includes an upgrade of the ENA HAL, introduces a new feature, and addresses three bug fixes. Thank you in advance to the net maintainers and community members for your time and effort reviewing the code. Best regards, Shai Brandes AWS Elastic Network Adapter team --- v2: Removed patch "net/ena: fix virtual address calc for unaligned BARs" which contained a problematic casting when compiling with 32-bit system v3: no change, there was some technical issue when sending the emails where part of the patches apeared on different series. Shai Brandes (7): net/ena/base: avoid recalculating desc per entry net/ena/base: coding style changes net/ena: separate doorbell logic for Rx and Tx net/ena: support fragment bypass mode net/ena: fix unhandled interrupt config failure net/ena: fix aenq timeout with low poll interval net/ena: upgrade driver version to 2.13.0 doc/guides/nics/ena.rst | 13 ++- doc/guides/rel_notes/release_25_07.rst| 9 ++ drivers/net/ena/base/ena_com.c| 39 +++- drivers/net/ena/base/ena_com.h| 8 ++ .../net/ena/base/ena_defs/ena_admin_defs.h| 15 +++ drivers/net/ena/base/ena_eth_com.c| 6 +- drivers/net/ena/base/ena_eth_com.h| 15 ++- drivers/net/ena/ena_ethdev.c | 98 +++ drivers/net/ena/ena_ethdev.h | 5 +- 9 files changed, 177 insertions(+), 31 deletions(-) -- 2.17.1
[PATCH v3 3/7] net/ena: separate doorbell logic for Rx and Tx
The function ena_com_write_sq_doorbell() currently
checks for LLQ mode using is_llq_max_tx_burst_exists()
which is relevant only for TX queues.
Since RX queues do not operate in LLQ mode, this check
is unnecessary for the RX path.
This patch separates the doorbell write logic into two
distinct handlers for RX and TX, eliminating the
irrelevant LLQ check in the RX path.
Signed-off-by: Shai Brandes
Reviewed-by: Amit Bernstein
Reviewed-by: Yosef Raisman
---
drivers/net/ena/base/ena_eth_com.h | 15 ++-
drivers/net/ena/ena_ethdev.c | 6 +++---
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ena/base/ena_eth_com.h
b/drivers/net/ena/base/ena_eth_com.h
index 8a12ed5fba..9e0a7af325 100644
--- a/drivers/net/ena/base/ena_eth_com.h
+++ b/drivers/net/ena/base/ena_eth_com.h
@@ -159,7 +159,20 @@ static inline bool ena_com_is_doorbell_needed(struct
ena_com_io_sq *io_sq,
return num_entries_needed > io_sq->entries_in_tx_burst_left;
}
-static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq)
+static inline int ena_com_write_rx_sq_doorbell(struct ena_com_io_sq *io_sq)
+{
+ u16 tail = io_sq->tail;
+
+ ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq),
+ "Write submission queue doorbell for queue: %d tail: %d\n",
+ io_sq->qid, tail);
+
+ ENA_REG_WRITE32(io_sq->bus, tail, io_sq->db_addr);
+
+ return 0;
+}
+
+static inline int ena_com_write_tx_sq_doorbell(struct ena_com_io_sq *io_sq)
{
u16 max_entries_in_tx_burst = io_sq->llq_info.max_entries_in_tx_burst;
u16 tail = io_sq->tail;
diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c
index a13506890f..d8ff6851d2 100644
--- a/drivers/net/ena/ena_ethdev.c
+++ b/drivers/net/ena/ena_ethdev.c
@@ -1835,7 +1835,7 @@ static int ena_populate_rx_queue(struct ena_ring *rxq,
unsigned int count)
/* When we submitted free resources to device... */
if (likely(i > 0)) {
/* ...let HW know that it can fill buffers with data. */
- ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
+ ena_com_write_rx_sq_doorbell(rxq->ena_com_io_sq);
rxq->next_to_use = next_to_use;
}
@@ -3163,7 +3163,7 @@ static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct
rte_mbuf *mbuf)
PMD_TX_LOG_LINE(DEBUG,
"LLQ Tx max burst size of queue %d achieved, writing
doorbell to send burst",
tx_ring->id);
- ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
+ ena_com_write_tx_sq_doorbell(tx_ring->ena_com_io_sq);
tx_ring->tx_stats.doorbells++;
tx_ring->pkts_without_db = false;
}
@@ -3296,7 +3296,7 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct
rte_mbuf **tx_pkts,
/* If there are ready packets to be xmitted... */
if (likely(tx_ring->pkts_without_db)) {
/* ...let HW do its best :-) */
- ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
+ ena_com_write_tx_sq_doorbell(tx_ring->ena_com_io_sq);
tx_ring->tx_stats.doorbells++;
tx_ring->pkts_without_db = false;
}
--
2.17.1
[PATCH v2 2/7] net/ena/base: coding style changes
Reordered variable declarations to follow the
reverse Christmas tree style.
Signed-off-by: Shai Brandes
Reviewed-by: Amit Bernstein
Reviewed-by: Yosef Raisman
---
drivers/net/ena/base/ena_com.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c
index 238716de29..588dc61387 100644
--- a/drivers/net/ena/base/ena_com.c
+++ b/drivers/net/ena/base/ena_com.c
@@ -308,8 +308,8 @@ static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct
ena_com_admin_queue
struct ena_admin_acq_entry
*comp,
size_t comp_size_in_bytes)
{
- unsigned long flags = 0;
struct ena_comp_ctx *comp_ctx;
+ unsigned long flags = 0;
ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
if (unlikely(!admin_queue->running_state)) {
@@ -616,10 +616,10 @@ static int
ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_c
*/
static int ena_com_set_llq(struct ena_com_dev *ena_dev)
{
+ struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
struct ena_com_admin_queue *admin_queue;
- struct ena_admin_set_feat_cmd cmd;
struct ena_admin_set_feat_resp resp;
- struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
+ struct ena_admin_set_feat_cmd cmd;
int ret;
memset(&cmd, 0x0, sizeof(cmd));
--
2.17.1
[PATCH v3 1/7] net/ena/base: avoid recalculating desc per entry
desc_per_entry is precomputed in ena_com_config_llq_info() using desc_stride_ctrl and desc_list_entry_size, which remain unchanged after device negotiation. Reuse the existing value instead of recalculating it in the fast path. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein Reviewed-by: Yosef Raisman --- drivers/net/ena/base/ena_eth_com.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/net/ena/base/ena_eth_com.c b/drivers/net/ena/base/ena_eth_com.c index 90dd85c7ff..c6668238e5 100644 --- a/drivers/net/ena/base/ena_eth_com.c +++ b/drivers/net/ena/base/ena_eth_com.c @@ -248,11 +248,7 @@ static int ena_com_sq_update_llq_tail(struct ena_com_io_sq *io_sq) 0x0, llq_info->desc_list_entry_size); pkt_ctrl->idx = 0; - if (unlikely(llq_info->desc_stride_ctrl == ENA_ADMIN_SINGLE_DESC_PER_ENTRY)) - pkt_ctrl->descs_left_in_line = 1; - else - pkt_ctrl->descs_left_in_line = - llq_info->desc_list_entry_size / io_sq->desc_entry_size; + pkt_ctrl->descs_left_in_line = llq_info->descs_per_entry; } return ENA_COM_OK; -- 2.17.1
Re: eal patches with other licenses
On Thu, May 22, 2025 at 10:29:46AM +0200, Morten Brørup wrote: > Andre, > > Please try asking the respective original authors of getline() and asprintf() > if they are willing to license these functions to the DPDK project under the > BSD-3-Clause license. Or perhaps generally offer dual-license with > BSD-3-Clause as an alternative to their original license. > > -Morten I sent an email to them. I'll let you know when/if they respond.
Re: [RFC v2 5/6] dts: add trex traffic generator to dts framework
Reviewed-by: Dean Marx
[PATCH v2 0/7] net/ena: release 2.13.0
This patchset includes an upgrade of the ENA HAL, introduces a new feature, and addresses three bug fixes. Thank you in advance to the net maintainers and community members for your time and effort reviewing the code. Best regards, Shai Brandes AWS Elastic Network Adapter team --- v2: Removed patch "net/ena: fix virtual address calc for unaligned BARs" which contained a problematic casting when compiling with 32-bit system Shai Brandes (7): net/ena/base: avoid recalculating desc per entry net/ena/base: coding style changes net/ena: separate doorbell logic for Rx and Tx net/ena: support fragment bypass mode net/ena: fix unhandled interrupt config failure net/ena: fix aenq timeout with low poll interval net/ena: upgrade driver version to 2.13.0 doc/guides/nics/ena.rst | 13 ++- doc/guides/rel_notes/release_25_07.rst| 9 ++ drivers/net/ena/base/ena_com.c| 39 +++- drivers/net/ena/base/ena_com.h| 8 ++ .../net/ena/base/ena_defs/ena_admin_defs.h| 15 +++ drivers/net/ena/base/ena_eth_com.c| 6 +- drivers/net/ena/base/ena_eth_com.h| 15 ++- drivers/net/ena/ena_ethdev.c | 98 +++ drivers/net/ena/ena_ethdev.h | 5 +- 9 files changed, 177 insertions(+), 31 deletions(-) -- 2.17.1
[PATCH v2 3/7] net/ena: separate doorbell logic for Rx and Tx
The function ena_com_write_sq_doorbell() currently
checks for LLQ mode using is_llq_max_tx_burst_exists()
which is relevant only for TX queues.
Since RX queues do not operate in LLQ mode, this check
is unnecessary for the RX path.
This patch separates the doorbell write logic into two
distinct handlers for RX and TX, eliminating the
irrelevant LLQ check in the RX path.
Signed-off-by: Shai Brandes
Reviewed-by: Amit Bernstein
Reviewed-by: Yosef Raisman
---
drivers/net/ena/base/ena_eth_com.h | 15 ++-
drivers/net/ena/ena_ethdev.c | 6 +++---
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ena/base/ena_eth_com.h
b/drivers/net/ena/base/ena_eth_com.h
index 8a12ed5fba..9e0a7af325 100644
--- a/drivers/net/ena/base/ena_eth_com.h
+++ b/drivers/net/ena/base/ena_eth_com.h
@@ -159,7 +159,20 @@ static inline bool ena_com_is_doorbell_needed(struct
ena_com_io_sq *io_sq,
return num_entries_needed > io_sq->entries_in_tx_burst_left;
}
-static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq)
+static inline int ena_com_write_rx_sq_doorbell(struct ena_com_io_sq *io_sq)
+{
+ u16 tail = io_sq->tail;
+
+ ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq),
+ "Write submission queue doorbell for queue: %d tail: %d\n",
+ io_sq->qid, tail);
+
+ ENA_REG_WRITE32(io_sq->bus, tail, io_sq->db_addr);
+
+ return 0;
+}
+
+static inline int ena_com_write_tx_sq_doorbell(struct ena_com_io_sq *io_sq)
{
u16 max_entries_in_tx_burst = io_sq->llq_info.max_entries_in_tx_burst;
u16 tail = io_sq->tail;
diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c
index a13506890f..d8ff6851d2 100644
--- a/drivers/net/ena/ena_ethdev.c
+++ b/drivers/net/ena/ena_ethdev.c
@@ -1835,7 +1835,7 @@ static int ena_populate_rx_queue(struct ena_ring *rxq,
unsigned int count)
/* When we submitted free resources to device... */
if (likely(i > 0)) {
/* ...let HW know that it can fill buffers with data. */
- ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
+ ena_com_write_rx_sq_doorbell(rxq->ena_com_io_sq);
rxq->next_to_use = next_to_use;
}
@@ -3163,7 +3163,7 @@ static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct
rte_mbuf *mbuf)
PMD_TX_LOG_LINE(DEBUG,
"LLQ Tx max burst size of queue %d achieved, writing
doorbell to send burst",
tx_ring->id);
- ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
+ ena_com_write_tx_sq_doorbell(tx_ring->ena_com_io_sq);
tx_ring->tx_stats.doorbells++;
tx_ring->pkts_without_db = false;
}
@@ -3296,7 +3296,7 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct
rte_mbuf **tx_pkts,
/* If there are ready packets to be xmitted... */
if (likely(tx_ring->pkts_without_db)) {
/* ...let HW do its best :-) */
- ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
+ ena_com_write_tx_sq_doorbell(tx_ring->ena_com_io_sq);
tx_ring->tx_stats.doorbells++;
tx_ring->pkts_without_db = false;
}
--
2.17.1
[PATCH v2 4/7] net/ena: support fragment bypass mode
Introduce devarg `enable_frag_bypass` to toggle the fragment bypass
mode for egress packets.
When enabled, this feature bypasses the PPS limit enforced by EC2 for
fragmented egress packets on every ENI. Note that enabling this might
negatively impact network performance.
By default, this feature is disabled. To enable it set
`enable_frag_bypass=1`. If it cannot be enabled, a warning will be
printed, but driver initialization will proceed as normal.
Signed-off-by: Yosef Raisman
Signed-off-by: Shai Brandes
Reviewed-by: Amit Bernstein
---
doc/guides/nics/ena.rst | 9
doc/guides/rel_notes/release_25_07.rst| 5 ++
drivers/net/ena/base/ena_com.c| 33 +
drivers/net/ena/base/ena_com.h| 8
.../net/ena/base/ena_defs/ena_admin_defs.h| 15 ++
drivers/net/ena/ena_ethdev.c | 46 +++
drivers/net/ena/ena_ethdev.h | 2 +
7 files changed, 118 insertions(+)
diff --git a/doc/guides/nics/ena.rst b/doc/guides/nics/ena.rst
index a34575dc9b..a42deccd81 100644
--- a/doc/guides/nics/ena.rst
+++ b/doc/guides/nics/ena.rst
@@ -141,6 +141,15 @@ Runtime Configuration
**A non-zero value for this devarg is mandatory for control path
functionality
when binding ports to uio_pci_generic kernel module which lacks interrupt
support.**
+ * **enable_frag_bypass** (default 0)
+
+ Enable fragment bypass mode for egress packets. This mode bypasses the PPS
+ limit enforced by EC2 for fragmented egress packets on every ENI. Note
that
+ enabling it might negatively impact network performance.
+
+ 0 - Disabled (Default).
+
+ 1 - Enabled.
ENA Configuration Parameters
diff --git a/doc/guides/rel_notes/release_25_07.rst
b/doc/guides/rel_notes/release_25_07.rst
index 467536fe05..07b5feabc4 100644
--- a/doc/guides/rel_notes/release_25_07.rst
+++ b/doc/guides/rel_notes/release_25_07.rst
@@ -55,6 +55,11 @@ New Features
Also, make sure to start the actual text at the margin.
===
+* **Updated Amazon ENA (Elastic Network Adapter) net driver.**
+
+ * Added support for enabling fragment bypass mode for egress packets.
+This mode bypasses the PPS limit enforced by EC2 for fragmented egress
packets on every ENI.
+
* **Added Mucse rnp net driver.**
Added a new network PMD which supports Mucse 10 Gigabit Ethernet NICs.
diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c
index 588dc61387..9715a627c1 100644
--- a/drivers/net/ena/base/ena_com.c
+++ b/drivers/net/ena/base/ena_com.c
@@ -3459,3 +3459,36 @@ int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
return 0;
}
+int ena_com_set_frag_bypass(struct ena_com_dev *ena_dev, bool enable)
+{
+ struct ena_admin_set_feat_resp set_feat_resp;
+ struct ena_com_admin_queue *admin_queue;
+ struct ena_admin_set_feat_cmd cmd;
+ int ret;
+
+ if (!ena_com_check_supported_feature_id(ena_dev,
ENA_ADMIN_FRAG_BYPASS)) {
+ ena_trc_dbg(ena_dev, "Feature %d isn't supported\n",
+ ENA_ADMIN_FRAG_BYPASS);
+ return ENA_COM_UNSUPPORTED;
+ }
+
+ memset(&cmd, 0x0, sizeof(cmd));
+ admin_queue = &ena_dev->admin_queue;
+
+ cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
+ cmd.aq_common_descriptor.flags = 0;
+ cmd.feat_common.feature_id = ENA_ADMIN_FRAG_BYPASS;
+ cmd.feat_common.feature_version =
ENA_ADMIN_FRAG_BYPASS_FEATURE_VERSION_0;
+ cmd.u.frag_bypass.enable = (u8)enable;
+
+ ret = ena_com_execute_admin_command(admin_queue,
+ (struct ena_admin_aq_entry *)&cmd,
+ sizeof(cmd),
+ (struct ena_admin_acq_entry
*)&set_feat_resp,
+ sizeof(set_feat_resp));
+
+ if (unlikely(ret))
+ ena_trc_err(ena_dev, "Failed to enable frag bypass. error:
%d\n", ret);
+
+ return ret;
+}
diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h
index b2aede1be1..f064095fd1 100644
--- a/drivers/net/ena/base/ena_com.h
+++ b/drivers/net/ena/base/ena_com.h
@@ -1109,6 +1109,14 @@ static inline bool
ena_com_get_missing_admin_interrupt(struct ena_com_dev *ena_d
return ena_dev->admin_queue.is_missing_admin_interrupt;
}
+/* ena_com_set_frag_bypass - set fragment bypass
+ * @ena_dev: ENA communication layer struct
+ * @enable: true if fragment bypass is enabled, false otherwise.
+ *
+ * @return - 0 on success, negative value on failure.
+ */
+int ena_com_set_frag_bypass(struct ena_com_dev *ena_dev, bool enable);
+
/* ena_com_io_sq_to_ena_dev - Extract ena_com_dev using contained field io_sq.
* @io_sq: IO submit queue struct
*
diff --git a/drivers/net/ena/base/ena_defs/en
[PATCH v2 5/7] net/ena: fix unhandled interrupt config failure
Fixed the device initialization routine to correctly handle
failure during the registration or enabling of interrupts
when operating in control path interrupt mode.
Fixes: ca1dfa85f0d3 ("net/ena: add control path pure polling mode")
Cc: sta...@dpdk.org
Signed-off-by: Shai Brandes
Reviewed-by: Amit Bernstein
Reviewed-by: Yosef Raisman
---
doc/guides/rel_notes/release_25_07.rst | 2 ++
drivers/net/ena/ena_ethdev.c | 20 ++--
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/doc/guides/rel_notes/release_25_07.rst
b/doc/guides/rel_notes/release_25_07.rst
index 07b5feabc4..e7fecace4f 100644
--- a/doc/guides/rel_notes/release_25_07.rst
+++ b/doc/guides/rel_notes/release_25_07.rst
@@ -59,6 +59,8 @@ New Features
* Added support for enabling fragment bypass mode for egress packets.
This mode bypasses the PPS limit enforced by EC2 for fragmented egress
packets on every ENI.
+ * Fixed the device initialization routine to correctly handle failure during
the registration
+or enabling of interrupts when operating in control path interrupt mode.
* **Added Mucse rnp net driver.**
diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c
index 4caad9006e..f26f08ca85 100644
--- a/drivers/net/ena/ena_ethdev.c
+++ b/drivers/net/ena/ena_ethdev.c
@@ -2465,8 +2465,16 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
if (!adapter->control_path_poll_interval) {
/* Control path interrupt mode */
- rte_intr_callback_register(intr_handle,
ena_control_path_handler, eth_dev);
- rte_intr_enable(intr_handle);
+ rc = rte_intr_callback_register(intr_handle,
ena_control_path_handler, eth_dev);
+ if (unlikely(rc < 0)) {
+ PMD_DRV_LOG_LINE(ERR, "Failed to register control path
interrupt");
+ goto err_stats_destroy;
+ }
+ rc = rte_intr_enable(intr_handle);
+ if (unlikely(rc < 0)) {
+ PMD_DRV_LOG_LINE(ERR, "Failed to enable control path
interrupt");
+ goto err_control_path_destroy;
+ }
ena_com_set_admin_polling_mode(ena_dev, false);
} else {
/* Control path polling mode */
@@ -2485,6 +2493,14 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
return 0;
err_control_path_destroy:
+ if (!adapter->control_path_poll_interval) {
+ rc = rte_intr_callback_unregister_sync(intr_handle,
+ ena_control_path_handler,
+ eth_dev);
+ if (unlikely(rc < 0))
+ PMD_INIT_LOG_LINE(ERR, "Failed to unregister interrupt
handler");
+ }
+err_stats_destroy:
rte_free(adapter->drv_stats);
err_indirect_table_destroy:
ena_indirect_table_release(adapter);
--
2.17.1
[PATCH v2 6/7] net/ena: fix aenq timeout with low poll interval
The driver can work in polling-based functionality of the admin
queue, eliminating the need for interrupts in the control-path.
This mode is mandatory when using the uio_pci_generic driver,
which lacks interrupt support.
The control_path_poll_interval devarg is being set within the range
[1..1000]. A value of 0 disables the polling mechanism.
This value defines the interval in milliseconds at which the driver
checks for asynchronous notifications from the device.
Testing revealed that setting this interval below 500 milliseconds
might lead to false detection of device unresponsiveness.
This patch clamps the user-defined value to the updated valid range
[500..1000] that ensures reliable aenq monitoring.
Fixes: ca1dfa85f0d3 ("net/ena: add control path pure polling mode")
Cc: sta...@dpdk.org
Signed-off-by: Shai Brandes
Reviewed-by: Amit Bernstein
Reviewed-by: Yosef Raisman
---
doc/guides/nics/ena.rst| 4 +++-
doc/guides/rel_notes/release_25_07.rst | 2 ++
drivers/net/ena/ena_ethdev.c | 24 ++--
drivers/net/ena/ena_ethdev.h | 3 ++-
4 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/doc/guides/nics/ena.rst b/doc/guides/nics/ena.rst
index a42deccd81..decb6be766 100644
--- a/doc/guides/nics/ena.rst
+++ b/doc/guides/nics/ena.rst
@@ -136,7 +136,9 @@ Runtime Configuration
0 - Disable (Admin queue will work in interrupt mode).
- [1..1000] - Number of milliseconds to wait between periodic inspection of
the admin queues.
+ [500..1000] – Time in milliseconds to wait between periodic checks of the
admin queues.
+ If a value outside this range is specified, the driver will automatically
adjust it to
+ fit within the valid range.
**A non-zero value for this devarg is mandatory for control path
functionality
when binding ports to uio_pci_generic kernel module which lacks interrupt
support.**
diff --git a/doc/guides/rel_notes/release_25_07.rst
b/doc/guides/rel_notes/release_25_07.rst
index e7fecace4f..662b0db49e 100644
--- a/doc/guides/rel_notes/release_25_07.rst
+++ b/doc/guides/rel_notes/release_25_07.rst
@@ -61,6 +61,8 @@ New Features
This mode bypasses the PPS limit enforced by EC2 for fragmented egress
packets on every ENI.
* Fixed the device initialization routine to correctly handle failure during
the registration
or enabling of interrupts when operating in control path interrupt mode.
+ * Fixed an issue where the device might be incorrectly reported as
unresponsive when using
+polling-based admin queue functionality with a poll interval of less than
500 milliseconds.
* **Added Mucse rnp net driver.**
diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c
index f26f08ca85..182e063bf4 100644
--- a/drivers/net/ena/ena_ethdev.c
+++ b/drivers/net/ena/ena_ethdev.c
@@ -30,6 +30,8 @@
#define GET_L4_HDR_LEN(mbuf) \
((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \
mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
+#define CLAMP_VAL(val, min, max) \
+ (RTE_MIN(RTE_MAX((val), (typeof(val))(min)), (typeof(val))(max)))
#define ETH_GSTRING_LEN32
@@ -3756,25 +3758,19 @@ static int ena_process_uint_devarg(const char *key,
uint64_value * rte_get_timer_hz();
}
} else if (strcmp(key, ENA_DEVARG_CONTROL_PATH_POLL_INTERVAL) == 0) {
- if (uint64_value > ENA_MAX_CONTROL_PATH_POLL_INTERVAL_MSEC) {
- PMD_INIT_LOG_LINE(ERR,
- "Control path polling interval is too long: %"
PRIu64 " msecs. "
- "Maximum allowed: %d msecs.",
- uint64_value,
ENA_MAX_CONTROL_PATH_POLL_INTERVAL_MSEC);
- return -EINVAL;
- } else if (uint64_value == 0) {
+ if (uint64_value == 0) {
PMD_INIT_LOG_LINE(INFO,
- "Control path polling interval is set to zero.
Operating in "
- "interrupt mode.");
- adapter->control_path_poll_interval = 0;
+ "Control path polling is disabled - Operating
in interrupt mode");
} else {
+ uint64_value = CLAMP_VAL(uint64_value,
+ ENA_MIN_CONTROL_PATH_POLL_INTERVAL_MSEC,
+ ENA_MAX_CONTROL_PATH_POLL_INTERVAL_MSEC);
PMD_INIT_LOG_LINE(INFO,
- "Control path polling interval is set to %"
PRIu64 " msecs.",
+ "Control path polling interval is %" PRIu64 "
msec",
uint64_value);
- adapter->control_path_poll_interval =
uint64_value * USEC_PER_MSEC;
[PATCH v3 2/7] net/ena/base: coding style changes
Reordered variable declarations to follow the
reverse Christmas tree style.
Signed-off-by: Shai Brandes
Reviewed-by: Amit Bernstein
Reviewed-by: Yosef Raisman
---
drivers/net/ena/base/ena_com.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c
index 238716de29..588dc61387 100644
--- a/drivers/net/ena/base/ena_com.c
+++ b/drivers/net/ena/base/ena_com.c
@@ -308,8 +308,8 @@ static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct
ena_com_admin_queue
struct ena_admin_acq_entry
*comp,
size_t comp_size_in_bytes)
{
- unsigned long flags = 0;
struct ena_comp_ctx *comp_ctx;
+ unsigned long flags = 0;
ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
if (unlikely(!admin_queue->running_state)) {
@@ -616,10 +616,10 @@ static int
ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_c
*/
static int ena_com_set_llq(struct ena_com_dev *ena_dev)
{
+ struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
struct ena_com_admin_queue *admin_queue;
- struct ena_admin_set_feat_cmd cmd;
struct ena_admin_set_feat_resp resp;
- struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
+ struct ena_admin_set_feat_cmd cmd;
int ret;
memset(&cmd, 0x0, sizeof(cmd));
--
2.17.1
Re: [RFC v2 3/6] dts: add asynchronous support to ssh sessions.
Reviewed-by: Dean Marx
Re: [RFC v2 4/6] dts: add extended timeout option to interactive shells.
Reviewed-by: Dean Marx
[PATCH v2] fix eal/linux: unregister alarm callback before free
This was flagged by Address sanitizer as a use after free. The
intr_handle ptr is shared between the main thread and the interrupt
thread. The interrupt thread can dereference the ptr after free (from
the alarm callback). free is called when the main thread cleans up.
The interrupt thread never terminates (eal_intr_thread_main) so
use rte_intr_callback_unregister_sync during cleanup to
ensure the callback is removed before freeing the ptr.
To be more defensive clear out the pointer and registration
variable if we can unregister.
rte_intr_callback_unregister_sync may (optionally) use traces
so the alarm cleanup must happen before eal_trace_fini to avoid
accessing freed memory.
Bugzilla ID: 1683
Signed-off-by: Rui Ferreira
---
.mailmap | 1 +
lib/eal/linux/eal.c | 3 ++-
lib/eal/linux/eal_alarm.c | 9 -
3 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/.mailmap b/.mailmap
index d8439b79ce..907c5ea967 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1332,6 +1332,7 @@ Rosen Xu
Roy Franz
Roy Pledge
Roy Shterman
+Rui Ferreira
Ruifeng Wang
Rushil Gupta
Ryan E Hall
diff --git a/lib/eal/linux/eal.c b/lib/eal/linux/eal.c
index 20f777b8b0..b448db1392 100644
--- a/lib/eal/linux/eal.c
+++ b/lib/eal/linux/eal.c
@@ -1329,9 +1329,10 @@ rte_eal_cleanup(void)
rte_mp_channel_cleanup();
eal_bus_cleanup();
rte_trace_save();
+ /* may use trace, must be called before eal_trace_fini */
+ rte_eal_alarm_cleanup();
eal_trace_fini();
eal_mp_dev_hotplug_cleanup();
- rte_eal_alarm_cleanup();
/* after this point, any DPDK pointers will become dangling */
rte_eal_memory_detach();
rte_eal_malloc_heap_cleanup();
diff --git a/lib/eal/linux/eal_alarm.c b/lib/eal/linux/eal_alarm.c
index b216a007a3..eb6a21d4f0 100644
--- a/lib/eal/linux/eal_alarm.c
+++ b/lib/eal/linux/eal_alarm.c
@@ -57,7 +57,14 @@ static void eal_alarm_callback(void *arg);
void
rte_eal_alarm_cleanup(void)
{
- rte_intr_instance_free(intr_handle);
+ /* unregister callback using intr_handle in interrupt thread */
+ int ret = rte_intr_callback_unregister_sync(intr_handle,
+ eal_alarm_callback, (void *)-1);
+ if (ret >= 0) {
+ rte_intr_instance_free(intr_handle);
+ intr_handle = NULL;
+ handler_registered = 0;
+ }
}
int
--
2.35.3
Re: [dpdk-dev] Regarding HQOS with run-to-completion Model
On Thu, 22 May 2025 08:15:14 +0530 farooq basha wrote: > Thanks Stephen for addressing my queries , and it is helpful. > > One more follow up question on the same , Can DPDK HQOS be customized > based on Use case ? > > For example: Hqos config for one of the use cases , *One Port , One > Subport , 16 Pipes & Each Pipe with only one TC*. > 16 pipe config was allowed but changing the 13TCs > to 1TC is not allowed per Pipe. > > Can I still use 13 TCs but use the QueueSize as 0, Can that impact > performance ? > No. Current qos sched code has hard coded assumptions on number of pipes etc. I think it is modeled after some carrier standard and is not generally that useful.
Re: [RFC v2 6/6] dts: add performance test functions to test suite api
Reviewed-by: Dean Marx
[DPDK/core Bug 1711] Warnings from unaligned access on 32 bit build
https://bugs.dpdk.org/show_bug.cgi?id=1711 Bug ID: 1711 Summary: Warnings from unaligned access on 32 bit build Product: DPDK Version: unspecified Hardware: All OS: All Status: UNCONFIRMED Severity: minor Priority: Normal Component: core Assignee: dev@dpdk.org Reporter: step...@networkplumber.org Target Milestone: --- Created attachment 316 --> https://bugs.dpdk.org/attachment.cgi?id=316&action=edit Build output with clang 32 bit Building 32 bit with clang produces these warnings about atomic operations on 8 bit values that are not properly aligned. Doing atomic on unaligned is possible but slow on 32 bit x86 but may not work at all on other platforms like Arm. -- You are receiving this mail because: You are the assignee for the bug.
[PATCH v6 1/9] crypto/zsda: add skeleton
Add crypto driver skeleton for zsda devices.
Signed-off-by: Hanxiao Li
---
MAINTAINERS | 6 ++
doc/guides/cryptodevs/index.rst | 1 +
doc/guides/cryptodevs/zsda.rst| 26 ++
drivers/common/zsda/meson.build | 12 ++-
drivers/common/zsda/zsda_device.c | 14 +++-
drivers/common/zsda/zsda_device.h | 10 +++
drivers/common/zsda/zsda_qp.c | 9 ++
drivers/common/zsda/zsda_qp_common.h | 5 +-
drivers/crypto/zsda/zsda_crypto_pmd.c | 115 ++
drivers/crypto/zsda/zsda_crypto_pmd.h | 49 +++
10 files changed, 244 insertions(+), 3 deletions(-)
create mode 100644 doc/guides/cryptodevs/zsda.rst
create mode 100644 drivers/crypto/zsda/zsda_crypto_pmd.c
create mode 100644 drivers/crypto/zsda/zsda_crypto_pmd.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 167cc74a15..3e16789250 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1270,6 +1270,12 @@ F: drivers/crypto/virtio/
F: doc/guides/cryptodevs/virtio.rst
F: doc/guides/cryptodevs/features/virtio.ini
+ZTE Storage Data Accelerator (ZSDA)
+M: Hanxiao Li
+F: drivers/crypto/zsda/
+F: doc/guides/cryptodevs/zsda.rst
+F: doc/guides/cryptodevs/features/zsda.ini
+
Compression Drivers
---
diff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst
index 1e57a9fe86..be2620f185 100644
--- a/doc/guides/cryptodevs/index.rst
+++ b/doc/guides/cryptodevs/index.rst
@@ -34,3 +34,4 @@ Crypto Device Drivers
uadk
virtio
zuc
+zsda
diff --git a/doc/guides/cryptodevs/zsda.rst b/doc/guides/cryptodevs/zsda.rst
new file mode 100644
index 00..0a7aeb2d50
--- /dev/null
+++ b/doc/guides/cryptodevs/zsda.rst
@@ -0,0 +1,26 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+Copyright(c) 2025 ZTE Corporation.
+
+ZTE Storage Data Accelerator (ZSDA) Poll Mode Driver
+
+
+The ZSDA crypto PMD provides poll mode Cipher and Hash driver
+support for the following hardware accelerator devices:
+
+* ``ZTE Processing accelerators 1cf2``
+
+
+Features
+
+
+
+Limitations
+---
+
+
+Installation
+
+
+
+Testing
+---
diff --git a/drivers/common/zsda/meson.build b/drivers/common/zsda/meson.build
index be4fbaedb3..e897c3a931 100644
--- a/drivers/common/zsda/meson.build
+++ b/drivers/common/zsda/meson.build
@@ -7,7 +7,7 @@ if is_windows
subdir_done()
endif
-deps += ['bus_pci', 'mbuf', 'compressdev']
+deps += ['bus_pci', 'compressdev', 'cryptodev']
sources += files(
'zsda_device.c',
'zsda_logs.c',
@@ -24,3 +24,13 @@ if zsda_compress
sources += files(join_paths(zsda_compress_relpath, f))
endforeach
endif
+
+zsda_crypto = true
+zsda_crypto_path = 'crypto/zsda'
+zsda_crypto_relpath = '../../' + zsda_crypto_path
+includes += include_directories(zsda_crypto_relpath)
+if zsda_crypto
+foreach f: ['zsda_crypto_pmd.c']
+sources += files(join_paths(zsda_crypto_relpath, f))
+endforeach
+endif
diff --git a/drivers/common/zsda/zsda_device.c
b/drivers/common/zsda/zsda_device.c
index 8a89dc7fc9..0d1e772fe4 100644
--- a/drivers/common/zsda/zsda_device.c
+++ b/drivers/common/zsda/zsda_device.c
@@ -152,6 +152,7 @@ zsda_pci_dev_destroy(struct zsda_pci_device *zsda_pci_dev,
{
zsda_comp_dev_destroy(zsda_pci_dev);
+ zsda_crypto_dev_destroy(zsda_pci_dev);
return zsda_pci_device_release(pci_dev);
}
@@ -177,9 +178,20 @@ zsda_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
ret = zsda_comp_dev_create(zsda_pci_dev);
if (ret)
- ZSDA_LOG(ERR, "Failed! dev create.");
+ ZSDA_LOG(ERR, "Failed! comp_dev create.");
+
+ ret = zsda_crypto_dev_create(zsda_pci_dev);
+ if (ret) {
+ ZSDA_LOG(ERR, "Failed! crypto_dev create.");
+ goto exit;
+ }
return ret;
+
+exit:
+ zsda_comp_dev_destroy(zsda_pci_dev);
+
+ return ZSDA_FAILED;
}
static int
diff --git a/drivers/common/zsda/zsda_device.h
b/drivers/common/zsda/zsda_device.h
index dd0fa35ba6..036e157b8d 100644
--- a/drivers/common/zsda/zsda_device.h
+++ b/drivers/common/zsda/zsda_device.h
@@ -7,6 +7,7 @@
#include "zsda_qp_common.h"
#include "zsda_comp_pmd.h"
+#include "zsda_crypto_pmd.h"
#define MAX_QPS_ON_FUNCTION128
#define ZSDA_DEV_NAME_MAX_LEN 64
@@ -21,6 +22,11 @@ struct zsda_device_info {
* Register with this rather than with the one in
* pci_dev so that its driver can have a compression-specific name
*/
+ struct rte_device crypto_rte_dev;
+ /**< This represents the crypto subset of this pci device.
+* Register with this rather than with the one in
+* pci_dev so that its driver can have a crypto-specific name
+*/
struct rte_pci_device *pci_dev;
};
@@ -52,6 +58,10 @@ struct zsda_pci_device {
struct zsda_comp_dev_private *comp_dev;
[PATCH v6 7/9] crypto/zsda: add dequeue datapath
Add crypto dequeue datapath configuration for zsda device.
Signed-off-by: Hanxiao Li
---
drivers/crypto/zsda/zsda_crypto.c | 16
drivers/crypto/zsda/zsda_crypto.h | 2 ++
drivers/crypto/zsda/zsda_crypto_pmd.c | 12 ++--
3 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/crypto/zsda/zsda_crypto.c
b/drivers/crypto/zsda/zsda_crypto.c
index 65303af663..8bf3eca14f 100644
--- a/drivers/crypto/zsda/zsda_crypto.c
+++ b/drivers/crypto/zsda/zsda_crypto.c
@@ -254,3 +254,19 @@ zsda_hash_wqe_build(void *op_in, const struct zsda_queue
*queue,
return ret;
}
+
+int
+zsda_crypto_callback(void *cookie_in, struct zsda_cqe *cqe)
+{
+ struct zsda_op_cookie *tmp_cookie = cookie_in;
+ struct rte_crypto_op *op = tmp_cookie->op;
+
+ if (!(CQE_ERR0(cqe->err0) || CQE_ERR1(cqe->err1)))
+ op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
+ else {
+ op->status = RTE_CRYPTO_OP_STATUS_ERROR;
+ return ZSDA_FAILED;
+ }
+
+ return ZSDA_SUCCESS;
+}
diff --git a/drivers/crypto/zsda/zsda_crypto.h
b/drivers/crypto/zsda/zsda_crypto.h
index 17efa8c60f..1ebcbd42c9 100644
--- a/drivers/crypto/zsda/zsda_crypto.h
+++ b/drivers/crypto/zsda/zsda_crypto.h
@@ -42,4 +42,6 @@ int zsda_crypto_wqe_build(void *op_in, const struct
zsda_queue *queue,
int zsda_hash_wqe_build(void *op_in, const struct zsda_queue *queue,
void **op_cookies, const uint16_t new_tail);
+int zsda_crypto_callback(void *cookie_in, struct zsda_cqe *cqe);
+
#endif /* _ZSDA_CRYPTO_H_ */
diff --git a/drivers/crypto/zsda/zsda_crypto_pmd.c
b/drivers/crypto/zsda/zsda_crypto_pmd.c
index 6e60c1ff83..f86d1115f4 100644
--- a/drivers/crypto/zsda/zsda_crypto_pmd.c
+++ b/drivers/crypto/zsda/zsda_crypto_pmd.c
@@ -143,7 +143,7 @@ zsda_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,
task_q_info.nb_des = nb_des;
task_q_info.socket_id = socket_id;
task_q_info.qp_id = qp_id;
- task_q_info.rx_cb = NULL;
+ task_q_info.rx_cb = zsda_crypto_callback;
task_q_info.type = ZSDA_SERVICE_CRYPTO_ENCRY;
task_q_info.service_str = "encry";
@@ -243,6 +243,14 @@ zsda_crypto_enqueue_op_burst(void *qp, struct
rte_crypto_op **ops,
nb_ops);
}
+static uint16_t
+zsda_crypto_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
+ uint16_t nb_ops)
+{
+ return zsda_dequeue_burst((struct zsda_qp *)qp, (void **)ops,
+nb_ops);
+}
+
int
zsda_crypto_dev_create(struct zsda_pci_device *zsda_pci_dev)
{
@@ -283,7 +291,7 @@ zsda_crypto_dev_create(struct zsda_pci_device *zsda_pci_dev)
cryptodev->dev_ops = &crypto_zsda_ops;
cryptodev->enqueue_burst = zsda_crypto_enqueue_op_burst;
- cryptodev->dequeue_burst = NULL;
+ cryptodev->dequeue_burst = zsda_crypto_dequeue_op_burst;
cryptodev->feature_flags = 0;
crypto_dev_priv = cryptodev->data->dev_private;
--
2.27.0
[PATCH v6 3/9] crypto/zsda: add statistics
Add crypto statistics operations for zsda devices.
Signed-off-by: Hanxiao Li
---
drivers/crypto/zsda/zsda_crypto_pmd.c | 24 ++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/crypto/zsda/zsda_crypto_pmd.c
b/drivers/crypto/zsda/zsda_crypto_pmd.c
index 04c4e45843..8b44ebe61f 100644
--- a/drivers/crypto/zsda/zsda_crypto_pmd.c
+++ b/drivers/crypto/zsda/zsda_crypto_pmd.c
@@ -78,6 +78,26 @@ zsda_dev_info_get(struct rte_cryptodev *dev,
}
}
+static void
+zsda_crypto_stats_get(struct rte_cryptodev *dev, struct rte_cryptodev_stats
*stats)
+{
+ struct zsda_qp_stat comm = {0};
+
+ zsda_stats_get(dev->data->queue_pairs, dev->data->nb_queue_pairs,
+ &comm);
+ stats->enqueued_count = comm.enqueued_count;
+ stats->dequeued_count = comm.dequeued_count;
+ stats->enqueue_err_count = comm.enqueue_err_count;
+ stats->dequeue_err_count = comm.dequeue_err_count;
+}
+
+static void
+zsda_crypto_stats_reset(struct rte_cryptodev *dev)
+{
+ zsda_stats_reset(dev->data->queue_pairs, dev->data->nb_queue_pairs);
+}
+
+
static struct rte_cryptodev_ops crypto_zsda_ops = {
.dev_configure = zsda_dev_config,
.dev_start = zsda_dev_start,
@@ -85,8 +105,8 @@ static struct rte_cryptodev_ops crypto_zsda_ops = {
.dev_close = zsda_dev_close,
.dev_infos_get = zsda_dev_info_get,
- .stats_get = NULL,
- .stats_reset = NULL,
+ .stats_get = zsda_crypto_stats_get,
+ .stats_reset = zsda_crypto_stats_reset,
.queue_pair_setup = NULL,
.queue_pair_release = NULL,
--
2.27.0
[PATCH v6 5/9] crypto/zsda: add session configuration
Add crypto session configuration for zsda device.
Signed-off-by: Hanxiao Li
---
drivers/common/zsda/meson.build | 2 +-
drivers/crypto/zsda/zsda_crypto_pmd.c | 45 +-
drivers/crypto/zsda/zsda_crypto_session.c | 498 ++
drivers/crypto/zsda/zsda_crypto_session.h | 78
4 files changed, 619 insertions(+), 4 deletions(-)
create mode 100644 drivers/crypto/zsda/zsda_crypto_session.c
create mode 100644 drivers/crypto/zsda/zsda_crypto_session.h
diff --git a/drivers/common/zsda/meson.build b/drivers/common/zsda/meson.build
index e897c3a931..f2d1e29c7a 100644
--- a/drivers/common/zsda/meson.build
+++ b/drivers/common/zsda/meson.build
@@ -30,7 +30,7 @@ zsda_crypto_path = 'crypto/zsda'
zsda_crypto_relpath = '../../' + zsda_crypto_path
includes += include_directories(zsda_crypto_relpath)
if zsda_crypto
-foreach f: ['zsda_crypto_pmd.c']
+foreach f: ['zsda_crypto_pmd.c', 'zsda_crypto_session.c']
sources += files(join_paths(zsda_crypto_relpath, f))
endforeach
endif
diff --git a/drivers/crypto/zsda/zsda_crypto_pmd.c
b/drivers/crypto/zsda/zsda_crypto_pmd.c
index 001ea56520..6e7d1c241d 100644
--- a/drivers/crypto/zsda/zsda_crypto_pmd.c
+++ b/drivers/crypto/zsda/zsda_crypto_pmd.c
@@ -5,6 +5,7 @@
#include
#include "zsda_crypto_pmd.h"
+#include "zsda_crypto_session.h"
uint8_t zsda_crypto_driver_id;
@@ -172,6 +173,44 @@ zsda_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,
return ret;
}
+static unsigned int
+zsda_sym_session_private_size_get(struct rte_cryptodev *dev __rte_unused)
+{
+ return RTE_ALIGN_CEIL(sizeof(struct zsda_sym_session), 8);
+}
+
+static int
+zsda_sym_session_configure(struct rte_cryptodev *dev __rte_unused,
+ struct rte_crypto_sym_xform *xform,
+ struct rte_cryptodev_sym_session *sess)
+{
+ void *sess_private_data;
+ int ret;
+
+ if (unlikely(sess == NULL)) {
+ ZSDA_LOG(ERR, "Invalid session struct");
+ return -EINVAL;
+ }
+
+ sess_private_data = CRYPTODEV_GET_SYM_SESS_PRIV(sess);
+
+ ret = zsda_crypto_session_parameters_set(
+ sess_private_data, xform);
+
+ if (ret != ZSDA_SUCCESS)
+ ZSDA_LOG(ERR, "Failed configure session parameters");
+
+ return ret;
+}
+
+static void
+zsda_sym_session_clear(struct rte_cryptodev *dev __rte_unused,
+ struct rte_cryptodev_sym_session *sess)
+{
+ struct zsda_sym_session *sess_priv = CRYPTODEV_GET_SYM_SESS_PRIV(sess);
+ memset(sess_priv, 0, sizeof(struct zsda_sym_session));
+}
+
static struct rte_cryptodev_ops crypto_zsda_ops = {
.dev_configure = zsda_dev_config,
.dev_start = zsda_dev_start,
@@ -184,9 +223,9 @@ static struct rte_cryptodev_ops crypto_zsda_ops = {
.queue_pair_setup = zsda_qp_setup,
.queue_pair_release = zsda_qp_release,
- .sym_session_get_size = NULL,
- .sym_session_configure = NULL,
- .sym_session_clear = NULL,
+ .sym_session_get_size = zsda_sym_session_private_size_get,
+ .sym_session_configure = zsda_sym_session_configure,
+ .sym_session_clear = zsda_sym_session_clear,
};
static const char zsda_crypto_drv_name[] = RTE_STR(CRYPTODEV_NAME_ZSDA_PMD);
diff --git a/drivers/crypto/zsda/zsda_crypto_session.c
b/drivers/crypto/zsda/zsda_crypto_session.c
new file mode 100644
index 00..5087ae248a
--- /dev/null
+++ b/drivers/crypto/zsda/zsda_crypto_session.c
@@ -0,0 +1,498 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2025 ZTE Corporation
+ */
+
+#include "cryptodev_pmd.h"
+#include "rte_byteorder.h"
+
+#include "zsda_crypto_pmd.h"
+#include "zsda_crypto_session.h"
+
+/ AES KEY EXPANSION /
+/**
+ * AES S-boxes
+ * Sbox table: 8bits input convert to 8bits output
+ **/
+static const unsigned char aes_sbox[256] = {
+ /* 0 12 3 45 6 7 89 A B
+* C DE F
+*/
+ 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b,
+ 0xfe, 0xd7, 0xab, 0x76, 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0,
+ 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, 0xb7, 0xfd, 0x93, 0x26,
+ 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,
+ 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2,
+ 0xeb, 0x27, 0xb2, 0x75, 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0,
+ 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, 0x53, 0xd1, 0x00, 0xed,
+ 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
+ 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f,
+ 0x50, 0x3c, 0x9f, 0xa8, 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5,
+ 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, 0xcd, 0x0c, 0x13, 0xec,
+ 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x
[PATCH v6 6/9] crypto/zsda: add enqueue datapath
Add crypto enqueue datapath configuration for zsda device.
Signed-off-by: Hanxiao Li
---
drivers/common/zsda/meson.build | 2 +-
drivers/crypto/zsda/zsda_crypto.c | 256 ++
drivers/crypto/zsda/zsda_crypto.h | 45 +
drivers/crypto/zsda/zsda_crypto_pmd.c | 23 ++-
4 files changed, 318 insertions(+), 8 deletions(-)
create mode 100644 drivers/crypto/zsda/zsda_crypto.c
create mode 100644 drivers/crypto/zsda/zsda_crypto.h
diff --git a/drivers/common/zsda/meson.build b/drivers/common/zsda/meson.build
index f2d1e29c7a..ac942b7bb9 100644
--- a/drivers/common/zsda/meson.build
+++ b/drivers/common/zsda/meson.build
@@ -30,7 +30,7 @@ zsda_crypto_path = 'crypto/zsda'
zsda_crypto_relpath = '../../' + zsda_crypto_path
includes += include_directories(zsda_crypto_relpath)
if zsda_crypto
-foreach f: ['zsda_crypto_pmd.c', 'zsda_crypto_session.c']
+foreach f: ['zsda_crypto_pmd.c', 'zsda_crypto_session.c', 'zsda_crypto.c']
sources += files(join_paths(zsda_crypto_relpath, f))
endforeach
endif
diff --git a/drivers/crypto/zsda/zsda_crypto.c
b/drivers/crypto/zsda/zsda_crypto.c
new file mode 100644
index 00..65303af663
--- /dev/null
+++ b/drivers/crypto/zsda/zsda_crypto.c
@@ -0,0 +1,256 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2025 ZTE Corporation
+ */
+
+#include "zsda_crypto.h"
+
+#define choose_dst_mbuf(mbuf_src, mbuf_dst) ((mbuf_dst) == NULL ? (mbuf_src) :
(mbuf_dst))
+#define LBADS_MAX_REMAINDER (16 - 1)
+
+int
+zsda_encry_match(const void *op_in)
+{
+ const struct rte_crypto_op *op = op_in;
+ struct rte_cryptodev_sym_session *session = op->sym->session;
+ struct zsda_sym_session *sess =
+ (struct zsda_sym_session *)session->driver_priv_data;
+
+ if (sess->chain_order == ZSDA_SYM_CHAIN_ONLY_CIPHER &&
+ sess->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
+ return 1;
+ else
+ return 0;
+}
+
+int
+zsda_decry_match(const void *op_in)
+{
+ const struct rte_crypto_op *op = op_in;
+ struct rte_cryptodev_sym_session *session = op->sym->session;
+ struct zsda_sym_session *sess =
+ (struct zsda_sym_session *)session->driver_priv_data;
+
+ if (sess->chain_order == ZSDA_SYM_CHAIN_ONLY_CIPHER &&
+ sess->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT)
+ return 1;
+ else
+ return 0;
+}
+
+int
+zsda_hash_match(const void *op_in)
+{
+ const struct rte_crypto_op *op = op_in;
+ struct rte_cryptodev_sym_session *session = op->sym->session;
+ struct zsda_sym_session *sess =
+ (struct zsda_sym_session *)session->driver_priv_data;
+
+ if (sess->chain_order == ZSDA_SYM_CHAIN_ONLY_AUTH)
+ return 1;
+ else
+ return 0;
+}
+
+static uint8_t
+zsda_opcode_hash_get(struct zsda_sym_session *sess)
+{
+ switch (sess->auth.algo) {
+ case RTE_CRYPTO_AUTH_SHA1:
+ return ZSDA_OPC_HASH_SHA1;
+
+ case RTE_CRYPTO_AUTH_SHA224:
+ return ZSDA_OPC_HASH_SHA2_224;
+
+ case RTE_CRYPTO_AUTH_SHA256:
+ return ZSDA_OPC_HASH_SHA2_256;
+
+ case RTE_CRYPTO_AUTH_SHA384:
+ return ZSDA_OPC_HASH_SHA2_384;
+
+ case RTE_CRYPTO_AUTH_SHA512:
+ return ZSDA_OPC_HASH_SHA2_512;
+
+ case RTE_CRYPTO_AUTH_SM3:
+ return ZSDA_OPC_HASH_SM3;
+ default:
+ break;
+ }
+
+ return ZSDA_OPC_INVALID;
+}
+
+static uint8_t
+zsda_opcode_crypto_get(struct zsda_sym_session *sess)
+{
+ if (sess->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) {
+ if (sess->cipher.algo == RTE_CRYPTO_CIPHER_AES_XTS &&
+ sess->cipher.key_encry.length == 32)
+ return ZSDA_OPC_EC_AES_XTS_256;
+ else if (sess->cipher.algo == RTE_CRYPTO_CIPHER_AES_XTS &&
+sess->cipher.key_encry.length == 64)
+ return ZSDA_OPC_EC_AES_XTS_512;
+ else if (sess->cipher.algo == RTE_CRYPTO_CIPHER_SM4_XTS)
+ return ZSDA_OPC_EC_SM4_XTS_256;
+ } else if (sess->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT) {
+ if (sess->cipher.algo == RTE_CRYPTO_CIPHER_AES_XTS &&
+ sess->cipher.key_decry.length == 32)
+ return ZSDA_OPC_DC_AES_XTS_256;
+ else if (sess->cipher.algo == RTE_CRYPTO_CIPHER_AES_XTS &&
+sess->cipher.key_decry.length == 64)
+ return ZSDA_OPC_DC_AES_XTS_512;
+ else if (sess->cipher.algo == RTE_CRYPTO_CIPHER_SM4_XTS)
+ return ZSDA_OPC_DC_SM4_XTS_256;
+ }
+ return ZSDA_OPC_INVALID;
+}
+
+static int
+zsda_len_lbads_chk(uint32_t data_len, uint32_t lbads_size)
+{
+ if (data_len < 16) {
+ ZSDA_LOG(ERR, "data_len wrong data_len 0x%x!", data_len);
+
[PATCH v6 0/9] crypto/zsda: add zsda cryptodev driver
v6: - Modify the code according to the advise v5: - Modify the code according to the advise v4: - change some "sym" to "crypto". v3: - Modify the code according to the advise v2: - Modify the errors about cryptodevs/zsda.rst. - Modify the errors about author. v1: - Add zsda cryptodev driver. Hanxiao Li (9): crypto/zsda: add skeleton crypto/zsda: add device operations crypto/zsda: add statistics crypto/zsda: add queue pair configuration crypto/zsda: add session configuration crypto/zsda: add enqueue datapath crypto/zsda: add dequeue datapath crypto/zsda: add capabilities app/test: add zsda cryptodev test MAINTAINERS | 6 + app/test/test_cryptodev.c | 7 + app/test/test_cryptodev.h | 1 + doc/guides/cryptodevs/features/zsda.ini | 51 ++ doc/guides/cryptodevs/index.rst | 1 + doc/guides/cryptodevs/zsda.rst| 58 ++ doc/guides/rel_notes/release_25_07.rst| 8 + drivers/common/zsda/meson.build | 12 +- drivers/common/zsda/zsda_device.c | 14 +- drivers/common/zsda/zsda_device.h | 10 + drivers/common/zsda/zsda_qp.c | 9 + drivers/common/zsda/zsda_qp_common.h | 5 +- drivers/crypto/zsda/zsda_crypto.c | 272 ++ drivers/crypto/zsda/zsda_crypto.h | 47 ++ .../crypto/zsda/zsda_crypto_capabilities.h| 111 drivers/crypto/zsda/zsda_crypto_pmd.c | 364 + drivers/crypto/zsda/zsda_crypto_pmd.h | 49 ++ drivers/crypto/zsda/zsda_crypto_session.c | 498 ++ drivers/crypto/zsda/zsda_crypto_session.h | 78 +++ 19 files changed, 1598 insertions(+), 3 deletions(-) create mode 100644 doc/guides/cryptodevs/features/zsda.ini create mode 100644 doc/guides/cryptodevs/zsda.rst create mode 100644 drivers/crypto/zsda/zsda_crypto.c create mode 100644 drivers/crypto/zsda/zsda_crypto.h create mode 100644 drivers/crypto/zsda/zsda_crypto_capabilities.h create mode 100644 drivers/crypto/zsda/zsda_crypto_pmd.c create mode 100644 drivers/crypto/zsda/zsda_crypto_pmd.h create mode 100644 drivers/crypto/zsda/zsda_crypto_session.c create mode 100644 drivers/crypto/zsda/zsda_crypto_session.h -- 2.27.0
[PATCH v6 4/9] crypto/zsda: add queue pair configuration
Add crypto queue pair configuration operations for zsda device.
Signed-off-by: Hanxiao Li
---
drivers/crypto/zsda/zsda_crypto_pmd.c | 80 ++-
1 file changed, 77 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/zsda/zsda_crypto_pmd.c
b/drivers/crypto/zsda/zsda_crypto_pmd.c
index 8b44ebe61f..001ea56520 100644
--- a/drivers/crypto/zsda/zsda_crypto_pmd.c
+++ b/drivers/crypto/zsda/zsda_crypto_pmd.c
@@ -35,9 +35,20 @@ zsda_dev_stop(struct rte_cryptodev *dev)
}
static int
-zsda_dev_close(struct rte_cryptodev *dev __rte_unused)
+zsda_qp_release(struct rte_cryptodev *dev, uint16_t queue_pair_id)
+{
+ return zsda_queue_pair_release(
+ (struct zsda_qp **)&(dev->data->queue_pairs[queue_pair_id]));
+}
+
+static int
+zsda_dev_close(struct rte_cryptodev *dev)
{
int ret = ZSDA_SUCCESS;
+ uint16_t i;
+
+ for (i = 0; i < dev->data->nb_queue_pairs; i++)
+ ret |= zsda_qp_release(dev, i);
return ret;
}
@@ -98,6 +109,69 @@ zsda_crypto_stats_reset(struct rte_cryptodev *dev)
}
+static int
+zsda_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,
+ const struct rte_cryptodev_qp_conf *qp_conf,
+ int socket_id)
+{
+ int ret = ZSDA_SUCCESS;
+ struct zsda_qp *qp_new;
+ struct zsda_qp **qp_addr =
+ (struct zsda_qp **)&(dev->data->queue_pairs[qp_id]);
+ struct zsda_crypto_dev_private *crypto_dev_priv =
dev->data->dev_private;
+ struct zsda_pci_device *zsda_pci_dev = crypto_dev_priv->zsda_pci_dev;
+ uint32_t nb_des = qp_conf->nb_descriptors;
+ struct task_queue_info task_q_info;
+
+ nb_des = (nb_des == NB_DES) ? nb_des : NB_DES;
+
+ if (*qp_addr != NULL) {
+ ret = zsda_qp_release(dev, qp_id);
+ if (ret)
+ return ret;
+ }
+
+ qp_new = rte_zmalloc_socket("zsda PMD qp metadata", sizeof(*qp_new),
+ RTE_CACHE_LINE_SIZE, socket_id);
+ if (qp_new == NULL) {
+ ZSDA_LOG(ERR, "Failed to alloc mem for qp struct");
+ return -ENOMEM;
+ }
+
+ task_q_info.nb_des = nb_des;
+ task_q_info.socket_id = socket_id;
+ task_q_info.qp_id = qp_id;
+ task_q_info.rx_cb = NULL;
+
+ task_q_info.type = ZSDA_SERVICE_CRYPTO_ENCRY;
+ task_q_info.service_str = "encry";
+ task_q_info.tx_cb = NULL;
+ task_q_info.match = NULL;
+ ret = zsda_task_queue_setup(zsda_pci_dev, qp_new, &task_q_info);
+
+ task_q_info.type = ZSDA_SERVICE_CRYPTO_DECRY;
+ task_q_info.service_str = "decry";
+ task_q_info.tx_cb = NULL;
+ task_q_info.match = NULL;
+ ret |= zsda_task_queue_setup(zsda_pci_dev, qp_new, &task_q_info);
+
+ task_q_info.type = ZSDA_SERVICE_HASH_ENCODE;
+ task_q_info.service_str = "hash";
+ task_q_info.tx_cb = NULL;
+ task_q_info.match = NULL;
+ ret |= zsda_task_queue_setup(zsda_pci_dev, qp_new, &task_q_info);
+
+ if (ret) {
+ ZSDA_LOG(ERR, "zsda_task_queue_setup crypto is failed!");
+ rte_free(qp_new);
+ return ret;
+ }
+
+ *qp_addr = qp_new;
+
+ return ret;
+}
+
static struct rte_cryptodev_ops crypto_zsda_ops = {
.dev_configure = zsda_dev_config,
.dev_start = zsda_dev_start,
@@ -107,8 +181,8 @@ static struct rte_cryptodev_ops crypto_zsda_ops = {
.stats_get = zsda_crypto_stats_get,
.stats_reset = zsda_crypto_stats_reset,
- .queue_pair_setup = NULL,
- .queue_pair_release = NULL,
+ .queue_pair_setup = zsda_qp_setup,
+ .queue_pair_release = zsda_qp_release,
.sym_session_get_size = NULL,
.sym_session_configure = NULL,
--
2.27.0
[PATCH v6 8/9] crypto/zsda: add capabilities
Add crypto capabilities scope for zsda device.
Signed-off-by: Hanxiao Li
---
doc/guides/cryptodevs/features/zsda.ini | 51
doc/guides/cryptodevs/zsda.rst| 26
doc/guides/rel_notes/release_25_07.rst| 8 ++
.../crypto/zsda/zsda_crypto_capabilities.h| 111 ++
drivers/crypto/zsda/zsda_crypto_pmd.c | 29 -
5 files changed, 224 insertions(+), 1 deletion(-)
create mode 100644 doc/guides/cryptodevs/features/zsda.ini
create mode 100644 drivers/crypto/zsda/zsda_crypto_capabilities.h
diff --git a/doc/guides/cryptodevs/features/zsda.ini
b/doc/guides/cryptodevs/features/zsda.ini
new file mode 100644
index 00..b0f10f8de9
--- /dev/null
+++ b/doc/guides/cryptodevs/features/zsda.ini
@@ -0,0 +1,51 @@
+;
+; Supported features of the 'zsda' crypto driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Symmetric crypto = Y
+HW Accelerated = Y
+In Place SGL = Y
+OOP SGL In SGL Out = Y
+OOP SGL In LB Out = Y
+OOP LB In SGL Out = Y
+OOP LB In LB Out = Y
+
+;
+; Supported crypto algorithms of the 'zsda' crypto driver.
+;
+[Cipher]
+AES XTS (128) = Y
+AES XTS (256) = Y
+SM4 XTS= Y
+
+;
+; Supported authentication algorithms of the 'zsda' crypto driver.
+;
+[Auth]
+SHA1 = Y
+SHA224 = Y
+SHA256 = Y
+SHA384 = Y
+SHA512 = Y
+SM3 = Y
+
+
+;
+; Supported AEAD algorithms of the 'zsda' crypto driver.
+;
+[AEAD]
+
+
+;
+; Supported Asymmetric algorithms of the 'zsda' crypto driver.
+;
+[Asymmetric]
+
+
+;
+; Supported Operating systems of the 'zsda' crypto driver.
+;
+[OS]
+Linux = Y
diff --git a/doc/guides/cryptodevs/zsda.rst b/doc/guides/cryptodevs/zsda.rst
index 0a7aeb2d50..2b7de0422d 100644
--- a/doc/guides/cryptodevs/zsda.rst
+++ b/doc/guides/cryptodevs/zsda.rst
@@ -13,14 +13,40 @@ support for the following hardware accelerator devices:
Features
+The ZSDA SYM PMD has support for:
+
+Cipher algorithms:
+
+* ``RTE_CRYPTO_CIPHER_AES_XTS``
+* ``RTE_CRYPTO_CIPHER_SM4_XTS``
+
+Hash algorithms:
+
+* ``RTE_CRYPTO_AUTH_SHA1``
+* ``RTE_CRYPTO_AUTH_SHA224``
+* ``RTE_CRYPTO_AUTH_SHA256``
+* ``RTE_CRYPTO_AUTH_SHA384``
+* ``RTE_CRYPTO_AUTH_SHA512``
+* ``RTE_CRYPTO_AUTH_SM3``
+
Limitations
---
+* Only supports the session-oriented API implementation (session-less APIs are
+ not supported).
+* No BSD and Windows support.
+* Queue-pairs are thread-safe on Intel CPUs but Queues are not (that is, within
+ a single queue-pair all enqueues to the TX queue must be done from one thread
+ and all dequeues from the RX queue must be done from one thread, but enqueues
+ and dequeues may be done in different threads.)
+
Installation
+The ZSDA crypto service is built by default with a standard DPDK build.
+
Testing
---
diff --git a/doc/guides/rel_notes/release_25_07.rst
b/doc/guides/rel_notes/release_25_07.rst
index 093b85d206..8cd5d53ef3 100644
--- a/doc/guides/rel_notes/release_25_07.rst
+++ b/doc/guides/rel_notes/release_25_07.rst
@@ -56,6 +56,14 @@ New Features
===
+* **Added ZTE Storage Data Accelerator (ZSDA) crypto driver.**
+
+ Added a crypto driver for ZSDA devices
+ to support some encrypt, decrypt and hash algorithm.
+
+ See the :doc:`../cryptodevs/zsda` guide for more details on the new driver.
+
+
Removed Items
-
diff --git a/drivers/crypto/zsda/zsda_crypto_capabilities.h
b/drivers/crypto/zsda/zsda_crypto_capabilities.h
new file mode 100644
index 00..d00bdd2468
--- /dev/null
+++ b/drivers/crypto/zsda/zsda_crypto_capabilities.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2025 ZTE Corporation
+ */
+
+#ifndef _ZSDA_SYM_CAPABILITIES_H_
+#define _ZSDA_SYM_CAPABILITIES_H_
+
+static const struct rte_cryptodev_capabilities zsda_crypto_dev_capabilities[]
= {
+ {/* SHA1 */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ { .sym = {.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ { .auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA1,
+ .block_size = 64,
+ .key_size = {.min = 0, .max = 0, .increment =
0},
+ .digest_size = {.min = 20, .max = 20,
.increment = 2},
+ .iv_size = {0} },
+ } },
+ }
+ },
+ {/* SHA224 */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ { .sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ { .auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA224,
+ .block_size = 64,
+ .key_size = {.min = 0, .max = 0, .increment =
0},
+ .digest_siz
[PATCH v6 9/9] app/test: add zsda cryptodev test
Add crypto test for zsda device and driver.
Signed-off-by: Hanxiao Li
---
app/test/test_cryptodev.c | 7 +++
app/test/test_cryptodev.h | 1 +
doc/guides/cryptodevs/zsda.rst | 6 ++
3 files changed, 14 insertions(+)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 31a4905a97..ca2ed39b48 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -20233,6 +20233,12 @@ test_cryptodev_dpaa_sec_raw_api(void)
return
run_cryptodev_raw_testsuite(RTE_STR(CRYPTODEV_NAME_DPAA_SEC_PMD));
}
+static int
+test_cryptodev_zsda(void)
+{
+ return run_cryptodev_testsuite(RTE_STR(CRYPTODEV_NAME_ZSDA_SYM_PMD));
+}
+
REGISTER_DRIVER_TEST(cryptodev_cn10k_raw_api_autotest,
test_cryptodev_cn10k_raw_api);
REGISTER_DRIVER_TEST(cryptodev_dpaa2_sec_raw_api_autotest,
@@ -20270,3 +20276,4 @@ REGISTER_DRIVER_TEST(cryptodev_nitrox_autotest,
test_cryptodev_nitrox);
REGISTER_DRIVER_TEST(cryptodev_bcmfs_autotest, test_cryptodev_bcmfs);
REGISTER_DRIVER_TEST(cryptodev_cn9k_autotest, test_cryptodev_cn9k);
REGISTER_DRIVER_TEST(cryptodev_cn10k_autotest, test_cryptodev_cn10k);
+REGISTER_DRIVER_TEST(cryptodev_zsda_autotest, test_cryptodev_zsda);
diff --git a/app/test/test_cryptodev.h b/app/test/test_cryptodev.h
index 22bcb4969b..a80c11baf4 100644
--- a/app/test/test_cryptodev.h
+++ b/app/test/test_cryptodev.h
@@ -73,6 +73,7 @@
#define CRYPTODEV_NAME_CN10K_PMD crypto_cn10k
#define CRYPTODEV_NAME_MLX5_PMDcrypto_mlx5
#define CRYPTODEV_NAME_UADK_PMDcrypto_uadk
+#define CRYPTODEV_NAME_ZSDA_SYM_PMDcrypto_zsda
enum cryptodev_api_test_type {
diff --git a/doc/guides/cryptodevs/zsda.rst b/doc/guides/cryptodevs/zsda.rst
index 2b7de0422d..0e1d8fd215 100644
--- a/doc/guides/cryptodevs/zsda.rst
+++ b/doc/guides/cryptodevs/zsda.rst
@@ -50,3 +50,9 @@ The ZSDA crypto service is built by default with a standard
DPDK build.
Testing
---
+
+ZSDA SYM crypto PMD can be tested by running the test application::
+
+cd .//app/test
+./dpdk-test -l1 -n1 -a
+RTE>>cryptodev_zsda_autotest
--
2.27.0
[PATCH v6 2/9] crypto/zsda: add device operations
Add crypto device operations for zsda devices.
Signed-off-by: Hanxiao Li
---
drivers/crypto/zsda/zsda_crypto_pmd.c | 82 +--
1 file changed, 77 insertions(+), 5 deletions(-)
diff --git a/drivers/crypto/zsda/zsda_crypto_pmd.c
b/drivers/crypto/zsda/zsda_crypto_pmd.c
index 99acfa3418..04c4e45843 100644
--- a/drivers/crypto/zsda/zsda_crypto_pmd.c
+++ b/drivers/crypto/zsda/zsda_crypto_pmd.c
@@ -8,12 +8,82 @@
uint8_t zsda_crypto_driver_id;
+static int
+zsda_dev_config(__rte_unused struct rte_cryptodev *dev,
+ __rte_unused struct rte_cryptodev_config *config)
+{
+ return ZSDA_SUCCESS;
+}
+
+static int
+zsda_dev_start(struct rte_cryptodev *dev)
+{
+ struct zsda_crypto_dev_private *crypto_dev = dev->data->dev_private;
+ int ret;
+
+ ret = zsda_queue_start(crypto_dev->zsda_pci_dev->pci_dev);
+
+ return ret;
+}
+
+static void
+zsda_dev_stop(struct rte_cryptodev *dev)
+{
+ struct zsda_crypto_dev_private *crypto_dev = dev->data->dev_private;
+
+ zsda_queue_stop(crypto_dev->zsda_pci_dev->pci_dev);
+}
+
+static int
+zsda_dev_close(struct rte_cryptodev *dev __rte_unused)
+{
+ int ret = ZSDA_SUCCESS;
+ return ret;
+}
+
+static uint16_t
+zsda_crypto_max_nb_qps(void)
+{
+ uint16_t encrypt = zsda_nb_qps.encrypt;
+ uint16_t decrypt = zsda_nb_qps.decrypt;
+ uint16_t hash = zsda_nb_qps.hash;
+ uint16_t min = 0;
+
+ if ((encrypt == MAX_QPS_ON_FUNCTION) ||
+ (decrypt == MAX_QPS_ON_FUNCTION) ||
+ (hash == MAX_QPS_ON_FUNCTION))
+ min = MAX_QPS_ON_FUNCTION;
+ else {
+ min = (encrypt < decrypt) ? encrypt : decrypt;
+ min = (min < hash) ? min : hash;
+ }
+
+ if (min == 0)
+ return MAX_QPS_ON_FUNCTION;
+ return min;
+}
+
+static void
+zsda_dev_info_get(struct rte_cryptodev *dev,
+ struct rte_cryptodev_info *info)
+{
+ struct zsda_crypto_dev_private *crypto_dev_priv =
dev->data->dev_private;
+
+ if (info != NULL) {
+ info->max_nb_queue_pairs = zsda_crypto_max_nb_qps();
+ info->feature_flags = dev->feature_flags;
+ info->capabilities = crypto_dev_priv->zsda_crypto_capabilities;
+ info->driver_id = zsda_crypto_driver_id;
+ info->sym.max_nb_sessions = 0;
+ }
+}
+
static struct rte_cryptodev_ops crypto_zsda_ops = {
- .dev_configure = NULL,
- .dev_start = NULL,
- .dev_stop = NULL,
- .dev_close = NULL,
- .dev_infos_get = NULL,
+ .dev_configure = zsda_dev_config,
+ .dev_start = zsda_dev_start,
+ .dev_stop = zsda_dev_stop,
+ .dev_close = zsda_dev_close,
+ .dev_infos_get = zsda_dev_info_get,
.stats_get = NULL,
.stats_reset = NULL,
@@ -105,6 +175,8 @@ zsda_crypto_dev_destroy(struct zsda_pci_device
*zsda_pci_dev)
if (rte_eal_process_type() == RTE_PROC_PRIMARY)
rte_memzone_free(crypto_dev_priv->capa_mz);
+ zsda_dev_close(crypto_dev_priv->cryptodev);
+
rte_cryptodev_pmd_destroy(crypto_dev_priv->cryptodev);
zsda_devs[zsda_pci_dev->zsda_dev_id].crypto_rte_dev.name = NULL;
zsda_pci_dev->crypto_dev_priv = NULL;
--
2.27.0
Re: [PATCH v4] event/dlb2: consolidate AVX512 and SSE changes
On Tue, Apr 08, 2025 at 08:00:48AM -0500, Tirthendu Sarkar wrote: > Streamline code for AVX512 and SSE by consolidating the common code and > adding runtime check for selecting appropriate path based on CPU > capability. > > Signed-off-by: Tirthendu Sarkar > > --- > v4: > - Modify some AVX512 instructions to resolve compilation error on >older compliers > v3: > - Simplified code for AVX/SSE paths > v2: > - Addressed review comments [Bruce Richardson] > --- > drivers/event/dlb2/dlb2.c| 78 - > drivers/event/dlb2/dlb2_avx512.c | 287 +++ > drivers/event/dlb2/dlb2_priv.h | 10 +- > drivers/event/dlb2/dlb2_sse.c| 242 +++--- > 4 files changed, 127 insertions(+), 490 deletions(-) > Acked-by: Bruce Richardson
Re: [EXTERNAL] [PATCH 0/2] uadk: realize async mode
Hi, Akhil
On Wed, 21 May 2025 at 20:39, Akhil Goyal wrote:
>
> > Realize async mode to replace sync mode for better performance
> >
> > Zhangfei Gao (2):
> > compress/uadk: use async mode to replace sync mode
> > crypto/uadk: use async mode to replace sync mode
> >
> > drivers/compress/uadk/uadk_compress_pmd.c | 107 --
> > .../compress/uadk/uadk_compress_pmd_private.h | 2 +-
> > drivers/crypto/uadk/uadk_crypto_pmd.c | 321 +-
> > drivers/crypto/uadk/uadk_crypto_pmd_private.h | 8 +-
> > 4 files changed, 318 insertions(+), 120 deletions(-)
>
> This patchset is not building for me atleast. Please fix compilation.
>
> ninja: Entering directory `./build-gcc-static'
> [2/31] Compiling C object
> drivers/libtmp_rte_compress_uadk.a.p/compress_uadk_uadk_compress_pmd.c.o
> FAILED:
> drivers/libtmp_rte_compress_uadk.a.p/compress_uadk_uadk_compress_pmd.c.o
> ccache gcc -Idrivers/libtmp_rte_compress_uadk.a.p -Idrivers -I../drivers
> -Idrivers/compress/uadk -I../drivers/compress/uadk -Ilib/compressdev
> -I../lib/compressdev -Ilib/eal/common -I../lib/eal/common -I. -I.. -Iconfig
> -I../config -Ilib/eal/include -I../lib/eal/include -Ilib/eal/linux/include
> -I../lib/eal/linux/include -Ilib/eal/x86/include -I../lib/eal/x86/include
> -I../kernel/linux -Ilib/eal -I../lib/eal -Ilib/kvargs -I../lib/kvargs
> -Ilib/log -I../lib/log -Ilib/metrics -I../lib/metrics -Ilib/telemetry
> -I../lib/telemetry -Ilib/mbuf -I../lib/mbuf -Ilib/mempool -I../lib/mempool
> -Ilib/ring -I../lib/ring -Idrivers/bus/vdev -I../drivers/bus/vdev
> -I/home/gakhil/up/uadk/build_x86/include -fdiagnostics-color=always
> -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -Wextra -Werror -std=c11 -O2 -g
> -include rte_config.h -Wvla -Wcast-qual -Wdeprecated -Wformat
> -Wformat-nonliteral -Wformat-security -Wmissing-declarations
> -Wmissing-prototypes -Wnested-externs -Wold-style-definition -Wpointer-arith
> -Wsign-compare -Wstrict-prototypes -Wundef -Wwrite-strings
> -Wno-packed-not-aligned -Wno-missing-field-initializers -D_GNU_SOURCE -fPIC
> -march=native -mrtm -DALLOW_EXPERIMENTAL_API -DALLOW_INTERNAL_API
> -Wno-format-truncation -Wno-address-of-packed-member
> -DRTE_LOG_DEFAULT_LOGTYPE=pmd.compress.uadk -MD -MQ
> drivers/libtmp_rte_compress_uadk.a.p/compress_uadk_uadk_compress_pmd.c.o -MF
> drivers/libtmp_rte_compress_uadk.a.p/compress_uadk_uadk_compress_pmd.c.o.d -o
> drivers/libtmp_rte_compress_uadk.a.p/compress_uadk_uadk_compress_pmd.c.o -c
> ../drivers/compress/uadk/uadk_compress_pmd.c
> ../drivers/compress/uadk/uadk_compress_pmd.c: In function
> ‘uadk_compress_pmd_config’:
> ../drivers/compress/uadk/uadk_compress_pmd.c:35:9: error: variable ‘cparams’
> has initializer but incomplete type
>35 | struct wd_ctx_params cparams = {0};
> | ^
> ../drivers/compress/uadk/uadk_compress_pmd.c:35:34: error: excess elements in
> struct initializer [-Werror]
>35 | struct wd_ctx_params cparams = {0};
> | ^
> ../drivers/compress/uadk/uadk_compress_pmd.c:35:34: note: (near
> initialization for ‘cparams’)
> ../drivers/compress/uadk/uadk_compress_pmd.c:35:23: error: storage size of
> ‘cparams’ isn’t known
>35 | struct wd_ctx_params cparams = {0};
> | ^~~
> ../drivers/compress/uadk/uadk_compress_pmd.c:42:42: error: dereferencing
> pointer to incomplete type ‘struct wd_ctx_nums’
>42 | ctx_set_num = calloc(WD_DIR_MAX, sizeof(*ctx_set_num));
> | ^~~~
> ../drivers/compress/uadk/uadk_compress_pmd.c:50:16: error: implicit
> declaration of function ‘numa_allocate_nodemask’
> [-Werror=implicit-function-declaration]
>50 | cparams.bmp = numa_allocate_nodemask();
> |^~
> ../drivers/compress/uadk/uadk_compress_pmd.c:50:16: error: nested extern
> declaration of ‘numa_allocate_nodemask’ [-Werror=nested-externs]
> ../drivers/compress/uadk/uadk_compress_pmd.c:57:2: error: implicit
> declaration of function ‘numa_bitmask_setall’
> [-Werror=implicit-function-declaration]
>57 | numa_bitmask_setall(cparams.bmp);
> | ^~~
> ../drivers/compress/uadk/uadk_compress_pmd.c:57:2: error: nested extern
> declaration of ‘numa_bitmask_setall’ [-Werror=nested-externs]
> ../drivers/compress/uadk/uadk_compress_pmd.c:60:14: error: invalid use of
> undefined type ‘struct wd_ctx_nums’
>60 | ctx_set_num[i].async_ctx_num = UADK_COMP_DEF_CTXS;
> | ^
> ../drivers/compress/uadk/uadk_compress_pmd.c:62:8: error: implicit
> declaration of function ‘wd_comp_init2_’; did you mean ‘wd_comp_init’?
> [-Werror=implicit-function-declaration]
>62 | ret = wd_comp_init2_(alg_name, SCHED_POLICY_RR, TASK_HW, &cparams);
> |^~
> |wd_comp_init
> ../drivers/compress/uadk/uadk_compress_pmd.c:62:8: error: nested extern
> declaration of ‘wd_comp_in
Re: [PATCH] net/ice: fix support for 3 scheduler levels
On Wed, May 21, 2025 at 11:52:21AM +0100, Loftus, Ciara wrote:
> >
> > When using only 3 scheduler levels, the VSI node needs to be a node
> > further down the scheduler hierarchy, rather than one up it as with all
> > other possible level settings (5-9). Take account of this possibility in
> > the code.
> >
> > Fixes: 4ace7701eb44 ("net/ice: provide parameter to limit scheduler layers")
> > Cc: sta...@dpdk.org
> >
> > Signed-off-by: Bruce Richardson
> > ---
> > drivers/net/intel/ice/ice_tm.c | 12
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/drivers/net/intel/ice/ice_tm.c b/drivers/net/intel/ice/ice_tm.c
> > index ff3a6cd77f..f2d8e12181 100644
> > --- a/drivers/net/intel/ice/ice_tm.c
> > +++ b/drivers/net/intel/ice/ice_tm.c
> > @@ -818,6 +818,18 @@ commit_new_hierarchy(struct rte_eth_dev *dev)
> > uint8_t qg_lvl = q_lvl - 1;
> >
> > struct ice_sched_node *new_vsi_root = hw->vsi_ctx[pf->main_vsi-
> > >idx]->sched.vsi_node[0];
> > + /* handle case where VSI node needs to move DOWN the hierarchy */
> > + while (new_vsi_root->tx_sched_layer < new_root_level) {
> > + if (new_vsi_root->num_children == 0)
> > + return -1;
> > + /* remove all child nodes but the first */
> > + while (new_vsi_root->num_children > 1)
> > + free_sched_node_recursive(pi, new_vsi_root,
> > + new_vsi_root->children[1],
> > + new_vsi_root->vsi_handle);
> > + new_vsi_root = new_vsi_root->children[0];
> > + }
> > + /* handle case where VSI node needs to move UP the hierarchy */
> > while (new_vsi_root->tx_sched_layer > new_root_level)
> > new_vsi_root = new_vsi_root->parent;
>
> Acked-by: Ciara Loftus
>
Applied to dpdk-next-net-intel.
/Bruce
RE: [EXTERNAL] [dpdk-dev] [PATCH ] net/cnxk: support ESP based RSS hashing
> -Original Message- > From: psathe...@marvell.com > Sent: Wednesday, April 2, 2025 1:55 PM > To: Nithin Kumar Dabilpuram ; Kiran Kumar > Kokkilagadda ; Sunil Kumar Kori > ; Satha Koteswara Rao Kottidi > ; Harman Kalra > Cc: dev@dpdk.org; Satheesh Paul Antonysamy > Subject: [EXTERNAL] [dpdk-dev] [PATCH ] net/cnxk: support ESP based RSS > hashing > > From: Satheesh Paul Support ESP based RSS > hashing. Signed-off-by: Satheesh Paul Reviewed-by: > Kiran Kumar K --- > drivers/common/cnxk/roc_mbox. h | 1 + drivers/net/cnxk/cnxk_ethdev. c > > From: Satheesh Paul > > Support ESP based RSS hashing. > > Signed-off-by: Satheesh Paul > Reviewed-by: Kiran Kumar K Applied to dpdk-next-net-mrvl/for-main. Thanks
[dpdk-dev] [PATCH ] common/cnxk: fix E-tag pattern parsing
From: Satheesh Paul
E-tag pattern parsing was using wrong length leading
to a segfault. Fixing this by using the correct length
of the pattern item.
Fixes: c34ea71b878d ("common/cnxk: add NPC parsing API")
Cc: sta...@dpdk.org
Signed-off-by: Satheesh Paul
Reviewed-by: Kiran Kumar K
---
drivers/common/cnxk/roc_npc.c | 5 +++--
drivers/common/cnxk/roc_npc_parse.c | 2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c
index 3fd59667d8..3fa3ddcbfc 100644
--- a/drivers/common/cnxk/roc_npc.c
+++ b/drivers/common/cnxk/roc_npc.c
@@ -995,10 +995,11 @@ npc_parse_pattern(struct npc *npc, const struct
roc_npc_item_info pattern[],
pst->mcam_data = (uint8_t *)flow->mcam_data;
pst->mcam_mask = (uint8_t *)flow->mcam_mask;
- while (pattern->type != ROC_NPC_ITEM_TYPE_END &&
- layer < PLT_DIM(parse_stage_funcs)) {
+ while (pattern->type != ROC_NPC_ITEM_TYPE_END && layer <
PLT_DIM(parse_stage_funcs)) {
/* Skip place-holders */
pattern = npc_parse_skip_void_and_any_items(pattern);
+ if (pattern->type == ROC_NPC_ITEM_TYPE_END)
+ break;
pst->pattern = pattern;
rc = parse_stage_funcs[layer](pst);
diff --git a/drivers/common/cnxk/roc_npc_parse.c
b/drivers/common/cnxk/roc_npc_parse.c
index b52024f434..37b43995db 100644
--- a/drivers/common/cnxk/roc_npc_parse.c
+++ b/drivers/common/cnxk/roc_npc_parse.c
@@ -531,6 +531,7 @@ npc_parse_lb(struct npc_parse_state *pst)
*/
lt = NPC_LT_LB_ETAG;
lflags = 0;
+ info.len = pattern->size;
last_pattern = pst->pattern;
pattern = npc_parse_skip_void_and_any_items(pst->pattern + 1);
@@ -545,7 +546,6 @@ npc_parse_lb(struct npc_parse_state *pst)
lflags = NPC_F_ETAG_CTAG;
last_pattern = pattern;
}
- info.len = pattern->size;
} else if (pst->pattern->type == ROC_NPC_ITEM_TYPE_QINQ) {
info.hw_mask = NULL;
info.len = pattern->size;
--
2.42.0
Re: [RFC PATCH 3/7] argparse: make argparse EAL-args compatible
On Tue, May 20, 2025 at 05:40:20PM +0100, Bruce Richardson wrote: > The argparse library was missing two key features which made it > unsuitable for use by EAL or any program wanting similar behaviour. > > 1. It didn't stop parsing arguments when it hit a "--" character > 2. It never returned the number of arguments parsed > > Fix both these issues - the latter is a change to the ABI, since we now > return >= 0 rather than == 0 on success. However, the ABI is still > experimental so we can make exactly these sorts of tweaks to it. > > Signed-off-by: Bruce Richardson > --- Thinking about it further, for EAL we can actually do without these changes to the argparse library*. However, this is also functionality that may be useful in other cases, so looking for feedback on whether to continue with this patch, or drop it? Question: * should argparse library stop processing args at "--"? * should argparse library return number of args parsed, or zero on success? /Bruce *The reason we don't need these is because we clone the argv data on eal_init so we can return it via telemetry library. This splits the args into eal and non-eal args, so we can use just the "eal" arg array to pass to arg-parse, if we don't include this patch.
Re: [v5,1/9] crypto/zsda: add skeleton
Hi akhil: There is a critical warning, maybe can called error, that the patches can't be applied. Because I formatted some files in patch "[v1] compress/zsda: code formatting", whose link is https://patches.dpdk.org/project/dpdk/patch/20250522062351.2266776-1-li.hanx...@zte.com.cn/ The crypto patches were changed based on the [v1] patch. So do I need to resubmit the crypto patches after you accepted the [v1] patch?
RE: [EXTERNAL] Re: [v5,1/9] crypto/zsda: add skeleton
> Hi akhil: > > There is a critical warning, maybe can called error, that the patches can't be > applied. > > Because I formatted some files in patch "[v1] compress/zsda: code formatting", > whose link is > https://patches.dpdk.org/project/dpdk/patch/20250522062351.2266776-1- > li.hanx...@zte.com.cn/ > > > The crypto patches were changed based on the [v1] patch. > > So do I need to resubmit the crypto patches after you accepted the [v1] patch? I wanted to take your crypto PMD first. And then you can submit your compress cleanup afterwards. The crypto pmd was almost ready for merge. You just need to fix the typo and comments.
Addressing git.dpdk.org downtime
Hello everyone, We’re aware that https://git.dpdk.org has been experiencing availability issues lately, largely due to abusive bots and crawlers overloading the servers and ignoring traditional controls like robots.txt. To address this, we're preparing to deploy Anubis, a traffic-challenging tool, to help ensure reliable and continued access for the community, starting with our cgit instance. This approach has been adopted by several other open-source projects recently to reduce disruptive automated traffic. Please reach out if you have questions or encounter issues. See: https://github.com/TecharoHQ/anubis Thanks, Ali
eal patches with other licenses
Andre, Please try asking the respective original authors of getline() and asprintf() if they are willing to license these functions to the DPDK project under the BSD-3-Clause license. Or perhaps generally offer dual-license with BSD-3-Clause as an alternative to their original license. -Morten
Re: [PATCH] net/mlx5: align PF and VF/SF MAC addresses handling
Hi,
On 16/05/2025 10:10 AM, Gavin Li wrote:
In the mlx5_dev_spawn function, the Virtual Function (VF) synchronizes MAC
addresses from the kernel using netlink. It queries the netdev-configured
MACs and populates the list in the PMD device data, including multicast
MAC addresses. These addresses are later used for control flow creation,
allowing traffic for the listed MACs to be received. However, the Physical
Function (PF) does not synchronize with the kernel and thus does not add
any multicast MAC address rules when enabling traffic. This discrepancy
causes the IFF_ALLMULTI ioctl code to malfunction, as it fails to disable
all multicast traffic, leaving the VF still able to see it.
To align PF and VF behavior, only unicast MAC address flows should be
added.
Fixes: 272733b5ebfd ("net/mlx5: use flow to enable unicast traffic")
Cc: sta...@dpdk.org
Signed-off-by: Gavin Li
---
Patch applied to next-net-mlx,
--
Kindest regards
Raslan Darawsheh
Re: Addressing git.dpdk.org downtime
On Thu, May 22, 2025 at 08:36:28AM +, Ali Alnubani wrote: > Hello everyone, > > We’re aware that https://git.dpdk.org has been experiencing availability > issues lately, largely due to abusive bots and crawlers overloading the > servers and ignoring traditional controls like robots.txt. > > To address this, we're preparing to deploy Anubis, a traffic-challenging > tool, to help ensure reliable and continued access for the community, > starting with our cgit instance. This approach has been adopted by several > other open-source projects recently to reduce disruptive automated traffic. > > Please reach out if you have questions or encounter issues. > > See: https://github.com/TecharoHQ/anubis > > Thanks, > Ali Thanks Ali, (and others involved) for taking action on this. To everyone else in the community, just a reminder that, rather than accessing dpdk.org site directly, you can use "https://github.com/DPDK/dpdk"; as a source for getting and browsing the DPDK source code. The github mirror is always in sync with the main tree, and, as an added convenience, also has the various "next" trees mirrored to it too. This means that you don't need to clone multiple trees to get e.g. next-net tree as well as main tree. For any companies looking to have internal mirrors of the DPDK repository for internal use, it's recommended that those mirrors be based on github rather than on dpdk.org directly. This all helps reduce load on the server. Thanks, /Bruce
[PATCH v3] ethdev: fix the bug where the flag variables are assigned
Set the values of the promiscuous and all_multicast variables
according to the return value.
Fixes: af75078fece3 ("first public release")
Fixes: de5ccf0775ae ("ethdev: do nothing if all-multicast mode is
applied again")
Cc: sta...@dpdk.org
Signed-off-by: Morten Brørup
Signed-off-by: Sunyang Wu
---
lib/ethdev/rte_ethdev.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c
index d4197322a0..c27d3e5041 100644
--- a/lib/ethdev/rte_ethdev.c
+++ b/lib/ethdev/rte_ethdev.c
@@ -3044,10 +3044,9 @@ rte_eth_promiscuous_disable(uint16_t port_id)
if (dev->dev_ops->promiscuous_disable == NULL)
return -ENOTSUP;
- dev->data->promiscuous = 0;
diag = dev->dev_ops->promiscuous_disable(dev);
- if (diag != 0)
- dev->data->promiscuous = 1;
+ if (!diag)
+ dev->data->promiscuous = 0;
diag = eth_err(port_id, diag);
@@ -3112,10 +3111,10 @@ rte_eth_allmulticast_disable(uint16_t port_id)
if (dev->dev_ops->allmulticast_disable == NULL)
return -ENOTSUP;
- dev->data->all_multicast = 0;
+
diag = dev->dev_ops->allmulticast_disable(dev);
- if (diag != 0)
- dev->data->all_multicast = 1;
+ if (!diag)
+ dev->data->all_multicast = 0;
diag = eth_err(port_id, diag);
--
2.19.0.rc0.windows.1
Re: [dpdk-dev] Regarding HQOS with run-to-completion Model
Thanks Stephen for addressing my queries , and it is helpful. One more follow up question on the same , Can DPDK HQOS be customized based on Use case ? For example: Hqos config for one of the use cases , *One Port , One Subport , 16 Pipes & Each Pipe with only one TC*. 16 pipe config was allowed but changing the 13TCs to 1TC is not allowed per Pipe. Can I still use 13 TCs but use the QueueSize as 0, Can that impact performance ? Thanks Farooq.J On Wed, May 21, 2025 at 7:48 PM Stephen Hemminger < step...@networkplumber.org> wrote: > On Mon, 28 Apr 2025 16:55:07 +0530 > farooq basha wrote: > > > Hello DevTeam, > > > > I am planning to use DPDK HQOS for Traffic shaping with a > > run-to-completion Model. While I was reading the dpdk-qos document, I > came > > across the following statement. > > > > "*Running enqueue and dequeue operations for the same output port from > > different cores is likely to cause significant impact on scheduler’s > > performance and it is therefore not recommended"* > > > > Let's take an example, Port1 & Port2 have 4 Rx queues and each Queue > > mapped to a different CPU. Traffic coming on port1 gets forwarded to > port2 > > . With the above limitation application needs to take a lock before doing > > rte_sched_port_enqueue & dequeue operation. Performance is limited to > only > > 1 CPU even though Traffic is coming on 4 Different CPUs. > > > > Correct me if my understanding is Wrong? > > > > Thanks > > Basha > > The HQOS code is not thread safe so yes you need a lock. > The traffic scheduling (QOS) needs to be at last stage of the pipeline just > before mbufs are passed to the device. > > The issue is that QOS is single threaded, so lock is required. > > The statement is misleading, the real overhead is the lock; the secondary > overhead is the cache miss that will happen if processing on different > cores. > But if you are doing that you are going to cut performance a lot from cache > misses. >
RE: [EXTERNAL] [PATCH 0/2] uadk: realize async mode
> Hi, Akhil
>
> On Wed, 21 May 2025 at 20:39, Akhil Goyal wrote:
> >
> > > Realize async mode to replace sync mode for better performance
> > >
> > > Zhangfei Gao (2):
> > > compress/uadk: use async mode to replace sync mode
> > > crypto/uadk: use async mode to replace sync mode
> > >
> > > drivers/compress/uadk/uadk_compress_pmd.c | 107 --
> > > .../compress/uadk/uadk_compress_pmd_private.h | 2 +-
> > > drivers/crypto/uadk/uadk_crypto_pmd.c | 321 +-
> > > drivers/crypto/uadk/uadk_crypto_pmd_private.h | 8 +-
> > > 4 files changed, 318 insertions(+), 120 deletions(-)
> >
> > This patchset is not building for me atleast. Please fix compilation.
> >
> > ninja: Entering directory `./build-gcc-static'
> > [2/31] Compiling C object
> drivers/libtmp_rte_compress_uadk.a.p/compress_uadk_uadk_compress_pmd.c.
> o
> > FAILED:
> drivers/libtmp_rte_compress_uadk.a.p/compress_uadk_uadk_compress_pmd.c.
> o
> > ccache gcc -Idrivers/libtmp_rte_compress_uadk.a.p -Idrivers -I../drivers -
> Idrivers/compress/uadk -I../drivers/compress/uadk -Ilib/compressdev -
> I../lib/compressdev -Ilib/eal/common -I../lib/eal/common -I. -I.. -Iconfig -
> I../config -Ilib/eal/include -I../lib/eal/include -Ilib/eal/linux/include -
> I../lib/eal/linux/include -Ilib/eal/x86/include -I../lib/eal/x86/include -
> I../kernel/linux -Ilib/eal -I../lib/eal -Ilib/kvargs -I../lib/kvargs
> -Ilib/log -I../lib/log -
> Ilib/metrics -I../lib/metrics -Ilib/telemetry -I../lib/telemetry -Ilib/mbuf -
> I../lib/mbuf -Ilib/mempool -I../lib/mempool -Ilib/ring -I../lib/ring -
> Idrivers/bus/vdev -I../drivers/bus/vdev -
> I/home/gakhil/up/uadk/build_x86/include -fdiagnostics-color=always -
> D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -Wextra -Werror -std=c11 -O2 -g -
> include rte_config.h -Wvla -Wcast-qual -Wdeprecated -Wformat -Wformat-
> nonliteral -Wformat-security -Wmissing-declarations -Wmissing-prototypes -
> Wnested-externs -Wold-style-definition -Wpointer-arith -Wsign-compare -
> Wstrict-prototypes -Wundef -Wwrite-strings -Wno-packed-not-aligned -Wno-
> missing-field-initializers -D_GNU_SOURCE -fPIC -march=native -mrtm -
> DALLOW_EXPERIMENTAL_API -DALLOW_INTERNAL_API -Wno-format-truncation
> -Wno-address-of-packed-member -
> DRTE_LOG_DEFAULT_LOGTYPE=pmd.compress.uadk -MD -MQ
> drivers/libtmp_rte_compress_uadk.a.p/compress_uadk_uadk_compress_pmd.c.
> o -MF
> drivers/libtmp_rte_compress_uadk.a.p/compress_uadk_uadk_compress_pmd.c.
> o.d -o
> drivers/libtmp_rte_compress_uadk.a.p/compress_uadk_uadk_compress_pmd.c.
> o -c ../drivers/compress/uadk/uadk_compress_pmd.c
> > ../drivers/compress/uadk/uadk_compress_pmd.c: In function
> ‘uadk_compress_pmd_config’:
> > ../drivers/compress/uadk/uadk_compress_pmd.c:35:9: error: variable
> ‘cparams’ has initializer but incomplete type
> >35 | struct wd_ctx_params cparams = {0};
> > | ^
> > ../drivers/compress/uadk/uadk_compress_pmd.c:35:34: error: excess elements
> in struct initializer [-Werror]
> >35 | struct wd_ctx_params cparams = {0};
> > | ^
> > ../drivers/compress/uadk/uadk_compress_pmd.c:35:34: note: (near
> initialization for ‘cparams’)
> > ../drivers/compress/uadk/uadk_compress_pmd.c:35:23: error: storage size of
> ‘cparams’ isn’t known
> >35 | struct wd_ctx_params cparams = {0};
> > | ^~~
> > ../drivers/compress/uadk/uadk_compress_pmd.c:42:42: error: dereferencing
> pointer to incomplete type ‘struct wd_ctx_nums’
> >42 | ctx_set_num = calloc(WD_DIR_MAX, sizeof(*ctx_set_num));
> > | ^~~~
> > ../drivers/compress/uadk/uadk_compress_pmd.c:50:16: error: implicit
> declaration of function ‘numa_allocate_nodemask’ [-Werror=implicit-function-
> declaration]
> >50 | cparams.bmp = numa_allocate_nodemask();
> > |^~
> > ../drivers/compress/uadk/uadk_compress_pmd.c:50:16: error: nested extern
> declaration of ‘numa_allocate_nodemask’ [-Werror=nested-externs]
> > ../drivers/compress/uadk/uadk_compress_pmd.c:57:2: error: implicit
> declaration of function ‘numa_bitmask_setall’ [-Werror=implicit-function-
> declaration]
> >57 | numa_bitmask_setall(cparams.bmp);
> > | ^~~
> > ../drivers/compress/uadk/uadk_compress_pmd.c:57:2: error: nested extern
> declaration of ‘numa_bitmask_setall’ [-Werror=nested-externs]
> > ../drivers/compress/uadk/uadk_compress_pmd.c:60:14: error: invalid use of
> undefined type ‘struct wd_ctx_nums’
> >60 | ctx_set_num[i].async_ctx_num = UADK_COMP_DEF_CTXS;
> > | ^
> > ../drivers/compress/uadk/uadk_compress_pmd.c:62:8: error: implicit
> declaration of function ‘wd_comp_init2_’; did you mean ‘wd_comp_init’? [-
> Werror=implicit-function-declaration]
> >62 | ret = wd_comp_init2_(alg_name, SCHED_POLICY_RR, TASK_HW,
> &cparams);
> > |^~
> > |wd_comp_init
>
Re: [PATCH v2 1/2] net: fix offset calculation for GENEVE packet
Acked-by: Dengdui Huang
On 2025/5/21 13:11, sk...@marvell.com wrote:
> From: Sunil Kumar Kori
>
> While parsing packet headers, offset must be added to get next
> header but for geneve header parsing offset is overwritten.
> Also inner_l2_len is not set in case of geneve packets.
>
> Fixes: 64ed7f854cf4 ("net: add tunnel packet type parsing")
>
> Signed-off-by: Sunil Kumar Kori
> ---
> lib/net/rte_net.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/lib/net/rte_net.c b/lib/net/rte_net.c
> index be24690fdf..1264f33d61 100644
> --- a/lib/net/rte_net.c
> +++ b/lib/net/rte_net.c
> @@ -251,7 +251,8 @@ ptype_tunnel_with_udp(uint16_t *proto, const struct
> rte_mbuf *m,
> if (unlikely(gnh == NULL))
> return 0;
> geneve_len = sizeof(*gnh) + gnh->opt_len * 4;
> - *off = geneve_len;
> + *off += geneve_len;
> + hdr_lens->inner_l2_len = sizeof(struct rte_udp_hdr) +
> geneve_len;
> *proto = gnh->proto;
> if (gnh->proto == 0)
> *proto = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4);
[PATCH v4 1/3] net: fix GTP packet parsing
After parsing the GTP packet header, the next protocol type should
be converted from RTE_GTP_TYPE_IPV4/IPV6 to RTE_ETHER_TYPE_IPV4/IPV6.
Otherwise, the next protocol cannot be parsed.
Bugzilla ID: 1672
Fixes: 64ed7f854cf4 ("net: add tunnel packet type parsing")
Cc: sta...@dpdk.org
Signed-off-by: Dengdui Huang
Acked-by: Jie Hai
---
lib/net/rte_net.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/lib/net/rte_net.c b/lib/net/rte_net.c
index be24690fdf..1771588a09 100644
--- a/lib/net/rte_net.c
+++ b/lib/net/rte_net.c
@@ -231,7 +231,13 @@ ptype_tunnel_with_udp(uint16_t *proto, const struct
rte_mbuf *m,
*/
if (gh->msg_type == 0xff) {
ip_ver = *(const uint8_t *)((const char *)gh + gtp_len);
- *proto = (ip_ver) & 0xf0;
+ ip_ver = (ip_ver) & 0xf0;
+ if (ip_ver == RTE_GTP_TYPE_IPV4)
+ *proto = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4);
+ else if (ip_ver == RTE_GTP_TYPE_IPV6)
+ *proto = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV6);
+ else
+ *proto = 0;
} else {
*proto = 0;
}
--
2.33.0
[PATCH v4 3/3] app/testpmd: fix obtain inner info of tunnel packet
l2_len for tunneling packets should contain Outer_L4_len.
Additionally, the current offset used for the inner Ethernet
header is incorrect. This patch fixes these issues.
Fixes: 76730c7b9b5a ("app/testpmd: use packet type parsing API")
Cc: sta...@dpdk.org
Signed-off-by: Dengdui Huang
---
app/test-pmd/csumonly.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/app/test-pmd/csumonly.c b/app/test-pmd/csumonly.c
index fa0002d321..d488eed470 100644
--- a/app/test-pmd/csumonly.c
+++ b/app/test-pmd/csumonly.c
@@ -711,11 +711,11 @@ pkt_burst_checksum_forward(struct fwd_stream *fs)
if (txp->parse_tunnel && RTE_ETH_IS_TUNNEL_PKT(ptype) != 0) {
info.is_tunnel = 1;
update_tunnel_outer(&info);
- info.l2_len = hdr_lens.inner_l2_len +
hdr_lens.tunnel_len;
+ info.l2_len = hdr_lens.inner_l2_len;
info.l3_len = hdr_lens.inner_l3_len;
info.l4_len = hdr_lens.inner_l4_len;
- eth_hdr = (struct rte_ether_hdr *)(char *)l3_hdr +
- info.outer_l3_len + hdr_lens.tunnel_len;
+ eth_hdr = (struct rte_ether_hdr *)((char *)l3_hdr +
+ hdr_lens.l3_len + hdr_lens.l4_len +
hdr_lens.tunnel_len);
info.ethertype = get_ethertype_by_ptype(eth_hdr,
ptype &
RTE_PTYPE_INNER_L3_MASK);
tx_ol_flags |= get_tunnel_ol_flags_by_ptype(ptype);
--
2.33.0
[PATCH v4 2/3] net: fix parse the tunnel length of tunnel packet with UDP
Currently, the tunnel length info is not available when
get the tunnel packet type with UDP port. This patch
adds the parsing of the tunnel length info.
Fixes: 64ed7f854cf4 ("net: add tunnel packet type parsing")
Cc: sta...@dpdk.org
Signed-off-by: Dengdui Huang
---
lib/net/rte_net.c | 4
1 file changed, 4 insertions(+)
diff --git a/lib/net/rte_net.c b/lib/net/rte_net.c
index 1771588a09..67d57d5f04 100644
--- a/lib/net/rte_net.c
+++ b/lib/net/rte_net.c
@@ -197,6 +197,7 @@ ptype_tunnel_with_udp(uint16_t *proto, const struct
rte_mbuf *m,
switch (port_no) {
case RTE_VXLAN_DEFAULT_PORT: {
*off += sizeof(struct rte_vxlan_hdr);
+ hdr_lens->tunnel_len = sizeof(struct rte_vxlan_hdr);
hdr_lens->inner_l2_len = RTE_ETHER_VXLAN_HLEN;
*proto = RTE_VXLAN_GPE_TYPE_ETH; /* just for eth header parse.
*/
return RTE_PTYPE_TUNNEL_VXLAN;
@@ -208,6 +209,7 @@ ptype_tunnel_with_udp(uint16_t *proto, const struct
rte_mbuf *m,
if (unlikely(vgh == NULL))
return 0;
*off += sizeof(struct rte_vxlan_gpe_hdr);
+ hdr_lens->tunnel_len = sizeof(struct rte_vxlan_gpe_hdr);
hdr_lens->inner_l2_len = RTE_ETHER_VXLAN_GPE_HLEN;
*proto = vgh->proto;
@@ -243,6 +245,7 @@ ptype_tunnel_with_udp(uint16_t *proto, const struct
rte_mbuf *m,
}
*off += gtp_len;
hdr_lens->inner_l2_len = gtp_len + sizeof(struct rte_udp_hdr);
+ hdr_lens->tunnel_len = gtp_len;
if (port_no == RTE_GTPC_UDP_PORT)
return RTE_PTYPE_TUNNEL_GTPC;
else if (port_no == RTE_GTPU_UDP_PORT)
@@ -258,6 +261,7 @@ ptype_tunnel_with_udp(uint16_t *proto, const struct
rte_mbuf *m,
return 0;
geneve_len = sizeof(*gnh) + gnh->opt_len * 4;
*off = geneve_len;
+ hdr_lens->tunnel_len = geneve_len;
*proto = gnh->proto;
if (gnh->proto == 0)
*proto = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4);
--
2.33.0
[PATCH] rcu: add deprecation notice about limit on defer queue element size
The functions rte_rcu_qsbr_dq_create and rte_rcu_qsbr_dq_reclaim establish no limit on the size of each element in the defer queue. With DPDK 25.11 a hard limit will be set (``RTE_QSBR_ESIZE_MAX``). This will allow fixed C arrays to be used in the functions' implementations, avoiding VLAs and use of alloca(). Signed-off-by: Andre Muezerie --- doc/guides/rel_notes/deprecation.rst | 6 ++ 1 file changed, 6 insertions(+) diff --git a/doc/guides/rel_notes/deprecation.rst b/doc/guides/rel_notes/deprecation.rst index 36489f6e68..78b2a27b52 100644 --- a/doc/guides/rel_notes/deprecation.rst +++ b/doc/guides/rel_notes/deprecation.rst @@ -17,6 +17,12 @@ Other API and ABI deprecation notices are to be posted below. Deprecation Notices --- +* rcu: The functions ``rte_rcu_qsbr_dq_create`` and ``rte_rcu_qsbr_dq_reclaim`` + establish no limit on the size of each element in the defer queue. With + DPDK 25.11 a hard limit will be set (``RTE_QSBR_ESIZE_MAX``). This will + allow fixed C arrays to be used in the functions' implementations, + avoiding VLAs and use of alloca(). + * build: The ``enable_kmods`` option is deprecated and will be removed in a future release. Setting/clearing the option has no impact on the build. Instead, kernel modules will be always built for OS's where out-of-tree kernel modules -- 2.49.0.vfs.0.3
RE: [PATCH v1 3/4] ring: fix potential sync issue between head and tail values
Hi Konstanin,
In rte_ring the store-release on tail update guarantees that CAS
won't get reordered with the store-released of the tail update.
So, the sequence of events would look like this (combined view
of head and tail update)
Releaxed-load(new_head, N) > (A)
Relaxed-CAS(d->head, new_head, old_head) > (B)
Store-release-store(d->tail, new_head) > (C)
If we look at address dependencies, then...
(B) depends on (A) due to new_head address dependency.
(C) depends on (A) due to new_head address dependency.
So, dependency graph looks like this
(A)
/ \
vv
(B) (C)
There is no implicit dependence between (B) and (C), I think
this is the issue you are brining up.
Even though there is no dependence between the two,
the store-release of (C) ensures that (B) won't drop below it.
Therefore, the above graph can be turned into an ordered
sequence as shown below..
(A) -> (B) -> (C)
I haven't looked at the so-ring yet. Could it be possible that the
issue is due to something else introduced in that code?
Thanks,
--wathsala
> This patch aims several purposes:
> - provide an alternative (and I think a better) way to fix the
> issue discussed in previous patch:
> "ring/soring: fix synchronization issue between head and tail values"
> - make sure that such problem wouldn’t happen within other usages of
> __rte_ring_headtail_move_head() – both current rte_ring
> implementation and possible future use-cases.
> - step towards unification of move_head() implementations and
> removing rte_ring_generic_pvt.h
> It uses Acquire-Release memory ordering for CAS operation in move_head().
> That guarantees that corresponding ‘tail’ updates will be visible before
> current
> ‘head’ is updated.
> As I said before: I think that in theory the problem described in previous
> patch
> might happen with our conventional rte_ring too (when
> RTE_USE_C11_MEM_MODEL enabled).
> But, so far I didn’t manage to reproduce it in reality.
> For that reason and also because it touches a critical rte_ring code-path, I
> put
> these changes into a separate patch. Expect all interested stakeholders to
> come-
> up with their comments and observations.
> Regarding performance impact – on my boxes both ring_perf_autotest and
> ring_stress_autotest – show a mixed set of results: some of them become few
> cycles faster, another few cycles slower.
> But so far, I didn’t notice any real degradations with that patch.
>
> Fixes: b5458e2cc483 ("ring: introduce staged ordered ring")
> Fixes: 1cc363b8ce06 ("ring: introduce HTS ring mode")
> Fixes: e6ba4731c0f3 ("ring: introduce RTS ring mode")
> Fixes: 49594a63147a ("ring/c11: relax ordering for load and store of the
> head")
>
> Signed-off-by: Konstantin Ananyev
> ---
> lib/ring/rte_ring_c11_pvt.h | 27 +--
> lib/ring/rte_ring_hts_elem_pvt.h | 6 --
> lib/ring/rte_ring_rts_elem_pvt.h
> | 6 --
> lib/ring/soring.c| 5 -
> 4 files changed, 25 insertions(+), 19 deletions(-)
>
> diff --git a/lib/ring/rte_ring_c11_pvt.h b/lib/ring/rte_ring_c11_pvt.h index
> 0845cd6dcf..6d1c46df9a 100644
> --- a/lib/ring/rte_ring_c11_pvt.h
> +++ b/lib/ring/rte_ring_c11_pvt.h
> @@ -77,20 +77,19 @@ __rte_ring_headtail_move_head(struct
> rte_ring_headtail *d,
> int success;
> unsigned int max = n;
>
> + /* Ensure the head is read before tail */
> *old_head = rte_atomic_load_explicit(&d->head,
> - rte_memory_order_relaxed);
> + rte_memory_order_acquire);
> do {
> /* Reset n to the initial burst count */
> n = max;
>
> - /* Ensure the head is read before tail */
> - rte_atomic_thread_fence(rte_memory_order_acquire);
> -
> - /* load-acquire synchronize with store-release of ht->tail
> - * in update_tail.
> + /*
> + * Read s->tail value. Note that it will be loaded after
> + * d->head load, but before CAS operation for the d->head.
>*/
> stail = rte_atomic_load_explicit(&s->tail,
> - rte_memory_order_acquire);
> + rte_memory_order_relaxed);
>
> /* The subtraction is done between two unsigned 32bits value
>* (the result is always modulo 32 bits even if we have @@ -
> 112,11 +111,19 @@ __rte_ring_headtail_move_head(struct rte_ring_headtail
> *d,
> d->head = *new_head;
> success = 1;
> } else
> - /* on failure, *old_head is updated */
> + /*
> + * on failure, *old_head is updated.
> + * this CAS(ACQ_REL, ACQUIRE) serves as a hoist
> +
