[PATCH] D156799: Update generic scheduling to use A510 scheduling model
harviniriawan updated this revision to Diff 551951. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156799/new/ https://reviews.llvm.org/D156799 Files: clang/test/CodeGen/aarch64-ABI-align-packed-assembly.c llvm/lib/Target/AArch64/AArch64.td llvm/test/Analysis/CostModel/AArch64/vector-select.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2_lse128.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-outline_atomics.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc3.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8_1a.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a.ll llvm/test/CodeGen/AArch64/GlobalISel/aapcs_vararg_frame.ll llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll llvm/test/CodeGen/AArch64/GlobalISel/select-bitfield-insert.ll llvm/test/CodeGen/AArch64/GlobalISel/stacksave-stackrestore.ll llvm/test/CodeGen/AArch64/GlobalISel/store-merging.ll llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll llvm/test/CodeGen/AArch64/a57-csel.ll llvm/test/CodeGen/AArch64/aarch64-addv.ll llvm/test/CodeGen/AArch64/aarch64-be-bv.ll llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll llvm/test/CodeGen/AArch64/aarch64-combine-add-sub-mul.ll llvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll llvm/test/CodeGen/AArch64/aarch64-fixup-statepoint-regs-crash.ll llvm/test/CodeGen/AArch64/aarch64-fold-lslfast.ll llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll llvm/test/CodeGen/AArch64/aarch64-isel-csinc.ll llvm/test/CodeGen/AArch64/aarch64-load-ext.ll llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll llvm/test/CodeGen/AArch64/aarch64-mops-consecutive.ll llvm/test/CodeGen/AArch64/aarch64-mops.ll llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll llvm/test/CodeGen/AArch64/aarch64-pmull2.ll llvm/test/CodeGen/AArch64/aarch64-smull.ll llvm/test/CodeGen/AArch64/aarch64-uzp1-combine.ll llvm/test/CodeGen/AArch64/aarch64-wide-mul.ll llvm/test/CodeGen/AArch64/aarch64_fnmadd.ll llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll llvm/test/CodeGen/AArch64/abd-combine.ll llvm/test/CodeGen/AArch64/active_lane_mask.ll llvm/test/CodeGen/AArch64/add-extract.ll llvm/test/CodeGen/AArch64/addcarry-crash.ll llvm/test/CodeGen/AArch64/addsub-constant-folding.ll llvm/test/CodeGen/AArch64/addsub.ll llvm/test/CodeGen/AArch64/align-down.ll llvm/test/CodeGen/AArch64/and-mask-removal.ll llvm/test/CodeGen/AArch64/andorbrcompare.ll llvm/test/CodeGen/AArch64/argument-blocks-array-of-struct.ll llvm/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll llvm/test/CodeGen/AArch64/arm64-addrmode.ll llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll llvm/test/CodeGen/AArch64/arm64-cse.ll llvm/test/CodeGen/AArch64/arm64-csel.ll llvm/test/CodeGen/AArch64/arm64-dup.ll llvm/test/CodeGen/AArch64/arm64-fcopysign.ll llvm/test/CodeGen/AArch64/arm64-fmadd.ll llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-no-helper.ll llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll llvm/test/CodeGen/AArch64/arm64-inline-asm.ll llvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll llvm/test/CodeGen/AArch64/arm64-ld1.ll llvm/test/CodeGen/AArch64/arm64-ldp.ll llvm/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll llvm/test/CodeGen/AArch64/arm64-mul.ll llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll llvm/test/CodeGen/AArch64/arm64-neon-mul-div.ll llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll llvm/test/CodeGen/AArch64/arm64-non-pow2-ldst.ll llvm/test/CodeGen/AArch64/arm64-nvcast.ll llvm/test/CodeGen/AArch64/arm64-promote-const-complex-initializers.ll llvm/test/CodeGen/AArch64/arm64-register-pairing.ll llvm/test/CodeGen/AArch64/arm64-rev.ll llvm/test/CodeGen/AArch64/arm64-setcc-int-to-fp-combine.ll llvm/test/CodeGen/AArch64/arm64-setcc-swap-infloop.ll llvm/test/CodeGen/AArch64/arm64-sh
[PATCH] D156799: Update generic scheduling to use A510 scheduling model
harviniriawan updated this revision to Diff 551953. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156799/new/ https://reviews.llvm.org/D156799 Files: clang/test/CodeGen/aarch64-ABI-align-packed-assembly.c llvm/lib/Target/AArch64/AArch64.td llvm/test/Analysis/CostModel/AArch64/vector-select.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2_lse128.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-outline_atomics.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc3.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8_1a.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a.ll llvm/test/CodeGen/AArch64/GlobalISel/aapcs_vararg_frame.ll llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll llvm/test/CodeGen/AArch64/GlobalISel/select-bitfield-insert.ll llvm/test/CodeGen/AArch64/GlobalISel/stacksave-stackrestore.ll llvm/test/CodeGen/AArch64/GlobalISel/store-merging.ll llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll llvm/test/CodeGen/AArch64/a57-csel.ll llvm/test/CodeGen/AArch64/aarch64-addv.ll llvm/test/CodeGen/AArch64/aarch64-be-bv.ll llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll llvm/test/CodeGen/AArch64/aarch64-combine-add-sub-mul.ll llvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll llvm/test/CodeGen/AArch64/aarch64-fixup-statepoint-regs-crash.ll llvm/test/CodeGen/AArch64/aarch64-fold-lslfast.ll llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll llvm/test/CodeGen/AArch64/aarch64-isel-csinc.ll llvm/test/CodeGen/AArch64/aarch64-load-ext.ll llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll llvm/test/CodeGen/AArch64/aarch64-mops-consecutive.ll llvm/test/CodeGen/AArch64/aarch64-mops.ll llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll llvm/test/CodeGen/AArch64/aarch64-pmull2.ll llvm/test/CodeGen/AArch64/aarch64-smull.ll llvm/test/CodeGen/AArch64/aarch64-uzp1-combine.ll llvm/test/CodeGen/AArch64/aarch64-wide-mul.ll llvm/test/CodeGen/AArch64/aarch64_fnmadd.ll llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll llvm/test/CodeGen/AArch64/abd-combine.ll llvm/test/CodeGen/AArch64/active_lane_mask.ll llvm/test/CodeGen/AArch64/add-extract.ll llvm/test/CodeGen/AArch64/addcarry-crash.ll llvm/test/CodeGen/AArch64/addsub-constant-folding.ll llvm/test/CodeGen/AArch64/addsub.ll llvm/test/CodeGen/AArch64/align-down.ll llvm/test/CodeGen/AArch64/and-mask-removal.ll llvm/test/CodeGen/AArch64/andorbrcompare.ll llvm/test/CodeGen/AArch64/argument-blocks-array-of-struct.ll llvm/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll llvm/test/CodeGen/AArch64/arm64-addrmode.ll llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll llvm/test/CodeGen/AArch64/arm64-cse.ll llvm/test/CodeGen/AArch64/arm64-csel.ll llvm/test/CodeGen/AArch64/arm64-dup.ll llvm/test/CodeGen/AArch64/arm64-fcopysign.ll llvm/test/CodeGen/AArch64/arm64-fmadd.ll llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-no-helper.ll llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll llvm/test/CodeGen/AArch64/arm64-inline-asm.ll llvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll llvm/test/CodeGen/AArch64/arm64-ld1.ll llvm/test/CodeGen/AArch64/arm64-ldp.ll llvm/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll llvm/test/CodeGen/AArch64/arm64-mul.ll llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll llvm/test/CodeGen/AArch64/arm64-neon-mul-div.ll llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll llvm/test/CodeGen/AArch64/arm64-non-pow2-ldst.ll llvm/test/CodeGen/AArch64/arm64-nvcast.ll llvm/test/CodeGen/AArch64/arm64-promote-const-complex-initializers.ll llvm/test/CodeGen/AArch64/arm64-register-pairing.ll llvm/test/CodeGen/AArch64/arm64-rev.ll llvm/test/CodeGen/AArch64/arm64-setcc-int-to-fp-combine.ll llvm/test/CodeGen/AArch64/arm64-setcc-swap-infloop.ll llvm/test/CodeGen/AArch64/arm64-sh
[PATCH] D156799: Update generic scheduling to use A510 scheduling model
harviniriawan updated this revision to Diff 551978. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156799/new/ https://reviews.llvm.org/D156799 Files: clang/test/CodeGen/aarch64-ABI-align-packed-assembly.c llvm/lib/Target/AArch64/AArch64.td llvm/test/Analysis/CostModel/AArch64/vector-select.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2_lse128.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-outline_atomics.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc3.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8_1a.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a.ll llvm/test/CodeGen/AArch64/GlobalISel/aapcs_vararg_frame.ll llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll llvm/test/CodeGen/AArch64/GlobalISel/select-bitfield-insert.ll llvm/test/CodeGen/AArch64/GlobalISel/stacksave-stackrestore.ll llvm/test/CodeGen/AArch64/GlobalISel/store-merging.ll llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll llvm/test/CodeGen/AArch64/a57-csel.ll llvm/test/CodeGen/AArch64/aarch64-addv.ll llvm/test/CodeGen/AArch64/aarch64-be-bv.ll llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll llvm/test/CodeGen/AArch64/aarch64-combine-add-sub-mul.ll llvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll llvm/test/CodeGen/AArch64/aarch64-fixup-statepoint-regs-crash.ll llvm/test/CodeGen/AArch64/aarch64-fold-lslfast.ll llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll llvm/test/CodeGen/AArch64/aarch64-isel-csinc.ll llvm/test/CodeGen/AArch64/aarch64-load-ext.ll llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll llvm/test/CodeGen/AArch64/aarch64-mops-consecutive.ll llvm/test/CodeGen/AArch64/aarch64-mops.ll llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll llvm/test/CodeGen/AArch64/aarch64-pmull2.ll llvm/test/CodeGen/AArch64/aarch64-smull.ll llvm/test/CodeGen/AArch64/aarch64-uzp1-combine.ll llvm/test/CodeGen/AArch64/aarch64-wide-mul.ll llvm/test/CodeGen/AArch64/aarch64_fnmadd.ll llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll llvm/test/CodeGen/AArch64/abd-combine.ll llvm/test/CodeGen/AArch64/active_lane_mask.ll llvm/test/CodeGen/AArch64/add-extract.ll llvm/test/CodeGen/AArch64/addcarry-crash.ll llvm/test/CodeGen/AArch64/addsub-constant-folding.ll llvm/test/CodeGen/AArch64/addsub.ll llvm/test/CodeGen/AArch64/align-down.ll llvm/test/CodeGen/AArch64/and-mask-removal.ll llvm/test/CodeGen/AArch64/andorbrcompare.ll llvm/test/CodeGen/AArch64/argument-blocks-array-of-struct.ll llvm/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll llvm/test/CodeGen/AArch64/arm64-addrmode.ll llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll llvm/test/CodeGen/AArch64/arm64-cse.ll llvm/test/CodeGen/AArch64/arm64-csel.ll llvm/test/CodeGen/AArch64/arm64-dup.ll llvm/test/CodeGen/AArch64/arm64-fcopysign.ll llvm/test/CodeGen/AArch64/arm64-fmadd.ll llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-no-helper.ll llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll llvm/test/CodeGen/AArch64/arm64-inline-asm.ll llvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll llvm/test/CodeGen/AArch64/arm64-ld1.ll llvm/test/CodeGen/AArch64/arm64-ldp.ll llvm/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll llvm/test/CodeGen/AArch64/arm64-mul.ll llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll llvm/test/CodeGen/AArch64/arm64-neon-mul-div.ll llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll llvm/test/CodeGen/AArch64/arm64-non-pow2-ldst.ll llvm/test/CodeGen/AArch64/arm64-nvcast.ll llvm/test/CodeGen/AArch64/arm64-promote-const-complex-initializers.ll llvm/test/CodeGen/AArch64/arm64-register-pairing.ll llvm/test/CodeGen/AArch64/arm64-rev.ll llvm/test/CodeGen/AArch64/arm64-setcc-int-to-fp-combine.ll llvm/test/CodeGen/AArch64/arm64-setcc-swap-infloop.ll llvm/test/CodeGen/AArch64/arm64-sh
[PATCH] D156799: Update generic scheduling to use A510 scheduling model
harviniriawan updated this revision to Diff 546884. harviniriawan marked 23 inline comments as done. Herald added a project: clang. Herald added a subscriber: cfe-commits. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156799/new/ https://reviews.llvm.org/D156799 Files: clang/test/CodeGen/aarch64-ABI-align-packed-assembly.c llvm/lib/Target/AArch64/AArch64.td llvm/test/Analysis/CostModel/AArch64/vector-select.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2_lse128.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-outline_atomics.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc3.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8_1a.ll llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a.ll llvm/test/CodeGen/AArch64/GlobalISel/aapcs_vararg_frame.ll llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll llvm/test/CodeGen/AArch64/GlobalISel/select-bitfield-insert.ll llvm/test/CodeGen/AArch64/GlobalISel/store-merging.ll llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll llvm/test/CodeGen/AArch64/a57-csel.ll llvm/test/CodeGen/AArch64/aarch64-addv.ll llvm/test/CodeGen/AArch64/aarch64-be-bv.ll llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll llvm/test/CodeGen/AArch64/aarch64-combine-add-sub-mul.ll llvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll llvm/test/CodeGen/AArch64/aarch64-fixup-statepoint-regs-crash.ll llvm/test/CodeGen/AArch64/aarch64-fold-lslfast.ll llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll llvm/test/CodeGen/AArch64/aarch64-isel-csinc.ll llvm/test/CodeGen/AArch64/aarch64-load-ext.ll llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll llvm/test/CodeGen/AArch64/aarch64-mops-consecutive.ll llvm/test/CodeGen/AArch64/aarch64-mops.ll llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll llvm/test/CodeGen/AArch64/aarch64-pmull2.ll llvm/test/CodeGen/AArch64/aarch64-smull.ll llvm/test/CodeGen/AArch64/aarch64-uzp1-combine.ll llvm/test/CodeGen/AArch64/aarch64-wide-mul.ll llvm/test/CodeGen/AArch64/aarch64_fnmadd.ll llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll llvm/test/CodeGen/AArch64/abd-combine.ll llvm/test/CodeGen/AArch64/active_lane_mask.ll llvm/test/CodeGen/AArch64/add-extract.ll llvm/test/CodeGen/AArch64/addcarry-crash.ll llvm/test/CodeGen/AArch64/addsub-constant-folding.ll llvm/test/CodeGen/AArch64/addsub.ll llvm/test/CodeGen/AArch64/align-down.ll llvm/test/CodeGen/AArch64/and-mask-removal.ll llvm/test/CodeGen/AArch64/andorbrcompare.ll llvm/test/CodeGen/AArch64/argument-blocks-array-of-struct.ll llvm/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll llvm/test/CodeGen/AArch64/arm64-addrmode.ll llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll llvm/test/CodeGen/AArch64/arm64-cse.ll llvm/test/CodeGen/AArch64/arm64-csel.ll llvm/test/CodeGen/AArch64/arm64-fcopysign.ll llvm/test/CodeGen/AArch64/arm64-fmadd.ll llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-no-helper.ll llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll llvm/test/CodeGen/AArch64/arm64-inline-asm.ll llvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll llvm/test/CodeGen/AArch64/arm64-ld1.ll llvm/test/CodeGen/AArch64/arm64-ldp.ll llvm/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll llvm/test/CodeGen/AArch64/arm64-mul.ll llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll llvm/test/CodeGen/AArch64/arm64-neon-mul-div.ll llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll llvm/test/CodeGen/AArch64/arm64-non-pow2-ldst.ll llvm/test/CodeGen/AArch64/arm64-nvcast.ll llvm/test/CodeGen/AArch64/arm64-promote-const-complex-initializers.ll llvm/test/CodeGen/AArch64/arm64-register-pairing.ll llvm/test/CodeGen/AArch64/arm64-rev.ll llvm/test/CodeGen/AArch64/arm64-setcc-int-to-fp-combine.ll llvm/test/CodeGen/AArch64/arm64-setcc-swap-infloop.ll llvm/test/CodeGen/AA
[PATCH] D156799: Update generic scheduling to use A510 scheduling model
harviniriawan added inline comments. Comment at: llvm/test/CodeGen/AArch64/stack-guard-sysreg.ll:1 -; RUN: split-file %s %t ; RUN: cat %t/main.ll %t/a.ll > %t/a2.ll ; RUN: cat %t/main.ll %t/b.ll > %t/b2.ll dmgreen wrote: > Can you explain this one? Are the two versions now too different to keep the > same? Yes indeed. the ones with CHECK-ADD annoyingly is scheduled slightly differently due to it being ADD instead of LDR Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156799/new/ https://reviews.llvm.org/D156799 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
