from:"Zhang Kang via Phabricator via cfe\-commits"

[PATCH] D55192: [PowerPC] VSX register support for inline assembly

2018-12-07 Thread Zhang Kang via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rC348572: [PowerPC] VSX register support for inline assembly 
(authored by ZhangKang, committed by ).
Herald added a subscriber: cfe-commits.

Changed prior to commit:
  https://reviews.llvm.org/D55192?vs=177132&id=177141#toc

Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55192/new/

https://reviews.llvm.org/D55192

Files:
  lib/Basic/Targets/PPC.cpp
  lib/Basic/Targets/PPC.h
  test/CodeGen/inline-asm-matching-ppc-vsx.c


Index: test/CodeGen/inline-asm-matching-ppc-vsx.c
===
--- test/CodeGen/inline-asm-matching-ppc-vsx.c
+++ test/CodeGen/inline-asm-matching-ppc-vsx.c
@@ -0,0 +1,20 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-feature +vsx \
+// RUN:   -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+
+// This case is to test VSX register support in the clobbers list for inline 
asm.
+void testVSX (void) {
+  unsigned int a = 0;
+  unsigned int *dbell=&a;
+  int d;
+  __asm__ __volatile__ (
+"lxvw4x  %%vs32, 0, %2\n\t"
+"stxvw4x %%vs32, 0, %1"
+: "=m"(*(volatile unsigned int*)(dbell))
+: "r" (dbell), "r" (&d)
+: "vs32"
+  );
+}
+
+// CHECK: call void asm sideeffect "lxvw4x  %vs32, 0, $2\0A\09stxvw4x %vs32, 
0, $1", "=*m,r,r,~{vs32}"
Index: lib/Basic/Targets/PPC.cpp
===
--- lib/Basic/Targets/PPC.cpp
+++ lib/Basic/Targets/PPC.cpp
@@ -412,6 +412,36 @@
   return llvm::makeArrayRef(GCCRegAliases);
 }
 
+// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
+// vs0 ~ vs31 is mapping to 32 - 63,
+// vs32 ~ vs63 is mapping to 77 - 108. 
+const TargetInfo::AddlRegName GCCAddlRegNames[] = {
+// Table of additional register names to use in user input.
+{{"vs0"}, 32},   {{"vs1"}, 33},   {{"vs2"}, 34},   {{"vs3"}, 35}, 
+{{"vs4"}, 36},   {{"vs5"}, 37},   {{"vs6"}, 38},   {{"vs7"}, 39},
+{{"vs8"}, 40},   {{"vs9"}, 41},   {{"vs10"}, 42},  {{"vs11"}, 43},
+{{"vs12"}, 44},  {{"vs13"}, 45},  {{"vs14"}, 46},  {{"vs15"}, 47},
+{{"vs16"}, 48},  {{"vs17"}, 49},  {{"vs18"}, 50},  {{"vs19"}, 51},
+{{"vs20"}, 52},  {{"vs21"}, 53},  {{"vs22"}, 54},  {{"vs23"}, 55},
+{{"vs24"}, 56},  {{"vs25"}, 57},  {{"vs26"}, 58},  {{"vs27"}, 59},
+{{"vs28"}, 60},  {{"vs29"}, 61},  {{"vs30"}, 62},  {{"vs31"}, 63},
+{{"vs32"}, 77},  {{"vs33"}, 78},  {{"vs34"}, 79},  {{"vs35"}, 80},
+{{"vs36"}, 81},  {{"vs37"}, 82},  {{"vs38"}, 83},  {{"vs39"}, 84},
+{{"vs40"}, 85},  {{"vs41"}, 86},  {{"vs42"}, 87},  {{"vs43"}, 88},
+{{"vs44"}, 89},  {{"vs45"}, 90},  {{"vs46"}, 91},  {{"vs47"}, 92},
+{{"vs48"}, 93},  {{"vs49"}, 94},  {{"vs50"}, 95},  {{"vs51"}, 96},
+{{"vs52"}, 97},  {{"vs53"}, 98},  {{"vs54"}, 99},  {{"vs55"}, 100},
+{{"vs56"}, 101}, {{"vs57"}, 102}, {{"vs58"}, 103}, {{"vs59"}, 104},
+{{"vs60"}, 105}, {{"vs61"}, 106}, {{"vs62"}, 107}, {{"vs63"}, 108},
+};
+
+ArrayRef PPCTargetInfo::getGCCAddlRegNames() const {
+  if (ABI == "elfv2")
+return llvm::makeArrayRef(GCCAddlRegNames);
+  else 
+return TargetInfo::getGCCAddlRegNames(); 
+}
+
 static constexpr llvm::StringLiteral ValidCPUNames[] = {
 {"generic"}, {"440"}, {"450"}, {"601"},{"602"},
 {"603"}, {"603e"},{"603ev"},   {"604"},{"604e"},
Index: lib/Basic/Targets/PPC.h
===
--- lib/Basic/Targets/PPC.h
+++ lib/Basic/Targets/PPC.h
@@ -176,6 +176,8 @@
 
   ArrayRef getGCCRegAliases() const override;
 
+  ArrayRef getGCCAddlRegNames() const override;
+
   bool validateAsmConstraint(const char *&Name,
  TargetInfo::ConstraintInfo &Info) const override {
 switch (*Name) {


Index: test/CodeGen/inline-asm-matching-ppc-vsx.c
===
--- test/CodeGen/inline-asm-matching-ppc-vsx.c
+++ test/CodeGen/inline-asm-matching-ppc-vsx.c
@@ -0,0 +1,20 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-feature +vsx \
+// RUN:   -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+
+// This case is to test VSX register support in the clobbers list for inline asm.
+void testVSX (void) {
+  unsigned int a = 0;
+  unsigned int *dbell=&a;
+  int d;
+  __asm__ __volatile__ (
+"lxvw4x  %%vs32, 0, %2\n\t"
+"stxvw4x %%vs32, 0, %1"
+: "=m"(*(volatile unsigned int*)(dbell))
+: "r" (dbell), "r" (&d)
+: "vs32"
+  );
+}
+
+// CHECK: call void asm sideeffect "lxvw4x  %vs32, 0, $2\0A\09stxvw4x %vs32, 0, $1", "=*m,r,r,~{vs32}"
Index: lib/Basic/Targets/PPC.cpp
===
--- lib/Basic/Targets/PPC.cpp
+++ lib/Basic/Targets/PPC.cpp
@@ -412,6 +412,36 @@
   return llvm::makeArrayRef(GCCRegA

[PATCH] D85599: [Clang] Consider __builtin_trap() and __builtin_debugtrap() as terminator

2020-08-09 Thread Zhang Kang via Phabricator via cfe-commits

ZhangKang created this revision.
ZhangKang added reviewers: PowerPC, nemanjai, ahatanak, vitalybuka, dblaikie.
ZhangKang added a project: LLVM.
Herald added subscribers: Sanitizers, cfe-commits, steven.zhang, wuzish, 
dexonsmith, kristof.beyls.
Herald added projects: clang, Sanitizers.
ZhangKang requested review of this revision.

In some backend like ARM, PowerPC, TRAP instrcution is as a terminator. 
But in clang, we didn't as __builtin_trap() and  __builtin_debugtrap()  as 
terminator.
This bug has caused 6 lit cases error on PPC.

For below case,

  void test_builtin_trap() {
volatile int i = 0;
__builtin_trap();
volatile int j = i;
  }

we use `clang sim.c -target powerpc-unknown-unknown  -c` to build it, we will 
get below error:

  *** Bad machine code: Non-terminator instruction after the first terminator 
***
  - function:test_builtin_trap
  - basic block: %bb.0 entry (0x1002c61f1f8)
  - instruction: %1:gprc = LWZ 0, %stack.0.i :: (volatile dereferenceable load 
4 from %ir.i)
  First terminator was: TRAP
  
  *** Bad machine code: Non-terminator instruction after the first terminator 
***
  - function:test_builtin_trap
  - basic block: %bb.0 entry (0x1002c61f1f8)
  - instruction: STW killed %1:gprc, 0, %stack.1.j :: (volatile store 4 into 
%ir.j)
  First terminator was: TRAP
  fatal error: error in backend: Found 2 machine code errors.

This patch is to fix above bug.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D85599

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc.c
  compiler-rt/test/profile/gcov-__gcov_flush-terminate.c


Index: compiler-rt/test/profile/gcov-__gcov_flush-terminate.c
===
--- compiler-rt/test/profile/gcov-__gcov_flush-terminate.c
+++ compiler-rt/test/profile/gcov-__gcov_flush-terminate.c
@@ -19,6 +19,6 @@
   __gcov_reset();  // CHECK-NEXT: 1: [[#@LINE]]:
   i = 42;  // CHECK-NEXT: 1: [[#@LINE]]:
   __builtin_trap();// CHECK-NEXT: 1: [[#@LINE]]:
-  i = 84;  // CHECK-NEXT: 1: [[#@LINE]]:
-  return 0;// CHECK-NEXT: 1: [[#@LINE]]:
+  i = 84;  // CHECK-NEXT: -: [[#@LINE]]:
+  return 0;// CHECK-NEXT: -: [[#@LINE]]:
 }
Index: clang/test/CodeGen/builtins-ppc.c
===
--- clang/test/CodeGen/builtins-ppc.c
+++ clang/test/CodeGen/builtins-ppc.c
@@ -27,3 +27,23 @@
   // CHECK: call double @llvm.ppc.setrnd(i32 %2)
   res = __builtin_setrnd(x);
 }
+
+void test_builtin_trap() {
+  volatile int i = 0;
+  __builtin_trap();
+  volatile int j = i;
+
+  // CHECK-LABEL: test_builtin_trap
+  // CHECK: call void @llvm.trap()
+  // CHECK: unreachable
+}
+
+void test_builtin_debugtrap() {
+  volatile int i = 0;
+  __builtin_debugtrap();
+  volatile int j = i;
+
+  // CHECK-LABEL: test_builtin_debugtrap
+  // CHECK: call void @llvm.debugtrap()
+  // CHECK: unreachable
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -2351,8 +2351,24 @@
 Function *F = CGM.getIntrinsic(Intrinsic::clear_cache);
 return RValue::get(Builder.CreateCall(F, {Begin, End}));
   }
-  case Builtin::BI__builtin_trap:
-return RValue::get(EmitTrapCall(Intrinsic::trap));
+  case Builtin::BI__builtin_trap: {
+Builder.CreateCall(CGM.getIntrinsic(Intrinsic::trap));
+Builder.CreateUnreachable();
+
+// We do need to preserve an insertion point.
+EmitBlock(createBasicBlock("trap.cont"));
+
+return RValue::get(nullptr);
+  }
+  case Builtin::BI__builtin_debugtrap: {
+Builder.CreateCall(CGM.getIntrinsic(Intrinsic::debugtrap));
+Builder.CreateUnreachable();
+
+// We do need to preserve an insertion point.
+EmitBlock(createBasicBlock("debugtrap.cont"));
+
+return RValue::get(nullptr);
+  }
   case Builtin::BI__debugbreak:
 return RValue::get(EmitTrapCall(Intrinsic::debugtrap));
   case Builtin::BI__builtin_unreachable: {


Index: compiler-rt/test/profile/gcov-__gcov_flush-terminate.c
===
--- compiler-rt/test/profile/gcov-__gcov_flush-terminate.c
+++ compiler-rt/test/profile/gcov-__gcov_flush-terminate.c
@@ -19,6 +19,6 @@
   __gcov_reset();  // CHECK-NEXT: 1: [[#@LINE]]:
   i = 42;  // CHECK-NEXT: 1: [[#@LINE]]:
   __builtin_trap();// CHECK-NEXT: 1: [[#@LINE]]:
-  i = 84;  // CHECK-NEXT: 1: [[#@LINE]]:
-  return 0;// CHECK-NEXT: 1: [[#@LINE]]:
+  i = 84;  // CHECK-NEXT: -: [[#@LINE]]:
+  return 0;// CHECK-NEXT: -: [[#@LINE]]:
 }
Index: clang/test/CodeGen/builtins-ppc.c
===

[PATCH] D85599: [Clang] Consider __builtin_trap() and __builtin_debugtrap() as terminator

2020-08-10 Thread Zhang Kang via Phabricator via cfe-commits

ZhangKang updated this revision to Diff 284250.
ZhangKang added a comment.

Fix the case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85599/new/

https://reviews.llvm.org/D85599

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc.c
  clang/test/CodeGenCXX/vararg-non-pod.cpp
  compiler-rt/test/profile/gcov-__gcov_flush-terminate.c


Index: compiler-rt/test/profile/gcov-__gcov_flush-terminate.c
===
--- compiler-rt/test/profile/gcov-__gcov_flush-terminate.c
+++ compiler-rt/test/profile/gcov-__gcov_flush-terminate.c
@@ -19,6 +19,6 @@
   __gcov_reset();  // CHECK-NEXT: 1: [[#@LINE]]:
   i = 42;  // CHECK-NEXT: 1: [[#@LINE]]:
   __builtin_trap();// CHECK-NEXT: 1: [[#@LINE]]:
-  i = 84;  // CHECK-NEXT: 1: [[#@LINE]]:
-  return 0;// CHECK-NEXT: 1: [[#@LINE]]:
+  i = 84;  // CHECK-NEXT: -: [[#@LINE]]:
+  return 0;// CHECK-NEXT: -: [[#@LINE]]:
 }
Index: clang/test/CodeGenCXX/vararg-non-pod.cpp
===
--- clang/test/CodeGenCXX/vararg-non-pod.cpp
+++ clang/test/CodeGenCXX/vararg-non-pod.cpp
@@ -12,5 +12,5 @@
 void test(X x) {
   // CHECK: call void @llvm.trap()
   vararg(x);
-  // CHECK: ret void
+  // CHECK: unreachable
 }
Index: clang/test/CodeGen/builtins-ppc.c
===
--- clang/test/CodeGen/builtins-ppc.c
+++ clang/test/CodeGen/builtins-ppc.c
@@ -27,3 +27,23 @@
   // CHECK: call double @llvm.ppc.setrnd(i32 %2)
   res = __builtin_setrnd(x);
 }
+
+void test_builtin_trap() {
+  volatile int i = 0;
+  __builtin_trap();
+  volatile int j = i;
+
+  // CHECK-LABEL: test_builtin_trap
+  // CHECK: call void @llvm.trap()
+  // CHECK: unreachable
+}
+
+void test_builtin_debugtrap() {
+  volatile int i = 0;
+  __builtin_debugtrap();
+  volatile int j = i;
+
+  // CHECK-LABEL: test_builtin_debugtrap
+  // CHECK: call void @llvm.debugtrap()
+  // CHECK: unreachable
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -2351,8 +2351,24 @@
 Function *F = CGM.getIntrinsic(Intrinsic::clear_cache);
 return RValue::get(Builder.CreateCall(F, {Begin, End}));
   }
-  case Builtin::BI__builtin_trap:
-return RValue::get(EmitTrapCall(Intrinsic::trap));
+  case Builtin::BI__builtin_trap: {
+RValue::get(EmitTrapCall(Intrinsic::trap));
+Builder.CreateUnreachable();
+
+// We do need to preserve an insertion point.
+EmitBlock(createBasicBlock("trap.cont"));
+
+return RValue::get(nullptr);
+  }
+  case Builtin::BI__builtin_debugtrap: {
+RValue::get(EmitTrapCall(Intrinsic::debugtrap));
+Builder.CreateUnreachable();
+
+// We do need to preserve an insertion point.
+EmitBlock(createBasicBlock("debugtrap.cont"));
+
+return RValue::get(nullptr);
+  }
   case Builtin::BI__debugbreak:
 return RValue::get(EmitTrapCall(Intrinsic::debugtrap));
   case Builtin::BI__builtin_unreachable: {


Index: compiler-rt/test/profile/gcov-__gcov_flush-terminate.c
===
--- compiler-rt/test/profile/gcov-__gcov_flush-terminate.c
+++ compiler-rt/test/profile/gcov-__gcov_flush-terminate.c
@@ -19,6 +19,6 @@
   __gcov_reset();  // CHECK-NEXT: 1: [[#@LINE]]:
   i = 42;  // CHECK-NEXT: 1: [[#@LINE]]:
   __builtin_trap();// CHECK-NEXT: 1: [[#@LINE]]:
-  i = 84;  // CHECK-NEXT: 1: [[#@LINE]]:
-  return 0;// CHECK-NEXT: 1: [[#@LINE]]:
+  i = 84;  // CHECK-NEXT: -: [[#@LINE]]:
+  return 0;// CHECK-NEXT: -: [[#@LINE]]:
 }
Index: clang/test/CodeGenCXX/vararg-non-pod.cpp
===
--- clang/test/CodeGenCXX/vararg-non-pod.cpp
+++ clang/test/CodeGenCXX/vararg-non-pod.cpp
@@ -12,5 +12,5 @@
 void test(X x) {
   // CHECK: call void @llvm.trap()
   vararg(x);
-  // CHECK: ret void
+  // CHECK: unreachable
 }
Index: clang/test/CodeGen/builtins-ppc.c
===
--- clang/test/CodeGen/builtins-ppc.c
+++ clang/test/CodeGen/builtins-ppc.c
@@ -27,3 +27,23 @@
   // CHECK: call double @llvm.ppc.setrnd(i32 %2)
   res = __builtin_setrnd(x);
 }
+
+void test_builtin_trap() {
+  volatile int i = 0;
+  __builtin_trap();
+  volatile int j = i;
+
+  // CHECK-LABEL: test_builtin_trap
+  // CHECK: call void @llvm.trap()
+  // CHECK: unreachable
+}
+
+void test_builtin_debugtrap() {
+  volatile int i = 0;
+  __builtin_debugtrap();
+  volatile int j = i;
+
+  // CHECK-LABEL: test_builtin_debugtrap
+

[PATCH] D85599: [PowerPC] Remove isTerminator for TRAP instruction

2020-08-10 Thread Zhang Kang via Phabricator via cfe-commits

ZhangKang added a comment.

In D85599#2206033 , @efriedma wrote:

> Fixing a MachineVerifier issue by patching clang is generally wrong; if the 
> IR is valid, the backend should do something sane with it.  If the IR isn't 
> valid, the IR Verifier should complain.
>
> Here, I'd say the IR is valid; adding a special case to the IR rules here 
> would be a pain.  So the right fix involves changing isel and/or the 
> definitions of the the instructions in question.

Yes, after the TRAP has been handled, the program should be continued. So I 
have removed the isTerminator for TRAP on PPC.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85599/new/

https://reviews.llvm.org/D85599

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[PATCH] D85599: [Clang] Consider __builtin_trap() and __builtin_debugtrap() as terminator

2020-08-10 Thread Zhang Kang via Phabricator via cfe-commits

ZhangKang updated this revision to Diff 284424.
ZhangKang added a comment.
Herald added a subscriber: hiraditya.

Remoeve isTerminator for TRAP instruction.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85599/new/

https://reviews.llvm.org/D85599

Files:
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins.ll


Index: llvm/test/CodeGen/PowerPC/builtins.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s
+
+define void @test_builtin_trap() {
+; CHECK-LABEL: test_builtin_trap:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:stw 3, -4(1)
+; CHECK-NEXT:trap
+; CHECK-NEXT:lwz 3, -4(1)
+; CHECK-NEXT:stw 3, -8(1)
+; CHECK-NEXT:blr
+entry:
+  %i = alloca i32, align 4
+  %j = alloca i32, align 4
+  store volatile i32 0, i32* %i, align 4
+  call void @llvm.trap()
+  %0 = load volatile i32, i32* %i, align 4
+  store volatile i32 %0, i32* %j, align 4
+  ret void
+}
+
+declare void @llvm.trap()
+
+define void @test_builtin_debugtrap() {
+; CHECK-LABEL: test_builtin_debugtrap:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:stw 3, -4(1)
+; CHECK-NEXT:trap
+; CHECK-NEXT:lwz 3, -4(1)
+; CHECK-NEXT:stw 3, -8(1)
+; CHECK-NEXT:blr
+entry:
+  %i = alloca i32, align 4
+  %j = alloca i32, align 4
+  store volatile i32 0, i32* %i, align 4
+  call void @llvm.debugtrap()
+  %0 = load volatile i32, i32* %i, align 4
+  store volatile i32 %0, i32* %j, align 4
+  ret void
+}
+
+declare void @llvm.debugtrap()
+
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2060,7 +2060,7 @@
   "stwat $rS, $rA, $FC", IIC_LdStStore>,
 Requires<[IsISA3_0]>;
 
-let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
+let isBarrier = 1, hasCtrlDep = 1 in
 def TRAP  : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
 
 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),


Index: llvm/test/CodeGen/PowerPC/builtins.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s
+
+define void @test_builtin_trap() {
+; CHECK-LABEL: test_builtin_trap:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:stw 3, -4(1)
+; CHECK-NEXT:trap
+; CHECK-NEXT:lwz 3, -4(1)
+; CHECK-NEXT:stw 3, -8(1)
+; CHECK-NEXT:blr
+entry:
+  %i = alloca i32, align 4
+  %j = alloca i32, align 4
+  store volatile i32 0, i32* %i, align 4
+  call void @llvm.trap()
+  %0 = load volatile i32, i32* %i, align 4
+  store volatile i32 %0, i32* %j, align 4
+  ret void
+}
+
+declare void @llvm.trap()
+
+define void @test_builtin_debugtrap() {
+; CHECK-LABEL: test_builtin_debugtrap:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:stw 3, -4(1)
+; CHECK-NEXT:trap
+; CHECK-NEXT:lwz 3, -4(1)
+; CHECK-NEXT:stw 3, -8(1)
+; CHECK-NEXT:blr
+entry:
+  %i = alloca i32, align 4
+  %j = alloca i32, align 4
+  store volatile i32 0, i32* %i, align 4
+  call void @llvm.debugtrap()
+  %0 = load volatile i32, i32* %i, align 4
+  store volatile i32 %0, i32* %j, align 4
+  ret void
+}
+
+declare void @llvm.debugtrap()
+
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2060,7 +2060,7 @@
   "stwat $rS, $rA, $FC", IIC_LdStStore>,
 Requires<[IsISA3_0]>;
 
-let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
+let isBarrier = 1, hasCtrlDep = 1 in
 def TRAP  : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
 
 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
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[PATCH] D55192: [PowerPC] VSX register support for inline assembly

[PATCH] D85599: [Clang] Consider __builtin_trap() and __builtin_debugtrap() as terminator

[PATCH] D85599: [Clang] Consider __builtin_trap() and __builtin_debugtrap() as terminator

[PATCH] D85599: [PowerPC] Remove isTerminator for TRAP instruction

[PATCH] D85599: [Clang] Consider __builtin_trap() and __builtin_debugtrap() as terminator

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