[PATCH] D151867: [Clang][RISCV] Make generic clz/ctz builtins defined for zero on RISCV targets.

2023-06-01 Thread Yunze Zhu(Thead) via Phabricator via cfe-commits 
Yunzezhu created this revision.
Yunzezhu added reviewers: asb, craig.topper, kito-cheng.
Yunzezhu added a project: clang.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, kristof.beyls, 
arichardson.
Herald added a project: All.
Yunzezhu requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.

For now llvm intrinsic ctlz/cttz are supported by extension zbb and xtheadbb,
and both extensions support returning well-defined results for zero inputs.
It's possible to set isCLZForZeroUndef flag to false by default on RISCV targets
as ARM and other target does.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D151867

Files:
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c

Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -26,6 +26,32 @@
   return __builtin_riscv_orc_b_64(a);
 }
 
+// RV64ZBB-LABEL: @clz_32_generic(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int clz_32_generic(int a) {
+  return __builtin_clz(a);
+}
+
+// RV64ZBB-LABEL: @clz_64_generic(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT:store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 false)
+// RV64ZBB-NEXT:[[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZBB-NEXT:[[CONV:%.*]] = sext i32 [[CAST]] to i64
+// RV64ZBB-NEXT:ret i64 [[CONV]]
+//
+long clz_64_generic(long a) {
+  return __builtin_clzl(a);
+}
+
 // RV64ZBB-LABEL: @clz_32(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
@@ -50,6 +76,32 @@
   return __builtin_riscv_clz_64(a);
 }
 
+// RV64ZBB-LABEL: @ctz_32_generic(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int ctz_32_generic(int a) {
+  return __builtin_ctz(a);
+}
+
+// RV64ZBB-LABEL: @ctz_64_generic(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT:store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 false)
+// RV64ZBB-NEXT:[[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZBB-NEXT:[[CONV:%.*]] = sext i32 [[CAST]] to i64
+// RV64ZBB-NEXT:ret i64 [[CONV]]
+//
+long ctz_64_generic(long a) {
+  return __builtin_ctzl(a);
+}
+
 // RV64ZBB-LABEL: @ctz_32(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -14,6 +14,18 @@
   return __builtin_riscv_orc_b_32(a);
 }
 
+// RV32ZBB-LABEL: @clz_32_generic(
+// RV32ZBB-NEXT:  entry:
+// RV32ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBB-NEXT:store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV32ZBB-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
+// RV32ZBB-NEXT:ret i32 [[TMP1]]
+//
+int clz_32_generic(int a) {
+  return __builtin_clz(a);
+}
+
 // RV32ZBB-LABEL: @clz_32(
 // RV32ZBB-NEXT:  entry:
 // RV32ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
@@ -26,6 +38,18 @@
   return __builtin_riscv_clz_32(a);
 }
 
+// RV32ZBB-LABEL: @ctz_32_generic(
+// RV32ZBB-NEXT:  entry:
+// RV32ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBB-NEXT:store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV32ZBB-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
+// RV32ZBB-NEXT:ret i32 [[TMP

[PATCH] D149401: [Clang][RISCV] Set native half type to legal when has zfh extension

2023-04-27 Thread Yunze Zhu(Thead) via Phabricator via cfe-commits 
Yunzezhu created this revision.
Yunzezhu added reviewers: asb, kito-cheng, craig.topper.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, 
arichardson.
Herald added a project: All.
Yunzezhu requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

Issue: When processing a f16 type value, a f16 value is extended to f32 after 
load and processed in f32 form, and truncated back to f16 before store, even 
when the target has zfh extension, which indicates the target has native half 
type float support, and such kind of extend/truncate actions are not necessary.

Some changes:
1.Set native half type to legal when has zfh extension, which prevent 
unnecessary promotion from f16 to f32, and unpromotion back to f16.
2.Add related test case to test generation of half type float.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D149401

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/CodeGen/RISCV/_Float16-add.c


Index: clang/test/CodeGen/RISCV/_Float16-add.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/_Float16-add.c
@@ -0,0 +1,19 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zfh -emit-llvm %s -o - \
+// RUN:   | FileCheck %s
+
+_Float16 x;
+_Float16 y;
+_Float16 z;
+// CHECK-LABEL: @func(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load half, ptr @y, align 2
+// CHECK-NEXT:[[TMP1:%.*]] = load half, ptr @z, align 2
+// CHECK-NEXT:[[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]]
+// CHECK-NEXT:store half [[ADD]], ptr @x, align 2
+// CHECK-NEXT:ret void
+//
+void func()
+{
+  x = y + z;
+}
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -349,6 +349,11 @@
 ISAInfo = std::move(*ParseResult);
   }
 
+  // Turn on native half type support by set half type to legal.
+  if (ISAInfo->hasExtension("zfh")){
+HasLegalHalfType = true;
+  }
+
   if (ABI.empty())
 ABI = ISAInfo->computeDefaultABI().str();
 


Index: clang/test/CodeGen/RISCV/_Float16-add.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/_Float16-add.c
@@ -0,0 +1,19 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zfh -emit-llvm %s -o - \
+// RUN:   | FileCheck %s
+
+_Float16 x;
+_Float16 y;
+_Float16 z;
+// CHECK-LABEL: @func(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load half, ptr @y, align 2
+// CHECK-NEXT:[[TMP1:%.*]] = load half, ptr @z, align 2
+// CHECK-NEXT:[[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]]
+// CHECK-NEXT:store half [[ADD]], ptr @x, align 2
+// CHECK-NEXT:ret void
+//
+void func()
+{
+  x = y + z;
+}
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -349,6 +349,11 @@
 ISAInfo = std::move(*ParseResult);
   }
 
+  // Turn on native half type support by set half type to legal.
+  if (ISAInfo->hasExtension("zfh")){
+HasLegalHalfType = true;
+  }
+
   if (ABI.empty())
 ABI = ISAInfo->computeDefaultABI().str();
 
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[PATCH] D149401: [Clang][RISCV] Set native half type to legal when has zfh extension

2023-04-27 Thread Yunze Zhu(Thead) via Phabricator via cfe-commits 
Yunzezhu abandoned this revision.
Yunzezhu added a comment.

In D149401#4304053 , @craig.topper 
wrote:

> Is this the same as https://reviews.llvm.org/D145071

Yes and I will abandon this one.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149401/new/

https://reviews.llvm.org/D149401

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[PATCH] D151867: [Clang][RISCV] Make generic clz/ctz builtins defined for zero on RISCV targets.

2023-06-06 Thread Yunze Zhu(Thead) via Phabricator via cfe-commits 
Yunzezhu updated this revision to Diff 528698.
Yunzezhu added a comment.

I made the flag isCLZForZeroUndef set to false only when target support 
extension zbb or xtheadbb, and this will prevent making codegen worse when 
target does not support abb or xtheadbb.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151867/new/

https://reviews.llvm.org/D151867

Files:
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c

Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -26,6 +26,32 @@
   return __builtin_riscv_orc_b_64(a);
 }
 
+// RV64ZBB-LABEL: @clz_32_generic(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int clz_32_generic(int a) {
+  return __builtin_clz(a);
+}
+
+// RV64ZBB-LABEL: @clz_64_generic(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT:store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 false)
+// RV64ZBB-NEXT:[[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZBB-NEXT:[[CONV:%.*]] = sext i32 [[CAST]] to i64
+// RV64ZBB-NEXT:ret i64 [[CONV]]
+//
+long clz_64_generic(long a) {
+  return __builtin_clzl(a);
+}
+
 // RV64ZBB-LABEL: @clz_32(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
@@ -50,6 +76,32 @@
   return __builtin_riscv_clz_64(a);
 }
 
+// RV64ZBB-LABEL: @ctz_32_generic(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int ctz_32_generic(int a) {
+  return __builtin_ctz(a);
+}
+
+// RV64ZBB-LABEL: @ctz_64_generic(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT:store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 false)
+// RV64ZBB-NEXT:[[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZBB-NEXT:[[CONV:%.*]] = sext i32 [[CAST]] to i64
+// RV64ZBB-NEXT:ret i64 [[CONV]]
+//
+long ctz_64_generic(long a) {
+  return __builtin_ctzl(a);
+}
+
 // RV64ZBB-LABEL: @ctz_32(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
@@ -2,6 +2,18 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadbb -emit-llvm %s -o - \
 // RUN: | FileCheck %s  -check-prefix=RV64XTHEADBB
 
+// RV64XTHEADBB-LABEL: @clz_32_generic(
+// RV64XTHEADBB-NEXT:  entry:
+// RV64XTHEADBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64XTHEADBB-NEXT:store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64XTHEADBB-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64XTHEADBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
+// RV64XTHEADBB-NEXT:ret i32 [[TMP1]]
+//
+int clz_32_generic(int a) {
+  return __builtin_clz(a);
+}
+
 // RV64XTHEADBB-LABEL: @clz_32(
 // RV64XTHEADBB-NEXT:  entry:
 // RV64XTHEADBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
@@ -27,6 +39,20 @@
   return __builtin_riscv_clz_32(~a);
 }
 
+// RV64XTHEADBB-LABEL: @clz_64_generic(
+// RV64XTHEADBB-NEXT:  entry:
+// RV64XTHEADBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64XTHEADBB-NEXT:store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
+// RV64XTHEADBB-NEXT:[[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
+// RV64XTHEADBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 false)
+// RV64XTHEADBB-NEXT:[[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64XTHEADBB-NEXT:[[CONV:%.*]] = sext i32 [[CAST]] to i64
+// RV64XTHEADBB-NEXT:ret i64 [[CONV]]
+//
+long clz_64_generic(long a) {
+  return __builtin_clzl(a);

[PATCH] D152250: [Clang][RISCV] Add test cases for intrinsics clz/ctz codegen when has extension zbb/xtheadbb

2023-06-06 Thread Yunze Zhu(Thead) via Phabricator via cfe-commits 
Yunzezhu created this revision.
Yunzezhu added reviewers: asb, craig.topper, kito-cheng.
Yunzezhu added a project: clang.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, arichardson.
Herald added a project: All.
Yunzezhu requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.

Add test cases for intrinsics clz/ctz when has extension zbb/xtheadbb to 
demonstrate future changes in codegen.

This patch helps demonstrate codegen changes made in 
https://reviews.llvm.org/D151867 .


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152250

Files:
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c

Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -26,6 +26,32 @@
   return __builtin_riscv_orc_b_64(a);
 }
 
+// RV64ZBB-LABEL: @clz_32_generic(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 true)
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int clz_32_generic(int a) {
+  return __builtin_clz(a);
+}
+
+// RV64ZBB-LABEL: @clz_64_generic(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT:store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 true)
+// RV64ZBB-NEXT:[[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZBB-NEXT:[[CONV:%.*]] = sext i32 [[CAST]] to i64
+// RV64ZBB-NEXT:ret i64 [[CONV]]
+//
+long clz_64_generic(long a) {
+  return __builtin_clzl(a);
+}
+
 // RV64ZBB-LABEL: @clz_32(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
@@ -50,6 +76,32 @@
   return __builtin_riscv_clz_64(a);
 }
 
+// RV64ZBB-LABEL: @ctz_32_generic(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 true)
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int ctz_32_generic(int a) {
+  return __builtin_ctz(a);
+}
+
+// RV64ZBB-LABEL: @ctz_64_generic(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT:store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 true)
+// RV64ZBB-NEXT:[[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZBB-NEXT:[[CONV:%.*]] = sext i32 [[CAST]] to i64
+// RV64ZBB-NEXT:ret i64 [[CONV]]
+//
+long ctz_64_generic(long a) {
+  return __builtin_ctzl(a);
+}
+
 // RV64ZBB-LABEL: @ctz_32(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
@@ -2,6 +2,18 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadbb -emit-llvm %s -o - \
 // RUN: | FileCheck %s  -check-prefix=RV64XTHEADBB
 
+// RV64XTHEADBB-LABEL: @clz_32_generic(
+// RV64XTHEADBB-NEXT:  entry:
+// RV64XTHEADBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64XTHEADBB-NEXT:store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64XTHEADBB-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64XTHEADBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 true)
+// RV64XTHEADBB-NEXT:ret i32 [[TMP1]]
+//
+int clz_32_generic(int a) {
+  return __builtin_clz(a);
+}
+
 // RV64XTHEADBB-LABEL: @clz_32(
 // RV64XTHEADBB-NEXT:  entry:
 // RV64XTHEADBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
@@ -27,6 +39,20 @@
   return __builtin_riscv_clz_32(~a);
 }
 
+// RV64XTHEADBB-LABEL: @clz_64_generic(
+// RV64XTHEADBB-NEXT:  entry:
+// RV64XTHEADBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64XTHEADBB-NEXT:store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
+/

[PATCH] D151867: [Clang][RISCV] Make generic clz/ctz builtins defined for zero on RISCV targets.

2023-06-06 Thread Yunze Zhu(Thead) via Phabricator via cfe-commits 
Yunzezhu added a comment.

In D151867#4398483 , @asb wrote:

> Could you please post a separate patch that has a test that will show the 
> codegen change (and demonstrate how it is unchanged when zbb or xtheadbb)?

Sure. I post a patch to demonstrate current codegen behavior for clz/ctz 
intrinsics when has ebb or xtheadbb: https://reviews.llvm.org/D152250.


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[PATCH] D151867: [Clang][RISCV] Make generic clz/ctz builtins defined for zero on RISCV targets.

2023-06-06 Thread Yunze Zhu(Thead) via Phabricator via cfe-commits 
Yunzezhu added a comment.

In D151867#4400255 , @craig.topper 
wrote:

> From the C language perspective with this change, __builtin_clz/ctz is still 
> considered undefined for 0 and code that uses it is ill-formed. 
> `isCLZForZeroUndef` is only intended to prevent the middle end from 
> optimizing based on the undefinedness and creating surprises. See also 
> https://discourse.llvm.org/t/should-ubsan-detect-0-input-to-builtin-clz-ctz-regardless-of-target/71060

I see __builtin_clz/ctz returning an undefined value for 0 input matches gcc's 
document, but when I test __builtin_clz/ctz with 0 input on gcc, it returns a 
valid value rather than an undefined value. It looks gcc does not follow gcc's 
document. I'm not sure which one is better that match document to return 
undefined for 0, or match gcc's behavior to return defined value?


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[PATCH] D151867: [Clang][RISCV] Make generic clz/ctz builtins defined for zero on RISCV targets.

2023-06-07 Thread Yunze Zhu(Thead) via Phabricator via cfe-commits 
Yunzezhu abandoned this revision.
Yunzezhu added a comment.

In D151867#4401987 , @craig.topper 
wrote:

> In D151867#4401952 , @Yunzezhu 
> wrote:
>
>> In D151867#4400255 , @craig.topper 
>> wrote:
>>
>>> From the C language perspective with this change, __builtin_clz/ctz is 
>>> still considered undefined for 0 and code that uses it is ill-formed. 
>>> `isCLZForZeroUndef` is only intended to prevent the middle end from 
>>> optimizing based on the undefinedness and creating surprises. See also 
>>> https://discourse.llvm.org/t/should-ubsan-detect-0-input-to-builtin-clz-ctz-regardless-of-target/71060
>>
>> I see __builtin_clz/ctz returning an undefined value for 0 input matches 
>> gcc's document, but when I test __builtin_clz/ctz with 0 input on gcc, it 
>> returns a valid value rather than an undefined value. It looks gcc does not 
>> follow gcc's document. I'm not sure which one is better that match document 
>> to return undefined for 0, or match gcc's behavior to return defined value?
>
> From what I can see in the assembly here https://godbolt.org/z/s4qqz83EK, 
> gcc's undefined behavior sanitizer does consider an input of 0 to be 
> undefined.

Got it.


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[PATCH] D152250: [Clang][RISCV] Add test cases for intrinsics clz/ctz codegen when has extension zbb/xtheadbb

2023-06-07 Thread Yunze Zhu(Thead) via Phabricator via cfe-commits 
Yunzezhu abandoned this revision.
Yunzezhu added a comment.

Abandon this revision because https://reviews.llvm.org/D151867 is abandoned.


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