[PATCH] D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD added inline comments.



Comment at: clang/lib/Driver/Driver.cpp:660
+
+if (RVArch == llvm::Triple::riscv64 &&
+ArchName.startswith_insensitive("rv32"))

Do we need to throw error (or warning) when these two (`RVArch` and `ArchName`) 
don't match?


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[PATCH] D126042: [RISCV][NFC] Remove `*=` operator for LMULType

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
eopXD added reviewers: khchen, kito.cheng.
Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb, arichardson.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

LMULType always manipulate on Log2LMUL, let all manipulations go
through LMULType::MulLog2LMUL.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126042

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -77,12 +77,6 @@
 
 void LMULType::MulLog2LMUL(int log2LMUL) { Log2LMUL += log2LMUL; }
 
-LMULType &LMULType::operator*=(uint32_t RHS) {
-  assert(isPowerOf2_32(RHS));
-  this->Log2LMUL = this->Log2LMUL + Log2_32(RHS);
-  return *this;
-}
-
 RVVType::RVVType(BasicType BT, int Log2LMUL,
  const PrototypeDescriptor &prototype)
 : BT(BT), LMUL(LMULType(Log2LMUL)) {
@@ -628,17 +622,17 @@
   switch (static_cast(Transformer.VTM)) {
   case VectorTypeModifier::Widening2XVector:
 ElementBitwidth *= 2;
-LMUL *= 2;
+LMUL.MulLog2LMUL(1);
 Scale = LMUL.getScale(ElementBitwidth);
 break;
   case VectorTypeModifier::Widening4XVector:
 ElementBitwidth *= 4;
-LMUL *= 4;
+LMUL.MulLog2LMUL(2);
 Scale = LMUL.getScale(ElementBitwidth);
 break;
   case VectorTypeModifier::Widening8XVector:
 ElementBitwidth *= 8;
-LMUL *= 8;
+LMUL.MulLog2LMUL(3);
 Scale = LMUL.getScale(ElementBitwidth);
 break;
   case VectorTypeModifier::MaskVector:
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -156,7 +156,6 @@
   std::string str() const;
   llvm::Optional getScale(unsigned ElementBitwidth) const;
   void MulLog2LMUL(int Log2LMUL);
-  LMULType &operator*=(uint32_t RHS);
 };
 
 class RVVType;


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -77,12 +77,6 @@
 
 void LMULType::MulLog2LMUL(int log2LMUL) { Log2LMUL += log2LMUL; }
 
-LMULType &LMULType::operator*=(uint32_t RHS) {
-  assert(isPowerOf2_32(RHS));
-  this->Log2LMUL = this->Log2LMUL + Log2_32(RHS);
-  return *this;
-}
-
 RVVType::RVVType(BasicType BT, int Log2LMUL,
  const PrototypeDescriptor &prototype)
 : BT(BT), LMUL(LMULType(Log2LMUL)) {
@@ -628,17 +622,17 @@
   switch (static_cast(Transformer.VTM)) {
   case VectorTypeModifier::Widening2XVector:
 ElementBitwidth *= 2;
-LMUL *= 2;
+LMUL.MulLog2LMUL(1);
 Scale = LMUL.getScale(ElementBitwidth);
 break;
   case VectorTypeModifier::Widening4XVector:
 ElementBitwidth *= 4;
-LMUL *= 4;
+LMUL.MulLog2LMUL(2);
 Scale = LMUL.getScale(ElementBitwidth);
 break;
   case VectorTypeModifier::Widening8XVector:
 ElementBitwidth *= 8;
-LMUL *= 8;
+LMUL.MulLog2LMUL(3);
 Scale = LMUL.getScale(ElementBitwidth);
 break;
   case VectorTypeModifier::MaskVector:
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -156,7 +156,6 @@
   std::string str() const;
   llvm::Optional getScale(unsigned ElementBitwidth) const;
   void MulLog2LMUL(int Log2LMUL);
-  LMULType &operator*=(uint32_t RHS);
 };
 
 class RVVType;
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[PATCH] D126042: [RISCV][NFC] Remove `*=` operator for LMULType

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGda201aa4242e: [RISCV][NFC] Remove `*=` operator for LMULType 
(authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126042/new/

https://reviews.llvm.org/D126042

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -77,12 +77,6 @@
 
 void LMULType::MulLog2LMUL(int log2LMUL) { Log2LMUL += log2LMUL; }
 
-LMULType &LMULType::operator*=(uint32_t RHS) {
-  assert(isPowerOf2_32(RHS));
-  this->Log2LMUL = this->Log2LMUL + Log2_32(RHS);
-  return *this;
-}
-
 RVVType::RVVType(BasicType BT, int Log2LMUL,
  const PrototypeDescriptor &prototype)
 : BT(BT), LMUL(LMULType(Log2LMUL)) {
@@ -628,17 +622,17 @@
   switch (static_cast(Transformer.VTM)) {
   case VectorTypeModifier::Widening2XVector:
 ElementBitwidth *= 2;
-LMUL *= 2;
+LMUL.MulLog2LMUL(1);
 Scale = LMUL.getScale(ElementBitwidth);
 break;
   case VectorTypeModifier::Widening4XVector:
 ElementBitwidth *= 4;
-LMUL *= 4;
+LMUL.MulLog2LMUL(2);
 Scale = LMUL.getScale(ElementBitwidth);
 break;
   case VectorTypeModifier::Widening8XVector:
 ElementBitwidth *= 8;
-LMUL *= 8;
+LMUL.MulLog2LMUL(3);
 Scale = LMUL.getScale(ElementBitwidth);
 break;
   case VectorTypeModifier::MaskVector:
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -156,7 +156,6 @@
   std::string str() const;
   llvm::Optional getScale(unsigned ElementBitwidth) const;
   void MulLog2LMUL(int Log2LMUL);
-  LMULType &operator*=(uint32_t RHS);
 };
 
 class RVVType;


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -77,12 +77,6 @@
 
 void LMULType::MulLog2LMUL(int log2LMUL) { Log2LMUL += log2LMUL; }
 
-LMULType &LMULType::operator*=(uint32_t RHS) {
-  assert(isPowerOf2_32(RHS));
-  this->Log2LMUL = this->Log2LMUL + Log2_32(RHS);
-  return *this;
-}
-
 RVVType::RVVType(BasicType BT, int Log2LMUL,
  const PrototypeDescriptor &prototype)
 : BT(BT), LMUL(LMULType(Log2LMUL)) {
@@ -628,17 +622,17 @@
   switch (static_cast(Transformer.VTM)) {
   case VectorTypeModifier::Widening2XVector:
 ElementBitwidth *= 2;
-LMUL *= 2;
+LMUL.MulLog2LMUL(1);
 Scale = LMUL.getScale(ElementBitwidth);
 break;
   case VectorTypeModifier::Widening4XVector:
 ElementBitwidth *= 4;
-LMUL *= 4;
+LMUL.MulLog2LMUL(2);
 Scale = LMUL.getScale(ElementBitwidth);
 break;
   case VectorTypeModifier::Widening8XVector:
 ElementBitwidth *= 8;
-LMUL *= 8;
+LMUL.MulLog2LMUL(3);
 Scale = LMUL.getScale(ElementBitwidth);
 break;
   case VectorTypeModifier::MaskVector:
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -156,7 +156,6 @@
   std::string str() const;
   llvm::Optional getScale(unsigned ElementBitwidth) const;
   void MulLog2LMUL(int Log2LMUL);
-  LMULType &operator*=(uint32_t RHS);
 };
 
 class RVVType;
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[PATCH] D136783: Pre-commit test case

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136783

Files:
  clang/test/Parser/pragma-loop.cpp


Index: clang/test/Parser/pragma-loop.cpp
===
--- clang/test/Parser/pragma-loop.cpp
+++ clang/test/Parser/pragma-loop.cpp
@@ -301,3 +301,39 @@
 void foo(void) {
 #pragma clang loop vectorize_predicate(enable)
 /* expected-error {{expected statement}} */ }
+
+void foo(int *List, int Length) {
+  int i;
+#pragma clang loop vectorize(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop interleave(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop unroll(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop vectorize_predicate(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop pipeline(disable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop vectorize_width(2, scalable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop interleave_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop unroll_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop pipeline_initiation_interval(2, extra)
+  while (i-6 < Length) {
+List[i] = i;
+  }
+}


Index: clang/test/Parser/pragma-loop.cpp
===
--- clang/test/Parser/pragma-loop.cpp
+++ clang/test/Parser/pragma-loop.cpp
@@ -301,3 +301,39 @@
 void foo(void) {
 #pragma clang loop vectorize_predicate(enable)
 /* expected-error {{expected statement}} */ }
+
+void foo(int *List, int Length) {
+  int i;
+#pragma clang loop vectorize(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop interleave(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop unroll(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop vectorize_predicate(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop pipeline(disable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ #pragma clang loop vectorize_width(2, scalable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ #pragma clang loop interleave_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ #pragma clang loop unroll_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ #pragma clang loop pipeline_initiation_interval(2, extra)
+  while (i-6 < Length) {
+List[i] = i;
+  }
+}
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[PATCH] D136784: [Clang] Improve diagnotisc message for loop hint pragma

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead.
Herald added a project: clang.

Originally the loop hint is not displayed correctly in the diagnostic.
This patch fixes it.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136784

Files:
  clang/lib/Parse/ParsePragma.cpp
  clang/test/Parser/pragma-loop.cpp


Index: clang/test/Parser/pragma-loop.cpp
===
--- clang/test/Parser/pragma-loop.cpp
+++ clang/test/Parser/pragma-loop.cpp
@@ -305,34 +305,34 @@
 void foo(int *List, int Length) {
   int i;
 #pragma clang loop vectorize(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop vectorize' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop interleave(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop interleave' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop unroll(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop unroll' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop vectorize_predicate(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
vectorize_predicate' - ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop pipeline(disable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop pipeline' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop vectorize_width(2, scalable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop interleave_count(2, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop unroll_count(2, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop pipeline_initiation_interval(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
vectorize_width' - ignored}}*/ #pragma clang loop vectorize_width(2, scalable, 
extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
interleave_count' - ignored}}*/ #pragma clang loop interleave_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop unroll_count' 
- ignored}}*/ #pragma clang loop unroll_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
pipeline_initiation_interval' - ignored}}*/ #pragma clang loop 
pipeline_initiation_interval(2, extra)
   while (i-6 < Length) {
 List[i] = i;
   }
Index: clang/lib/Parse/ParsePragma.cpp
===
--- clang/lib/Parse/ParsePragma.cpp
+++ clang/lib/Parse/ParsePragma.cpp
@@ -1303,6 +1303,8 @@
 
 static std::string PragmaLoopHintString(Token PragmaName, Token Option) {
   StringRef Str = PragmaName.getIdentifierInfo()->getName();
+  if (Str == "loop")
+return (llvm::Twine("clang loop ") + 
Option.getIdentifierInfo()->getName()).str();
   std::string ClangLoopStr = (llvm::Twine("clang loop ") + Str).str();
   return std::string(llvm::StringSwitch(Str)
  .Case("loop", ClangLoopStr)


Index: clang/test/Parser/pragma-loop.cpp
===
--- clang/test/Parser/pragma-loop.cpp
+++ clang/test/Parser/pragma-loop.cpp
@@ -305,34 +305,34 @@
 void foo(int *List, int Length) {
   int i;
 #pragma clang loop vectorize(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop vectorize' - ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop interleave(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop interleave' - ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop unroll(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+/* exp

[PATCH] D136784: [Clang] Improve diagnotisc message for loop hint pragma

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 470913.
eopXD added a comment.

Trigger upon parent revision.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136784/new/

https://reviews.llvm.org/D136784

Files:
  clang/lib/Parse/ParsePragma.cpp
  clang/test/Parser/pragma-loop.cpp


Index: clang/test/Parser/pragma-loop.cpp
===
--- clang/test/Parser/pragma-loop.cpp
+++ clang/test/Parser/pragma-loop.cpp
@@ -305,34 +305,34 @@
 void foo(int *List, int Length) {
   int i;
 #pragma clang loop vectorize(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop vectorize' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop interleave(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop interleave' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop unroll(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop unroll' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop vectorize_predicate(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
vectorize_predicate' - ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop pipeline(disable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop pipeline' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop vectorize_width(2, scalable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop interleave_count(2, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop unroll_count(2, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop pipeline_initiation_interval(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
vectorize_width' - ignored}}*/ #pragma clang loop vectorize_width(2, scalable, 
extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
interleave_count' - ignored}}*/ #pragma clang loop interleave_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop unroll_count' 
- ignored}}*/ #pragma clang loop unroll_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
pipeline_initiation_interval' - ignored}}*/ #pragma clang loop 
pipeline_initiation_interval(2, extra)
   while (i-6 < Length) {
 List[i] = i;
   }
Index: clang/lib/Parse/ParsePragma.cpp
===
--- clang/lib/Parse/ParsePragma.cpp
+++ clang/lib/Parse/ParsePragma.cpp
@@ -1303,6 +1303,8 @@
 
 static std::string PragmaLoopHintString(Token PragmaName, Token Option) {
   StringRef Str = PragmaName.getIdentifierInfo()->getName();
+  if (Str == "loop")
+return (llvm::Twine("clang loop ") + 
Option.getIdentifierInfo()->getName()).str();
   std::string ClangLoopStr = (llvm::Twine("clang loop ") + Str).str();
   return std::string(llvm::StringSwitch(Str)
  .Case("loop", ClangLoopStr)


Index: clang/test/Parser/pragma-loop.cpp
===
--- clang/test/Parser/pragma-loop.cpp
+++ clang/test/Parser/pragma-loop.cpp
@@ -305,34 +305,34 @@
 void foo(int *List, int Length) {
   int i;
 #pragma clang loop vectorize(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop vectorize' - ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop interleave(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop interleave' - ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop unroll(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop unroll' - ignored}}*/ while (i-6 < Length) {
 Li

[PATCH] D136783: Pre-commit test case for D136784

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 471047.
eopXD added a comment.

Update to latest main. (Triggering CI again)


Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/test/Parser/pragma-loop.cpp


Index: clang/test/Parser/pragma-loop.cpp
===
--- clang/test/Parser/pragma-loop.cpp
+++ clang/test/Parser/pragma-loop.cpp
@@ -301,3 +301,39 @@
 void foo(void) {
 #pragma clang loop vectorize_predicate(enable)
 /* expected-error {{expected statement}} */ }
+
+void foo(int *List, int Length) {
+  int i;
+#pragma clang loop vectorize(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop interleave(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop unroll(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop vectorize_predicate(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop pipeline(disable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop vectorize_width(2, scalable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop interleave_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop unroll_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop pipeline_initiation_interval(2, extra)
+  while (i-6 < Length) {
+List[i] = i;
+  }
+}


Index: clang/test/Parser/pragma-loop.cpp
===
--- clang/test/Parser/pragma-loop.cpp
+++ clang/test/Parser/pragma-loop.cpp
@@ -301,3 +301,39 @@
 void foo(void) {
 #pragma clang loop vectorize_predicate(enable)
 /* expected-error {{expected statement}} */ }
+
+void foo(int *List, int Length) {
+  int i;
+#pragma clang loop vectorize(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop interleave(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop unroll(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop vectorize_predicate(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop pipeline(disable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ #pragma clang loop vectorize_width(2, scalable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ #pragma clang loop interleave_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ #pragma clang loop unroll_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ #pragma clang loop pipeline_initiation_interval(2, extra)
+  while (i-6 < Length) {
+List[i] = i;
+  }
+}
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[PATCH] D136784: [Clang] Improve diagnostic message for loop hint pragma

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 471048.
eopXD added a comment.

Rebase upon latest main and simplify existing checks.


Repository:
  rG LLVM Github Monorepo

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Files:
  clang/lib/Parse/ParsePragma.cpp
  clang/test/Parser/pragma-loop.cpp


Index: clang/test/Parser/pragma-loop.cpp
===
--- clang/test/Parser/pragma-loop.cpp
+++ clang/test/Parser/pragma-loop.cpp
@@ -305,34 +305,34 @@
 void foo(int *List, int Length) {
   int i;
 #pragma clang loop vectorize(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop vectorize' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop interleave(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop interleave' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop unroll(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop unroll' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop vectorize_predicate(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
vectorize_predicate' - ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop pipeline(disable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop pipeline' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop vectorize_width(2, scalable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop interleave_count(2, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop unroll_count(2, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop pipeline_initiation_interval(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
vectorize_width' - ignored}}*/ #pragma clang loop vectorize_width(2, scalable, 
extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
interleave_count' - ignored}}*/ #pragma clang loop interleave_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop unroll_count' 
- ignored}}*/ #pragma clang loop unroll_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
pipeline_initiation_interval' - ignored}}*/ #pragma clang loop 
pipeline_initiation_interval(2, extra)
   while (i-6 < Length) {
 List[i] = i;
   }
Index: clang/lib/Parse/ParsePragma.cpp
===
--- clang/lib/Parse/ParsePragma.cpp
+++ clang/lib/Parse/ParsePragma.cpp
@@ -1303,9 +1303,10 @@
 
 static std::string PragmaLoopHintString(Token PragmaName, Token Option) {
   StringRef Str = PragmaName.getIdentifierInfo()->getName();
+  if (Str == "loop")
+return (llvm::Twine("clang loop ") + 
Option.getIdentifierInfo()->getName()).str();
   std::string ClangLoopStr = (llvm::Twine("clang loop ") + Str).str();
   return std::string(llvm::StringSwitch(Str)
- .Case("loop", ClangLoopStr)
  .Case("unroll_and_jam", Str)
  .Case("unroll", Str)
  .Default(""));


Index: clang/test/Parser/pragma-loop.cpp
===
--- clang/test/Parser/pragma-loop.cpp
+++ clang/test/Parser/pragma-loop.cpp
@@ -305,34 +305,34 @@
 void foo(int *List, int Length) {
   int i;
 #pragma clang loop vectorize(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop vectorize' - ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop interleave(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop interleave' - ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop unroll(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clan

[PATCH] D136784: [Clang] Improve diagnostic message for loop hint pragma

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD marked an inline comment as done.
eopXD added inline comments.



Comment at: clang/lib/Parse/ParsePragma.cpp:1306
   StringRef Str = PragmaName.getIdentifierInfo()->getName();
+  if (Str == "loop")
+return (llvm::Twine("clang loop ") + 
Option.getIdentifierInfo()->getName()).str();

SjoerdMeijer wrote:
> We've got some duplication now, as "loop" is also checked in line 1310. Can 
> you see if you can merge these checks, simplify things here a bit?
Yes, the case for `loop` in below can now be removed. Thank you.


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[PATCH] D136784: [Clang] Improve diagnostic message for loop hint pragma

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 471057.
eopXD marked an inline comment as done.
eopXD added a comment.

Update code based on suggestion.


Repository:
  rG LLVM Github Monorepo

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Files:
  clang/lib/Parse/ParsePragma.cpp
  clang/test/Parser/pragma-loop.cpp


Index: clang/test/Parser/pragma-loop.cpp
===
--- clang/test/Parser/pragma-loop.cpp
+++ clang/test/Parser/pragma-loop.cpp
@@ -305,34 +305,34 @@
 void foo(int *List, int Length) {
   int i;
 #pragma clang loop vectorize(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop vectorize' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop interleave(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop interleave' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop unroll(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop unroll' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop vectorize_predicate(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
vectorize_predicate' - ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop pipeline(disable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop pipeline' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop vectorize_width(2, scalable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop interleave_count(2, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop unroll_count(2, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop pipeline_initiation_interval(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
vectorize_width' - ignored}}*/ #pragma clang loop vectorize_width(2, scalable, 
extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
interleave_count' - ignored}}*/ #pragma clang loop interleave_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop unroll_count' 
- ignored}}*/ #pragma clang loop unroll_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
pipeline_initiation_interval' - ignored}}*/ #pragma clang loop 
pipeline_initiation_interval(2, extra)
   while (i-6 < Length) {
 List[i] = i;
   }
Index: clang/lib/Parse/ParsePragma.cpp
===
--- clang/lib/Parse/ParsePragma.cpp
+++ clang/lib/Parse/ParsePragma.cpp
@@ -1305,7 +1305,9 @@
   StringRef Str = PragmaName.getIdentifierInfo()->getName();
   std::string ClangLoopStr = (llvm::Twine("clang loop ") + Str).str();
   return std::string(llvm::StringSwitch(Str)
- .Case("loop", ClangLoopStr)
+ .Case("loop", (llvm::Twine("clang loop ") +
+Option.getIdentifierInfo()->getName())
+   .str())
  .Case("unroll_and_jam", Str)
  .Case("unroll", Str)
  .Default(""));


Index: clang/test/Parser/pragma-loop.cpp
===
--- clang/test/Parser/pragma-loop.cpp
+++ clang/test/Parser/pragma-loop.cpp
@@ -305,34 +305,34 @@
 void foo(int *List, int Length) {
   int i;
 #pragma clang loop vectorize(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop vectorize' - ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop interleave(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop interleave' - ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop unroll(enable, extra)
-/* expected-warning {{extr

[PATCH] D136784: [Clang] Improve diagnostic message for loop hint pragma

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD marked an inline comment as done.
eopXD added inline comments.



Comment at: clang/lib/Parse/ParsePragma.cpp:1306
   StringRef Str = PragmaName.getIdentifierInfo()->getName();
+  if (Str == "loop")
+return (llvm::Twine("clang loop ") + 
Option.getIdentifierInfo()->getName()).str();

SjoerdMeijer wrote:
> eopXD wrote:
> > SjoerdMeijer wrote:
> > > We've got some duplication now, as "loop" is also checked in line 1310. 
> > > Can you see if you can merge these checks, simplify things here a bit?
> > Yes, the case for `loop` in below can now be removed. Thank you.
> I was hoping that modifying the "loop" case would work:
> 
>   .Case("loop", (llvm::Twine("clang loop ") + 
> Option.getIdentifierInfo()->getName()).str());
> 
> 
Your suggestion is better than mine, thank you :)


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[PATCH] D136783: Pre-commit test case for D136784

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG97dcbd124d54: Pre-commit test case for D136784 (authored by 
eopXD).

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Files:
  clang/test/Parser/pragma-loop.cpp


Index: clang/test/Parser/pragma-loop.cpp
===
--- clang/test/Parser/pragma-loop.cpp
+++ clang/test/Parser/pragma-loop.cpp
@@ -301,3 +301,39 @@
 void foo(void) {
 #pragma clang loop vectorize_predicate(enable)
 /* expected-error {{expected statement}} */ }
+
+void foo(int *List, int Length) {
+  int i;
+#pragma clang loop vectorize(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop interleave(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop unroll(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop vectorize_predicate(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop pipeline(disable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop vectorize_width(2, scalable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop interleave_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop unroll_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop pipeline_initiation_interval(2, extra)
+  while (i-6 < Length) {
+List[i] = i;
+  }
+}


Index: clang/test/Parser/pragma-loop.cpp
===
--- clang/test/Parser/pragma-loop.cpp
+++ clang/test/Parser/pragma-loop.cpp
@@ -301,3 +301,39 @@
 void foo(void) {
 #pragma clang loop vectorize_predicate(enable)
 /* expected-error {{expected statement}} */ }
+
+void foo(int *List, int Length) {
+  int i;
+#pragma clang loop vectorize(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop interleave(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop unroll(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop vectorize_predicate(enable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+#pragma clang loop pipeline(disable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+List[i] = i;
+  }
+
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ #pragma clang loop vectorize_width(2, scalable, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ #pragma clang loop interleave_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ #pragma clang loop unroll_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ #pragma clang loop pipeline_initiation_interval(2, extra)
+  while (i-6 < Length) {
+List[i] = i;
+  }
+}
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[PATCH] D136784: [Clang] Improve diagnostic message for loop hint pragma

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 471344.
eopXD added a comment.

Update code to handle when IdentifierInfo is null.
The .Case syntax seems to evaulate expression in other non-trigger cases.
The "loop" case was triggered for test case in loop unroll and jam, resulting
in segmentation fault. Anyway the updated code shall be safe now.


Repository:
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Files:
  clang/lib/Parse/ParsePragma.cpp
  clang/test/Parser/pragma-loop.cpp


Index: clang/test/Parser/pragma-loop.cpp
===
--- clang/test/Parser/pragma-loop.cpp
+++ clang/test/Parser/pragma-loop.cpp
@@ -305,34 +305,34 @@
 void foo(int *List, int Length) {
   int i;
 #pragma clang loop vectorize(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop vectorize' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop interleave(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop interleave' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop unroll(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop unroll' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop vectorize_predicate(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
vectorize_predicate' - ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop pipeline(disable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop pipeline' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop vectorize_width(2, scalable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop interleave_count(2, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop unroll_count(2, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop pipeline_initiation_interval(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
vectorize_width' - ignored}}*/ #pragma clang loop vectorize_width(2, scalable, 
extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
interleave_count' - ignored}}*/ #pragma clang loop interleave_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop unroll_count' 
- ignored}}*/ #pragma clang loop unroll_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
pipeline_initiation_interval' - ignored}}*/ #pragma clang loop 
pipeline_initiation_interval(2, extra)
   while (i-6 < Length) {
 List[i] = i;
   }
Index: clang/lib/Parse/ParsePragma.cpp
===
--- clang/lib/Parse/ParsePragma.cpp
+++ clang/lib/Parse/ParsePragma.cpp
@@ -1303,7 +1303,9 @@
 
 static std::string PragmaLoopHintString(Token PragmaName, Token Option) {
   StringRef Str = PragmaName.getIdentifierInfo()->getName();
-  std::string ClangLoopStr = (llvm::Twine("clang loop ") + Str).str();
+  std::string ClangLoopStr("clang loop ");
+  if (Str == "loop" && Option.getIdentifierInfo())
+ClangLoopStr += Option.getIdentifierInfo()->getName();
   return std::string(llvm::StringSwitch(Str)
  .Case("loop", ClangLoopStr)
  .Case("unroll_and_jam", Str)


Index: clang/test/Parser/pragma-loop.cpp
===
--- clang/test/Parser/pragma-loop.cpp
+++ clang/test/Parser/pragma-loop.cpp
@@ -305,34 +305,34 @@
 void foo(int *List, int Length) {
   int i;
 #pragma clang loop vectorize(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop vectorize' - ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop interleave(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop inte

[PATCH] D136784: [Clang] Improve diagnostic message for loop hint pragma

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGbeb997799d82: [Clang] Improve diagnostic message for loop 
hint pragma (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136784/new/

https://reviews.llvm.org/D136784

Files:
  clang/lib/Parse/ParsePragma.cpp
  clang/test/Parser/pragma-loop.cpp


Index: clang/test/Parser/pragma-loop.cpp
===
--- clang/test/Parser/pragma-loop.cpp
+++ clang/test/Parser/pragma-loop.cpp
@@ -305,34 +305,34 @@
 void foo(int *List, int Length) {
   int i;
 #pragma clang loop vectorize(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop vectorize' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop interleave(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop interleave' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop unroll(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop unroll' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop vectorize_predicate(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
vectorize_predicate' - ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop pipeline(disable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop pipeline' - 
ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop vectorize_width(2, scalable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop interleave_count(2, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop unroll_count(2, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - 
ignored}}*/ #pragma clang loop pipeline_initiation_interval(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
vectorize_width' - ignored}}*/ #pragma clang loop vectorize_width(2, scalable, 
extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
interleave_count' - ignored}}*/ #pragma clang loop interleave_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop unroll_count' 
- ignored}}*/ #pragma clang loop unroll_count(2, extra)
+/* expected-warning {{extra tokens at end of '#pragma clang loop 
pipeline_initiation_interval' - ignored}}*/ #pragma clang loop 
pipeline_initiation_interval(2, extra)
   while (i-6 < Length) {
 List[i] = i;
   }
Index: clang/lib/Parse/ParsePragma.cpp
===
--- clang/lib/Parse/ParsePragma.cpp
+++ clang/lib/Parse/ParsePragma.cpp
@@ -1303,7 +1303,9 @@
 
 static std::string PragmaLoopHintString(Token PragmaName, Token Option) {
   StringRef Str = PragmaName.getIdentifierInfo()->getName();
-  std::string ClangLoopStr = (llvm::Twine("clang loop ") + Str).str();
+  std::string ClangLoopStr("clang loop ");
+  if (Str == "loop" && Option.getIdentifierInfo())
+ClangLoopStr += Option.getIdentifierInfo()->getName();
   return std::string(llvm::StringSwitch(Str)
  .Case("loop", ClangLoopStr)
  .Case("unroll_and_jam", Str)


Index: clang/test/Parser/pragma-loop.cpp
===
--- clang/test/Parser/pragma-loop.cpp
+++ clang/test/Parser/pragma-loop.cpp
@@ -305,34 +305,34 @@
 void foo(int *List, int Length) {
   int i;
 #pragma clang loop vectorize(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop vectorize' - ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop interleave(enable, extra)
-/* expected-warning {{extra tokens at end of '#pragma clang loop loop' - ignored}}*/ while (i-6 < Length) {
+/* expected-warning {{extra tokens at end of '#pragma clang loop interleave' - ignored}}*/ while (i-6 < Length) {
 List[i] = i;
   }
 
 #pragma clang loop unroll(enable, extra)
-/* expected-warning {{extra tokens at en

[PATCH] D134407: [FPEnv] Remove inaccurate comments regarding signaling NaN for isless

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
Herald added a project: All.
eopXD requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

By draft of C23 (https://www.open-std.org/jtc1/sc22/wg14/www/docs/n2912.pdf),
the description for isless macro under 7.12.17.3 says,

The isless macro determines whether its first argument is less than its second
argument. The value of isless(x,y) is always equal to (x)< (y); however, unlike
(x) < (y), isless(x,y) does not raise the invalid floating-point exception when
x and y are unordered and neither is a signaling NaN.

isless should trap when encountering signaling NaN.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134407

Files:
  clang/lib/CodeGen/CGBuiltin.cpp


Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -2976,7 +2976,6 @@
 // Ordered comparisons: we know the arguments to these are matching scalar
 // floating point values.
 CodeGenFunction::CGFPOptionsRAII FPOptsRAII(*this, E);
-// FIXME: for strictfp/IEEE-754 we need to not trap on SNaN here.
 Value *LHS = EmitScalarExpr(E->getArg(0));
 Value *RHS = EmitScalarExpr(E->getArg(1));
 


Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -2976,7 +2976,6 @@
 // Ordered comparisons: we know the arguments to these are matching scalar
 // floating point values.
 CodeGenFunction::CGFPOptionsRAII FPOptsRAII(*this, E);
-// FIXME: for strictfp/IEEE-754 we need to not trap on SNaN here.
 Value *LHS = EmitScalarExpr(E->getArg(0));
 Value *RHS = EmitScalarExpr(E->getArg(1));
 
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[PATCH] D134407: [FPEnv] Remove inaccurate comments regarding signaling NaN for isless

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG10409bf86e58: [FPEnv] Remove inaccurate comments regarding 
signaling NaN for isless (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134407/new/

https://reviews.llvm.org/D134407

Files:
  clang/lib/CodeGen/CGBuiltin.cpp


Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -2976,7 +2976,6 @@
 // Ordered comparisons: we know the arguments to these are matching scalar
 // floating point values.
 CodeGenFunction::CGFPOptionsRAII FPOptsRAII(*this, E);
-// FIXME: for strictfp/IEEE-754 we need to not trap on SNaN here.
 Value *LHS = EmitScalarExpr(E->getArg(0));
 Value *RHS = EmitScalarExpr(E->getArg(1));
 


Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -2976,7 +2976,6 @@
 // Ordered comparisons: we know the arguments to these are matching scalar
 // floating point values.
 CodeGenFunction::CGFPOptionsRAII FPOptsRAII(*this, E);
-// FIXME: for strictfp/IEEE-754 we need to not trap on SNaN here.
 Value *LHS = EmitScalarExpr(E->getArg(0));
 Value *RHS = EmitScalarExpr(E->getArg(1));
 
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[PATCH] D134513: [RISCV][Clang] Replace all undef value with poison

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
eopXD added reviewers: nlopes, khchen, craig.topper.
Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb, arichardson.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

Address remaining work that dates back to discussion in D126745 



Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134513

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnot.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfabs.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnot.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vundefined.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vwcvt.c

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[PATCH] D134513: [RISCV][Clang] Replace all undef value with poison

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG75279aeecd1d: [RISCV][Clang] Replace all undef value with 
poison (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134513/new/

https://reviews.llvm.org/D134513

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnot.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfabs.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnot.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vundefined.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vwcvt.c

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[PATCH] D134745: [LV][Metadata] Add loop.interleave.enable for loop vectorizer

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
eopXD added reviewers: sdesmalen, paulwalker-arm, fhahn, reames, hfinkel.
Herald added subscribers: frasercrmck, luismarques, apazos, sameer.abuasal, 
s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, 
asb, hiraditya.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, MaskRay.
Herald added projects: clang, LLVM.

Adding this metadata allows {loop.vectorize.enable, false} to be used
without disabling the whole pass.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134745

Files:
  clang/lib/CodeGen/CGLoopInfo.cpp
  clang/lib/CodeGen/CGLoopInfo.h
  clang/test/CodeGenCXX/pragma-loop-predicate.cpp
  clang/test/CodeGenCXX/pragma-loop-safety.cpp
  clang/test/CodeGenCXX/pragma-loop.cpp
  llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
  llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
  
llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll
  llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
  llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
  llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll
  
llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
  llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.ll
  llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll
  llvm/test/Transforms/LoopVectorize/explicit_outer_detection.ll
  llvm/test/Transforms/LoopVectorize/explicit_outer_nonuniform_inner.ll
  llvm/test/Transforms/LoopVectorize/explicit_outer_uniform_diverg_branch.ll
  llvm/test/Transforms/LoopVectorize/no_switch.ll
  llvm/test/Transforms/LoopVectorize/no_switch_disable_vectorization.ll
  llvm/test/Transforms/LoopVectorize/nounroll.ll
  llvm/test/Transforms/LoopVectorize/optsize.ll
  llvm/test/Transforms/LoopVectorize/outer-loop-vec-phi-predecessor-order.ll
  llvm/test/Transforms/LoopVectorize/outer_loop_test1.ll
  llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
  llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
  llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
  llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
  llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
  llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
  llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll

Index: llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
@@ -196,5 +196,6 @@
 exit:
   ret void
 }
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
@@ -68,5 +68,6 @@
   ret void
 }
 
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
@@ -77,5 +77,6 @@
   ret void
 }
 
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
@@ -69,6 +69,7 @@
   ret void
 }
 
-!1 = distinct !{!1, !2, !3}
+!1 = distinct !{!1, !2, !3, !4}
 !2 = !{!"llvm.loop.vectorize.width", i32 4}
 !3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!4 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
@@ -43,5 +43,6 @@
   ret void
 }
 
-!0 = distinct !{!0, !1}
+!0 = 

[PATCH] D134745: [LV][Metadata] Add loop.interleave.enable for loop vectorizer

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eopXD added a comment.

Please feel free to add appropriate reviewer to this patch.


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[PATCH] D134745: [LV][Metadata] Add loop.interleave.enable for loop vectorizer

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eopXD updated this revision to Diff 463261.
eopXD added a comment.

Update comment.


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Files:
  clang/lib/CodeGen/CGLoopInfo.cpp
  clang/lib/CodeGen/CGLoopInfo.h
  clang/test/CodeGenCXX/pragma-loop-predicate.cpp
  clang/test/CodeGenCXX/pragma-loop-safety.cpp
  clang/test/CodeGenCXX/pragma-loop.cpp
  llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
  llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
  
llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll
  llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
  llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
  llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll
  
llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
  llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.ll
  llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll
  llvm/test/Transforms/LoopVectorize/explicit_outer_detection.ll
  llvm/test/Transforms/LoopVectorize/explicit_outer_nonuniform_inner.ll
  llvm/test/Transforms/LoopVectorize/explicit_outer_uniform_diverg_branch.ll
  llvm/test/Transforms/LoopVectorize/no_switch.ll
  llvm/test/Transforms/LoopVectorize/no_switch_disable_vectorization.ll
  llvm/test/Transforms/LoopVectorize/nounroll.ll
  llvm/test/Transforms/LoopVectorize/optsize.ll
  llvm/test/Transforms/LoopVectorize/outer-loop-vec-phi-predecessor-order.ll
  llvm/test/Transforms/LoopVectorize/outer_loop_test1.ll
  llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
  llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
  llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
  llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
  llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
  llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
  llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll

Index: llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
@@ -196,5 +196,6 @@
 exit:
   ret void
 }
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
@@ -68,5 +68,6 @@
   ret void
 }
 
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
@@ -77,5 +77,6 @@
   ret void
 }
 
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
@@ -69,6 +69,7 @@
   ret void
 }
 
-!1 = distinct !{!1, !2, !3}
+!1 = distinct !{!1, !2, !3, !4}
 !2 = !{!"llvm.loop.vectorize.width", i32 4}
 !3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!4 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
@@ -43,5 +43,6 @@
   ret void
 }
 
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
===
--- llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
+++ llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
@@ -2,7 +2,7 @@
 ; REQUIRES: asserts
 
 ; CHECK: LV: Checking a loop in 'foo'
-; CHECK: LV: Loop hints: 

[PATCH] D134745: [LV][Metadata] Add loop.interleave.enable for loop vectorizer

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD marked an inline comment as done.
eopXD added a comment.

After this patch, we can remove setVectorizeWidth(1) and setInterleaveCount(1) 
when vectorize(disable) and interleave(disable) is specified. For now it is not 
removed to keep the patch limited and simple enough.


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[PATCH] D134745: [LV][Metadata] Add loop.interleave.enable for loop vectorizer

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 463299.
eopXD added a comment.

Fix grammar error in comment.


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Files:
  clang/lib/CodeGen/CGLoopInfo.cpp
  clang/lib/CodeGen/CGLoopInfo.h
  clang/test/CodeGenCXX/pragma-loop-predicate.cpp
  clang/test/CodeGenCXX/pragma-loop-safety.cpp
  clang/test/CodeGenCXX/pragma-loop.cpp
  llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
  llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
  
llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll
  llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
  llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
  llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll
  
llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
  llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.ll
  llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll
  llvm/test/Transforms/LoopVectorize/explicit_outer_detection.ll
  llvm/test/Transforms/LoopVectorize/explicit_outer_nonuniform_inner.ll
  llvm/test/Transforms/LoopVectorize/explicit_outer_uniform_diverg_branch.ll
  llvm/test/Transforms/LoopVectorize/no_switch.ll
  llvm/test/Transforms/LoopVectorize/no_switch_disable_vectorization.ll
  llvm/test/Transforms/LoopVectorize/nounroll.ll
  llvm/test/Transforms/LoopVectorize/optsize.ll
  llvm/test/Transforms/LoopVectorize/outer-loop-vec-phi-predecessor-order.ll
  llvm/test/Transforms/LoopVectorize/outer_loop_test1.ll
  llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
  llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
  llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
  llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
  llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
  llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
  llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll

Index: llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
@@ -196,5 +196,6 @@
 exit:
   ret void
 }
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
@@ -68,5 +68,6 @@
   ret void
 }
 
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
@@ -77,5 +77,6 @@
   ret void
 }
 
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
@@ -69,6 +69,7 @@
   ret void
 }
 
-!1 = distinct !{!1, !2, !3}
+!1 = distinct !{!1, !2, !3, !4}
 !2 = !{!"llvm.loop.vectorize.width", i32 4}
 !3 = !{!"llvm.loop.vectorize.enable", i1 true}
+!4 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
===
--- llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
+++ llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll
@@ -43,5 +43,6 @@
   ret void
 }
 
-!0 = distinct !{!0, !1}
+!0 = distinct !{!0, !1, !2}
 !1 = !{!"llvm.loop.vectorize.enable", i1 true}
+!2 = !{!"llvm.loop.interleave.enable", i1 false}
Index: llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
===
--- llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
+++ llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
@@ -2,7 +2,7 @@
 ; REQUIRES: asserts
 
 ; CHECK: LV: Checking a loop in 'foo'
-; CHECK: LV

[PATCH] D128142: [MemProf] Memprof profile matching and annotation

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD added a comment.

I see that this revision is reverted along with reversion of D128143 
, I see that D128143 
 is re-commited.
The commit message of D128143  says that it 
depends on this patch. Does the dependence still exist?


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[PATCH] D128142: [MemProf] Memprof profile matching and annotation

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD added a comment.

Please disregard my previous comment, I missed the latest commit.


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[PATCH] D134745: [LV][Metadata] Add loop.interleave.enable for loop vectorizer

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD added a comment.

Gentle ping, thank you ;)


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[PATCH] D134745: [LV][Metadata] Add loop.interleave.enable for loop vectorizer

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD added a comment.

@fhahn Thank you very much for the review, backward compatibility is a good 
point. I will update the revision.


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[PATCH] D134745: [LV][Metadata] Add loop.interleave.enable for loop vectorizer

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD added a comment.

Hi @fhahn,

After a second thought, I think posting a clear RFC [0] to the community that 
defines the
problem and goal this patch tries to achieve so the community is notified of 
such change
is a better approach than directly updating this patch. Please consider to drop 
by and
give a review.

Thank you very much for your time.

[0] [[RFC] Enabling LoopVectorizer for vectorization width of 
1](https://discourse.llvm.org/t/rfc-enabling-loopvectorizer-for-vectorization-width-of-1/65769)

Regards,

eop Chen


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[PATCH] D135519: [RISCV] Remove some vsetvli intrinsics under Zve32*.

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD accepted this revision.
eopXD added a comment.
This revision is now accepted and ready to land.

Looks good to me. I think this should solve 
https://github.com/riscv/riscv-v-spec/issues/832.


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[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:772
+
+  if ((Exts.count("zvkb") || Exts.count("zvknhb")) && !Exts.count("zve64x"))
+return createStringError(

With this check, the check for these extensions on top are redundant.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:1675
 
+include "RISCVInstrInfoZvk.td" //SIFIVE
 include "RISCVInstrInfoVPseudos.td"

Got to remove the company name here ;)



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td:8
+//===--===//
+///
+// This file describes the RISC-V instructions from the standard 'Zvk',

`///` -> `//`, and same below.


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[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD added inline comments.



Comment at: llvm/test/MC/RISCV/rvv/rv64zvksed_invalid.s:1
+# RUN: not llvm-mc -triple=riscv64 --mattr=+zve32x 
--mattr=+experimental-zvksed -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR

I see similar files uses `-invalid` instead of `_invalid`. Probably good to 
follow that.


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[PATCH] D139025: [NFC][RISCV] Extract utility to calculate value through MajorVersion and MinorVersion

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG1953c7e03b08: [NFC][RISCV] Extract utility to calculate 
value through MajorVersion and… (authored by eopXD).

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Files:
  clang/lib/Basic/Targets/RISCV.cpp


Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -118,6 +118,10 @@
   return R;
 }
 
+static unsigned getVersionValue(unsigned MajorVersion, unsigned MinorVersion) {
+  return MajorVersion * 100 + MinorVersion * 1000;
+}
+
 void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
   Builder.defineMacro("__ELF__");
@@ -153,10 +157,10 @@
   for (auto &Extension : ISAInfo->getExtensions()) {
 auto ExtName = Extension.first;
 auto ExtInfo = Extension.second;
-unsigned Version =
-(ExtInfo.MajorVersion * 100) + (ExtInfo.MinorVersion * 1000);
 
-Builder.defineMacro(Twine("__riscv_", ExtName), Twine(Version));
+Builder.defineMacro(
+Twine("__riscv_", ExtName),
+Twine(getVersionValue(ExtInfo.MajorVersion, ExtInfo.MinorVersion)));
   }
 
   if (ISAInfo->hasExtension("m") || ISAInfo->hasExtension("zmmul"))
@@ -194,8 +198,7 @@
   if (ISAInfo->hasExtension("zve32x")) {
 Builder.defineMacro("__riscv_vector");
 // Currently we support the v0.10 RISC-V V intrinsics.
-unsigned Version = (0 * 100) + (10 * 1000);
-Builder.defineMacro("__riscv_v_intrinsic", Twine(Version));
+Builder.defineMacro("__riscv_v_intrinsic", Twine(getVersionValue(0, 10)));
   }
 }
 


Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -118,6 +118,10 @@
   return R;
 }
 
+static unsigned getVersionValue(unsigned MajorVersion, unsigned MinorVersion) {
+  return MajorVersion * 100 + MinorVersion * 1000;
+}
+
 void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
   Builder.defineMacro("__ELF__");
@@ -153,10 +157,10 @@
   for (auto &Extension : ISAInfo->getExtensions()) {
 auto ExtName = Extension.first;
 auto ExtInfo = Extension.second;
-unsigned Version =
-(ExtInfo.MajorVersion * 100) + (ExtInfo.MinorVersion * 1000);
 
-Builder.defineMacro(Twine("__riscv_", ExtName), Twine(Version));
+Builder.defineMacro(
+Twine("__riscv_", ExtName),
+Twine(getVersionValue(ExtInfo.MajorVersion, ExtInfo.MinorVersion)));
   }
 
   if (ISAInfo->hasExtension("m") || ISAInfo->hasExtension("zmmul"))
@@ -194,8 +198,7 @@
   if (ISAInfo->hasExtension("zve32x")) {
 Builder.defineMacro("__riscv_vector");
 // Currently we support the v0.10 RISC-V V intrinsics.
-unsigned Version = (0 * 100) + (10 * 1000);
-Builder.defineMacro("__riscv_v_intrinsic", Twine(Version));
+Builder.defineMacro("__riscv_v_intrinsic", Twine(getVersionValue(0, 10)));
   }
 }
 
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[PATCH] D140389: [NFC][RISCV] Rename data member 'DefaultPolicy' to 'PolicyAttrs'

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
Herald added subscribers: sunshaoce, VincentWu, vkmr, frasercrmck, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

The naming here is strange since the value may still be updated.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140389

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -163,14 +163,14 @@
 OS << "  ID = Intrinsic::riscv_" + RVVI->getIRName() + ";\n";
   if (RVVI->getNF() >= 2)
 OS << "  NF = " + utostr(RVVI->getNF()) + ";\n";
-  // We had initialized DefaultPolicy as TU/TUMU in CodeGen function.
-  if (!RVVI->getDefaultPolicy().isTUPolicy() &&
-  !RVVI->getDefaultPolicy().isTUMUPolicy() && !RVVI->hasPassthruOperand() &&
+  // We had initialized PolicyAttrs as TU/TUMU in CodeGen function.
+  if (!RVVI->getPolicyAttrs().isTUPolicy() &&
+  !RVVI->getPolicyAttrs().isTUMUPolicy() && !RVVI->hasPassthruOperand() &&
   !RVVI->hasManualCodegen() && RVVI->hasVL())
-OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
+OS << "  PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n";
 
   if (RVVI->hasManualCodegen()) {
-OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
+OS << "  PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n";
 OS << RVVI->getManualCodegen();
 OS << "break;\n";
 return;
@@ -191,13 +191,12 @@
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);\n";
   if (RVVI->hasPolicyOperand())
 OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(),"
-  " DefaultPolicy));\n";
-  if (RVVI->hasMaskedOffOperand() &&
-  RVVI->getDefaultPolicy().isTAMAPolicy())
+  " PolicyAttrs));\n";
+  if (RVVI->hasMaskedOffOperand() && RVVI->getPolicyAttrs().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   // Masked reduction cases.
   if (!RVVI->hasMaskedOffOperand() && RVVI->hasPassthruOperand() &&
-  RVVI->getDefaultPolicy().isTAMAPolicy())
+  RVVI->getPolicyAttrs().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
 } else {
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end());\n";
@@ -205,9 +204,8 @@
   } else {
 if (RVVI->hasPolicyOperand())
   OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(), "
-"DefaultPolicy));\n";
-else if (RVVI->hasPassthruOperand() &&
- RVVI->getDefaultPolicy().isTAPolicy())
+"PolicyAttrs));\n";
+else if (RVVI->hasPassthruOperand() && RVVI->getPolicyAttrs().isTAPolicy())
   OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   }
 
@@ -444,7 +442,7 @@
   llvm::stable_sort(Defs, [](const std::unique_ptr &A,
  const std::unique_ptr &B) {
 if (A->getIRName() == B->getIRName())
-  return (A->getDefaultPolicy() < B->getDefaultPolicy());
+  return (A->getPolicyAttrs() < B->getPolicyAttrs());
 return (A->getIRName() < B->getIRName());
   });
 
@@ -458,7 +456,7 @@
 StringRef CurIRName = Def->getIRName();
 if (CurIRName != PrevDef->getIRName() ||
 (Def->getManualCodegen() != PrevDef->getManualCodegen()) ||
-(Def->getDefaultPolicy() != PrevDef->getDefaultPolicy())) {
+(Def->getPolicyAttrs() != PrevDef->getPolicyAttrs())) {
   emitCodeGenSwitchBody(PrevDef, OS);
 }
 PrevDef = Def.get();
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -848,12 +848,11 @@
 bool SupportOverloading, bool HasBuiltinAlias, StringRef ManualCodegen,
 const RVVTypes &OutInTypes, const std::vector &NewIntrinsicTypes,
 const std::vector &RequiredFeatures, unsigned NF,
-Policy NewDefaultPolicy, bool IsPrototypeDefaultTU)
+Policy NewPolicyAttrs, bool IsPrototypeDefaultTU)
 : IRName(IRName), IsMasked(IsMasked),
   HasMaskedOffOperand(HasMaskedOffOperand), HasVL(HasVL), Scheme(Scheme),
   SupportOverloading(SupportOverloading), Ha

[PATCH] D140389: [NFC][RISCV] Rename data member 'DefaultPolicy' to 'PolicyAttrs'

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD added a comment.

Just throwing out the question here, I would be happy to rename it to anything 
else that makes sense rather than the current.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140389/new/

https://reviews.llvm.org/D140389

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[PATCH] D140389: [NFC][RISCV] Rename data member 'DefaultPolicy' to 'PolicyAttrs'

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 484758.
eopXD added a comment.

Rebase upon latest main.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140389/new/

https://reviews.llvm.org/D140389

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -163,14 +163,14 @@
 OS << "  ID = Intrinsic::riscv_" + RVVI->getIRName() + ";\n";
   if (RVVI->getNF() >= 2)
 OS << "  NF = " + utostr(RVVI->getNF()) + ";\n";
-  // We had initialized DefaultPolicy as TU/TUMU in CodeGen function.
-  if (!RVVI->getDefaultPolicy().isTUPolicy() &&
-  !RVVI->getDefaultPolicy().isTUMUPolicy() && !RVVI->hasPassthruOperand() &&
+  // We had initialized PolicyAttrs as TU/TUMU in CodeGen function.
+  if (!RVVI->getPolicyAttrs().isTUPolicy() &&
+  !RVVI->getPolicyAttrs().isTUMUPolicy() && !RVVI->hasPassthruOperand() &&
   !RVVI->hasManualCodegen() && RVVI->hasVL())
-OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
+OS << "  PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n";
 
   if (RVVI->hasManualCodegen()) {
-OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
+OS << "  PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n";
 if (RVVI->isMasked())
   OS << "IsMasked = true;\n";
 else
@@ -195,13 +195,12 @@
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);\n";
   if (RVVI->hasPolicyOperand())
 OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(),"
-  " DefaultPolicy));\n";
-  if (RVVI->hasMaskedOffOperand() &&
-  RVVI->getDefaultPolicy().isTAMAPolicy())
+  " PolicyAttrs));\n";
+  if (RVVI->hasMaskedOffOperand() && RVVI->getPolicyAttrs().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   // Masked reduction cases.
   if (!RVVI->hasMaskedOffOperand() && RVVI->hasPassthruOperand() &&
-  RVVI->getDefaultPolicy().isTAMAPolicy())
+  RVVI->getPolicyAttrs().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
 } else {
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end());\n";
@@ -209,9 +208,8 @@
   } else {
 if (RVVI->hasPolicyOperand())
   OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(), "
-"DefaultPolicy));\n";
-else if (RVVI->hasPassthruOperand() &&
- RVVI->getDefaultPolicy().isTAPolicy())
+"PolicyAttrs));\n";
+else if (RVVI->hasPassthruOperand() && RVVI->getPolicyAttrs().isTAPolicy())
   OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   }
 
@@ -448,7 +446,7 @@
   llvm::stable_sort(Defs, [](const std::unique_ptr &A,
  const std::unique_ptr &B) {
 if (A->getIRName() == B->getIRName())
-  return (A->getDefaultPolicy() < B->getDefaultPolicy());
+  return (A->getPolicyAttrs() < B->getPolicyAttrs());
 return (A->getIRName() < B->getIRName());
   });
 
@@ -462,7 +460,7 @@
 StringRef CurIRName = Def->getIRName();
 if (CurIRName != PrevDef->getIRName() ||
 (Def->getManualCodegen() != PrevDef->getManualCodegen()) ||
-(Def->getDefaultPolicy() != PrevDef->getDefaultPolicy())) {
+(Def->getPolicyAttrs() != PrevDef->getPolicyAttrs())) {
   emitCodeGenSwitchBody(PrevDef, OS);
 }
 PrevDef = Def.get();
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -848,12 +848,11 @@
 bool SupportOverloading, bool HasBuiltinAlias, StringRef ManualCodegen,
 const RVVTypes &OutInTypes, const std::vector &NewIntrinsicTypes,
 const std::vector &RequiredFeatures, unsigned NF,
-Policy NewDefaultPolicy, bool IsPrototypeDefaultTU)
+Policy NewPolicyAttrs, bool IsPrototypeDefaultTU)
 : IRName(IRName), IsMasked(IsMasked),
   HasMaskedOffOperand(HasMaskedOffOperand), HasVL(HasVL), Scheme(Scheme),
   SupportOverloading(SupportOverloading), HasBuiltinAlias(HasBuiltinAlias),
-  ManualCodegen(ManualCodegen.str()), NF(NF),
-  DefaultPolicy(NewDefaultPolicy) {
+  ManualCodegen(ManualCodegen.str()), NF(NF), PolicyAttrs(NewPolicyAttrs) {
 
   // Init BuiltinName, Name and OverloadedName
   BuiltinName = NewName.str();
@@ -868,7 +867,7 @@
 OverloadedName += "_" + OverloadedSuffix.str();
 
   updateNamesAndPolicy(IsMasked, hasPolicy(), IsPrototypeDef

[PATCH] D140661: [NFC][Clang] Reduce for-loop with SmallVectorUtility

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
Herald added subscribers: frasercrmck, luismarques, apazos, sameer.abuasal, 
s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

As topic, this commit reduces the for-loops with utilities of SmallVector.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140661

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/Support/RISCVVIntrinsicUtils.cpp

Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -939,8 +939,7 @@
 // (void, op0 address, op1 address, ..., maskedoff0, maskedoff1, ...)
 PrototypeDescriptor MaskoffType = NewPrototype[1];
 MaskoffType.TM &= ~static_cast(TypeModifier::Pointer);
-for (unsigned I = 0; I < NF; ++I)
-  NewPrototype.insert(NewPrototype.begin() + NF + 1, MaskoffType);
+NewPrototype.insert(NewPrototype.begin() + NF + 1, NF, MaskoffType);
   }
 }
 // Erase passthru operand for TAM
@@ -983,8 +982,7 @@
   // (void, op0 address, op1 address, maskedoff0, maskedoff1, ...)
   PrototypeDescriptor MaskoffType = Prototype[1];
   MaskoffType.TM &= ~static_cast(TypeModifier::Pointer);
-  for (unsigned I = 0; I < NF; ++I)
-NewPrototype.insert(NewPrototype.begin() + NF + 1, MaskoffType);
+  NewPrototype.insert(NewPrototype.begin() + NF + 1, NF, MaskoffType);
 }
  }
 
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -848,8 +848,7 @@
 // builtin: (val0 address, ..., mask, maskedoff0, ..., ptr, vl)
 // intrinsic: (maskedoff0, ..., ptr, mask, vl)
 if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC) {
-  for (unsigned I = 0; I < NF; ++I)
-Operands.push_back(llvm::PoisonValue::get(ResultType));
+  Operands.append(NF, llvm::PoisonValue::get(ResultType));
   Operands.push_back(Ops[NF + 1]);
   Operands.push_back(Ops[NF]);
   Operands.push_back(Ops[NF + 2]);
@@ -867,8 +866,7 @@
 // TU builtin: (val0 address, ..., passthru0, ..., ptr, vl)
 // intrinsic: (passthru0, passthru1, ..., ptr, vl)
 if (DefaultPolicy == TAIL_AGNOSTIC) {
-  for (unsigned I = 0; I < NF; ++I)
-Operands.push_back(llvm::PoisonValue::get(ResultType));
+  Operands.append(NF, llvm::PoisonValue::get(ResultType));
   Operands.push_back(Ops[NF]);
   Operands.push_back(Ops[NF + 1]);
 } else {
@@ -927,8 +925,7 @@
 // builtin: (val0 address, ..., mask, maskedoff0, ..., ptr, new_vl, vl)
 // intrinsic: (maskedoff0, ..., ptr, mask, vl)
 if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC) {
-  for (unsigned I = 0; I < NF; ++I)
-Operands.push_back(llvm::PoisonValue::get(ResultType));
+  Operands.append(NF, llvm::PoisonValue::get(ResultType));
   Operands.push_back(Ops[NF + 1]);
   Operands.push_back(Ops[NF]);
   Operands.push_back(Ops[NF + 3]);
@@ -948,8 +945,7 @@
 // TU builtin: (val0 address, ..., passthru0, ..., ptr, new_vl, vl)
 // intrinsic: (passthru0, passthru1, ..., ptr, vl)
 if (DefaultPolicy == TAIL_AGNOSTIC) {
-  for (unsigned I = 0; I < NF; ++I)
-Operands.push_back(llvm::PoisonValue::get(ResultType));
+  Operands.append(NF, llvm::PoisonValue::get(ResultType));
   Operands.push_back(Ops[NF]);
   Operands.push_back(Ops[NF + 2]);
   NewVL = Ops[NF + 1];
@@ -1010,8 +1006,7 @@
 // builtin: (val0 address, ..., mask, maskedoff0, ..., ptr, stride, vl)
 // intrinsic: (maskedoff0, ..., ptr, stride, mask, vl)
 if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC) {
-  for (unsigned I = 0; I < NF; ++I)
-Operands.push_back(llvm::PoisonValue::get(ResultType));
+  Operands.append(NF, llvm::PoisonValue::get(ResultType));
   Operands.push_back(Ops[NF + 1]);
   Operands.push_back(Ops[NF + 2]);
   Operands.push_back(Ops[NF]);
@@ -1031,8 +1026,7 @@
 // TU builtin: (val0 address, ..., passthru0, ..., ptr, stride, vl)
 // intrinsic: (passthru0, passthru1, ..., ptr, stride, vl)
 if (DefaultPolicy == TAIL_AGNOSTIC) {
-  for (unsigned I = 0; I < NF; ++I)
-Operands.push_back(llvm::PoisonValue::get(ResultType));
+  Operands.append(NF, llvm::PoisonValue::get(ResultType));
   Operands.push_back(Ops[NF]);
   O

[PATCH] D140662: [NFC][Clang][RISCV] Reduce boilerplate when determining prototype for segment loads

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
eopXD added reviewers: craig.topper, kito-cheng, khchen.
Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead.
Herald added a project: clang.

Depends on D140661 


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140662

Files:
  clang/include/clang/Basic/riscv_vector.td

Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -843,39 +843,30 @@
   ResultType = ConvertType(E->getArg(0)->getType()->getPointeeType());
   IntrinsicTypes = {ResultType, Ops.back()->getType()};
   SmallVector Operands;
-  if (IsMasked) {
-// TAMA builtin: (val0 address, ..., mask, ptr, vl)
-// builtin: (val0 address, ..., mask, maskedoff0, ..., ptr, vl)
-// intrinsic: (maskedoff0, ..., ptr, mask, vl)
-if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC) {
-  Operands.append(NF, llvm::PoisonValue::get(ResultType));
-  Operands.push_back(Ops[NF + 1]);
-  Operands.push_back(Ops[NF]);
-  Operands.push_back(Ops[NF + 2]);
-} else {
-  for (unsigned I = 0; I < NF; ++I)
-Operands.push_back(Ops[NF + I + 1]);
-  Operands.push_back(Ops[2 * NF + 1]);
-  Operands.push_back(Ops[NF]);
-  Operands.push_back(Ops[2 * NF + 2]);
-}
+
+  // Intrinsic is in the form of below,
+  // Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Mask, VL, Policy)
+  // Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, VL)
+  // where the Vectors is poison when the policy behavior allows us to not care
+  // about any masked-off elements.
+  Value *PassThruOperand = IsMasked ?
+(DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC) ?
+  llvm::PoisonValue::get(ResultType) : Ops[NF + 1] :
+(DefaultPolicy == TAIL_AGNOSTIC) ?
+  llvm::PoisonValue::get(ResultType) : Ops[NF];
+  unsigned PtrOperandIdx = IsMasked ?
+(DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC) ? NF + 1 : 2 * NF + 1 :
+(DefaultPolicy == TAIL_AGNOSTIC) ? NF : 2 * NF;
+  Value *PtrOperand = Ops[PtrOperandIdx];
+  Value *VLOperand = Ops[PtrOperandIdx + 1];
+  Operands.append(NF, PassThruOperand);
+  Operands.push_back(PtrOperand);
+  if (IsMasked)
+Operands.push_back(Ops[NF]);
+  Operands.push_back(VLOperand);
+  if (IsMasked)
 Operands.push_back(ConstantInt::get(Ops.back()->getType(), DefaultPolicy));
-assert(Operands.size() == NF + 4);
-  } else {
-// TA builtin: (val0 address, val1 address, ..., ptr, vl)
-// TU builtin: (val0 address, ..., passthru0, ..., ptr, vl)
-// intrinsic: (passthru0, passthru1, ..., ptr, vl)
-if (DefaultPolicy == TAIL_AGNOSTIC) {
-  Operands.append(NF, llvm::PoisonValue::get(ResultType));
-  Operands.push_back(Ops[NF]);
-  Operands.push_back(Ops[NF + 1]);
-} else {
-  for (unsigned I = 0; I < NF; ++I)
-Operands.push_back(Ops[NF + I]);
-  Operands.push_back(Ops[2 * NF]);
-  Operands.push_back(Ops[2 * NF + 1]);
-}
-  }
+
   llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
   llvm::Value *LoadValue = Builder.CreateCall(F, Operands, "");
   clang::CharUnits Align =
@@ -918,45 +909,31 @@
   ResultType = ConvertType(E->getArg(0)->getType()->getPointeeType());
   IntrinsicTypes = {ResultType, Ops.back()->getType()};
   SmallVector Operands;
-  Value *NewVL;
 
-  if (IsMasked) {
-// TAMA builtin: (val0 address, ..., mask, ptr, new_vl, vl)
-// builtin: (val0 address, ..., mask, maskedoff0, ..., ptr, new_vl, vl)
-// intrinsic: (maskedoff0, ..., ptr, mask, vl)
-if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC) {
-  Operands.append(NF, llvm::PoisonValue::get(ResultType));
-  Operands.push_back(Ops[NF + 1]);
-  Operands.push_back(Ops[NF]);
-  Operands.push_back(Ops[NF + 3]);
-  NewVL = Ops[NF + 2];
-} else {
-  for (unsigned I = 0; I < NF; ++I)
-Operands.push_back(Ops[NF + I + 1]);
-  Operands.push_back(Ops[2 * NF + 1]);
-  Operands.push_back(Ops[NF]);
-  Operands.push_back(Ops[2 * NF + 3]);
-  NewVL = Ops[2 * NF + 2];
-}
+  // Intrinsic is in the form of below,
+  // Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Mask, NewVL, VL, Policy)

[PATCH] D140661: [NFC][Clang][RISCV] Reduce for-loop with SmallVector utility

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG904a79f99153: [NFC][Clang][RISCV] Reduce for-loop with 
SmallVector utility (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140661/new/

https://reviews.llvm.org/D140661

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/Support/RISCVVIntrinsicUtils.cpp

Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -939,8 +939,7 @@
 // (void, op0 address, op1 address, ..., maskedoff0, maskedoff1, ...)
 PrototypeDescriptor MaskoffType = NewPrototype[1];
 MaskoffType.TM &= ~static_cast(TypeModifier::Pointer);
-for (unsigned I = 0; I < NF; ++I)
-  NewPrototype.insert(NewPrototype.begin() + NF + 1, MaskoffType);
+NewPrototype.insert(NewPrototype.begin() + NF + 1, NF, MaskoffType);
   }
 }
 // Erase passthru operand for TAM
@@ -983,8 +982,7 @@
   // (void, op0 address, op1 address, maskedoff0, maskedoff1, ...)
   PrototypeDescriptor MaskoffType = Prototype[1];
   MaskoffType.TM &= ~static_cast(TypeModifier::Pointer);
-  for (unsigned I = 0; I < NF; ++I)
-NewPrototype.insert(NewPrototype.begin() + NF + 1, MaskoffType);
+  NewPrototype.insert(NewPrototype.begin() + NF + 1, NF, MaskoffType);
 }
  }
 
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -848,8 +848,7 @@
 // builtin: (val0 address, ..., mask, maskedoff0, ..., ptr, vl)
 // intrinsic: (maskedoff0, ..., ptr, mask, vl)
 if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC) {
-  for (unsigned I = 0; I < NF; ++I)
-Operands.push_back(llvm::PoisonValue::get(ResultType));
+  Operands.append(NF, llvm::PoisonValue::get(ResultType));
   Operands.push_back(Ops[NF + 1]);
   Operands.push_back(Ops[NF]);
   Operands.push_back(Ops[NF + 2]);
@@ -867,8 +866,7 @@
 // TU builtin: (val0 address, ..., passthru0, ..., ptr, vl)
 // intrinsic: (passthru0, passthru1, ..., ptr, vl)
 if (DefaultPolicy == TAIL_AGNOSTIC) {
-  for (unsigned I = 0; I < NF; ++I)
-Operands.push_back(llvm::PoisonValue::get(ResultType));
+  Operands.append(NF, llvm::PoisonValue::get(ResultType));
   Operands.push_back(Ops[NF]);
   Operands.push_back(Ops[NF + 1]);
 } else {
@@ -927,8 +925,7 @@
 // builtin: (val0 address, ..., mask, maskedoff0, ..., ptr, new_vl, vl)
 // intrinsic: (maskedoff0, ..., ptr, mask, vl)
 if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC) {
-  for (unsigned I = 0; I < NF; ++I)
-Operands.push_back(llvm::PoisonValue::get(ResultType));
+  Operands.append(NF, llvm::PoisonValue::get(ResultType));
   Operands.push_back(Ops[NF + 1]);
   Operands.push_back(Ops[NF]);
   Operands.push_back(Ops[NF + 3]);
@@ -948,8 +945,7 @@
 // TU builtin: (val0 address, ..., passthru0, ..., ptr, new_vl, vl)
 // intrinsic: (passthru0, passthru1, ..., ptr, vl)
 if (DefaultPolicy == TAIL_AGNOSTIC) {
-  for (unsigned I = 0; I < NF; ++I)
-Operands.push_back(llvm::PoisonValue::get(ResultType));
+  Operands.append(NF, llvm::PoisonValue::get(ResultType));
   Operands.push_back(Ops[NF]);
   Operands.push_back(Ops[NF + 2]);
   NewVL = Ops[NF + 1];
@@ -1010,8 +1006,7 @@
 // builtin: (val0 address, ..., mask, maskedoff0, ..., ptr, stride, vl)
 // intrinsic: (maskedoff0, ..., ptr, stride, mask, vl)
 if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC) {
-  for (unsigned I = 0; I < NF; ++I)
-Operands.push_back(llvm::PoisonValue::get(ResultType));
+  Operands.append(NF, llvm::PoisonValue::get(ResultType));
   Operands.push_back(Ops[NF + 1]);
   Operands.push_back(Ops[NF + 2]);
   Operands.push_back(Ops[NF]);
@@ -1031,8 +1026,7 @@
 // TU builtin: (val0 address, ..., passthru0, ..., ptr, stride, vl)
 // intrinsic: (passthru0, passthru1, ..., ptr, stride, vl)
 if (DefaultPolicy == TAIL_AGNOSTIC) {
-  for (unsigned I = 0; I < NF; ++I)
-Operands.push_back(llvm::PoisonValue::get(ResultType));
+  Operands.append(NF, llvm::PoisonValue::get(ResultType));
   Operands.push_back(Ops[NF]);
   Operands.push_back(Ops[NF + 1]);
   Operands.push_back(Ops[NF + 2]);
@@ -1086,8 +1080,7 @@
 // builtin: (val0 address, ..., mask, maskedoff0, ..., ptr, index, vl)
 // intrinsic: (maskedoff0, ..., ptr, index, mask, vl)
 

[PATCH] D140662: [NFC][Clang][RISCV] Reduce boilerplate when determining prototype for segment loads

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 485270.
eopXD added a comment.

Rebase to latest main.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140662/new/

https://reviews.llvm.org/D140662

Files:
  clang/include/clang/Basic/riscv_vector.td

Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -843,39 +843,30 @@
   ResultType = ConvertType(E->getArg(0)->getType()->getPointeeType());
   IntrinsicTypes = {ResultType, Ops.back()->getType()};
   SmallVector Operands;
-  if (IsMasked) {
-// TAMA builtin: (val0 address, ..., mask, ptr, vl)
-// builtin: (val0 address, ..., mask, maskedoff0, ..., ptr, vl)
-// intrinsic: (maskedoff0, ..., ptr, mask, vl)
-if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC) {
-  Operands.append(NF, llvm::PoisonValue::get(ResultType));
-  Operands.push_back(Ops[NF + 1]);
-  Operands.push_back(Ops[NF]);
-  Operands.push_back(Ops[NF + 2]);
-} else {
-  for (unsigned I = 0; I < NF; ++I)
-Operands.push_back(Ops[NF + I + 1]);
-  Operands.push_back(Ops[2 * NF + 1]);
-  Operands.push_back(Ops[NF]);
-  Operands.push_back(Ops[2 * NF + 2]);
-}
+
+  // Intrinsic is in the form of below,
+  // Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Mask, VL, Policy)
+  // Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, VL)
+  // where the Vectors is poison when the policy behavior allows us to not care
+  // about any masked-off elements.
+  Value *PassThruOperand = IsMasked ?
+(DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC) ?
+  llvm::PoisonValue::get(ResultType) : Ops[NF + 1] :
+(DefaultPolicy == TAIL_AGNOSTIC) ?
+  llvm::PoisonValue::get(ResultType) : Ops[NF];
+  unsigned PtrOperandIdx = IsMasked ?
+(DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC) ? NF + 1 : 2 * NF + 1 :
+(DefaultPolicy == TAIL_AGNOSTIC) ? NF : 2 * NF;
+  Value *PtrOperand = Ops[PtrOperandIdx];
+  Value *VLOperand = Ops[PtrOperandIdx + 1];
+  Operands.append(NF, PassThruOperand);
+  Operands.push_back(PtrOperand);
+  if (IsMasked)
+Operands.push_back(Ops[NF]);
+  Operands.push_back(VLOperand);
+  if (IsMasked)
 Operands.push_back(ConstantInt::get(Ops.back()->getType(), DefaultPolicy));
-assert(Operands.size() == NF + 4);
-  } else {
-// TA builtin: (val0 address, val1 address, ..., ptr, vl)
-// TU builtin: (val0 address, ..., passthru0, ..., ptr, vl)
-// intrinsic: (passthru0, passthru1, ..., ptr, vl)
-if (DefaultPolicy == TAIL_AGNOSTIC) {
-  Operands.append(NF, llvm::PoisonValue::get(ResultType));
-  Operands.push_back(Ops[NF]);
-  Operands.push_back(Ops[NF + 1]);
-} else {
-  for (unsigned I = 0; I < NF; ++I)
-Operands.push_back(Ops[NF + I]);
-  Operands.push_back(Ops[2 * NF]);
-  Operands.push_back(Ops[2 * NF + 1]);
-}
-  }
+
   llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
   llvm::Value *LoadValue = Builder.CreateCall(F, Operands, "");
   clang::CharUnits Align =
@@ -918,45 +909,31 @@
   ResultType = ConvertType(E->getArg(0)->getType()->getPointeeType());
   IntrinsicTypes = {ResultType, Ops.back()->getType()};
   SmallVector Operands;
-  Value *NewVL;
 
-  if (IsMasked) {
-// TAMA builtin: (val0 address, ..., mask, ptr, new_vl, vl)
-// builtin: (val0 address, ..., mask, maskedoff0, ..., ptr, new_vl, vl)
-// intrinsic: (maskedoff0, ..., ptr, mask, vl)
-if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC) {
-  Operands.append(NF, llvm::PoisonValue::get(ResultType));
-  Operands.push_back(Ops[NF + 1]);
-  Operands.push_back(Ops[NF]);
-  Operands.push_back(Ops[NF + 3]);
-  NewVL = Ops[NF + 2];
-} else {
-  for (unsigned I = 0; I < NF; ++I)
-Operands.push_back(Ops[NF + I + 1]);
-  Operands.push_back(Ops[2 * NF + 1]);
-  Operands.push_back(Ops[NF]);
-  Operands.push_back(Ops[2 * NF + 3]);
-  NewVL = Ops[2 * NF + 2];
-}
+  // Intrinsic is in the form of below,
+  // Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Mask, NewVL, VL, Policy)
+  // Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, NewVL, VL)
+  // where the Vectors is poison when the policy behavior allows us to not care
+  // about any masked-off elements.
+  Value *PassThruOperand = IsMasked ?
+(DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC) ?
+  llvm::PoisonValue::get(ResultType) : Ops[NF + 1] :
+(DefaultPolicy == TAIL_AGNOSTIC) ?
+  llvm::PoisonValue::get(ResultType) : Ops[NF];
+   

[PATCH] D140389: [NFC][Clang][RISCV] Rename data member 'DefaultPolicy' to 'PolicyAttrs'

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 485310.
eopXD added a comment.

Rebae to latest main.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140389/new/

https://reviews.llvm.org/D140389

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -163,14 +163,14 @@
 OS << "  ID = Intrinsic::riscv_" + RVVI->getIRName() + ";\n";
   if (RVVI->getNF() >= 2)
 OS << "  NF = " + utostr(RVVI->getNF()) + ";\n";
-  // We had initialized DefaultPolicy as TU/TUMU in CodeGen function.
-  if (!RVVI->getDefaultPolicy().isTUPolicy() &&
-  !RVVI->getDefaultPolicy().isTUMUPolicy() && !RVVI->hasPassthruOperand() &&
+  // We had initialized PolicyAttrs as TU/TUMU in CodeGen function.
+  if (!RVVI->getPolicyAttrs().isTUPolicy() &&
+  !RVVI->getPolicyAttrs().isTUMUPolicy() && !RVVI->hasPassthruOperand() &&
   !RVVI->hasManualCodegen() && RVVI->hasVL())
-OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
+OS << "  PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n";
 
   if (RVVI->hasManualCodegen()) {
-OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
+OS << "  PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n";
 if (RVVI->isMasked())
   OS << "IsMasked = true;\n";
 else
@@ -195,13 +195,12 @@
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);\n";
   if (RVVI->hasPolicyOperand())
 OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(),"
-  " DefaultPolicy));\n";
-  if (RVVI->hasMaskedOffOperand() &&
-  RVVI->getDefaultPolicy().isTAMAPolicy())
+  " PolicyAttrs));\n";
+  if (RVVI->hasMaskedOffOperand() && RVVI->getPolicyAttrs().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   // Masked reduction cases.
   if (!RVVI->hasMaskedOffOperand() && RVVI->hasPassthruOperand() &&
-  RVVI->getDefaultPolicy().isTAMAPolicy())
+  RVVI->getPolicyAttrs().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
 } else {
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end());\n";
@@ -209,9 +208,8 @@
   } else {
 if (RVVI->hasPolicyOperand())
   OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(), "
-"DefaultPolicy));\n";
-else if (RVVI->hasPassthruOperand() &&
- RVVI->getDefaultPolicy().isTAPolicy())
+"PolicyAttrs));\n";
+else if (RVVI->hasPassthruOperand() && RVVI->getPolicyAttrs().isTAPolicy())
   OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   }
 
@@ -448,7 +446,7 @@
   llvm::stable_sort(Defs, [](const std::unique_ptr &A,
  const std::unique_ptr &B) {
 if (A->getIRName() == B->getIRName())
-  return (A->getDefaultPolicy() < B->getDefaultPolicy());
+  return (A->getPolicyAttrs() < B->getPolicyAttrs());
 return (A->getIRName() < B->getIRName());
   });
 
@@ -462,7 +460,7 @@
 StringRef CurIRName = Def->getIRName();
 if (CurIRName != PrevDef->getIRName() ||
 (Def->getManualCodegen() != PrevDef->getManualCodegen()) ||
-(Def->getDefaultPolicy() != PrevDef->getDefaultPolicy())) {
+(Def->getPolicyAttrs() != PrevDef->getPolicyAttrs())) {
   emitCodeGenSwitchBody(PrevDef, OS);
 }
 PrevDef = Def.get();
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -848,12 +848,11 @@
 bool SupportOverloading, bool HasBuiltinAlias, StringRef ManualCodegen,
 const RVVTypes &OutInTypes, const std::vector &NewIntrinsicTypes,
 const std::vector &RequiredFeatures, unsigned NF,
-Policy NewDefaultPolicy, bool IsPrototypeDefaultTU)
+Policy NewPolicyAttrs, bool IsPrototypeDefaultTU)
 : IRName(IRName), IsMasked(IsMasked),
   HasMaskedOffOperand(HasMaskedOffOperand), HasVL(HasVL), Scheme(Scheme),
   SupportOverloading(SupportOverloading), HasBuiltinAlias(HasBuiltinAlias),
-  ManualCodegen(ManualCodegen.str()), NF(NF),
-  DefaultPolicy(NewDefaultPolicy) {
+  ManualCodegen(ManualCodegen.str()), NF(NF), PolicyAttrs(NewPolicyAttrs) {
 
   // Init BuiltinName, Name and OverloadedName
   BuiltinName = NewName.str();
@@ -868,7 +867,7 @@
 OverloadedName += "_" + OverloadedSuffix.str();
 
   updateNamesAndPolicy(IsMasked, hasPolicy(), IsPrototypeDefaul

[PATCH] D140389: [NFC][Clang][RISCV] Rename data member 'DefaultPolicy' to 'PolicyAttrs'

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 485311.
eopXD added a comment.

Change: Recover mis-deleted lines.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140389/new/

https://reviews.llvm.org/D140389

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -163,14 +163,14 @@
 OS << "  ID = Intrinsic::riscv_" + RVVI->getIRName() + ";\n";
   if (RVVI->getNF() >= 2)
 OS << "  NF = " + utostr(RVVI->getNF()) + ";\n";
-  // We had initialized DefaultPolicy as TU/TUMU in CodeGen function.
-  if (!RVVI->getDefaultPolicy().isTUPolicy() &&
-  !RVVI->getDefaultPolicy().isTUMUPolicy() && !RVVI->hasPassthruOperand() &&
+  // We had initialized PolicyAttrs as TU/TUMU in CodeGen function.
+  if (!RVVI->getPolicyAttrs().isTUPolicy() &&
+  !RVVI->getPolicyAttrs().isTUMUPolicy() && !RVVI->hasPassthruOperand() &&
   !RVVI->hasManualCodegen() && RVVI->hasVL())
-OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
+OS << "  PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n";
 
   if (RVVI->hasManualCodegen()) {
-OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
+OS << "  PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n";
 if (RVVI->isMasked())
   OS << "IsMasked = true;\n";
 else
@@ -195,13 +195,12 @@
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);\n";
   if (RVVI->hasPolicyOperand())
 OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(),"
-  " DefaultPolicy));\n";
-  if (RVVI->hasMaskedOffOperand() &&
-  RVVI->getDefaultPolicy().isTAMAPolicy())
+  " PolicyAttrs));\n";
+  if (RVVI->hasMaskedOffOperand() && RVVI->getPolicyAttrs().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   // Masked reduction cases.
   if (!RVVI->hasMaskedOffOperand() && RVVI->hasPassthruOperand() &&
-  RVVI->getDefaultPolicy().isTAMAPolicy())
+  RVVI->getPolicyAttrs().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
 } else {
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end());\n";
@@ -209,9 +208,8 @@
   } else {
 if (RVVI->hasPolicyOperand())
   OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(), "
-"DefaultPolicy));\n";
-else if (RVVI->hasPassthruOperand() &&
- RVVI->getDefaultPolicy().isTAPolicy())
+"PolicyAttrs));\n";
+else if (RVVI->hasPassthruOperand() && RVVI->getPolicyAttrs().isTAPolicy())
   OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   }
 
@@ -448,7 +446,7 @@
   llvm::stable_sort(Defs, [](const std::unique_ptr &A,
  const std::unique_ptr &B) {
 if (A->getIRName() == B->getIRName())
-  return (A->getDefaultPolicy() < B->getDefaultPolicy());
+  return (A->getPolicyAttrs() < B->getPolicyAttrs());
 return (A->getIRName() < B->getIRName());
   });
 
@@ -462,7 +460,7 @@
 StringRef CurIRName = Def->getIRName();
 if (CurIRName != PrevDef->getIRName() ||
 (Def->getManualCodegen() != PrevDef->getManualCodegen()) ||
-(Def->getDefaultPolicy() != PrevDef->getDefaultPolicy())) {
+(Def->getPolicyAttrs() != PrevDef->getPolicyAttrs())) {
   emitCodeGenSwitchBody(PrevDef, OS);
 }
 PrevDef = Def.get();
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -848,12 +848,11 @@
 bool SupportOverloading, bool HasBuiltinAlias, StringRef ManualCodegen,
 const RVVTypes &OutInTypes, const std::vector &NewIntrinsicTypes,
 const std::vector &RequiredFeatures, unsigned NF,
-Policy NewDefaultPolicy, bool IsPrototypeDefaultTU)
+Policy NewPolicyAttrs, bool IsPrototypeDefaultTU)
 : IRName(IRName), IsMasked(IsMasked),
   HasMaskedOffOperand(HasMaskedOffOperand), HasVL(HasVL), Scheme(Scheme),
   SupportOverloading(SupportOverloading), HasBuiltinAlias(HasBuiltinAlias),
-  ManualCodegen(ManualCodegen.str()), NF(NF),
-  DefaultPolicy(NewDefaultPolicy) {
+  ManualCodegen(ManualCodegen.str()), NF(NF), PolicyAttrs(NewPolicyAttrs) {
 
   // Init BuiltinName, Name and OverloadedName
   BuiltinName = NewName.str();
@@ -868,7 +867,7 @@
 OverloadedName += "_" + OverloadedSuffix.str();
 
   updateNamesAndPolicy(IsMasked, hasPolicy(), IsPr

[PATCH] D140389: [NFC][Clang][RISCV] Rename data member 'DefaultPolicy' to 'PolicyAttrs'

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 485312.
eopXD added a comment.

Recover mis-deleted lines.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140389/new/

https://reviews.llvm.org/D140389

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -163,14 +163,14 @@
 OS << "  ID = Intrinsic::riscv_" + RVVI->getIRName() + ";\n";
   if (RVVI->getNF() >= 2)
 OS << "  NF = " + utostr(RVVI->getNF()) + ";\n";
-  // We had initialized DefaultPolicy as TU/TUMU in CodeGen function.
-  if (!RVVI->getDefaultPolicy().isTUPolicy() &&
-  !RVVI->getDefaultPolicy().isTUMUPolicy() && !RVVI->hasPassthruOperand() &&
+  // We had initialized PolicyAttrs as TU/TUMU in CodeGen function.
+  if (!RVVI->getPolicyAttrs().isTUPolicy() &&
+  !RVVI->getPolicyAttrs().isTUMUPolicy() && !RVVI->hasPassthruOperand() &&
   !RVVI->hasManualCodegen() && RVVI->hasVL())
-OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
+OS << "  PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n";
 
   if (RVVI->hasManualCodegen()) {
-OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
+OS << "  PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n";
 if (RVVI->isMasked())
   OS << "IsMasked = true;\n";
 else
@@ -195,13 +195,12 @@
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);\n";
   if (RVVI->hasPolicyOperand())
 OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(),"
-  " DefaultPolicy));\n";
-  if (RVVI->hasMaskedOffOperand() &&
-  RVVI->getDefaultPolicy().isTAMAPolicy())
+  " PolicyAttrs));\n";
+  if (RVVI->hasMaskedOffOperand() && RVVI->getPolicyAttrs().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   // Masked reduction cases.
   if (!RVVI->hasMaskedOffOperand() && RVVI->hasPassthruOperand() &&
-  RVVI->getDefaultPolicy().isTAMAPolicy())
+  RVVI->getPolicyAttrs().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
 } else {
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end());\n";
@@ -209,9 +208,8 @@
   } else {
 if (RVVI->hasPolicyOperand())
   OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(), "
-"DefaultPolicy));\n";
-else if (RVVI->hasPassthruOperand() &&
- RVVI->getDefaultPolicy().isTAPolicy())
+"PolicyAttrs));\n";
+else if (RVVI->hasPassthruOperand() && RVVI->getPolicyAttrs().isTAPolicy())
   OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   }
 
@@ -448,7 +446,7 @@
   llvm::stable_sort(Defs, [](const std::unique_ptr &A,
  const std::unique_ptr &B) {
 if (A->getIRName() == B->getIRName())
-  return (A->getDefaultPolicy() < B->getDefaultPolicy());
+  return (A->getPolicyAttrs() < B->getPolicyAttrs());
 return (A->getIRName() < B->getIRName());
   });
 
@@ -462,7 +460,7 @@
 StringRef CurIRName = Def->getIRName();
 if (CurIRName != PrevDef->getIRName() ||
 (Def->getManualCodegen() != PrevDef->getManualCodegen()) ||
-(Def->getDefaultPolicy() != PrevDef->getDefaultPolicy())) {
+(Def->getPolicyAttrs() != PrevDef->getPolicyAttrs())) {
   emitCodeGenSwitchBody(PrevDef, OS);
 }
 PrevDef = Def.get();
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -848,12 +848,11 @@
 bool SupportOverloading, bool HasBuiltinAlias, StringRef ManualCodegen,
 const RVVTypes &OutInTypes, const std::vector &NewIntrinsicTypes,
 const std::vector &RequiredFeatures, unsigned NF,
-Policy NewDefaultPolicy, bool IsPrototypeDefaultTU)
+Policy NewPolicyAttrs, bool IsPrototypeDefaultTU)
 : IRName(IRName), IsMasked(IsMasked),
   HasMaskedOffOperand(HasMaskedOffOperand), HasVL(HasVL), Scheme(Scheme),
   SupportOverloading(SupportOverloading), HasBuiltinAlias(HasBuiltinAlias),
-  ManualCodegen(ManualCodegen.str()), NF(NF),
-  DefaultPolicy(NewDefaultPolicy) {
+  ManualCodegen(ManualCodegen.str()), NF(NF), PolicyAttrs(NewPolicyAttrs) {
 
   // Init BuiltinName, Name and OverloadedName
   BuiltinName = NewName.str();
@@ -868,7 +867,7 @@
 OverloadedName += "_" + OverloadedSuffix.str();
 
   updateNamesAndPolicy(IsMasked, hasPolicy(), IsPrototypeD

[PATCH] D140389: [NFC][Clang][RISCV] Rename data member 'DefaultPolicy' to 'PolicyAttrs'

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG1deb6bce8931: [NFC][Clang][RISCV] Rename data member 
'DefaultPolicy' to 'PolicyAttrs' (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140389/new/

https://reviews.llvm.org/D140389

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -163,14 +163,14 @@
 OS << "  ID = Intrinsic::riscv_" + RVVI->getIRName() + ";\n";
   if (RVVI->getNF() >= 2)
 OS << "  NF = " + utostr(RVVI->getNF()) + ";\n";
-  // We had initialized DefaultPolicy as TU/TUMU in CodeGen function.
-  if (!RVVI->getDefaultPolicy().isTUPolicy() &&
-  !RVVI->getDefaultPolicy().isTUMUPolicy() && !RVVI->hasPassthruOperand() &&
+  // We had initialized PolicyAttrs as TU/TUMU in CodeGen function.
+  if (!RVVI->getPolicyAttrs().isTUPolicy() &&
+  !RVVI->getPolicyAttrs().isTUMUPolicy() && !RVVI->hasPassthruOperand() &&
   !RVVI->hasManualCodegen() && RVVI->hasVL())
-OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
+OS << "  PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n";
 
   if (RVVI->hasManualCodegen()) {
-OS << "  DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
+OS << "  PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n";
 if (RVVI->isMasked())
   OS << "IsMasked = true;\n";
 else
@@ -195,13 +195,12 @@
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);\n";
   if (RVVI->hasPolicyOperand())
 OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(),"
-  " DefaultPolicy));\n";
-  if (RVVI->hasMaskedOffOperand() &&
-  RVVI->getDefaultPolicy().isTAMAPolicy())
+  " PolicyAttrs));\n";
+  if (RVVI->hasMaskedOffOperand() && RVVI->getPolicyAttrs().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   // Masked reduction cases.
   if (!RVVI->hasMaskedOffOperand() && RVVI->hasPassthruOperand() &&
-  RVVI->getDefaultPolicy().isTAMAPolicy())
+  RVVI->getPolicyAttrs().isTAMAPolicy())
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
 } else {
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end());\n";
@@ -209,9 +208,8 @@
   } else {
 if (RVVI->hasPolicyOperand())
   OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(), "
-"DefaultPolicy));\n";
-else if (RVVI->hasPassthruOperand() &&
- RVVI->getDefaultPolicy().isTAPolicy())
+"PolicyAttrs));\n";
+else if (RVVI->hasPassthruOperand() && RVVI->getPolicyAttrs().isTAPolicy())
   OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   }
 
@@ -448,7 +446,7 @@
   llvm::stable_sort(Defs, [](const std::unique_ptr &A,
  const std::unique_ptr &B) {
 if (A->getIRName() == B->getIRName())
-  return (A->getDefaultPolicy() < B->getDefaultPolicy());
+  return (A->getPolicyAttrs() < B->getPolicyAttrs());
 return (A->getIRName() < B->getIRName());
   });
 
@@ -462,7 +460,7 @@
 StringRef CurIRName = Def->getIRName();
 if (CurIRName != PrevDef->getIRName() ||
 (Def->getManualCodegen() != PrevDef->getManualCodegen()) ||
-(Def->getDefaultPolicy() != PrevDef->getDefaultPolicy())) {
+(Def->getPolicyAttrs() != PrevDef->getPolicyAttrs())) {
   emitCodeGenSwitchBody(PrevDef, OS);
 }
 PrevDef = Def.get();
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -848,12 +848,11 @@
 bool SupportOverloading, bool HasBuiltinAlias, StringRef ManualCodegen,
 const RVVTypes &OutInTypes, const std::vector &NewIntrinsicTypes,
 const std::vector &RequiredFeatures, unsigned NF,
-Policy NewDefaultPolicy, bool IsPrototypeDefaultTU)
+Policy NewPolicyAttrs, bool IsPrototypeDefaultTU)
 : IRName(IRName), IsMasked(IsMasked),
   HasMaskedOffOperand(HasMaskedOffOperand), HasVL(HasVL), Scheme(Scheme),
   SupportOverloading(SupportOverloading), HasBuiltinAlias(HasBuiltinAlias),
-  ManualCodegen(ManualCodegen.str()), NF(NF),
-  DefaultPolicy(NewDefaultPolicy) {
+  ManualCodegen(ManualCodegen.str()), NF(NF), PolicyAttrs(NewPolicyAttrs) {
 
   // Init BuiltinName, Name and OverloadedName
   BuiltinName = NewName.str();
@@ -868,7 +867,7 @@
 Over

[PATCH] D140686: [Clang][RISCV] Update operand order for vmerge and vcompress

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
Herald added subscribers: sunshaoce, VincentWu, vkmr, frasercrmck, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

Old:
vint32m1_t vmerge_vvm_i32m1 (vbool32_t mask, vint32m1_t op1, vint32m1_t op2, 
size_t vl);
New:
vint32m1_t vmerge_vvm_i32m1 (vint32m1_t op1, vint32m1_t op2, vbool32_t 
selector, size_t vl);

Old:
vint32m1_t vcompress_vm_i32m1 (vbool32_t mask, vint32m1_t src, size_t vl);
New:
vint32m1_t vcompress_vm_i32m1 (vint32m1_t src, vbool32_t selector, size_t vl);

Address issues:
riscv-non-isa/rvv-intrinsic-doc#140
riscv-non-isa/rvv-intrinsic-doc#167


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140686

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c

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[PATCH] D140686: [WIP][Clang][RISCV] Update operand order for vmerge and vcompress

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD added a comment.

This patch is not ready yet since currently we don't have a pull request under 
rvv-intrinsic-doc to match to this. The pull request will be created in the 
near future.




Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c:514
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  
@llvm.riscv.vcompress.nxv1i32.i64( poison,  
[[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
-// CHECK-RV64-NEXT:ret  [[TMP0]]

The change from `poison` to `undef` is due to value filled in back in the 
default under `RISCVVEmitter.cpp`. I will have another patch amend this and 
rebase this patch upon the fix.


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[PATCH] D140687: [Clang][RISCV] Use poison instead of undef

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
eopXD added reviewers: kito-cheng, nlopes, craig.topper, khchen.
Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140687

Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmflt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfne.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmseq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmslt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsne.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul-eew64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredxor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c
  clang/test

[PATCH] D140678: [RISCV][WIP] Use SmallVector::append to replace some for loops in intrinsic creation. NFC

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD accepted this revision.
eopXD added a comment.
This revision is now accepted and ready to land.

Thank you for the patch. We can land this and then I have D140662 
 rebase upon it.


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[PATCH] D140686: [WIP][Clang][RISCV] Update operand order for vmerge and vcompress

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 485363.
eopXD added a comment.

Update code, recovered ManualCodeGen for vcompress and vmerge.
Deleted the `std::rotate` since it is not needed now due to the operand order 
change.


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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c

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[PATCH] D140686: [WIP][Clang][RISCV] Update operand order for vmerge and vcompress

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD added inline comments.



Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c:514
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  
@llvm.riscv.vcompress.nxv1i32.i64( poison,  
[[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
-// CHECK-RV64-NEXT:ret  [[TMP0]]

eopXD wrote:
> The change from `poison` to `undef` is due to value filled in back in the 
> default under `RISCVVEmitter.cpp`. I will have another patch amend this and 
> rebase this patch upon the fix.
Turns out I should fix the `ManaulCodeGen`. Fixed in latest update.


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[PATCH] D140687: [Clang][RISCV] Use poison instead of undef

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 485371.
eopXD added a comment.

Update leftout test cases.


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Files:
  clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmflt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfne.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmseq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmslt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsne.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul-eew64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredxor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul-eew64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c
  c

[PATCH] D140687: [Clang][RISCV] Use poison instead of undef

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG1972fb23cb36: [Clang][RISCV] Use poison instead of undef 
(authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140687/new/

https://reviews.llvm.org/D140687

Files:
  clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmflt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfne.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmseq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmslt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsne.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul-eew64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredxor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul-eew64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overl

[PATCH] D140662: [NFC][Clang][RISCV] Reduce boilerplate when determining prototype for segment loads

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 485589.
eopXD added a comment.

Update code based on landing of D140678 .

The motivation of this NFC patch comes from the struggle while I was tracing 
through them. I think the scattered comments of boilerplates with only 
something slightly different makes the code hard to read, that is why I am 
gathering the comments together into a sole paragraph. The multi-level 
if-statement has duplicated actions and gets me confused from time-to-time.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140662/new/

https://reviews.llvm.org/D140662

Files:
  clang/include/clang/Basic/riscv_vector.td

Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -812,6 +812,47 @@
 }
 
 defvar NFList = [2, 3, 4, 5, 6, 7, 8];
+/*
+Segment load builtin has different variants.
+
+Segment unit-stride load builtin,
+(Address0, ..., Address{NF - 1}, mask, Ptr, VL)
+(Address0, ..., Address{NF - 1}, mask, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, VL)
+Segment unit-stride fault-only-first load builtin,
+(Address0, ..., Address{NF - 1}, mask, Ptr, NewVL, VL)
+(Address0, ..., Address{NF - 1}, mask, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, NewVL, VL)
+Segment strided load builtin,
+(Address0, ..., Address{NF - 1}, mask, Ptr, Stride, VL)
+(Address0, ..., Address{NF - 1}, mask, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, Stride, VL)
+Segment indexed load builtin,
+(Address0, ..., Address{NF - 1}, mask, Ptr, Idx, VL)
+(Address0, ..., Address{NF - 1}, mask, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, Idx, VL)
+
+The Maskedoff parameter(s) exist when at least one of the policy behaviors
+(vta or vma) implies undisturbed.
+
+Segment load intrinsics has different variants similar to their builtins.
+
+Segment unit-stride load intrinsic,
+  Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Mask, VL, Policy)
+  Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, VL)
+Segment unit-stride fault-only-first load intrinsic,
+  Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Mask, VL, Policy)
+  Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, VL)
+Segment strided load intrinsic,
+  Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Stride, Mask, VL, Policy)
+  Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, Stride, VL)
+Segment indexed load intrinsic,
+  Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Index, Mask, VL, Policy)
+  Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, Index, VL)
+
+The Vector(s) is poison when the policy behavior allows us to not care
+about any masked-off elements.
+*/
 
 class PVString {
   string S =
@@ -842,36 +883,30 @@
 {
   ResultType = ConvertType(E->getArg(0)->getType()->getPointeeType());
   IntrinsicTypes = {ResultType, Ops.back()->getType()};
-  SmallVector Operands;
-  if (IsMasked) {
-// TAMA builtin: (val0 address, ..., mask, ptr, vl)
-// builtin: (val0 address, ..., mask, maskedoff0, ..., ptr, vl)
-// intrinsic: (maskedoff0, ..., ptr, mask, vl)
-if (PolicyAttrs == TAIL_AGNOSTIC_MASK_AGNOSTIC) {
-  Operands.append(NF, llvm::PoisonValue::get(ResultType));
-  Operands.push_back(Ops[NF + 1]);
-  Operands.push_back(Ops[NF]);
-  Operands.push_back(Ops[NF + 2]);
-} else {
+  SmallVector Operands;
+
+  // Please refer to comment under 'defvar NFList' in this file
+  if ((IsMasked && PolicyAttrs == TAIL_AGNOSTIC_MASK_AGNOSTIC) ||
+  (!IsMasked && PolicyAttrs == TAIL_AGNOSTIC))
+Operands.append(NF, llvm::PoisonValue::get(ResultType));
+  else {
+if (IsMasked)
   Operands.append(Ops.begin() + NF + 1, Ops.begin() + 2 * NF + 1);
-  Operands.push_back(Ops[2 * NF + 1]);
-  Operands.push_back(Ops[NF]);
-  Operands.push_back(Ops[2 * NF + 2]);
-}
-Operands.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
-assert(Operands.size() == NF + 4);
-  } else {
-// TA builtin: (val0 address, val1 address, ..., ptr, vl)
-// TU builtin: (val0 address, ..., passthru0, ..., ptr, vl)
-// intrinsic: (passthru0, passthru1, ..., ptr, vl)
-if (PolicyAttrs == TAIL_AGNOSTIC) {
-  Operands.append(NF, llvm::PoisonValue::get(ResultType));
-  Operands.push_back(Ops[NF]);
-  Operands.push_back(Ops[NF + 1]);
-} else {
-  Operands.append(Ops.begin() + NF, Ops.begin() + 2 * NF + 2);
-}
+else // Unmasked
+  Operands.append(Ops.begin() + NF, Ops.begin() + 2 * NF);
   }
+  unsigned PtrOperandIdx = IsMasked ?
+(PolicyAttrs == TAIL_AGNOSTIC_MASK_AGNOSTIC) ? NF + 1 : 2 * NF + 1 :
+(PolicyAttrs == TAIL_AGNOSTIC) ? NF : 2 * NF;
+  Value *PtrOperand = Ops[PtrOperandIdx];
+  Value *VLOperand = Ops[

[PATCH] D140662: [NFC][Clang][RISCV] Reduce boilerplate when determining prototype for segment loads

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 485604.
eopXD marked 2 inline comments as done.
eopXD edited the summary of this revision.
eopXD added a comment.

Update comment section for segment load.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140662/new/

https://reviews.llvm.org/D140662

Files:
  clang/include/clang/Basic/riscv_vector.td

Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -812,6 +812,80 @@
 }
 
 defvar NFList = [2, 3, 4, 5, 6, 7, 8];
+/*
+A segment load builtin has different variants.
+
+Therefore a segment unit-stride load builtin can have 4 variants,
+1. When unmasked and the policies are all specified as agnostic:
+  (Address0, ..., Address{NF - 1}, Ptr, VL)
+2. When masked and the policies are all specified as agnostic:
+(Address0, ..., Address{NF - 1}, Mask, Ptr, VL)
+3. When unmasked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, VL)
+4. When masked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Mask, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, VL)
+
+Other variants of segment load builtin share the same structure, but they
+have their own extra parameter.
+
+The segment unit-stride fault-only-first load builtin has a 'NewVL'
+operand after the 'Ptr' operand.
+1. When unmasked and the policies are all specified as agnostic:
+  (Address0, ..., Address{NF - 1}, Ptr, NewVL, VL)
+2. When masked and the policies are all specified as agnostic:
+(Address0, ..., Address{NF - 1}, Mask, Ptr, NewVL, VL)
+3. When unmasked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, NewVL, VL)
+4. When masked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Mask, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, NewVL, VL)
+
+The segment strided load builtin has a 'Stride' operand after the 'Ptr'
+operand.
+1. When unmasked and the policies are all specified as agnostic:
+  (Address0, ..., Address{NF - 1}, Ptr, Stride, VL)
+2. When masked and the policies are all specified as agnostic:
+(Address0, ..., Address{NF - 1}, Mask, Ptr, Stride, VL)
+3. When unmasked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, Stride, VL)
+4. When masked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Mask, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, Stride, VL)
+
+The segment indexed load builtin has a 'Idx' operand after the 'Ptr' operand.
+1. When unmasked and the policies are all specified as agnostic:
+  (Address0, ..., Address{NF - 1}, Ptr, Idx, VL)
+2. When masked and the policies are all specified as agnostic:
+(Address0, ..., Address{NF - 1}, Mask, Ptr, Idx, VL)
+3. When unmasked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, Idx, VL)
+4. When masked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Mask, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, Idx, VL)
+
+Segment load intrinsics has different variants similar to their builtins.
+
+Segment unit-stride load intrinsic,
+  Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Mask, VL, Policy)
+  Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, VL)
+Segment unit-stride fault-only-first load intrinsic,
+  Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Mask, VL, Policy)
+  Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, VL)
+Segment strided load intrinsic,
+  Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Stride, Mask, VL, Policy)
+  Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, Stride, VL)
+Segment indexed load intrinsic,
+  Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Index, Mask, VL, Policy)
+  Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, Index, VL)
+
+The Vector(s) is poison when the policy behavior allows us to not care
+about any masked-off elements.
+*/
 
 class PVString {
   string S =
@@ -842,36 +916,30 @@
 {
   ResultType = ConvertType(E->getArg(0)->getType()->getPointeeType());
   IntrinsicTypes = {ResultType, Ops.back()->getType()};
-  SmallVector Operands;
-  if (IsMasked) {
-// TAMA builtin: (val0 address, ..., mask, ptr, vl)
-// builtin: (val0 address, ..., mask, maskedoff0, ..., ptr, vl)
-// intrinsic: (maskedoff0, ..., ptr, mask, vl)
-if (PolicyAttrs == TAIL_AGNOSTIC_MASK_AGNOSTIC) {
-  Operands.append(NF, llvm::PoisonValue::get(ResultType));
-  Operands.push_back(Ops[NF + 1]);
-  Operands.push_back(Ops[NF]);
-  Operands.push_back(Ops[NF + 2]);
-} else {
+  SmallVector Operands;
+
+  // Please refer to 

[PATCH] D140662: [NFC][Clang][RISCV] Reduce boilerplate when determining prototype for segment loads

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 485606.
eopXD added a comment.

Update comment section: remove mis-indented indents.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140662/new/

https://reviews.llvm.org/D140662

Files:
  clang/include/clang/Basic/riscv_vector.td

Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -812,6 +812,80 @@
 }
 
 defvar NFList = [2, 3, 4, 5, 6, 7, 8];
+/*
+A segment load builtin has different variants.
+
+Therefore a segment unit-stride load builtin can have 4 variants,
+1. When unmasked and the policies are all specified as agnostic:
+(Address0, ..., Address{NF - 1}, Ptr, VL)
+2. When masked and the policies are all specified as agnostic:
+(Address0, ..., Address{NF - 1}, Mask, Ptr, VL)
+3. When unmasked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, VL)
+4. When masked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Mask, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, VL)
+
+Other variants of segment load builtin share the same structure, but they
+have their own extra parameter.
+
+The segment unit-stride fault-only-first load builtin has a 'NewVL'
+operand after the 'Ptr' operand.
+1. When unmasked and the policies are all specified as agnostic:
+(Address0, ..., Address{NF - 1}, Ptr, NewVL, VL)
+2. When masked and the policies are all specified as agnostic:
+(Address0, ..., Address{NF - 1}, Mask, Ptr, NewVL, VL)
+3. When unmasked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, NewVL, VL)
+4. When masked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Mask, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, NewVL, VL)
+
+The segment strided load builtin has a 'Stride' operand after the 'Ptr'
+operand.
+1. When unmasked and the policies are all specified as agnostic:
+(Address0, ..., Address{NF - 1}, Ptr, Stride, VL)
+2. When masked and the policies are all specified as agnostic:
+(Address0, ..., Address{NF - 1}, Mask, Ptr, Stride, VL)
+3. When unmasked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, Stride, VL)
+4. When masked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Mask, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, Stride, VL)
+
+The segment indexed load builtin has a 'Idx' operand after the 'Ptr' operand.
+1. When unmasked and the policies are all specified as agnostic:
+(Address0, ..., Address{NF - 1}, Ptr, Idx, VL)
+2. When masked and the policies are all specified as agnostic:
+(Address0, ..., Address{NF - 1}, Mask, Ptr, Idx, VL)
+3. When unmasked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, Idx, VL)
+4. When masked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Mask, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, Idx, VL)
+
+Segment load intrinsics has different variants similar to their builtins.
+
+Segment unit-stride load intrinsic,
+  Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Mask, VL, Policy)
+  Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, VL)
+Segment unit-stride fault-only-first load intrinsic,
+  Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Mask, VL, Policy)
+  Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, VL)
+Segment strided load intrinsic,
+  Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Stride, Mask, VL, Policy)
+  Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, Stride, VL)
+Segment indexed load intrinsic,
+  Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Index, Mask, VL, Policy)
+  Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, Index, VL)
+
+The Vector(s) is poison when the policy behavior allows us to not care
+about any masked-off elements.
+*/
 
 class PVString {
   string S =
@@ -842,36 +916,30 @@
 {
   ResultType = ConvertType(E->getArg(0)->getType()->getPointeeType());
   IntrinsicTypes = {ResultType, Ops.back()->getType()};
-  SmallVector Operands;
-  if (IsMasked) {
-// TAMA builtin: (val0 address, ..., mask, ptr, vl)
-// builtin: (val0 address, ..., mask, maskedoff0, ..., ptr, vl)
-// intrinsic: (maskedoff0, ..., ptr, mask, vl)
-if (PolicyAttrs == TAIL_AGNOSTIC_MASK_AGNOSTIC) {
-  Operands.append(NF, llvm::PoisonValue::get(ResultType));
-  Operands.push_back(Ops[NF + 1]);
-  Operands.push_back(Ops[NF]);
-  Operands.push_back(Ops[NF + 2]);
-} else {
+  SmallVector Operands;
+
+  // Please refer to comment under 'defvar NFList' in this file
+  if ((IsMasked && PolicyAttrs 

[PATCH] D140662: [NFC][Clang][RISCV] Reduce boilerplate when determining prototype for segment loads

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf2bec8702688: [NFC][Clang][RISCV] Reduce boilerplate when 
determining prototype for segment… (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140662/new/

https://reviews.llvm.org/D140662

Files:
  clang/include/clang/Basic/riscv_vector.td

Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -812,6 +812,80 @@
 }
 
 defvar NFList = [2, 3, 4, 5, 6, 7, 8];
+/*
+A segment load builtin has different variants.
+
+Therefore a segment unit-stride load builtin can have 4 variants,
+1. When unmasked and the policies are all specified as agnostic:
+(Address0, ..., Address{NF - 1}, Ptr, VL)
+2. When masked and the policies are all specified as agnostic:
+(Address0, ..., Address{NF - 1}, Mask, Ptr, VL)
+3. When unmasked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, VL)
+4. When masked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Mask, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, VL)
+
+Other variants of segment load builtin share the same structure, but they
+have their own extra parameter.
+
+The segment unit-stride fault-only-first load builtin has a 'NewVL'
+operand after the 'Ptr' operand.
+1. When unmasked and the policies are all specified as agnostic:
+(Address0, ..., Address{NF - 1}, Ptr, NewVL, VL)
+2. When masked and the policies are all specified as agnostic:
+(Address0, ..., Address{NF - 1}, Mask, Ptr, NewVL, VL)
+3. When unmasked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, NewVL, VL)
+4. When masked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Mask, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, NewVL, VL)
+
+The segment strided load builtin has a 'Stride' operand after the 'Ptr'
+operand.
+1. When unmasked and the policies are all specified as agnostic:
+(Address0, ..., Address{NF - 1}, Ptr, Stride, VL)
+2. When masked and the policies are all specified as agnostic:
+(Address0, ..., Address{NF - 1}, Mask, Ptr, Stride, VL)
+3. When unmasked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, Stride, VL)
+4. When masked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Mask, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, Stride, VL)
+
+The segment indexed load builtin has a 'Idx' operand after the 'Ptr' operand.
+1. When unmasked and the policies are all specified as agnostic:
+(Address0, ..., Address{NF - 1}, Ptr, Idx, VL)
+2. When masked and the policies are all specified as agnostic:
+(Address0, ..., Address{NF - 1}, Mask, Ptr, Idx, VL)
+3. When unmasked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, Idx, VL)
+4. When masked and one of the policies is specified as undisturbed:
+(Address0, ..., Address{NF - 1}, Mask, Maskedoff0, ..., Maskedoff{NF - 1},
+  Ptr, Idx, VL)
+
+Segment load intrinsics has different variants similar to their builtins.
+
+Segment unit-stride load intrinsic,
+  Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Mask, VL, Policy)
+  Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, VL)
+Segment unit-stride fault-only-first load intrinsic,
+  Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Mask, VL, Policy)
+  Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, VL)
+Segment strided load intrinsic,
+  Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Stride, Mask, VL, Policy)
+  Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, Stride, VL)
+Segment indexed load intrinsic,
+  Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Index, Mask, VL, Policy)
+  Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, Index, VL)
+
+The Vector(s) is poison when the policy behavior allows us to not care
+about any masked-off elements.
+*/
 
 class PVString {
   string S =
@@ -842,36 +916,30 @@
 {
   ResultType = ConvertType(E->getArg(0)->getType()->getPointeeType());
   IntrinsicTypes = {ResultType, Ops.back()->getType()};
-  SmallVector Operands;
-  if (IsMasked) {
-// TAMA builtin: (val0 address, ..., mask, ptr, vl)
-// builtin: (val0 address, ..., mask, maskedoff0, ..., ptr, vl)
-// intrinsic: (maskedoff0, ..., ptr, mask, vl)
-if (PolicyAttrs == TAIL_AGNOSTIC_MASK_AGNOSTIC) {
-  Operands.append(NF, llvm::PoisonValue::get(ResultType));
-  Operands.push_back(Ops[NF + 1]);
-  Operands.push_back(Ops[NF]);
-  Operands.push_back(Ops[NF + 2]);
-} e

[PATCH] D140686: [WIP][Clang][RISCV] Update operand order for vmerge and vcompress

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 485961.
eopXD added a comment.

Update test cases for vfmerge.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140686/new/

https://reviews.llvm.org/D140686

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c

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[PATCH] D140895: [WIP][Clang][RISCV] Remove default tail-undisturbed for vector reduction intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
Herald added subscribers: sunshaoce, VincentWu, vkmr, frasercrmck, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

The destination parameter is removed for non-policy unmasked intrinsics,
they are now tail agnostic. The non-policy masked intrinsics are tail
agnostic and masked undisturbed, just like normal instructions like
vadd.

This is the first commit of a patch-set that aims to remove the
`IsPrototypeDefaultTU` special case for the rvv-intrinsics.

The patch-set work towards the simplification proposal [0] of Nick
Knight, the plan is that after this patch-set, all non-policy
intrinsics will be aligned with default policy behavior of tail
agnostic and mask unsidturbed. Then the next patch-set will aim
towards changing non-policy intrinsics to tail agnostic and mask
agnostic.

[0] https://gist.github.com/nick-knight/6cb0b74b351a25323dfb1821d3a269b9


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140895

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredxor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredxor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c

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[PATCH] D140936: [WIP][2/6][RISCV][Clang] Remove default tail-undisturbed for vslideup intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
Herald added subscribers: sunshaoce, VincentWu, vkmr, frasercrmck, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

The destination parameter is still needed as elements of
0 <  i < max(vstart, OFFSET) in vd remains unchanged.

The default policy for non-policy (implicit) vslideup intrinsics
will be tail agnostic and mask undisturbed.

This is the 2nd commit of a patch-set that aims to remove the
IsPrototypeDefaultTU special case for the rvv-intrinsics.

Please refer to the cover letter in the 1st commit (D140895 
) for an overview.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140936

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c
@@ -8,7 +8,7 @@
 
 // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv1i8.i64( [[DST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv1i8.i64( [[DST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vint8mf8_t test_vslideup_vx_i8mf8(vint8mf8_t dst, vint8mf8_t src, size_t offset,
@@ -18,7 +18,7 @@
 
 // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf4(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv2i8.i64( [[DST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv2i8.i64( [[DST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vint8mf4_t test_vslideup_vx_i8mf4(vint8mf4_t dst, vint8mf4_t src, size_t offset,
@@ -28,7 +28,7 @@
 
 // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf2(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv4i8.i64( [[DST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv4i8.i64( [[DST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vint8mf2_t test_vslideup_vx_i8mf2(vint8mf2_t dst, vint8mf2_t src, size_t offset,
@@ -38,7 +38,7 @@
 
 // CHECK-RV64-LABEL: @test_vslideup_vx_i8m1(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv8i8.i64( [[DST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv8i8.i64( [[DST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vint8m1_t test_vslideup_vx_i8m1(vint8m1_t dst, vint8m1_t src, size_t offset,
@@ -48,7 +48,7 @@
 
 // CHECK-RV64-LABEL: @test_vslideup_vx_i8m2(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv16i8.i64( [[DST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv16i8.i64( [[DST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vint8m2_t test_vslideup_vx_i8m2(vint8m2_t dst, vint8m2_t src, size_t offset,
@@ -58,7 +58,7 @@
 
 // CHECK-RV64-LABEL: @test_vslideup_vx_i8m4(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv32i8.i64( [[DST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv32i8.i64( [[DST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vint8m4_t test_vslideup_vx_i8m4(vint8m4_t dst, vint8m4_t src, size_t offset,
@@ -68,7 +68,7 @@
 
 // CHECK-RV64-LABEL: @test_vslideup_vx_i8m8(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv64i8.i64( [[DST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv64i8.i64( [[DST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vint8m8_t test_vslideup_vx

[PATCH] D140937: [WIP][3/6][Clang][RISCV] Remove default tail-undisturbed for vslidedown intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
Herald added subscribers: sunshaoce, VincentWu, vkmr, frasercrmck, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

The destination parameter is removed for non-policy unmasked vslidedown
intrinsics.

The default policy for non-policy (implicit) vslidedown intrinsics will
be tail agnostic and mask undisturbed.

This is the 3rd commit of a patch-set that aims to remove the
IsPrototypeDefaultTU special case for the rvv-intrinsics.

Please refer to the cover letter in the 1st commit (D140895 
) for an
overview.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140937

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c

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[PATCH] D140937: [WIP][3/6][Clang][RISCV] Remove default tail-undisturbed for vslidedown intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 486137.
eopXD added a comment.

Bump CI.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140937/new/

https://reviews.llvm.org/D140937

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c

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[PATCH] D140941: [WIP][4/6][Clang][RISCV] Remove default tail-undisturbed for multiply-add intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
Herald added subscribers: sunshaoce, VincentWu, vkmr, frasercrmck, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

The destination parameter is still needed as the computation requires
so.

The default policy for non-policy (implicit) vslideup intrinsics
will be tail agnostic and mask undisturbed.

This is the 4th commit of a patch-set that aims to remove the
IsPrototypeDefaultTU special case for the rvv-intrinsics.

Please refer to the cover letter in the 1st commit (D140895 
) for an overview.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140941

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c

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[PATCH] D140954: [WIP][7/7][Clang][RISCV][NFC] Remove attribute `IsPrototypeDefaultTU`

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
Herald added subscribers: sunshaoce, VincentWu, vkmr, frasercrmck, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

This is the 7th commit of a patch-set that aims to remove the
IsPrototypeDefaultTU special case for the rvv-intrinsics.

This is the final commit of the patch-set. Now that no intrinsics is
using the attribute, we are safe to remove it.

Please refer to the cover letter in the 1st commit (D140895 
) for an
overview.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140954

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -66,7 +66,6 @@
   bool HasMasked :1;
   bool HasVL :1;
   bool HasMaskedOffOperand :1;
-  bool IsPrototypeDefaultTU : 1;
   bool HasTailPolicy : 1;
   bool HasMaskPolicy : 1;
   uint8_t UnMaskedPolicyScheme : 2;
@@ -518,7 +517,6 @@
 std::vector Log2LMULList = R->getValueAsListOfInts("Log2LMUL");
 bool HasTailPolicy = R->getValueAsBit("HasTailPolicy");
 bool HasMaskPolicy = R->getValueAsBit("HasMaskPolicy");
-bool IsPrototypeDefaultTU = R->getValueAsBit("IsPrototypeDefaultTU");
 bool SupportOverloading = R->getValueAsBit("SupportOverloading");
 bool HasBuiltinAlias = R->getValueAsBit("HasBuiltinAlias");
 StringRef ManualCodegen = R->getValueAsString("ManualCodegen");
@@ -549,13 +547,13 @@
 parsePrototypes(OverloadedSuffixProto);
 
 // Compute Builtin types
-auto Prototype = RVVIntrinsic::computeBuiltinTypes(
-BasicPrototype, /*IsMasked=*/false,
-/*HasMaskedOffOperand=*/false, HasVL, NF, IsPrototypeDefaultTU,
-UnMaskedPolicyScheme, Policy());
+auto Prototype =
+RVVIntrinsic::computeBuiltinTypes(BasicPrototype, /*IsMasked=*/false,
+  /*HasMaskedOffOperand=*/false, HasVL,
+  NF, UnMaskedPolicyScheme, Policy());
 auto MaskedPrototype = RVVIntrinsic::computeBuiltinTypes(
 BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, NF,
-IsPrototypeDefaultTU, MaskedPolicyScheme, Policy());
+MaskedPolicyScheme, Policy());
 
 // Create Intrinsics for each type and LMUL.
 for (char I : TypeRange) {
@@ -577,22 +575,22 @@
 /*IsMasked=*/false, /*HasMaskedOffOperand=*/false, HasVL,
 UnMaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
 ManualCodegen, *Types, IntrinsicTypes, RequiredFeatures, NF,
-Policy(), IsPrototypeDefaultTU));
+Policy()));
 if (UnMaskedPolicyScheme != PolicyScheme::SchemeNone)
   for (auto P : SupportedUnMaskedPolicies) {
 SmallVector PolicyPrototype =
 RVVIntrinsic::computeBuiltinTypes(
 BasicPrototype, /*IsMasked=*/false,
 /*HasMaskedOffOperand=*/false, HasVL, NF,
-IsPrototypeDefaultTU, UnMaskedPolicyScheme, P);
+UnMaskedPolicyScheme, P);
 std::optional PolicyTypes =
 TypeCache.computeTypes(BT, Log2LMUL, NF, PolicyPrototype);
 Out.push_back(std::make_unique(
 Name, SuffixStr, OverloadedName, OverloadedSuffixStr, IRName,
 /*IsMask=*/false, /*HasMaskedOffOperand=*/false, HasVL,
 UnMaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
-ManualCodegen, *PolicyTypes, IntrinsicTypes,
-RequiredFeatures, NF, P, IsPrototypeDefaultTU));
+ManualCodegen, *PolicyTypes, IntrinsicTypes, RequiredFeatures,
+NF, P));
   }
 if (!HasMasked)
   continue;
@@ -602,24 +600,23 @@
 Out.push_back(std::make_unique(
 Name, SuffixStr, OverloadedName, OverloadedSuffixStr, MaskedIRName,
 /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme,
-SupportOverloading, HasBuiltinAlias, ManualCodegen,
-*MaskTypes, IntrinsicTypes, RequiredFeatures, NF,
-Policy(), IsPrototypeDefaultTU));
+SupportOverloading, HasBuiltinAlias, ManualCodegen, *MaskTypes,
+IntrinsicTypes, RequiredFeatures, NF, Policy()));
 if (MaskedPolicySc

[PATCH] D140954: [WIP][7/7][Clang][RISCV][NFC] Remove attribute `IsPrototypeDefaultTU`

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 486170.
eopXD added a comment.

Bump CI.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140954/new/

https://reviews.llvm.org/D140954

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -66,7 +66,6 @@
   bool HasMasked :1;
   bool HasVL :1;
   bool HasMaskedOffOperand :1;
-  bool IsPrototypeDefaultTU : 1;
   bool HasTailPolicy : 1;
   bool HasMaskPolicy : 1;
   uint8_t UnMaskedPolicyScheme : 2;
@@ -518,7 +517,6 @@
 std::vector Log2LMULList = R->getValueAsListOfInts("Log2LMUL");
 bool HasTailPolicy = R->getValueAsBit("HasTailPolicy");
 bool HasMaskPolicy = R->getValueAsBit("HasMaskPolicy");
-bool IsPrototypeDefaultTU = R->getValueAsBit("IsPrototypeDefaultTU");
 bool SupportOverloading = R->getValueAsBit("SupportOverloading");
 bool HasBuiltinAlias = R->getValueAsBit("HasBuiltinAlias");
 StringRef ManualCodegen = R->getValueAsString("ManualCodegen");
@@ -549,13 +547,13 @@
 parsePrototypes(OverloadedSuffixProto);
 
 // Compute Builtin types
-auto Prototype = RVVIntrinsic::computeBuiltinTypes(
-BasicPrototype, /*IsMasked=*/false,
-/*HasMaskedOffOperand=*/false, HasVL, NF, IsPrototypeDefaultTU,
-UnMaskedPolicyScheme, Policy());
+auto Prototype =
+RVVIntrinsic::computeBuiltinTypes(BasicPrototype, /*IsMasked=*/false,
+  /*HasMaskedOffOperand=*/false, HasVL,
+  NF, UnMaskedPolicyScheme, Policy());
 auto MaskedPrototype = RVVIntrinsic::computeBuiltinTypes(
 BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, NF,
-IsPrototypeDefaultTU, MaskedPolicyScheme, Policy());
+MaskedPolicyScheme, Policy());
 
 // Create Intrinsics for each type and LMUL.
 for (char I : TypeRange) {
@@ -577,22 +575,22 @@
 /*IsMasked=*/false, /*HasMaskedOffOperand=*/false, HasVL,
 UnMaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
 ManualCodegen, *Types, IntrinsicTypes, RequiredFeatures, NF,
-Policy(), IsPrototypeDefaultTU));
+Policy()));
 if (UnMaskedPolicyScheme != PolicyScheme::SchemeNone)
   for (auto P : SupportedUnMaskedPolicies) {
 SmallVector PolicyPrototype =
 RVVIntrinsic::computeBuiltinTypes(
 BasicPrototype, /*IsMasked=*/false,
 /*HasMaskedOffOperand=*/false, HasVL, NF,
-IsPrototypeDefaultTU, UnMaskedPolicyScheme, P);
+UnMaskedPolicyScheme, P);
 std::optional PolicyTypes =
 TypeCache.computeTypes(BT, Log2LMUL, NF, PolicyPrototype);
 Out.push_back(std::make_unique(
 Name, SuffixStr, OverloadedName, OverloadedSuffixStr, IRName,
 /*IsMask=*/false, /*HasMaskedOffOperand=*/false, HasVL,
 UnMaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
-ManualCodegen, *PolicyTypes, IntrinsicTypes,
-RequiredFeatures, NF, P, IsPrototypeDefaultTU));
+ManualCodegen, *PolicyTypes, IntrinsicTypes, RequiredFeatures,
+NF, P));
   }
 if (!HasMasked)
   continue;
@@ -602,24 +600,23 @@
 Out.push_back(std::make_unique(
 Name, SuffixStr, OverloadedName, OverloadedSuffixStr, MaskedIRName,
 /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme,
-SupportOverloading, HasBuiltinAlias, ManualCodegen,
-*MaskTypes, IntrinsicTypes, RequiredFeatures, NF,
-Policy(), IsPrototypeDefaultTU));
+SupportOverloading, HasBuiltinAlias, ManualCodegen, *MaskTypes,
+IntrinsicTypes, RequiredFeatures, NF, Policy()));
 if (MaskedPolicyScheme == PolicyScheme::SchemeNone)
   continue;
 for (auto P : SupportedMaskedPolicies) {
   SmallVector PolicyPrototype =
   RVVIntrinsic::computeBuiltinTypes(
   BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL,
-  NF, IsPrototypeDefaultTU, MaskedPolicyScheme, P);
+  NF, MaskedPolicyScheme, P);
   std::optional PolicyTypes =
   TypeCache.computeTypes(BT, Log2LMUL, NF, PolicyPrototype);
   Out.push_back(std::make_unique(
   Name, SuffixStr, OverloadedName, OverloadedSuffixStr,
   MaskedIRName, /*IsMasked=*/true, HasMaskedOffOperand, HasVL,
   MaskedPolicySch

[PATCH] D140954: [WIP][7/7][Clang][RISCV][NFC] Remove attribute `IsPrototypeDefaultTU`

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 486174.
eopXD added a comment.

Bump CI.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140954/new/

https://reviews.llvm.org/D140954

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -66,7 +66,6 @@
   bool HasMasked :1;
   bool HasVL :1;
   bool HasMaskedOffOperand :1;
-  bool IsPrototypeDefaultTU : 1;
   bool HasTailPolicy : 1;
   bool HasMaskPolicy : 1;
   uint8_t UnMaskedPolicyScheme : 2;
@@ -518,7 +517,6 @@
 std::vector Log2LMULList = R->getValueAsListOfInts("Log2LMUL");
 bool HasTailPolicy = R->getValueAsBit("HasTailPolicy");
 bool HasMaskPolicy = R->getValueAsBit("HasMaskPolicy");
-bool IsPrototypeDefaultTU = R->getValueAsBit("IsPrototypeDefaultTU");
 bool SupportOverloading = R->getValueAsBit("SupportOverloading");
 bool HasBuiltinAlias = R->getValueAsBit("HasBuiltinAlias");
 StringRef ManualCodegen = R->getValueAsString("ManualCodegen");
@@ -549,13 +547,13 @@
 parsePrototypes(OverloadedSuffixProto);
 
 // Compute Builtin types
-auto Prototype = RVVIntrinsic::computeBuiltinTypes(
-BasicPrototype, /*IsMasked=*/false,
-/*HasMaskedOffOperand=*/false, HasVL, NF, IsPrototypeDefaultTU,
-UnMaskedPolicyScheme, Policy());
+auto Prototype =
+RVVIntrinsic::computeBuiltinTypes(BasicPrototype, /*IsMasked=*/false,
+  /*HasMaskedOffOperand=*/false, HasVL,
+  NF, UnMaskedPolicyScheme, Policy());
 auto MaskedPrototype = RVVIntrinsic::computeBuiltinTypes(
 BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, NF,
-IsPrototypeDefaultTU, MaskedPolicyScheme, Policy());
+MaskedPolicyScheme, Policy());
 
 // Create Intrinsics for each type and LMUL.
 for (char I : TypeRange) {
@@ -577,22 +575,22 @@
 /*IsMasked=*/false, /*HasMaskedOffOperand=*/false, HasVL,
 UnMaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
 ManualCodegen, *Types, IntrinsicTypes, RequiredFeatures, NF,
-Policy(), IsPrototypeDefaultTU));
+Policy()));
 if (UnMaskedPolicyScheme != PolicyScheme::SchemeNone)
   for (auto P : SupportedUnMaskedPolicies) {
 SmallVector PolicyPrototype =
 RVVIntrinsic::computeBuiltinTypes(
 BasicPrototype, /*IsMasked=*/false,
 /*HasMaskedOffOperand=*/false, HasVL, NF,
-IsPrototypeDefaultTU, UnMaskedPolicyScheme, P);
+UnMaskedPolicyScheme, P);
 std::optional PolicyTypes =
 TypeCache.computeTypes(BT, Log2LMUL, NF, PolicyPrototype);
 Out.push_back(std::make_unique(
 Name, SuffixStr, OverloadedName, OverloadedSuffixStr, IRName,
 /*IsMask=*/false, /*HasMaskedOffOperand=*/false, HasVL,
 UnMaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
-ManualCodegen, *PolicyTypes, IntrinsicTypes,
-RequiredFeatures, NF, P, IsPrototypeDefaultTU));
+ManualCodegen, *PolicyTypes, IntrinsicTypes, RequiredFeatures,
+NF, P));
   }
 if (!HasMasked)
   continue;
@@ -602,24 +600,23 @@
 Out.push_back(std::make_unique(
 Name, SuffixStr, OverloadedName, OverloadedSuffixStr, MaskedIRName,
 /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme,
-SupportOverloading, HasBuiltinAlias, ManualCodegen,
-*MaskTypes, IntrinsicTypes, RequiredFeatures, NF,
-Policy(), IsPrototypeDefaultTU));
+SupportOverloading, HasBuiltinAlias, ManualCodegen, *MaskTypes,
+IntrinsicTypes, RequiredFeatures, NF, Policy()));
 if (MaskedPolicyScheme == PolicyScheme::SchemeNone)
   continue;
 for (auto P : SupportedMaskedPolicies) {
   SmallVector PolicyPrototype =
   RVVIntrinsic::computeBuiltinTypes(
   BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL,
-  NF, IsPrototypeDefaultTU, MaskedPolicyScheme, P);
+  NF, MaskedPolicyScheme, P);
   std::optional PolicyTypes =
   TypeCache.computeTypes(BT, Log2LMUL, NF, PolicyPrototype);
   Out.push_back(std::make_unique(
   Name, SuffixStr, OverloadedName, OverloadedSuffixStr,
   MaskedIRName, /*IsMasked=*/true, HasMaskedOffOperand, HasVL,
   MaskedPolicySch

[PATCH] D141032: [Clang][RISCV] Expose vlenb to vread_csr

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
eopXD added reviewers: craig.topper, kito-cheng, frasercrmck.
Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, arichardson.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

This commit resolves: riscv-non-isa/rvv-intrinsic-doc#180


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141032

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c


Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
@@ -40,3 +40,12 @@
 unsigned long vread_csr_vcsr(void) {
   return vread_csr(RVV_VCSR);
 }
+
+// CHECK-LABEL: @vread_csr_vlenb(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, 
vlenb", "=r,~{memory}"() #[[ATTR1]], !srcloc !8
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vlenb(void) {
+  return vread_csr(RVV_VLENB);
+}
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1516,6 +1516,7 @@
   RVV_VXSAT,
   RVV_VXRM,
   RVV_VCSR,
+  RVV_VLENB,
 };
 
 static __inline__ __attribute__((__always_inline__, __nodebug__))
@@ -1534,6 +1535,9 @@
 case RVV_VCSR:
   __asm__ __volatile__ ("csrr\t%0, vcsr" : "=r"(__rv) : : "memory");
   break;
+case RVV_VLENB:
+  __asm__ __volatile__ ("csrr\t%0, vlenb" : "=r"(__rv) : : "memory");
+  break;
   }
   return __rv;
 }


Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
@@ -40,3 +40,12 @@
 unsigned long vread_csr_vcsr(void) {
   return vread_csr(RVV_VCSR);
 }
+
+// CHECK-LABEL: @vread_csr_vlenb(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vlenb", "=r,~{memory}"() #[[ATTR1]], !srcloc !8
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vlenb(void) {
+  return vread_csr(RVV_VLENB);
+}
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1516,6 +1516,7 @@
   RVV_VXSAT,
   RVV_VXRM,
   RVV_VCSR,
+  RVV_VLENB,
 };
 
 static __inline__ __attribute__((__always_inline__, __nodebug__))
@@ -1534,6 +1535,9 @@
 case RVV_VCSR:
   __asm__ __volatile__ ("csrr\t%0, vcsr" : "=r"(__rv) : : "memory");
   break;
+case RVV_VLENB:
+  __asm__ __volatile__ ("csrr\t%0, vlenb" : "=r"(__rv) : : "memory");
+  break;
   }
   return __rv;
 }
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[PATCH] D141032: [Clang][RISCV] Expose vlenb to user

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD added a comment.

Upon a second thought, with future extensions of the intrinsics, we will add 
rounding mode and exception intrinsics. The exposure of vxsat, vxrm, and vcsr 
in vread_csr and vwrite_csr will confuse user and we should remove them. 
Furthermore, vstart is pretty much always kept to zero, and intrinsic users 
probably should not have access to them.

With the considerations above, I think vread_csr and vwrite_csr can be removed 
in the future when the rounding mode and exception intrinsics are added. This 
is why this patch is opening up a separate function to provide access to vlenb 
and not choose to extend another member in the enum.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141032/new/

https://reviews.llvm.org/D141032

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[PATCH] D141032: [Clang][RISCV] Expose vlenb to user

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 486486.
eopXD edited the summary of this revision.
eopXD added a comment.

Update code. Add function `vlenb` instead of extending inside the `vread_csr` 
function.


Repository:
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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c


Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
@@ -0,0 +1,15 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone 
-emit-llvm %s -o - \
+// RUN: | opt -S -O2 | FileCheck  %s
+
+#include 
+
+// CHECK-LABEL: @test_vlenb(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, 
vlenb", "=r,~{memory}"() #[[ATTR1:[0-9]+]], !srcloc !4
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long test_vlenb(void) {
+  return vlenb();
+}
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1557,6 +1557,17 @@
 }
 }] in
 def vread_vwrite_csr: RVVHeader;
+let HeaderCode =
+[{
+static __inline__ __attribute__((__always_inline__, __nodebug__))
+unsigned long vlenb() {
+  unsigned long __rv = 0;
+  __asm__ __volatile__ ("csrr\t%0, vlenb" : "=r"(__rv) : : "memory");
+  return __rv;
+}
+}] in
+def vlenb: RVVHeader;
+
 
 // 6. Configuration-Setting Instructions
 // 6.1. vsetvli/vsetvl instructions


Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
@@ -0,0 +1,15 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
+// RUN: | opt -S -O2 | FileCheck  %s
+
+#include 
+
+// CHECK-LABEL: @test_vlenb(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vlenb", "=r,~{memory}"() #[[ATTR1:[0-9]+]], !srcloc !4
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long test_vlenb(void) {
+  return vlenb();
+}
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1557,6 +1557,17 @@
 }
 }] in
 def vread_vwrite_csr: RVVHeader;
+let HeaderCode =
+[{
+static __inline__ __attribute__((__always_inline__, __nodebug__))
+unsigned long vlenb() {
+  unsigned long __rv = 0;
+  __asm__ __volatile__ ("csrr\t%0, vlenb" : "=r"(__rv) : : "memory");
+  return __rv;
+}
+}] in
+def vlenb: RVVHeader;
+
 
 // 6. Configuration-Setting Instructions
 // 6.1. vsetvli/vsetvl instructions
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[PATCH] D141032: [Clang][RISCV] Expose vlenb to user

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD marked an inline comment as done.
eopXD added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:1559
   __asm__ __volatile__ ("csrw\tvcsr, %z0" : : "rJ"(__value) : "memory");
   break;
   }

pcwang-thead wrote:
> Should we report errors if `vwrite_csr(RVV_VLENB, some_value)`?
Thanks pointing this out. I think my second approach here won't create such 
problem.


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[PATCH] D141198: [NFC][Clang][RISCV] Reorganize test case for rvv intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
eopXD added reviewers: craig.topper, kito-cheng, frasercrmck, reames, jrtc27.
Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, arphaman, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

Separating auto-generated test cases and hand-craft ones. The
auto-generated ones are basic API tests generated from the intrinsic
generator [0].

This re-organization allows direct copy-and-paste from the produced
outputs of the generator in future API changes, which is discussed
and needs to be implemented towards a v1.0 RVV intrinsic.


Repository:
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https://reviews.llvm.org/D141198

Files:
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
  
clang/test/CodeGen/RISCV/

[PATCH] D141198: [Clang][RISCV][NFC] Reorganize test case for rvv intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 487094.
eopXD added a comment.

Rebase to latest main.


Repository:
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Files:
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-a

[PATCH] D141198: [Clang][RISCV][NFC] Reorganize test case for rvv intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD added a comment.

The testing time difference is shown below. I personally think 3 more minutes 
in testing is tolerable when considering `check-all`. The testing time increase 
comes from full test coverage to the intrinsics. Before this patch, some test 
cases only includes parts of the {SEW, LMUL} combination of an intrinsic to 
reduce avoid long compile time. We no longer suffer from long compile time as 
the intrinsics are now lazily added.

Before

  $ bin/llvm-lit ../clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded 
../clang/test/CodeGen/RISCV/rvv-intrinsics 
../clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted
  llvm-lit: 
/scratch/eopc/upstream-llvm-project/llvm/utils/lit/lit/llvm/config.py:459: 
note: using clang: /scratch/eopc/upstream-llvm-project/build/bin/clang
  -- Testing: 326 tests, 48 workers --
  Testing Time: 25.83s
Passed: 326

After

  $ bin/llvm-lit ../clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated
  llvm-lit: 
/scratch/eopc/upstream-llvm-project/llvm/utils/lit/lit/llvm/config.py:459: 
note: using clang: /scratch/eopc/upstream-llvm-project/build/bin/clang
  -- Testing: 566 tests, 48 workers --
  Testing Time: 225.61s
Passed: 566


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[PATCH] D141198: [Clang][RISCV][NFC] Reorganize test case for rvv intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD added a comment.

The patch application failure probably is due to the large amount of changes in 
this patch.


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[PATCH] D141198: [Clang][RISCV][NFC] Reorganize test case for rvv intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD added a comment.

I have created a branch under my forked repo. for people to checkout this 
commit conveniently.

https://github.com/eopXD/llvm-project/tree/reorganize-testcase


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[PATCH] D140686: [WIP][Clang][RISCV] Update operand order for vmerge and vcompress

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 487194.
eopXD added a comment.

Rebase upon D141198 .


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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c

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[PATCH] D141032: [Clang][RISCV] Expose vlenb to user

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 487206.
eopXD marked an inline comment as not done.
eopXD added a comment.

Update code. Apply suggestion from @pcwang-thead.


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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c


Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
@@ -0,0 +1,15 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone 
-emit-llvm %s -o - \
+// RUN: | opt -S -O2 | FileCheck  %s
+
+#include 
+
+// CHECK-LABEL: @test_vlenb(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 
@llvm.read_register.i64(metadata [[META4:![0-9]+]])
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long test_vlenb(void) {
+  return vlenb();
+}
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1558,6 +1558,32 @@
 }] in
 def vread_vwrite_csr: RVVHeader;
 
+let HeaderCode =
+[{
+#define vlenb() __builtin_rvv_vlenb()
+}] in
+def vlenb_macro: RVVHeader;
+
+let HasBuiltinAlias = false, HasVL = false, HasMasked = false,
+UnMaskedPolicyScheme = NonePolicy, MaskedPolicyScheme = NonePolicy,
+Log2LMUL = [0], IRName = "",
+ManualCodegen = [{
+{
+  LLVMContext &Context = CGM.getLLVMContext();
+  llvm::MDBuilder MDHelper(Context);
+
+  llvm::Metadata *Ops[] = {llvm::MDString::get(Context, "vlenb")};
+  llvm::MDNode *RegName = llvm::MDNode::get(Context, Ops);
+  llvm::Value *Metadata = llvm::MetadataAsValue::get(Context, RegName);
+  llvm::Function *F =
+CGM.getIntrinsic(llvm::Intrinsic::read_register, {Int64Ty});
+  return Builder.CreateCall(F, Metadata);
+}
+}] in
+{
+  def vlenb : RVVBuiltin<"", "u", "i">;
+}
+
 // 6. Configuration-Setting Instructions
 // 6.1. vsetvli/vsetvl instructions
 


Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
@@ -0,0 +1,15 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
+// RUN: | opt -S -O2 | FileCheck  %s
+
+#include 
+
+// CHECK-LABEL: @test_vlenb(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.read_register.i64(metadata [[META4:![0-9]+]])
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long test_vlenb(void) {
+  return vlenb();
+}
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1558,6 +1558,32 @@
 }] in
 def vread_vwrite_csr: RVVHeader;
 
+let HeaderCode =
+[{
+#define vlenb() __builtin_rvv_vlenb()
+}] in
+def vlenb_macro: RVVHeader;
+
+let HasBuiltinAlias = false, HasVL = false, HasMasked = false,
+UnMaskedPolicyScheme = NonePolicy, MaskedPolicyScheme = NonePolicy,
+Log2LMUL = [0], IRName = "",
+ManualCodegen = [{
+{
+  LLVMContext &Context = CGM.getLLVMContext();
+  llvm::MDBuilder MDHelper(Context);
+
+  llvm::Metadata *Ops[] = {llvm::MDString::get(Context, "vlenb")};
+  llvm::MDNode *RegName = llvm::MDNode::get(Context, Ops);
+  llvm::Value *Metadata = llvm::MetadataAsValue::get(Context, RegName);
+  llvm::Function *F =
+CGM.getIntrinsic(llvm::Intrinsic::read_register, {Int64Ty});
+  return Builder.CreateCall(F, Metadata);
+}
+}] in
+{
+  def vlenb : RVVBuiltin<"", "u", "i">;
+}
+
 // 6. Configuration-Setting Instructions
 // 6.1. vsetvli/vsetvl instructions
 
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[PATCH] D141032: [Clang][RISCV] Expose vlenb to user

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD marked 2 inline comments as done.
eopXD added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:1565
+  unsigned long __rv = 0;
+  __asm__ __volatile__ ("csrr\t%0, vlenb" : "=r"(__rv) : : "memory");
+  return __rv;

pcwang-thead wrote:
> Inline assembly may not be elegant since it can't be optimized in many ways. 
> We can eliminate some redundant reads of vlenb currently(done in D125564). So 
> I think we may add a builtin function and lower it to `llvm.read_register`?
Thank you for the tip. Please review.


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[PATCH] D141032: [Clang][RISCV] Expose vlenb to user

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 487293.
eopXD marked 5 inline comments as done.
eopXD added a comment.

Address comments from Craig.


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Files:
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  clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c


Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
@@ -0,0 +1,41 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --check-globals
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +v -disable-O0-optnone 
-emit-llvm %s -o - \
+// RUN: | opt -S -O2 | FileCheck --check-prefix=RV32 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone 
-emit-llvm %s -o - \
+// RUN: | opt -S -O2 | FileCheck --check-prefix=RV64 %s
+
+#include 
+
+// RV32-LABEL: @test_vlenb(
+// RV32-NEXT:  entry:
+// RV32-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.read_register.i32(metadata 
[[META4:![0-9]+]])
+// RV32-NEXT:ret i32 [[TMP0]]
+//
+// RV64-LABEL: @test_vlenb(
+// RV64-NEXT:  entry:
+// RV64-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.read_register.i64(metadata 
[[META4:![0-9]+]])
+// RV64-NEXT:ret i64 [[TMP0]]
+//
+unsigned long test_vlenb(void) {
+  return vlenb();
+}
+//.
+// RV32: attributes #0 = { mustprogress nofree noinline nosync nounwind 
willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" 
"stack-protector-buffer-size"="8" 
"target-features"="+32bit,+d,+f,+v,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b"
 }
+// RV32: attributes #1 = { mustprogress nocallback nofree nosync nounwind 
willreturn memory(read) }
+//.
+// RV64: attributes #0 = { mustprogress nofree noinline nosync nounwind 
willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" 
"stack-protector-buffer-size"="8" 
"target-features"="+64bit,+d,+f,+v,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b"
 }
+// RV64: attributes #1 = { mustprogress nocallback nofree nosync nounwind 
willreturn memory(read) }
+//.
+// RV32: !0 = !{i32 1, !"wchar_size", i32 4}
+// RV32: !1 = !{i32 1, !"target-abi", !"ilp32d"}
+// RV32: !2 = !{i32 1, !"SmallDataLimit", i32 0}
+// RV32: !3 = !{!"clang version 16.0.0 (g...@github.com:llvm/llvm-project.git 
e80f0cc0a318fe8473ba460d6a16166d81b303b1)"}
+// RV32: !4 = !{!"vlenb"}
+//.
+// RV64: !0 = !{i32 1, !"wchar_size", i32 4}
+// RV64: !1 = !{i32 1, !"target-abi", !"lp64d"}
+// RV64: !2 = !{i32 1, !"SmallDataLimit", i32 0}
+// RV64: !3 = !{!"clang version 16.0.0 (g...@github.com:llvm/llvm-project.git 
e80f0cc0a318fe8473ba460d6a16166d81b303b1)"}
+// RV64: !4 = !{!"vlenb"}
+//.
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1558,6 +1558,32 @@
 }] in
 def vread_vwrite_csr: RVVHeader;
 
+let HeaderCode =
+[{
+#define vlenb() __builtin_rvv_vlenb()
+}] in
+def vlenb_macro: RVVHeader;
+
+let HasBuiltinAlias = false, HasVL = false, HasMasked = false,
+UnMaskedPolicyScheme = NonePolicy, MaskedPolicyScheme = NonePolicy,
+Log2LMUL = [0], IRName = "",
+ManualCodegen = [{
+{
+  LLVMContext &Context = CGM.getLLVMContext();
+  llvm::MDBuilder MDHelper(Context);
+
+  llvm::Metadata *Ops[] = {llvm::MDString::get(Context, "vlenb")};
+  llvm::MDNode *RegName = llvm::MDNode::get(Context, Ops);
+  llvm::Value *Metadata = llvm::MetadataAsValue::get(Context, RegName);
+  llvm::Function *F =
+CGM.getIntrinsic(llvm::Intrinsic::read_register, {SizeTy});
+  return Builder.CreateCall(F, Metadata);
+}
+}] in
+{
+  def vlenb : RVVBuiltin<"", "u", "i">;
+}
+
 // 6. Configuration-Setting Instructions
 // 6.1. vsetvli/vsetvl instructions
 


Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
@@ -0,0 +1,41 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
+// RUN: | opt -S -O2 | FileCheck --check-prefix=RV32 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
+// RUN: | opt -S -O2 | FileCheck --check-prefix=RV64 %s
+
+#include 
+
+// RV32-LABEL: @test_vlenb(
+// RV32-NEXT:  entry:
+// RV32-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.read_register.i32(metadata [[META4:![0-9]+]])
+// RV32-NEXT:ret i32 [[TMP0]]
+//
+// RV64-LABEL: @test_vlenb(
+// RV64-NEXT:  entry:
+// RV64

[PATCH] D141032: [Clang][RISCV] Expose vlenb to user

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 487302.
eopXD added a comment.

Update code: Avoid emit clang version in test case.
@pcwang-thead Thank you for checking and providing the corresponding 
resolution. :)


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Files:
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  clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c


Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
@@ -0,0 +1,39 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --check-globals
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +v -disable-O0-optnone 
-emit-llvm -Qn %s -o - \
+// RUN: | opt -S -O2 | FileCheck --check-prefix=RV32 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone 
-emit-llvm -Qn %s -o - \
+// RUN: | opt -S -O2 | FileCheck --check-prefix=RV64 %s
+
+#include 
+
+// RV32-LABEL: @test_vlenb(
+// RV32-NEXT:  entry:
+// RV32-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.read_register.i32(metadata 
[[META3:![0-9]+]])
+// RV32-NEXT:ret i32 [[TMP0]]
+//
+// RV64-LABEL: @test_vlenb(
+// RV64-NEXT:  entry:
+// RV64-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.read_register.i64(metadata 
[[META3:![0-9]+]])
+// RV64-NEXT:ret i64 [[TMP0]]
+//
+unsigned long test_vlenb(void) {
+  return vlenb();
+}
+//.
+// RV32: attributes #0 = { mustprogress nofree noinline nosync nounwind 
willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" 
"stack-protector-buffer-size"="8" 
"target-features"="+32bit,+d,+f,+v,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b"
 }
+// RV32: attributes #1 = { mustprogress nocallback nofree nosync nounwind 
willreturn memory(read) }
+//.
+// RV64: attributes #0 = { mustprogress nofree noinline nosync nounwind 
willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" 
"stack-protector-buffer-size"="8" 
"target-features"="+64bit,+d,+f,+v,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b"
 }
+// RV64: attributes #1 = { mustprogress nocallback nofree nosync nounwind 
willreturn memory(read) }
+//.
+// RV32: !0 = !{i32 1, !"wchar_size", i32 4}
+// RV32: !1 = !{i32 1, !"target-abi", !"ilp32d"}
+// RV32: !2 = !{i32 1, !"SmallDataLimit", i32 0}
+// RV32: !3 = !{!"vlenb"}
+//.
+// RV64: !0 = !{i32 1, !"wchar_size", i32 4}
+// RV64: !1 = !{i32 1, !"target-abi", !"lp64d"}
+// RV64: !2 = !{i32 1, !"SmallDataLimit", i32 0}
+// RV64: !3 = !{!"vlenb"}
+//.
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1558,6 +1558,32 @@
 }] in
 def vread_vwrite_csr: RVVHeader;
 
+let HeaderCode =
+[{
+#define vlenb() __builtin_rvv_vlenb()
+}] in
+def vlenb_macro: RVVHeader;
+
+let HasBuiltinAlias = false, HasVL = false, HasMasked = false,
+UnMaskedPolicyScheme = NonePolicy, MaskedPolicyScheme = NonePolicy,
+Log2LMUL = [0], IRName = "",
+ManualCodegen = [{
+{
+  LLVMContext &Context = CGM.getLLVMContext();
+  llvm::MDBuilder MDHelper(Context);
+
+  llvm::Metadata *Ops[] = {llvm::MDString::get(Context, "vlenb")};
+  llvm::MDNode *RegName = llvm::MDNode::get(Context, Ops);
+  llvm::Value *Metadata = llvm::MetadataAsValue::get(Context, RegName);
+  llvm::Function *F =
+CGM.getIntrinsic(llvm::Intrinsic::read_register, {SizeTy});
+  return Builder.CreateCall(F, Metadata);
+}
+}] in
+{
+  def vlenb : RVVBuiltin<"", "u", "i">;
+}
+
 // 6. Configuration-Setting Instructions
 // 6.1. vsetvli/vsetvl instructions
 


Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
@@ -0,0 +1,39 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn %s -o - \
+// RUN: | opt -S -O2 | FileCheck --check-prefix=RV32 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm -Qn %s -o - \
+// RUN: | opt -S -O2 | FileCheck --check-prefix=RV64 %s
+
+#include 
+
+// RV32-LABEL: @test_vlenb(
+// RV32-NEXT:  entry:
+// RV32-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.read_register.i32(metadata [[META3:![0-9]+]])
+// RV32-NEXT:ret i32 [[TMP0]]
+//
+// RV64-LABEL: @test_vlenb(
+// RV64-NEXT:  entry:
+// RV64-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.read_register.i64(metadata [[META3:![0-9]+]])
+// RV64-NEXT:ret i64 [[TMP0]]
+//
+unsigned long test_vlenb(void) {

[PATCH] D141198: [Clang][RISCV][NFC] Reorganize test case for rvv intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 487317.
eopXD edited the summary of this revision.
eopXD added a comment.

Update test cases. Don't add target feature `zfh` and `zvfh` for intrinsics 
that does not have a floating-point type variant.


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Files:
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwred

[PATCH] D141198: [Clang][RISCV][NFC] Reorganize test case for rvv intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 487683.
eopXD added a comment.

Address comment from Craig.

Also separate test case according to their mnemonics.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141198/new/

https://reviews.llvm.org/D141198

Files:
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwms

[PATCH] D141032: [Clang][RISCV] Expose vlenb to user

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG96b52c1eec7b: [Clang][RISCV] Expose vlenb to user (authored 
by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141032/new/

https://reviews.llvm.org/D141032

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c


Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
@@ -0,0 +1,39 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --check-globals
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +v -disable-O0-optnone 
-emit-llvm -Qn %s -o - \
+// RUN: | opt -S -O2 | FileCheck --check-prefix=RV32 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone 
-emit-llvm -Qn %s -o - \
+// RUN: | opt -S -O2 | FileCheck --check-prefix=RV64 %s
+
+#include 
+
+// RV32-LABEL: @test_vlenb(
+// RV32-NEXT:  entry:
+// RV32-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.read_register.i32(metadata 
[[META3:![0-9]+]])
+// RV32-NEXT:ret i32 [[TMP0]]
+//
+// RV64-LABEL: @test_vlenb(
+// RV64-NEXT:  entry:
+// RV64-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.read_register.i64(metadata 
[[META3:![0-9]+]])
+// RV64-NEXT:ret i64 [[TMP0]]
+//
+unsigned long test_vlenb(void) {
+  return vlenb();
+}
+//.
+// RV32: attributes #0 = { mustprogress nofree noinline nosync nounwind 
willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" 
"stack-protector-buffer-size"="8" 
"target-features"="+32bit,+d,+f,+v,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b"
 }
+// RV32: attributes #1 = { mustprogress nocallback nofree nosync nounwind 
willreturn memory(read) }
+//.
+// RV64: attributes #0 = { mustprogress nofree noinline nosync nounwind 
willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" 
"stack-protector-buffer-size"="8" 
"target-features"="+64bit,+d,+f,+v,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b"
 }
+// RV64: attributes #1 = { mustprogress nocallback nofree nosync nounwind 
willreturn memory(read) }
+//.
+// RV32: !0 = !{i32 1, !"wchar_size", i32 4}
+// RV32: !1 = !{i32 1, !"target-abi", !"ilp32d"}
+// RV32: !2 = !{i32 1, !"SmallDataLimit", i32 0}
+// RV32: !3 = !{!"vlenb"}
+//.
+// RV64: !0 = !{i32 1, !"wchar_size", i32 4}
+// RV64: !1 = !{i32 1, !"target-abi", !"lp64d"}
+// RV64: !2 = !{i32 1, !"SmallDataLimit", i32 0}
+// RV64: !3 = !{!"vlenb"}
+//.
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1558,6 +1558,32 @@
 }] in
 def vread_vwrite_csr: RVVHeader;
 
+let HeaderCode =
+[{
+#define vlenb() __builtin_rvv_vlenb()
+}] in
+def vlenb_macro: RVVHeader;
+
+let HasBuiltinAlias = false, HasVL = false, HasMasked = false,
+UnMaskedPolicyScheme = NonePolicy, MaskedPolicyScheme = NonePolicy,
+Log2LMUL = [0], IRName = "",
+ManualCodegen = [{
+{
+  LLVMContext &Context = CGM.getLLVMContext();
+  llvm::MDBuilder MDHelper(Context);
+
+  llvm::Metadata *Ops[] = {llvm::MDString::get(Context, "vlenb")};
+  llvm::MDNode *RegName = llvm::MDNode::get(Context, Ops);
+  llvm::Value *Metadata = llvm::MetadataAsValue::get(Context, RegName);
+  llvm::Function *F =
+CGM.getIntrinsic(llvm::Intrinsic::read_register, {SizeTy});
+  return Builder.CreateCall(F, Metadata);
+}
+}] in
+{
+  def vlenb : RVVBuiltin<"", "u", "i">;
+}
+
 // 6. Configuration-Setting Instructions
 // 6.1. vsetvli/vsetvl instructions
 


Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c
@@ -0,0 +1,39 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn %s -o - \
+// RUN: | opt -S -O2 | FileCheck --check-prefix=RV32 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm -Qn %s -o - \
+// RUN: | opt -S -O2 | FileCheck --check-prefix=RV64 %s
+
+#include 
+
+// RV32-LABEL: @test_vlenb(
+// RV32-NEXT:  entry:
+// RV32-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.read_register.i32(metadata [[META3:![0-9]+]])
+// RV32-NEXT:ret i32 [[TMP0]]
+//
+// RV64-LABEL: @test_vlenb(
+// RV64-NEXT:  entry:
+// RV64-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.read_register.i64(metadata [[META3:![0-9]+]])
+// RV64-NEXT:ret i64 [[TMP0]]
+//
+unsigned long test

[PATCH] D141198: [Clang][RISCV][NFC] Reorganize test case for rvv intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 488055.
eopXD added a comment.

Rebase to latest main.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141198/new/

https://reviews.llvm.org/D141198

Files:
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerate

[PATCH] D141198: [Clang][RISCV][NFC] Reorganize test case for rvv intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 488061.
eopXD added a comment.

Recover mis-deleted handcrafted test case for vmulh, vmulhu, and vmulhsu on e8 
~ e64 with zve32x.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141198/new/

https://reviews.llvm.org/D141198

Files:
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-

[PATCH] D141198: [Clang][RISCV][NFC] Reorganize test case for rvv intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb9f75827fedb: [Clang][RISCV][NFC] Reorganize test case for 
rvv intrinsics (authored by eopXD).

Changed prior to commit:
  https://reviews.llvm.org/D141198?vs=488061&id=488086#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141198/new/

https://reviews.llvm.org/D141198

Files:
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
  

[PATCH] D140686: [WIP][Clang][RISCV] Update operand order for vmerge and vcompress

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 488093.
eopXD added a comment.

Rebase on top of landing of D141198 .


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140686/new/

https://reviews.llvm.org/D140686

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c

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[PATCH] D140895: [1/7][Clang][RISCV] Remove default tail-undisturbed for vector reduction intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 488140.
eopXD edited the summary of this revision.
eopXD added a comment.

Rebase on top of landing of D141198 .


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140895/new/

https://reviews.llvm.org/D140895

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c

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[PATCH] D140936: [2/7][Clang][RISCV] Remove default tail-undisturbed for vslideup intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 488144.
eopXD added a comment.

Rebase on top of landing of D141198 .


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140936/new/

https://reviews.llvm.org/D140936

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
@@ -9,7 +9,7 @@
 
 // CHECK-RV64-LABEL: @test_vslideup_vx_f16mf4(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv1f16.i64( [[DEST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv1f16.i64( [[DEST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vfloat16mf4_t test_vslideup_vx_f16mf4(vfloat16mf4_t dest, vfloat16mf4_t src, size_t offset, size_t vl) {
@@ -18,7 +18,7 @@
 
 // CHECK-RV64-LABEL: @test_vslideup_vx_f16mf2(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv2f16.i64( [[DEST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv2f16.i64( [[DEST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vfloat16mf2_t test_vslideup_vx_f16mf2(vfloat16mf2_t dest, vfloat16mf2_t src, size_t offset, size_t vl) {
@@ -27,7 +27,7 @@
 
 // CHECK-RV64-LABEL: @test_vslideup_vx_f16m1(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv4f16.i64( [[DEST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv4f16.i64( [[DEST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vfloat16m1_t test_vslideup_vx_f16m1(vfloat16m1_t dest, vfloat16m1_t src, size_t offset, size_t vl) {
@@ -36,7 +36,7 @@
 
 // CHECK-RV64-LABEL: @test_vslideup_vx_f16m2(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv8f16.i64( [[DEST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv8f16.i64( [[DEST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vfloat16m2_t test_vslideup_vx_f16m2(vfloat16m2_t dest, vfloat16m2_t src, size_t offset, size_t vl) {
@@ -45,7 +45,7 @@
 
 // CHECK-RV64-LABEL: @test_vslideup_vx_f16m4(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv16f16.i64( [[DEST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv16f16.i64( [[DEST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vfloat16m4_t test_vslideup_vx_f16m4(vfloat16m4_t dest, vfloat16m4_t src, size_t offset, size_t vl) {
@@ -54,7 +54,7 @@
 
 // CHECK-RV64-LABEL: @test_vslideup_vx_f16m8(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv32f16.i64( [[DEST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv32f16.i64( [[DEST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vfloat16m8_t test_vslideup_vx_f16m8(vfloat16m8_t dest, vfloat16m8_t src, size_t offset, size_t vl) {
@@ -63,7 +63,7 @@
 
 // CHECK-RV64-LABEL: @test_vslideup_vx_f32mf2(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv1f32.i64( [[DEST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv1f32.i64( [[DEST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 1)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vfloat32mf2_t test_vslideup_vx_f32mf2(vfloat32mf2_t dest, vfloat32mf2_t src, size_t offset, size_t vl) {
@@ -72,7 +72,7 @@
 
 // CHECK-RV64-LABEL: @test_vslideup_vx_f32m1(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv2f32.i64( [[DEST:%.*]],  [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vslideup.nxv2f32.i64( [[DEST:%.*]],  

[PATCH] D140941: [4/7][Clang][RISCV] Remove default tail-undisturbed for multiply-add intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 488150.
eopXD added a comment.

Rebase on top of landing of D141198 .


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140941/new/

https://reviews.llvm.org/D140941

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D140942: [5/7][Clang][RISCV] Remove default tail-undisturbed for vcompress intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 488152.
eopXD added a comment.

Rebase on top of landing of D141198 .


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140942/new/

https://reviews.llvm.org/D140942

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
@@ -9,532 +9,532 @@
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16mf4(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv1f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv1f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16mf4_t test_vcompress_vm_f16mf4(vbool64_t mask, vfloat16mf4_t dest, vfloat16mf4_t src, size_t vl) {
-  return vcompress(mask, dest, src, vl);
+vfloat16mf4_t test_vcompress_vm_f16mf4(vbool64_t mask, vfloat16mf4_t src, size_t vl) {
+  return vcompress(mask, src, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16mf2(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv2f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv2f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16mf2_t test_vcompress_vm_f16mf2(vbool32_t mask, vfloat16mf2_t dest, vfloat16mf2_t src, size_t vl) {
-  return vcompress(mask, dest, src, vl);
+vfloat16mf2_t test_vcompress_vm_f16mf2(vbool32_t mask, vfloat16mf2_t src, size_t vl) {
+  return vcompress(mask, src, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16m1(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv4f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv4f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m1_t test_vcompress_vm_f16m1(vbool16_t mask, vfloat16m1_t dest, vfloat16m1_t src, size_t vl) {
-  return vcompress(mask, dest, src, vl);
+vfloat16m1_t test_vcompress_vm_f16m1(vbool16_t mask, vfloat16m1_t src, size_t vl) {
+  return vcompress(mask, src, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16m2(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv8f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv8f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m2_t test_vcompress_vm_f16m2(vbool8_t mask, vfloat16m2_t dest, vfloat16m2_t src, size_t vl) {
-  return vcompress(mask, dest, src, vl);
+vfloat16m2_t test_vcompress_vm_f16m2(vbool8_t mask, vfloat16m2_t src, size_t vl) {
+  return vcompress(mask, src, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16m4(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv16f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv16f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m4_t test_vcompress_vm_f16m4(vbool4_t mask, vfloat16m4_t dest, vfloat16m4_t src, size_t vl) {
-  return vcompress(mask, dest, src, vl);
+vfloat16m4_t test_vcompress_vm_f16m4(vbool4_t mask, vfloat16m4_t src, size_t vl) {
+  return vcompress(mask, src, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16m8(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv32f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv32f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m8_t test_vcompress_vm_f16m8(vbool2_t mask, vfloat16m8_t dest, vfloat16m8_t src, size_t vl) {
-  return vcompress(mask, dest, src, vl);
+vfloat16m8_t test_vcompress_vm_f16m8(vbool2_t mask, vfloat16m8_t src, size_t vl) {
+  return vcompress(mask, src, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f32mf2(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = c

[PATCH] D140947: [6/7][Clang][RISCV] Remove default tail-undisturbed for vmv_s_x and vfmv_s_f intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 488156.
eopXD added a comment.

Rebase on top of landing of D141198 .


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140947/new/

https://reviews.llvm.org/D140947

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
@@ -547,15 +547,6 @@
   return vmv_x(src);
 }
 
-// CHECK-RV64-LABEL: @test_vmv_s_x_i8mf8(
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmv.s.x.nxv1i8.i64( [[DEST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]])
-// CHECK-RV64-NEXT:ret  [[TMP0]]
-//
-vint8mf8_t test_vmv_s_x_i8mf8(vint8mf8_t dest, int8_t src, size_t vl) {
-  return vmv_s(dest, src, vl);
-}
-
 // CHECK-RV64-LABEL: @test_vmv_x_s_i8mf4_i8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv2i8( [[SRC:%.*]])
@@ -565,15 +556,6 @@
   return vmv_x(src);
 }
 
-// CHECK-RV64-LABEL: @test_vmv_s_x_i8mf4(
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmv.s.x.nxv2i8.i64( [[DEST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]])
-// CHECK-RV64-NEXT:ret  [[TMP0]]
-//
-vint8mf4_t test_vmv_s_x_i8mf4(vint8mf4_t dest, int8_t src, size_t vl) {
-  return vmv_s(dest, src, vl);
-}
-
 // CHECK-RV64-LABEL: @test_vmv_x_s_i8mf2_i8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv4i8( [[SRC:%.*]])
@@ -583,15 +565,6 @@
   return vmv_x(src);
 }
 
-// CHECK-RV64-LABEL: @test_vmv_s_x_i8mf2(
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmv.s.x.nxv4i8.i64( [[DEST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]])
-// CHECK-RV64-NEXT:ret  [[TMP0]]
-//
-vint8mf2_t test_vmv_s_x_i8mf2(vint8mf2_t dest, int8_t src, size_t vl) {
-  return vmv_s(dest, src, vl);
-}
-
 // CHECK-RV64-LABEL: @test_vmv_x_s_i8m1_i8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv8i8( [[SRC:%.*]])
@@ -601,15 +574,6 @@
   return vmv_x(src);
 }
 
-// CHECK-RV64-LABEL: @test_vmv_s_x_i8m1(
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmv.s.x.nxv8i8.i64( [[DEST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]])
-// CHECK-RV64-NEXT:ret  [[TMP0]]
-//
-vint8m1_t test_vmv_s_x_i8m1(vint8m1_t dest, int8_t src, size_t vl) {
-  return vmv_s(dest, src, vl);
-}
-
 // CHECK-RV64-LABEL: @test_vmv_x_s_i8m2_i8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv16i8( [[SRC:%.*]])
@@ -619,15 +583,6 @@
   return vmv_x(src);
 }
 
-// CHECK-RV64-LABEL: @test_vmv_s_x_i8m2(
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmv.s.x.nxv16i8.i64( [[DEST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]])
-// CHECK-RV64-NEXT:ret  [[TMP0]]
-//
-vint8m2_t test_vmv_s_x_i8m2(vint8m2_t dest, int8_t src, size_t vl) {
-  return vmv_s(dest, src, vl);
-}
-
 // CHECK-RV64-LABEL: @test_vmv_x_s_i8m4_i8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv32i8( [[SRC:%.*]])
@@ -637,15 +592,6 @@
   return vmv_x(src);
 }
 
-// CHECK-RV64-LABEL: @test_vmv_s_x_i8m4(
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmv.s.x.nxv32i8.i64( [[DEST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]])
-// CHECK-RV64-NEXT:ret  [[TMP0]]
-//
-vint8m4_t test_vmv_s_x_i8m4(vint8m4_t dest, int8_t src, size_t vl) {
-  return vmv_s(dest, src, vl);
-}
-
 // CHECK-RV64-LABEL: @test_vmv_x_s_i8m8_i8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv64i8( [[SRC:%.*]])
@@ -655,15 +601,6 @@
   return vmv_x(src);
 }
 
-// CHECK-RV64-LABEL: @test_vmv_s_x_i8m8(
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmv.s.x.nxv64i8.i64( [[DEST:%.*]], i8 [[SRC:%.*]], i64 [[VL:%.*]])
-// CHECK-RV64-NEXT:ret  [[TMP0]]
-//
-vint8m8_t test_vmv_s_x_i8m8(vint8m8_t dest, int8_t src, size_t vl) {
-  return vmv_s(dest, src, vl);
-}
-
 // CHECK-RV64-LABEL: @test_vmv_x_s_i16mf4_i16(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv1i16( [[SRC:%.*]])
@@ -673,15 +610,6 @@
   return vmv_x(src);
 }
 
-// CHECK-RV64-LABEL: @test_vmv_s_x_i16mf4

[PATCH] D140954: [7/7][Clang][RISCV][NFC] Remove attribute `IsPrototypeDefaultTU`

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 488157.
eopXD added a comment.

Rebase on top of landing of D141198 .


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140954/new/

https://reviews.llvm.org/D140954

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -66,7 +66,6 @@
   bool HasMasked :1;
   bool HasVL :1;
   bool HasMaskedOffOperand :1;
-  bool IsPrototypeDefaultTU : 1;
   bool HasTailPolicy : 1;
   bool HasMaskPolicy : 1;
   uint8_t UnMaskedPolicyScheme : 2;
@@ -518,7 +517,6 @@
 std::vector Log2LMULList = R->getValueAsListOfInts("Log2LMUL");
 bool HasTailPolicy = R->getValueAsBit("HasTailPolicy");
 bool HasMaskPolicy = R->getValueAsBit("HasMaskPolicy");
-bool IsPrototypeDefaultTU = R->getValueAsBit("IsPrototypeDefaultTU");
 bool SupportOverloading = R->getValueAsBit("SupportOverloading");
 bool HasBuiltinAlias = R->getValueAsBit("HasBuiltinAlias");
 StringRef ManualCodegen = R->getValueAsString("ManualCodegen");
@@ -549,13 +547,13 @@
 parsePrototypes(OverloadedSuffixProto);
 
 // Compute Builtin types
-auto Prototype = RVVIntrinsic::computeBuiltinTypes(
-BasicPrototype, /*IsMasked=*/false,
-/*HasMaskedOffOperand=*/false, HasVL, NF, IsPrototypeDefaultTU,
-UnMaskedPolicyScheme, Policy());
+auto Prototype =
+RVVIntrinsic::computeBuiltinTypes(BasicPrototype, /*IsMasked=*/false,
+  /*HasMaskedOffOperand=*/false, HasVL,
+  NF, UnMaskedPolicyScheme, Policy());
 auto MaskedPrototype = RVVIntrinsic::computeBuiltinTypes(
 BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, NF,
-IsPrototypeDefaultTU, MaskedPolicyScheme, Policy());
+MaskedPolicyScheme, Policy());
 
 // Create Intrinsics for each type and LMUL.
 for (char I : TypeRange) {
@@ -577,22 +575,22 @@
 /*IsMasked=*/false, /*HasMaskedOffOperand=*/false, HasVL,
 UnMaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
 ManualCodegen, *Types, IntrinsicTypes, RequiredFeatures, NF,
-Policy(), IsPrototypeDefaultTU));
+Policy()));
 if (UnMaskedPolicyScheme != PolicyScheme::SchemeNone)
   for (auto P : SupportedUnMaskedPolicies) {
 SmallVector PolicyPrototype =
 RVVIntrinsic::computeBuiltinTypes(
 BasicPrototype, /*IsMasked=*/false,
 /*HasMaskedOffOperand=*/false, HasVL, NF,
-IsPrototypeDefaultTU, UnMaskedPolicyScheme, P);
+UnMaskedPolicyScheme, P);
 std::optional PolicyTypes =
 TypeCache.computeTypes(BT, Log2LMUL, NF, PolicyPrototype);
 Out.push_back(std::make_unique(
 Name, SuffixStr, OverloadedName, OverloadedSuffixStr, IRName,
 /*IsMask=*/false, /*HasMaskedOffOperand=*/false, HasVL,
 UnMaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
-ManualCodegen, *PolicyTypes, IntrinsicTypes,
-RequiredFeatures, NF, P, IsPrototypeDefaultTU));
+ManualCodegen, *PolicyTypes, IntrinsicTypes, RequiredFeatures,
+NF, P));
   }
 if (!HasMasked)
   continue;
@@ -602,24 +600,23 @@
 Out.push_back(std::make_unique(
 Name, SuffixStr, OverloadedName, OverloadedSuffixStr, MaskedIRName,
 /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme,
-SupportOverloading, HasBuiltinAlias, ManualCodegen,
-*MaskTypes, IntrinsicTypes, RequiredFeatures, NF,
-Policy(), IsPrototypeDefaultTU));
+SupportOverloading, HasBuiltinAlias, ManualCodegen, *MaskTypes,
+IntrinsicTypes, RequiredFeatures, NF, Policy()));
 if (MaskedPolicyScheme == PolicyScheme::SchemeNone)
   continue;
 for (auto P : SupportedMaskedPolicies) {
   SmallVector PolicyPrototype =
   RVVIntrinsic::computeBuiltinTypes(
   BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL,
-  NF, IsPrototypeDefaultTU, MaskedPolicyScheme, P);
+  NF, MaskedPolicyScheme, P);
   std::optional PolicyTypes =
   TypeCache.computeTypes(BT, Log2LMUL, NF, PolicyPrototype);
   Out.push_back(std::make_unique(
   Name, SuffixStr, OverloadedName, OverloadedSuffixStr,
   MaskedIRName, /*IsMasked=*/t

[PATCH] D137570: [Clang][Sema] Refactor category declaration under CheckForIncompatibleAttributes. NFC

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
eopXD added a reviewer: SjoerdMeijer.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead.
Herald added a project: clang.

This change allows extension of new categories be aware of adding more
code here.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137570

Files:
  clang/lib/Sema/SemaStmtAttr.cpp


Index: clang/lib/Sema/SemaStmtAttr.cpp
===
--- clang/lib/Sema/SemaStmtAttr.cpp
+++ clang/lib/Sema/SemaStmtAttr.cpp
@@ -306,21 +306,30 @@
   if (!DiagnoseMutualExclusions(S, Attrs))
 return;
 
-  // There are 6 categories of loop hints attributes: vectorize, interleave,
-  // unroll, unroll_and_jam, pipeline and distribute. Except for distribute 
they
-  // come in two variants: a state form and a numeric form.  The state form
-  // selectively defaults/enables/disables the transformation for the loop
-  // (for unroll, default indicates full unrolling rather than enabling the
-  // transformation). The numeric form form provides an integer hint (for
-  // example, unroll count) to the transformer. The following array accumulates
-  // the hints encountered while iterating through the attributes to check for
-  // compatibility.
+  enum CategoryType {
+Vectorize,
+Interleave,
+Unroll,
+UnrollAndJam,
+Distribute,
+Pipeline,
+VectorizePredicate,
+NumberOfCategories
+  };
+  // There are 7 categories of loop hints attributes: vectorize, interleave,
+  // unroll, unroll_and_jam, pipeline, distribute, and vectorize predicate.
+  // Except for distribute and vectorize predicate, they come in two variants: 
a
+  // state form and a numeric form.  The state form selectively
+  // defaults/enables/disables the transformation for the loop (for unroll,
+  // default indicates full unrolling rather than enabling the transformation).
+  // The numeric form form provides an integer hint (for example, unroll count)
+  // to the transformer. The following array accumulates the hints encountered
+  // while iterating through the attributes to check for compatibility.
   struct {
 const LoopHintAttr *StateAttr;
 const LoopHintAttr *NumericAttr;
-  } HintAttrs[] = {{nullptr, nullptr}, {nullptr, nullptr}, {nullptr, nullptr},
-   {nullptr, nullptr}, {nullptr, nullptr}, {nullptr, nullptr},
-   {nullptr, nullptr}};
+  } HintAttrs[CategoryType::NumberOfCategories];
+  memset(HintAttrs, 0, sizeof(HintAttrs));
 
   for (const auto *I : Attrs) {
 const LoopHintAttr *LH = dyn_cast(I);
@@ -329,16 +338,8 @@
 if (!LH)
   continue;
 
+CategoryType Category = CategoryType::NumberOfCategories;
 LoopHintAttr::OptionType Option = LH->getOption();
-enum {
-  Vectorize,
-  Interleave,
-  Unroll,
-  UnrollAndJam,
-  Distribute,
-  Pipeline,
-  VectorizePredicate
-} Category;
 switch (Option) {
 case LoopHintAttr::Vectorize:
 case LoopHintAttr::VectorizeWidth:
@@ -369,7 +370,7 @@
   break;
 };
 
-assert(Category < sizeof(HintAttrs) / sizeof(HintAttrs[0]));
+assert(Category != NumberOfCategories && "Unhandled loop hint option");
 auto &CategoryState = HintAttrs[Category];
 const LoopHintAttr *PrevAttr;
 if (Option == LoopHintAttr::Vectorize ||


Index: clang/lib/Sema/SemaStmtAttr.cpp
===
--- clang/lib/Sema/SemaStmtAttr.cpp
+++ clang/lib/Sema/SemaStmtAttr.cpp
@@ -306,21 +306,30 @@
   if (!DiagnoseMutualExclusions(S, Attrs))
 return;
 
-  // There are 6 categories of loop hints attributes: vectorize, interleave,
-  // unroll, unroll_and_jam, pipeline and distribute. Except for distribute they
-  // come in two variants: a state form and a numeric form.  The state form
-  // selectively defaults/enables/disables the transformation for the loop
-  // (for unroll, default indicates full unrolling rather than enabling the
-  // transformation). The numeric form form provides an integer hint (for
-  // example, unroll count) to the transformer. The following array accumulates
-  // the hints encountered while iterating through the attributes to check for
-  // compatibility.
+  enum CategoryType {
+Vectorize,
+Interleave,
+Unroll,
+UnrollAndJam,
+Distribute,
+Pipeline,
+VectorizePredicate,
+NumberOfCategories
+  };
+  // There are 7 categories of loop hints attributes: vectorize, interleave,
+  // unroll, unroll_and_jam, pipeline, distribute, and vectorize predicate.
+  // Except for distribute and vectorize predicate, they come in two variants: a
+  // state form and a numeric form.  The state form selectively
+  // defaults/enables/disables the transformation for the loop (for unroll,
+  // default indicates full unrolling rather than enabling the transformation).
+  // The numeric form form provides an integ

[PATCH] D137570: [Clang][Sema] Refactor category declaration under CheckForIncompatibleAttributes. NFC

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD added a comment.

Upon additional modification to this code base I am tempt to prefer having a 
`NumberOfCategories` under the enum and make the sanity check explicit. I 
understand this is totally a problem of personal taste so definitely feel free 
to argue with me :)


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[PATCH] D137570: [Clang][Sema] Refactor category declaration under CheckForIncompatibleAttributes. NFC

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 475043.
eopXD marked 3 inline comments as done.
eopXD added a comment.

Address comments from reviewers.


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Files:
  clang/lib/Sema/SemaStmtAttr.cpp


Index: clang/lib/Sema/SemaStmtAttr.cpp
===
--- clang/lib/Sema/SemaStmtAttr.cpp
+++ clang/lib/Sema/SemaStmtAttr.cpp
@@ -306,21 +306,34 @@
   if (!DiagnoseMutualExclusions(S, Attrs))
 return;
 
-  // There are 6 categories of loop hints attributes: vectorize, interleave,
-  // unroll, unroll_and_jam, pipeline and distribute. Except for distribute 
they
-  // come in two variants: a state form and a numeric form.  The state form
-  // selectively defaults/enables/disables the transformation for the loop
-  // (for unroll, default indicates full unrolling rather than enabling the
-  // transformation). The numeric form form provides an integer hint (for
-  // example, unroll count) to the transformer. The following array accumulates
-  // the hints encountered while iterating through the attributes to check for
-  // compatibility.
+  enum CategoryType {
+// For the following categories, they come in two variants: a state form 
and
+// a numeric form. The state form may be one of default, enable, and
+// disable. The numeric form provides an integer hint (for example, unroll
+// count) to the transformer.
+Vectorize,
+Interleave,
+UnrollAndJam,
+Pipeline,
+// For unroll, default indicates full unrolling rather than enabling the
+// transformation.
+Unroll,
+// The loop distribution transformation only has a state form that is
+// exposed by
+// #pragma clang loop distribute (enable | disable).
+Distribute,
+// The vector predication only has a state form that is exposed by
+// #pragma clang loop vectorize_predicate (enable | disable).
+VectorizePredicate,
+// This serves as a indicator to how many category are listed in this enum.
+NumberOfCategories
+  };
+  // The following array accumulates the hints encountered while iterating
+  // through the attributes to check for compatibility.
   struct {
 const LoopHintAttr *StateAttr;
 const LoopHintAttr *NumericAttr;
-  } HintAttrs[] = {{nullptr, nullptr}, {nullptr, nullptr}, {nullptr, nullptr},
-   {nullptr, nullptr}, {nullptr, nullptr}, {nullptr, nullptr},
-   {nullptr, nullptr}};
+  } HintAttrs[CategoryType::NumberOfCategories] = {};
 
   for (const auto *I : Attrs) {
 const LoopHintAttr *LH = dyn_cast(I);
@@ -329,16 +342,8 @@
 if (!LH)
   continue;
 
+CategoryType Category = CategoryType::NumberOfCategories;
 LoopHintAttr::OptionType Option = LH->getOption();
-enum {
-  Vectorize,
-  Interleave,
-  Unroll,
-  UnrollAndJam,
-  Distribute,
-  Pipeline,
-  VectorizePredicate
-} Category;
 switch (Option) {
 case LoopHintAttr::Vectorize:
 case LoopHintAttr::VectorizeWidth:
@@ -369,7 +374,7 @@
   break;
 };
 
-assert(Category < sizeof(HintAttrs) / sizeof(HintAttrs[0]));
+assert(Category != NumberOfCategories && "Unhandled loop hint option");
 auto &CategoryState = HintAttrs[Category];
 const LoopHintAttr *PrevAttr;
 if (Option == LoopHintAttr::Vectorize ||


Index: clang/lib/Sema/SemaStmtAttr.cpp
===
--- clang/lib/Sema/SemaStmtAttr.cpp
+++ clang/lib/Sema/SemaStmtAttr.cpp
@@ -306,21 +306,34 @@
   if (!DiagnoseMutualExclusions(S, Attrs))
 return;
 
-  // There are 6 categories of loop hints attributes: vectorize, interleave,
-  // unroll, unroll_and_jam, pipeline and distribute. Except for distribute they
-  // come in two variants: a state form and a numeric form.  The state form
-  // selectively defaults/enables/disables the transformation for the loop
-  // (for unroll, default indicates full unrolling rather than enabling the
-  // transformation). The numeric form form provides an integer hint (for
-  // example, unroll count) to the transformer. The following array accumulates
-  // the hints encountered while iterating through the attributes to check for
-  // compatibility.
+  enum CategoryType {
+// For the following categories, they come in two variants: a state form and
+// a numeric form. The state form may be one of default, enable, and
+// disable. The numeric form provides an integer hint (for example, unroll
+// count) to the transformer.
+Vectorize,
+Interleave,
+UnrollAndJam,
+Pipeline,
+// For unroll, default indicates full unrolling rather than enabling the
+// transformation.
+Unroll,
+// The loop distribution transformation only has a state form that is
+// exposed by
+// #pragma clang loop distribute (enable | disable).
+  

[PATCH] D137570: [Clang][Sema] Refactor category declaration under CheckForIncompatibleAttributes. NFC

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 475044.
eopXD added a comment.

Minor update in comments.


Repository:
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Files:
  clang/lib/Sema/SemaStmtAttr.cpp


Index: clang/lib/Sema/SemaStmtAttr.cpp
===
--- clang/lib/Sema/SemaStmtAttr.cpp
+++ clang/lib/Sema/SemaStmtAttr.cpp
@@ -306,21 +306,33 @@
   if (!DiagnoseMutualExclusions(S, Attrs))
 return;
 
-  // There are 6 categories of loop hints attributes: vectorize, interleave,
-  // unroll, unroll_and_jam, pipeline and distribute. Except for distribute 
they
-  // come in two variants: a state form and a numeric form.  The state form
-  // selectively defaults/enables/disables the transformation for the loop
-  // (for unroll, default indicates full unrolling rather than enabling the
-  // transformation). The numeric form form provides an integer hint (for
-  // example, unroll count) to the transformer. The following array accumulates
-  // the hints encountered while iterating through the attributes to check for
-  // compatibility.
+  enum CategoryType {
+// For the following categories, they come in two variants: a state form 
and
+// a numeric form. The state form may be one of default, enable, and
+// disable. The numeric form provides an integer hint (for example, unroll
+// count) to the transformer.
+Vectorize,
+Interleave,
+UnrollAndJam,
+Pipeline,
+// For unroll, default indicates full unrolling rather than enabling the
+// transformation.
+Unroll,
+// The loop distribution transformation only has a state form that is
+// exposed by #pragma clang loop distribute (enable | disable).
+Distribute,
+// The vector predication only has a state form that is exposed by
+// #pragma clang loop vectorize_predicate (enable | disable).
+VectorizePredicate,
+// This serves as a indicator to how many category are listed in this enum.
+NumberOfCategories
+  };
+  // The following array accumulates the hints encountered while iterating
+  // through the attributes to check for compatibility.
   struct {
 const LoopHintAttr *StateAttr;
 const LoopHintAttr *NumericAttr;
-  } HintAttrs[] = {{nullptr, nullptr}, {nullptr, nullptr}, {nullptr, nullptr},
-   {nullptr, nullptr}, {nullptr, nullptr}, {nullptr, nullptr},
-   {nullptr, nullptr}};
+  } HintAttrs[CategoryType::NumberOfCategories] = {};
 
   for (const auto *I : Attrs) {
 const LoopHintAttr *LH = dyn_cast(I);
@@ -329,16 +341,8 @@
 if (!LH)
   continue;
 
+CategoryType Category = CategoryType::NumberOfCategories;
 LoopHintAttr::OptionType Option = LH->getOption();
-enum {
-  Vectorize,
-  Interleave,
-  Unroll,
-  UnrollAndJam,
-  Distribute,
-  Pipeline,
-  VectorizePredicate
-} Category;
 switch (Option) {
 case LoopHintAttr::Vectorize:
 case LoopHintAttr::VectorizeWidth:
@@ -369,7 +373,7 @@
   break;
 };
 
-assert(Category < sizeof(HintAttrs) / sizeof(HintAttrs[0]));
+assert(Category != NumberOfCategories && "Unhandled loop hint option");
 auto &CategoryState = HintAttrs[Category];
 const LoopHintAttr *PrevAttr;
 if (Option == LoopHintAttr::Vectorize ||


Index: clang/lib/Sema/SemaStmtAttr.cpp
===
--- clang/lib/Sema/SemaStmtAttr.cpp
+++ clang/lib/Sema/SemaStmtAttr.cpp
@@ -306,21 +306,33 @@
   if (!DiagnoseMutualExclusions(S, Attrs))
 return;
 
-  // There are 6 categories of loop hints attributes: vectorize, interleave,
-  // unroll, unroll_and_jam, pipeline and distribute. Except for distribute they
-  // come in two variants: a state form and a numeric form.  The state form
-  // selectively defaults/enables/disables the transformation for the loop
-  // (for unroll, default indicates full unrolling rather than enabling the
-  // transformation). The numeric form form provides an integer hint (for
-  // example, unroll count) to the transformer. The following array accumulates
-  // the hints encountered while iterating through the attributes to check for
-  // compatibility.
+  enum CategoryType {
+// For the following categories, they come in two variants: a state form and
+// a numeric form. The state form may be one of default, enable, and
+// disable. The numeric form provides an integer hint (for example, unroll
+// count) to the transformer.
+Vectorize,
+Interleave,
+UnrollAndJam,
+Pipeline,
+// For unroll, default indicates full unrolling rather than enabling the
+// transformation.
+Unroll,
+// The loop distribution transformation only has a state form that is
+// exposed by #pragma clang loop distribute (enable | disable).
+Distribute,
+// The vector predication only has a state f

[PATCH] D137570: [Clang][Sema] Refactor category declaration under CheckForIncompatibleAttributes. NFC

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD added a comment.

@mikerice @jyu2
May you accept the revision please if this patch looks good to you? Thank you :)


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[PATCH] D137570: [Clang][Sema] Refactor category declaration under CheckForIncompatibleAttributes. NFC

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 475563.
eopXD added a comment.

Rebase to latest main.


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Files:
  clang/lib/Sema/SemaStmtAttr.cpp


Index: clang/lib/Sema/SemaStmtAttr.cpp
===
--- clang/lib/Sema/SemaStmtAttr.cpp
+++ clang/lib/Sema/SemaStmtAttr.cpp
@@ -306,21 +306,33 @@
   if (!DiagnoseMutualExclusions(S, Attrs))
 return;
 
-  // There are 6 categories of loop hints attributes: vectorize, interleave,
-  // unroll, unroll_and_jam, pipeline and distribute. Except for distribute 
they
-  // come in two variants: a state form and a numeric form.  The state form
-  // selectively defaults/enables/disables the transformation for the loop
-  // (for unroll, default indicates full unrolling rather than enabling the
-  // transformation). The numeric form provides an integer hint (for
-  // example, unroll count) to the transformer. The following array accumulates
-  // the hints encountered while iterating through the attributes to check for
-  // compatibility.
+  enum CategoryType {
+// For the following categories, they come in two variants: a state form 
and
+// a numeric form. The state form may be one of default, enable, and
+// disable. The numeric form provides an integer hint (for example, unroll
+// count) to the transformer.
+Vectorize,
+Interleave,
+UnrollAndJam,
+Pipeline,
+// For unroll, default indicates full unrolling rather than enabling the
+// transformation.
+Unroll,
+// The loop distribution transformation only has a state form that is
+// exposed by #pragma clang loop distribute (enable | disable).
+Distribute,
+// The vector predication only has a state form that is exposed by
+// #pragma clang loop vectorize_predicate (enable | disable).
+VectorizePredicate,
+// This serves as a indicator to how many category are listed in this enum.
+NumberOfCategories
+  };
+  // The following array accumulates the hints encountered while iterating
+  // through the attributes to check for compatibility.
   struct {
 const LoopHintAttr *StateAttr;
 const LoopHintAttr *NumericAttr;
-  } HintAttrs[] = {{nullptr, nullptr}, {nullptr, nullptr}, {nullptr, nullptr},
-   {nullptr, nullptr}, {nullptr, nullptr}, {nullptr, nullptr},
-   {nullptr, nullptr}};
+  } HintAttrs[CategoryType::NumberOfCategories] = {};
 
   for (const auto *I : Attrs) {
 const LoopHintAttr *LH = dyn_cast(I);
@@ -329,16 +341,8 @@
 if (!LH)
   continue;
 
+CategoryType Category = CategoryType::NumberOfCategories;
 LoopHintAttr::OptionType Option = LH->getOption();
-enum {
-  Vectorize,
-  Interleave,
-  Unroll,
-  UnrollAndJam,
-  Distribute,
-  Pipeline,
-  VectorizePredicate
-} Category;
 switch (Option) {
 case LoopHintAttr::Vectorize:
 case LoopHintAttr::VectorizeWidth:
@@ -369,7 +373,7 @@
   break;
 };
 
-assert(Category < sizeof(HintAttrs) / sizeof(HintAttrs[0]));
+assert(Category != NumberOfCategories && "Unhandled loop hint option");
 auto &CategoryState = HintAttrs[Category];
 const LoopHintAttr *PrevAttr;
 if (Option == LoopHintAttr::Vectorize ||


Index: clang/lib/Sema/SemaStmtAttr.cpp
===
--- clang/lib/Sema/SemaStmtAttr.cpp
+++ clang/lib/Sema/SemaStmtAttr.cpp
@@ -306,21 +306,33 @@
   if (!DiagnoseMutualExclusions(S, Attrs))
 return;
 
-  // There are 6 categories of loop hints attributes: vectorize, interleave,
-  // unroll, unroll_and_jam, pipeline and distribute. Except for distribute they
-  // come in two variants: a state form and a numeric form.  The state form
-  // selectively defaults/enables/disables the transformation for the loop
-  // (for unroll, default indicates full unrolling rather than enabling the
-  // transformation). The numeric form provides an integer hint (for
-  // example, unroll count) to the transformer. The following array accumulates
-  // the hints encountered while iterating through the attributes to check for
-  // compatibility.
+  enum CategoryType {
+// For the following categories, they come in two variants: a state form and
+// a numeric form. The state form may be one of default, enable, and
+// disable. The numeric form provides an integer hint (for example, unroll
+// count) to the transformer.
+Vectorize,
+Interleave,
+UnrollAndJam,
+Pipeline,
+// For unroll, default indicates full unrolling rather than enabling the
+// transformation.
+Unroll,
+// The loop distribution transformation only has a state form that is
+// exposed by #pragma clang loop distribute (enable | disable).
+Distribute,
+// The vector predication only has a state form that is e

[PATCH] D137570: [Clang][Sema] Refactor category declaration under CheckForIncompatibleAttributes. NFC

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG6dee23919a36: [Clang][Sema] Refactor category declaration 
under… (authored by eopXD).

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Files:
  clang/lib/Sema/SemaStmtAttr.cpp


Index: clang/lib/Sema/SemaStmtAttr.cpp
===
--- clang/lib/Sema/SemaStmtAttr.cpp
+++ clang/lib/Sema/SemaStmtAttr.cpp
@@ -306,21 +306,33 @@
   if (!DiagnoseMutualExclusions(S, Attrs))
 return;
 
-  // There are 6 categories of loop hints attributes: vectorize, interleave,
-  // unroll, unroll_and_jam, pipeline and distribute. Except for distribute 
they
-  // come in two variants: a state form and a numeric form.  The state form
-  // selectively defaults/enables/disables the transformation for the loop
-  // (for unroll, default indicates full unrolling rather than enabling the
-  // transformation). The numeric form provides an integer hint (for
-  // example, unroll count) to the transformer. The following array accumulates
-  // the hints encountered while iterating through the attributes to check for
-  // compatibility.
+  enum CategoryType {
+// For the following categories, they come in two variants: a state form 
and
+// a numeric form. The state form may be one of default, enable, and
+// disable. The numeric form provides an integer hint (for example, unroll
+// count) to the transformer.
+Vectorize,
+Interleave,
+UnrollAndJam,
+Pipeline,
+// For unroll, default indicates full unrolling rather than enabling the
+// transformation.
+Unroll,
+// The loop distribution transformation only has a state form that is
+// exposed by #pragma clang loop distribute (enable | disable).
+Distribute,
+// The vector predication only has a state form that is exposed by
+// #pragma clang loop vectorize_predicate (enable | disable).
+VectorizePredicate,
+// This serves as a indicator to how many category are listed in this enum.
+NumberOfCategories
+  };
+  // The following array accumulates the hints encountered while iterating
+  // through the attributes to check for compatibility.
   struct {
 const LoopHintAttr *StateAttr;
 const LoopHintAttr *NumericAttr;
-  } HintAttrs[] = {{nullptr, nullptr}, {nullptr, nullptr}, {nullptr, nullptr},
-   {nullptr, nullptr}, {nullptr, nullptr}, {nullptr, nullptr},
-   {nullptr, nullptr}};
+  } HintAttrs[CategoryType::NumberOfCategories] = {};
 
   for (const auto *I : Attrs) {
 const LoopHintAttr *LH = dyn_cast(I);
@@ -329,16 +341,8 @@
 if (!LH)
   continue;
 
+CategoryType Category = CategoryType::NumberOfCategories;
 LoopHintAttr::OptionType Option = LH->getOption();
-enum {
-  Vectorize,
-  Interleave,
-  Unroll,
-  UnrollAndJam,
-  Distribute,
-  Pipeline,
-  VectorizePredicate
-} Category;
 switch (Option) {
 case LoopHintAttr::Vectorize:
 case LoopHintAttr::VectorizeWidth:
@@ -369,7 +373,7 @@
   break;
 };
 
-assert(Category < sizeof(HintAttrs) / sizeof(HintAttrs[0]));
+assert(Category != NumberOfCategories && "Unhandled loop hint option");
 auto &CategoryState = HintAttrs[Category];
 const LoopHintAttr *PrevAttr;
 if (Option == LoopHintAttr::Vectorize ||


Index: clang/lib/Sema/SemaStmtAttr.cpp
===
--- clang/lib/Sema/SemaStmtAttr.cpp
+++ clang/lib/Sema/SemaStmtAttr.cpp
@@ -306,21 +306,33 @@
   if (!DiagnoseMutualExclusions(S, Attrs))
 return;
 
-  // There are 6 categories of loop hints attributes: vectorize, interleave,
-  // unroll, unroll_and_jam, pipeline and distribute. Except for distribute they
-  // come in two variants: a state form and a numeric form.  The state form
-  // selectively defaults/enables/disables the transformation for the loop
-  // (for unroll, default indicates full unrolling rather than enabling the
-  // transformation). The numeric form provides an integer hint (for
-  // example, unroll count) to the transformer. The following array accumulates
-  // the hints encountered while iterating through the attributes to check for
-  // compatibility.
+  enum CategoryType {
+// For the following categories, they come in two variants: a state form and
+// a numeric form. The state form may be one of default, enable, and
+// disable. The numeric form provides an integer hint (for example, unroll
+// count) to the transformer.
+Vectorize,
+Interleave,
+UnrollAndJam,
+Pipeline,
+// For unroll, default indicates full unrolling rather than enabling the
+// transformation.
+Unroll,
+// The loop distribution transformation only has a state form that is
+// exposed by #pragma clang loop distribute (enable | d

[PATCH] D141756: [6/15][Clang][RISCV][NFC] Instructions with a mask destination register is always tail agnostic

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGecbf5db88d28: [6/15][Clang][RISCV][NFC] Instructions with a 
mask destination register is… (authored by eopXD).

Changed prior to commit:
  https://reviews.llvm.org/D141756?vs=489301&id=491650#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141756/new/

https://reviews.llvm.org/D141756

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -915,9 +915,6 @@
 PolicyScheme DefaultScheme, Policy PolicyAttrs) {
   SmallVector NewPrototype(Prototype.begin(),
 Prototype.end());
-  // Update PolicyAttrs if need (TA or TAMA) for compute builtin types.
-  if (PolicyAttrs.isMAPolicy())
-PolicyAttrs.TailPolicy = Policy::PolicyType::Agnostic; // TAMA
   bool HasPassthruOp = DefaultScheme == PolicyScheme::HasPassthruOperand;
   if (IsMasked) {
 // If HasMaskedOffOperand, insert result type as first input operand if
@@ -998,10 +995,11 @@
 Policy(Policy::PolicyType::Agnostic, Policy::PolicyType::Agnostic,
HasTailPolicy, HasMaskPolicy)}; // TAM
   if (!HasTailPolicy && HasMaskPolicy)
-return {Policy(Policy::PolicyType::Omit, Policy::PolicyType::Agnostic,
+return {Policy(Policy::PolicyType::Agnostic, Policy::PolicyType::Agnostic,
HasTailPolicy, HasMaskPolicy), // MA
-Policy(Policy::PolicyType::Omit, Policy::PolicyType::Undisturbed,
-   HasTailPolicy, HasMaskPolicy)}; // MU
+Policy(Policy::PolicyType::Agnostic,
+   Policy::PolicyType::Undisturbed, HasTailPolicy,
+   HasMaskPolicy)}; // MU
   llvm_unreachable("An RVV instruction should not be without both tail policy "
"and mask policy");
 }
@@ -1040,6 +1038,10 @@
   appendPolicySuffix("_tum");
 else if (PolicyAttrs.isTAMAPolicy() && !PolicyAttrs.hasMaskPolicy())
   appendPolicySuffix("_tam");
+else if (PolicyAttrs.isMUPolicy() && !PolicyAttrs.hasTailPolicy())
+  appendPolicySuffix("_mu");
+else if (PolicyAttrs.isMAPolicy() && !PolicyAttrs.hasTailPolicy())
+  appendPolicySuffix("_ma");
 else if (PolicyAttrs.isTUMUPolicy())
   appendPolicySuffix("_tumu");
 else if (PolicyAttrs.isTAMUPolicy())
@@ -1052,13 +1054,7 @@
   appendPolicySuffix("_tu");
 else if (PolicyAttrs.isTAPolicy() && !IsMasked)
   appendPolicySuffix("_ta");
-else if (PolicyAttrs.isMUPolicy() && !PolicyAttrs.hasTailPolicy()) {
-  appendPolicySuffix("_mu");
-  PolicyAttrs.TailPolicy = Policy::PolicyType::Agnostic;
-} else if (PolicyAttrs.isMAPolicy() && !PolicyAttrs.hasTailPolicy()) {
-  appendPolicySuffix("_ma");
-  PolicyAttrs.TailPolicy = Policy::PolicyType::Agnostic;
-} else
+else
   llvm_unreachable("Unhandled policy condition");
   }
 }
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -134,13 +134,9 @@
 return TailPolicy == Undisturbed && MaskPolicy == Omit;
   }
 
-  bool isMAPolicy() const {
-return MaskPolicy == Agnostic && TailPolicy == Omit;
-  }
+  bool isMAPolicy() const { return MaskPolicy == Agnostic; }
 
-  bool isMUPolicy() const {
-return MaskPolicy == Undisturbed && TailPolicy == Omit;
-  }
+  bool isMUPolicy() const { return MaskPolicy == Undisturbed; }
 
   bool hasTailPolicy() const { return HasTailPolicy; }
 


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -915,9 +915,6 @@
 PolicyScheme DefaultScheme, Policy PolicyAttrs) {
   SmallVector NewPrototype(Prototype.begin(),
 Prototype.end());
-  // Update PolicyAttrs if need (TA or TAMA) for compute builtin types.
-  if (PolicyAttrs.isMAPolicy())
-PolicyAttrs.TailPolicy = Policy::PolicyType::Agnostic; // TAMA
   bool HasPassthruOp = DefaultScheme == PolicyScheme::HasPassthruOperand;
   if (IsMasked) {
 // If HasMaskedOffOperand, insert result type as first input operand if
@@ -998,10 +995,11 @@
 Policy(Policy::PolicyType::Agnostic, Policy::PolicyType::Agnostic,
HasTailPolicy, HasMaskPolicy)}; // TAM
   if (!HasTailPolicy && HasMaskPolicy)
-return {Policy(Policy::PolicyType::Omit, Policy::PolicyType::Agnostic,
+return {Policy(Policy:

[PATCH] D141759: [7/15][Clang][RISCV][NFC] Correct the default value for Policy to TAMU

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2a16e1ff7d27: [7/15][Clang][RISCV][NFC] Correct the default 
value for Policy to TAMU (authored by eopXD).

Changed prior to commit:
  https://reviews.llvm.org/D141759?vs=489302&id=491657#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141759/new/

https://reviews.llvm.org/D141759

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h


Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -99,8 +99,8 @@
 Agnostic,
 Omit, // No policy required.
   };
-  PolicyType TailPolicy = Omit;
-  PolicyType MaskPolicy = Omit;
+  PolicyType TailPolicy = Agnostic;
+  PolicyType MaskPolicy = Undisturbed;
   bool HasTailPolicy, HasMaskPolicy;
   Policy(bool HasTailPolicy, bool HasMaskPolicy)
   : IsUnspecified(true), HasTailPolicy(HasTailPolicy),


Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -99,8 +99,8 @@
 Agnostic,
 Omit, // No policy required.
   };
-  PolicyType TailPolicy = Omit;
-  PolicyType MaskPolicy = Omit;
+  PolicyType TailPolicy = Agnostic;
+  PolicyType MaskPolicy = Undisturbed;
   bool HasTailPolicy, HasMaskPolicy;
   Policy(bool HasTailPolicy, bool HasMaskPolicy)
   : IsUnspecified(true), HasTailPolicy(HasTailPolicy),
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