[clang] [NFC][Clang][RISCV] Fix index typos of riscv-v-spec doc in riscv_vector.td (PR #65944)

2023-09-11 Thread Ying Chen via cfe-commits 

https://github.com/punkyc created 
https://github.com/llvm/llvm-project/pull/65944:

Fix index typos, s.t. indexes in comments be same with riscv-v-spec doc. 

>From 01a0763aa8c624834c5f6a98df22e75f3f5ae96b Mon Sep 17 00:00:00 2001
From: Ying Chen 
Date: Mon, 11 Sep 2023 18:36:22 +0800
Subject: [PATCH] [NFC][Clang][RISCV] Fix index typos of riscv-v-spec doc in 
 riscv_vector.td

---
 clang/include/clang/Basic/riscv_vector.td | 168 +++---
 1 file changed, 84 insertions(+), 84 deletions(-)

diff --git a/clang/include/clang/Basic/riscv_vector.td 
b/clang/include/clang/Basic/riscv_vector.td
index 9b941e1cca85014..6f9f4ce0dd1916b 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -1601,8 +1601,8 @@ defm : RVVIndexedSegStoreTuple<"vsuxseg">;
 defm : RVVIndexedSegStoreTuple<"vsoxseg">;
 }
 
-// 12. Vector Integer Arithmetic Instructions
-// 12.1. Vector Single-Width Integer Add and Subtract
+// 11. Vector Integer Arithmetic Instructions
+// 11.1. Vector Single-Width Integer Add and Subtract
 let UnMaskedPolicyScheme = HasPassthruOperand in {
 defm vadd : RVVIntBinBuiltinSet;
 defm vsub : RVVIntBinBuiltinSet;
@@ -1612,7 +1612,7 @@ defm vrsub : RVVOutOp1BuiltinSet<"vrsub", "csil",
 }
 defm vneg_v : RVVPseudoUnaryBuiltin<"vrsub", "csil">;
 
-// 12.2. Vector Widening Integer Add/Subtract
+// 11.2. Vector Widening Integer Add/Subtract
 // Widening unsigned integer add/subtract, 2*SEW = SEW +/- SEW
 let UnMaskedPolicyScheme = HasPassthruOperand in {
 defm vwaddu : RVVUnsignedWidenBinBuiltinSet;
@@ -1632,7 +1632,7 @@ defm vwcvtu_x_x_v : RVVPseudoVWCVTBuiltin<"vwaddu", 
"vwcvtu_x", "csi",
 defm vwcvt_x_x_v : RVVPseudoVWCVTBuiltin<"vwadd", "vwcvt_x", "csi",
  [["w", "wv"]]>;
 
-// 12.3. Vector Integer Extension
+// 11.3. Vector Integer Extension
 let UnMaskedPolicyScheme = HasPassthruOperand in {
 let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
   def vsext_vf2 : RVVIntExt<"vsext", "w", "wv", "csi">;
@@ -1648,7 +1648,7 @@ let Log2LMUL = [-3, -2, -1, 0] in {
 }
 }
 
-// 12.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
+// 11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
 let HasMasked = false, MaskedPolicyScheme = NonePolicy in {
   let UnMaskedPolicyScheme = HasPassthruOperand in {
 defm vadc : RVVCarryinBuiltinSet;
@@ -1660,7 +1660,7 @@ let HasMasked = false, MaskedPolicyScheme = NonePolicy in 
{
   defm vmsbc : RVVIntMaskOutBuiltinSet;
 }
 
-// 12.5. Vector Bitwise Logical Instructions
+// 11.5. Vector Bitwise Logical Instructions
 let UnMaskedPolicyScheme = HasPassthruOperand in {
 defm vand : RVVIntBinBuiltinSet;
 defm vxor : RVVIntBinBuiltinSet;
@@ -1668,13 +1668,13 @@ defm vor : RVVIntBinBuiltinSet;
 }
 defm vnot_v : RVVPseudoVNotBuiltin<"vxor", "csil">;
 
-// 12.6. Vector Single-Width Bit Shift Instructions
+// 11.6. Vector Single-Width Bit Shift Instructions
 let UnMaskedPolicyScheme = HasPassthruOperand in {
 defm vsll : RVVShiftBuiltinSet;
 defm vsrl : RVVUnsignedShiftBuiltinSet;
 defm vsra : RVVSignedShiftBuiltinSet;
 
-// 12.7. Vector Narrowing Integer Right Shift Instructions
+// 11.7. Vector Narrowing Integer Right Shift Instructions
 defm vnsrl : RVVUnsignedNShiftBuiltinSet;
 defm vnsra : RVVSignedNShiftBuiltinSet;
 }
@@ -1682,7 +1682,7 @@ defm vncvt_x_x_w : RVVPseudoVNCVTBuiltin<"vnsrl", 
"vncvt_x", "csi",
  [["v", "vw"],
   ["Uv", "UvUw"]]>;
 
-// 12.8. Vector Integer Comparison Instructions
+// 11.8. Vector Integer Comparison Instructions
 let MaskedPolicyScheme = HasPassthruOperand,
 HasTailPolicy = false in {
 defm vmseq : RVVIntMaskOutBuiltinSet;
@@ -1697,14 +1697,14 @@ defm vmsgeu : RVVUnsignedMaskOutBuiltinSet;
 defm vmsge : RVVSignedMaskOutBuiltinSet;
 }
 
-// 12.9. Vector Integer Min/Max Instructions
+// 11.9. Vector Integer Min/Max Instructions
 let UnMaskedPolicyScheme = HasPassthruOperand in {
 defm vminu : RVVUnsignedBinBuiltinSet;
 defm vmin : RVVSignedBinBuiltinSet;
 defm vmaxu : RVVUnsignedBinBuiltinSet;
 defm vmax : RVVSignedBinBuiltinSet;
 
-// 12.10. Vector Single-Width Integer Multiply Instructions
+// 11.10. Vector Single-Width Integer Multiply Instructions
 defm vmul : RVVIntBinBuiltinSet;
 defm vmulh : RVVSignedBinBuiltinSet;
 defm vmulhu : RVVUnsignedBinBuiltinSet;
@@ -1712,14 +1712,14 @@ defm vmulhsu : RVVOutOp1BuiltinSet<"vmulhsu", "csil",
[["vv", "v", "vvUv"],
 ["vx", "v", "vvUe"]]>;
 
-// 12.11. Vector Integer Divide Instructions
+// 11.11. Vector Integer Divide Instructions
 defm vdivu : RVVUnsignedBinBuiltinSet;
 defm vdiv : RVVSignedBinBuiltinSet;
 defm vremu : RVVUnsignedBinBuiltinSet;
 defm vrem : RVVSignedBinBuiltinSet;
 }
 
-// 12.12. Vector Widening Integer Multiply Instructions
+// 11.12. Vector Widening Integer Multiply Instructions
 let Log2LMUL = [-3, -2, -1, 0

[clang] [NFC][Clang][RISCV] Fix index typos of riscv-v-spec doc in riscv_vector.td (PR #65944)

2023-09-11 Thread Ying Chen via cfe-commits 

https://github.com/punkyc review_requested 
https://github.com/llvm/llvm-project/pull/65944
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[clang] [NFC][Clang][RISCV] Fix index typos of riscv-v-spec doc in riscv_vector.td (PR #65944)

2023-09-11 Thread Ying Chen via cfe-commits 

https://github.com/punkyc updated 
https://github.com/llvm/llvm-project/pull/65944:

>From 01a0763aa8c624834c5f6a98df22e75f3f5ae96b Mon Sep 17 00:00:00 2001
From: Ying Chen 
Date: Mon, 11 Sep 2023 18:36:22 +0800
Subject: [PATCH 1/2] [NFC][Clang][RISCV] Fix index typos of riscv-v-spec doc
 in  riscv_vector.td

---
 clang/include/clang/Basic/riscv_vector.td | 168 +++---
 1 file changed, 84 insertions(+), 84 deletions(-)

diff --git a/clang/include/clang/Basic/riscv_vector.td 
b/clang/include/clang/Basic/riscv_vector.td
index 9b941e1cca85014..6f9f4ce0dd1916b 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -1601,8 +1601,8 @@ defm : RVVIndexedSegStoreTuple<"vsuxseg">;
 defm : RVVIndexedSegStoreTuple<"vsoxseg">;
 }
 
-// 12. Vector Integer Arithmetic Instructions
-// 12.1. Vector Single-Width Integer Add and Subtract
+// 11. Vector Integer Arithmetic Instructions
+// 11.1. Vector Single-Width Integer Add and Subtract
 let UnMaskedPolicyScheme = HasPassthruOperand in {
 defm vadd : RVVIntBinBuiltinSet;
 defm vsub : RVVIntBinBuiltinSet;
@@ -1612,7 +1612,7 @@ defm vrsub : RVVOutOp1BuiltinSet<"vrsub", "csil",
 }
 defm vneg_v : RVVPseudoUnaryBuiltin<"vrsub", "csil">;
 
-// 12.2. Vector Widening Integer Add/Subtract
+// 11.2. Vector Widening Integer Add/Subtract
 // Widening unsigned integer add/subtract, 2*SEW = SEW +/- SEW
 let UnMaskedPolicyScheme = HasPassthruOperand in {
 defm vwaddu : RVVUnsignedWidenBinBuiltinSet;
@@ -1632,7 +1632,7 @@ defm vwcvtu_x_x_v : RVVPseudoVWCVTBuiltin<"vwaddu", 
"vwcvtu_x", "csi",
 defm vwcvt_x_x_v : RVVPseudoVWCVTBuiltin<"vwadd", "vwcvt_x", "csi",
  [["w", "wv"]]>;
 
-// 12.3. Vector Integer Extension
+// 11.3. Vector Integer Extension
 let UnMaskedPolicyScheme = HasPassthruOperand in {
 let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
   def vsext_vf2 : RVVIntExt<"vsext", "w", "wv", "csi">;
@@ -1648,7 +1648,7 @@ let Log2LMUL = [-3, -2, -1, 0] in {
 }
 }
 
-// 12.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
+// 11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
 let HasMasked = false, MaskedPolicyScheme = NonePolicy in {
   let UnMaskedPolicyScheme = HasPassthruOperand in {
 defm vadc : RVVCarryinBuiltinSet;
@@ -1660,7 +1660,7 @@ let HasMasked = false, MaskedPolicyScheme = NonePolicy in 
{
   defm vmsbc : RVVIntMaskOutBuiltinSet;
 }
 
-// 12.5. Vector Bitwise Logical Instructions
+// 11.5. Vector Bitwise Logical Instructions
 let UnMaskedPolicyScheme = HasPassthruOperand in {
 defm vand : RVVIntBinBuiltinSet;
 defm vxor : RVVIntBinBuiltinSet;
@@ -1668,13 +1668,13 @@ defm vor : RVVIntBinBuiltinSet;
 }
 defm vnot_v : RVVPseudoVNotBuiltin<"vxor", "csil">;
 
-// 12.6. Vector Single-Width Bit Shift Instructions
+// 11.6. Vector Single-Width Bit Shift Instructions
 let UnMaskedPolicyScheme = HasPassthruOperand in {
 defm vsll : RVVShiftBuiltinSet;
 defm vsrl : RVVUnsignedShiftBuiltinSet;
 defm vsra : RVVSignedShiftBuiltinSet;
 
-// 12.7. Vector Narrowing Integer Right Shift Instructions
+// 11.7. Vector Narrowing Integer Right Shift Instructions
 defm vnsrl : RVVUnsignedNShiftBuiltinSet;
 defm vnsra : RVVSignedNShiftBuiltinSet;
 }
@@ -1682,7 +1682,7 @@ defm vncvt_x_x_w : RVVPseudoVNCVTBuiltin<"vnsrl", 
"vncvt_x", "csi",
  [["v", "vw"],
   ["Uv", "UvUw"]]>;
 
-// 12.8. Vector Integer Comparison Instructions
+// 11.8. Vector Integer Comparison Instructions
 let MaskedPolicyScheme = HasPassthruOperand,
 HasTailPolicy = false in {
 defm vmseq : RVVIntMaskOutBuiltinSet;
@@ -1697,14 +1697,14 @@ defm vmsgeu : RVVUnsignedMaskOutBuiltinSet;
 defm vmsge : RVVSignedMaskOutBuiltinSet;
 }
 
-// 12.9. Vector Integer Min/Max Instructions
+// 11.9. Vector Integer Min/Max Instructions
 let UnMaskedPolicyScheme = HasPassthruOperand in {
 defm vminu : RVVUnsignedBinBuiltinSet;
 defm vmin : RVVSignedBinBuiltinSet;
 defm vmaxu : RVVUnsignedBinBuiltinSet;
 defm vmax : RVVSignedBinBuiltinSet;
 
-// 12.10. Vector Single-Width Integer Multiply Instructions
+// 11.10. Vector Single-Width Integer Multiply Instructions
 defm vmul : RVVIntBinBuiltinSet;
 defm vmulh : RVVSignedBinBuiltinSet;
 defm vmulhu : RVVUnsignedBinBuiltinSet;
@@ -1712,14 +1712,14 @@ defm vmulhsu : RVVOutOp1BuiltinSet<"vmulhsu", "csil",
[["vv", "v", "vvUv"],
 ["vx", "v", "vvUe"]]>;
 
-// 12.11. Vector Integer Divide Instructions
+// 11.11. Vector Integer Divide Instructions
 defm vdivu : RVVUnsignedBinBuiltinSet;
 defm vdiv : RVVSignedBinBuiltinSet;
 defm vremu : RVVUnsignedBinBuiltinSet;
 defm vrem : RVVSignedBinBuiltinSet;
 }
 
-// 12.12. Vector Widening Integer Multiply Instructions
+// 11.12. Vector Widening Integer Multiply Instructions
 let Log2LMUL = [-3, -2, -1, 0, 1, 2], UnMaskedPolicyScheme = 
HasPassthruOperand in {
 defm vwmul :

[clang] [NFC][Clang][RISCV] Fix index typos of riscv-v-spec doc in riscv_vector.td (PR #65944)

2023-09-11 Thread Ying Chen via cfe-commits 


@@ -1660,29 +1660,29 @@ let HasMasked = false, MaskedPolicyScheme = NonePolicy 
in {
   defm vmsbc : RVVIntMaskOutBuiltinSet;
 }
 
-// 12.5. Vector Bitwise Logical Instructions
+// 11.5. Vector Bitwise Logical Instructions
 let UnMaskedPolicyScheme = HasPassthruOperand in {
 defm vand : RVVIntBinBuiltinSet;
 defm vxor : RVVIntBinBuiltinSet;
 defm vor : RVVIntBinBuiltinSet;
 }
 defm vnot_v : RVVPseudoVNotBuiltin<"vxor", "csil">;
 
-// 12.6. Vector Single-Width Bit Shift Instructions
+// 11.6. Vector Single-Width Bit Shift Instructions

punkyc wrote:

Fix it.

https://github.com/llvm/llvm-project/pull/65944
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[clang] [NFC][Clang][RISCV] Fix index typos of riscv-v-spec doc in riscv_vector.td (PR #65944)

2023-09-11 Thread Ying Chen via cfe-commits 


@@ -1660,29 +1660,29 @@ let HasMasked = false, MaskedPolicyScheme = NonePolicy 
in {
   defm vmsbc : RVVIntMaskOutBuiltinSet;
 }
 
-// 12.5. Vector Bitwise Logical Instructions
+// 11.5. Vector Bitwise Logical Instructions
 let UnMaskedPolicyScheme = HasPassthruOperand in {
 defm vand : RVVIntBinBuiltinSet;
 defm vxor : RVVIntBinBuiltinSet;
 defm vor : RVVIntBinBuiltinSet;
 }
 defm vnot_v : RVVPseudoVNotBuiltin<"vxor", "csil">;
 
-// 12.6. Vector Single-Width Bit Shift Instructions
+// 11.6. Vector Single-Width Bit Shift Instructions
 let UnMaskedPolicyScheme = HasPassthruOperand in {
 defm vsll : RVVShiftBuiltinSet;
 defm vsrl : RVVUnsignedShiftBuiltinSet;
 defm vsra : RVVSignedShiftBuiltinSet;
 
-// 12.7. Vector Narrowing Integer Right Shift Instructions
+// 11.7. Vector Narrowing Integer Right Shift Instructions
 defm vnsrl : RVVUnsignedNShiftBuiltinSet;
 defm vnsra : RVVSignedNShiftBuiltinSet;
 }
 defm vncvt_x_x_w : RVVPseudoVNCVTBuiltin<"vnsrl", "vncvt_x", "csi",
  [["v", "vw"],
   ["Uv", "UvUw"]]>;
 
-// 12.8. Vector Integer Comparison Instructions
+// 11.8. Vector Integer Comparison Instructions

punkyc wrote:

Fix it.

https://github.com/llvm/llvm-project/pull/65944
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[clang] [NFC][Clang][RISCV] Fix index typos of riscv-v-spec doc in riscv_vector.td (PR #65944)

2023-09-11 Thread Ying Chen via cfe-commits 


@@ -2262,11 +2262,11 @@ defm vmfgt : RVVFloatingMaskOutBuiltinSet;
 defm vmfge : RVVFloatingMaskOutBuiltinSet;
 }
 
-// 14.14. Vector Floating-Point Classify Instruction
+// 13.14. Vector Floating-Point Classify Instruction
 let Name = "vfclass_v", UnMaskedPolicyScheme = HasPassthruOperand in
   def vfclass : RVVOp0Builtin<"Uv", "Uvv", "xfd">;
 
-// 14.15. Vector Floating-Point Merge Instructio
+// 13.15. Vector Floating-Point Merge Instructio

punkyc wrote:

Fix it.

https://github.com/llvm/llvm-project/pull/65944
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[clang] [NFC][Clang][RISCV] Fix typos of riscv-v-spec doc in riscv_vector.td (PR #65944)

2023-09-11 Thread Ying Chen via cfe-commits 

https://github.com/punkyc edited https://github.com/llvm/llvm-project/pull/65944
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[clang] [llvm] [RISCV] Add shlcofideleg extension (PR #141572)

2025-05-27 Thread Ying Chen via cfe-commits 

https://github.com/punkyc created 
https://github.com/llvm/llvm-project/pull/141572

This is for `shlcofideleg` extension, that supports delegating LCOFI interrupts 
to VS-mode.

Spec: https://github.com/riscv/riscv-isa-manual/blob/main/src/supervisor.adoc

>From 385ae3040ae39d62702c430e2d0b79b80b30e36b Mon Sep 17 00:00:00 2001
From: punkyc 
Date: Tue, 27 May 2025 17:21:12 +0800
Subject: [PATCH] [RISCV] Add shlcofideleg extension

---
 clang/test/Driver/print-supported-extensions-riscv.c | 1 +
 clang/test/Preprocessor/riscv-target-features.c  | 9 +
 llvm/docs/RISCVUsage.rst | 1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td   | 4 
 llvm/test/CodeGen/RISCV/attributes.ll| 4 
 llvm/test/MC/RISCV/attribute-arch.s  | 3 +++
 llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 1 +
 7 files changed, 23 insertions(+)

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 7b4f46cdb4443..e4f593fbd6df1 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -119,6 +119,7 @@
 // CHECK-NEXT: sha  1.0   'Sha' (Augmented Hypervisor)
 // CHECK-NEXT: shcounterenw 1.0   'Shcounterenw' (Support 
writeable hcounteren enable bit for any hpmcounter that is not read-only zero)
 // CHECK-NEXT: shgatpa  1.0   'Shgatpa' (SvNNx4 mode 
supported for all modes supported by satp, as well as Bare)
+// CHECK-NEXT: shlcofideleg 1.0   'Shlcofideleg' (Delegating 
LCOFI interrupts to VS-mode)
 // CHECK-NEXT: shtvala  1.0   'Shtvala' (htval provides 
all needed values)
 // CHECK-NEXT: shvsatpa 1.0   'Shvsatpa' (vsatp supports 
all modes supported by satp)
 // CHECK-NEXT: shvstvala1.0   'Shvstvala' (vstval provides 
all needed values)
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index e3b456e0245f7..86085c21a95aa 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -24,6 +24,7 @@
 // CHECK-NOT: __riscv_sha {{.*$}}
 // CHECK-NOT: __riscv_shcounterenw {{.*$}}
 // CHECK-NOT: __riscv_shgatpa {{.*$}}
+// CHECK-NOT: __riscv_shlcofideleg {{.*$}}
 // CHECK-NOT: __riscv_shtvala {{.*$}}
 // CHECK-NOT: __riscv_shvsatpa {{.*$}}
 // CHECK-NOT: __riscv_shvstvala {{.*$}}
@@ -370,6 +371,14 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-SHGATPA-EXT %s
 // CHECK-SHGATPA-EXT: __riscv_shgatpa 100{{$}}
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ishlcofideleg -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SHLCOFIDELEG-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ishlcofideleg -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SHLCOFIDELEG-EXT %s
+// CHECK-SHLCOFIDELEG-EXT: __riscv_shlcofideleg 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ishtvala -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-SHTVALA-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 9ac21052eb66c..7d0d0cc21a27d 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -123,6 +123,7 @@ on support follow.
  ``Sha``   Supported
  ``Shcounterenw``  Assembly Support (`See note 
<#riscv-profiles-extensions-note>`__)
  ``Shgatpa``   Assembly Support (`See note 
<#riscv-profiles-extensions-note>`__)
+ ``Shlcofideleg``  Supported
  ``Shtvala``   Assembly Support (`See note 
<#riscv-profiles-extensions-note>`__)
  ``Shvsatpa``  Assembly Support (`See note 
<#riscv-profiles-extensions-note>`__)
  ``Shvstvala`` Assembly Support (`See note 
<#riscv-profiles-extensions-note>`__)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 86576ed190d14..690068d05aaab 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -906,6 +906,10 @@ def FeatureStdExtShvsatpa
 : RISCVExtension<1, 0,
  "vsatp supports all modes supported by satp">;
 
+def FeatureStdExtShlcofideleg
+: RISCVExtension<1, 0,
+ "Delegating LCOFI Interrupts to VS-mode">;
+
 def FeatureStdExtSmaia
 : RISCVExtension<1, 0,
  "Advanced Interrupt Architecture Machine Level">;
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll 
b/llvm/test/CodeGen/RISCV/attributes.ll
index 68b472936ecdf..ba8969b5a5382 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -47,6 +47,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+shcounterenw %s -o - | FileCheck 
--check-prefixes=CHECK,RV32SHCOUNTERENW %s
 ; RUN: llc -mtriple=riscv32 -

[clang] [llvm] [RISCV] Add shlcofideleg extension (PR #141572)

2025-05-29 Thread Ying Chen via cfe-commits 

punkyc wrote:

@topperc @wangpc-pp Please help to merge.

https://github.com/llvm/llvm-project/pull/141572
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[clang] [llvm] [RISCV] Add shlcofideleg extension (PR #141572)

2025-05-29 Thread Ying Chen via cfe-commits 

https://github.com/punkyc updated 
https://github.com/llvm/llvm-project/pull/141572

>From 385ae3040ae39d62702c430e2d0b79b80b30e36b Mon Sep 17 00:00:00 2001
From: punkyc 
Date: Tue, 27 May 2025 17:21:12 +0800
Subject: [PATCH 1/3] [RISCV] Add shlcofideleg extension

---
 clang/test/Driver/print-supported-extensions-riscv.c | 1 +
 clang/test/Preprocessor/riscv-target-features.c  | 9 +
 llvm/docs/RISCVUsage.rst | 1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td   | 4 
 llvm/test/CodeGen/RISCV/attributes.ll| 4 
 llvm/test/MC/RISCV/attribute-arch.s  | 3 +++
 llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 1 +
 7 files changed, 23 insertions(+)

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 7b4f46cdb4443..e4f593fbd6df1 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -119,6 +119,7 @@
 // CHECK-NEXT: sha  1.0   'Sha' (Augmented Hypervisor)
 // CHECK-NEXT: shcounterenw 1.0   'Shcounterenw' (Support 
writeable hcounteren enable bit for any hpmcounter that is not read-only zero)
 // CHECK-NEXT: shgatpa  1.0   'Shgatpa' (SvNNx4 mode 
supported for all modes supported by satp, as well as Bare)
+// CHECK-NEXT: shlcofideleg 1.0   'Shlcofideleg' (Delegating 
LCOFI interrupts to VS-mode)
 // CHECK-NEXT: shtvala  1.0   'Shtvala' (htval provides 
all needed values)
 // CHECK-NEXT: shvsatpa 1.0   'Shvsatpa' (vsatp supports 
all modes supported by satp)
 // CHECK-NEXT: shvstvala1.0   'Shvstvala' (vstval provides 
all needed values)
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index e3b456e0245f7..86085c21a95aa 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -24,6 +24,7 @@
 // CHECK-NOT: __riscv_sha {{.*$}}
 // CHECK-NOT: __riscv_shcounterenw {{.*$}}
 // CHECK-NOT: __riscv_shgatpa {{.*$}}
+// CHECK-NOT: __riscv_shlcofideleg {{.*$}}
 // CHECK-NOT: __riscv_shtvala {{.*$}}
 // CHECK-NOT: __riscv_shvsatpa {{.*$}}
 // CHECK-NOT: __riscv_shvstvala {{.*$}}
@@ -370,6 +371,14 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-SHGATPA-EXT %s
 // CHECK-SHGATPA-EXT: __riscv_shgatpa 100{{$}}
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ishlcofideleg -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SHLCOFIDELEG-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ishlcofideleg -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SHLCOFIDELEG-EXT %s
+// CHECK-SHLCOFIDELEG-EXT: __riscv_shlcofideleg 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ishtvala -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-SHTVALA-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 9ac21052eb66c..7d0d0cc21a27d 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -123,6 +123,7 @@ on support follow.
  ``Sha``   Supported
  ``Shcounterenw``  Assembly Support (`See note 
<#riscv-profiles-extensions-note>`__)
  ``Shgatpa``   Assembly Support (`See note 
<#riscv-profiles-extensions-note>`__)
+ ``Shlcofideleg``  Supported
  ``Shtvala``   Assembly Support (`See note 
<#riscv-profiles-extensions-note>`__)
  ``Shvsatpa``  Assembly Support (`See note 
<#riscv-profiles-extensions-note>`__)
  ``Shvstvala`` Assembly Support (`See note 
<#riscv-profiles-extensions-note>`__)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 86576ed190d14..690068d05aaab 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -906,6 +906,10 @@ def FeatureStdExtShvsatpa
 : RISCVExtension<1, 0,
  "vsatp supports all modes supported by satp">;
 
+def FeatureStdExtShlcofideleg
+: RISCVExtension<1, 0,
+ "Delegating LCOFI Interrupts to VS-mode">;
+
 def FeatureStdExtSmaia
 : RISCVExtension<1, 0,
  "Advanced Interrupt Architecture Machine Level">;
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll 
b/llvm/test/CodeGen/RISCV/attributes.ll
index 68b472936ecdf..ba8969b5a5382 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -47,6 +47,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+shcounterenw %s -o - | FileCheck 
--check-prefixes=CHECK,RV32SHCOUNTERENW %s
 ; RUN: llc -mtriple=riscv32 -mattr=+shgatpa %s -o - | FileCheck 
--check-prefixes=CHECK,RV32SHGATPA %s
 ; RUN: llc -mtriple=riscv32 -mattr=+shvsatpa %s -o - | FileCheck 
--check-prefixes=CHECK,RV32S