[clang] d40e809 - [PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility

2021-07-15 Thread Victor Huang via cfe-commits 

Author: Victor Huang
Date: 2021-07-15T10:23:54-05:00
New Revision: d40e8091bd1f48e8d3f64e4f99952f0139e9c27b

URL: 
https://github.com/llvm/llvm-project/commit/d40e8091bd1f48e8d3f64e4f99952f0139e9c27b
DIFF: 
https://github.com/llvm/llvm-project/commit/d40e8091bd1f48e8d3f64e4f99952f0139e9c27b.diff

LOG: [PowerPC] Add PowerPC rotate related builtins and emit target independent 
code for XL compatibility

This patch is in a series of patches to provide builtins for compatibility
with the XL compiler. This patch adds the builtins and emit target independent
code for rotate related operations.

Reviewed By: nemanjai, #powerpc

Differential revision: https://reviews.llvm.org/D104744

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/include/clang/Sema/Sema.h
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-error.c

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 09769b3f974eb..6bbd70c8368ec 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -83,6 +83,10 @@ BUILTIN(__builtin_ppc_mulhwu, "UiUiUi", "")
 BUILTIN(__builtin_ppc_maddhd, "LLiLLiLLiLLi", "")
 BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "")
 BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "")
+// Rotate
+BUILTIN(__builtin_ppc_rlwnm, "UiUiIUiIUi", "")
+BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "")
+BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 

diff  --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td 
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index f4c189a3d178f..779093977da8f 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -9726,6 +9726,8 @@ def err_argument_not_shifted_byte : Error<
   "argument should be an 8-bit value shifted by a multiple of 8 bits">;
 def err_argument_not_shifted_byte_or_xxff : Error<
   "argument should be an 8-bit value shifted by a multiple of 8 bits, or in 
the form 0x??FF">;
+def err_argument_not_contiguous_bit_field : Error<
+  "argument %0 value should represent a contiguous bit field">;
 def err_rotation_argument_to_cadd
 : Error<"argument should be the value 90 or 270">;
 def err_rotation_argument_to_cmla

diff  --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 3435834fbf5b3..8201e61fa63d8 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -12573,6 +12573,7 @@ class Sema final {
   bool SemaBuiltinComplex(CallExpr *TheCall);
   bool SemaBuiltinVSX(CallExpr *TheCall);
   bool SemaBuiltinOSLogFormat(CallExpr *TheCall);
+  bool SemaValueIsRunOfOnes(CallExpr *TheCall, unsigned ArgNum);
 
 public:
   // Used by C++ template instantiation.

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index b79b30d7a4cdb..947e8c945c887 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -140,6 +140,9 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__maddhd", "__builtin_ppc_maddhd");
   Builder.defineMacro("__maddhdu", "__builtin_ppc_maddhdu");
   Builder.defineMacro("__maddld", "__builtin_ppc_maddld");
+  Builder.defineMacro("__rlwnm", "__builtin_ppc_rlwnm");
+  Builder.defineMacro("__rlwimi", "__builtin_ppc_rlwimi");
+  Builder.defineMacro("__rldimi", "__builtin_ppc_rldimi");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 2819931664ba4..67f57015e49fd 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15172,6 +15172,31 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 else
   return Builder.CreateSub(Ops[0], Ops[1], "vsubuqm");
   }
+  // Rotate and insert under mask operation.
+  // __rldimi(rs, is, shift, mask)
+  // (rotl64(rs, shift) & mask) | (is & ~mask)
+  // __rlwimi(rs, is, shift, mask)
+  // (rotl(rs, shift) & mask) | (is & ~mask)
+  case PPC::BI__builtin_ppc_rldimi:
+  case PPC::BI__builtin_ppc_rlwimi: {
+llvm::Type *Ty = Ops[0]->getType();
+Function *F = CGM.getIntrinsic(Intrinsic::fshl, Ty);
+if (BuiltinID == PPC::BI__builtin_ppc_rldimi)
+  Ops[2] = Builder.CreateZExt(Ops[2], Int64Ty);
+Value *Shift = Builder.CreateCall(F, {Ops[0], Ops[0], Ops[2]});
+Value *X = Builder.CreateAnd(Shift, Ops[3]);
+Value *Y = Builder.CreateAnd(Ops[1], Builder.CreateNot(Ops[3]));
+return Builder.CreateOr(X, Y);
+  }
+  // Rotate and insert under mask operation.
+  // __rlwn

[clang] 803cf7a - [PowerPC][NFC] Add the missing 'REQUIRES: powerpc-registered-target.' in the builtins' front end test cases for XL compatibility

2021-07-15 Thread Victor Huang via cfe-commits 

Author: Victor Huang
Date: 2021-07-15T16:09:45-05:00
New Revision: 803cf7ac0c7be0eb48a99562e99aae578617755a

URL: 
https://github.com/llvm/llvm-project/commit/803cf7ac0c7be0eb48a99562e99aae578617755a
DIFF: 
https://github.com/llvm/llvm-project/commit/803cf7ac0c7be0eb48a99562e99aae578617755a.diff

LOG: [PowerPC][NFC] Add the missing 'REQUIRES: powerpc-registered-target.' in 
the builtins' front end test cases for XL compatibility

Added: 


Modified: 
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
clang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c
clang/test/CodeGen/builtins-ppc-xlcompat-multiply.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
clang/test/CodeGen/builtins-ppc-xlcompat-trap-64bit-only.c
clang/test/CodeGen/builtins-ppc-xlcompat-trap.c

Removed: 




diff  --git 
a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
index f0a8ff184311..f305166f2b08 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
@@ -1,3 +1,4 @@
+// REQUIRES: powerpc-registered-target
 // RUN: not %clang_cc1 -triple=powerpc-unknown-aix -emit-llvm %s -o - 2>&1 |\
 // RUN: FileCheck %s --check-prefix=CHECK32-ERROR
 // RUN: %clang_cc1 -O2 -triple=powerpc64-unknown-aix -emit-llvm %s -o - | \

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
index 4ffa29a09455..2ae031cbeca8 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
@@ -1,3 +1,4 @@
+// REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -O2 -triple=powerpc-unknown-aix -emit-llvm %s -o - | \
 // RUN: FileCheck %s
 // RUN: %clang_cc1 -O2 -triple=powerpc64-unknown-aix -emit-llvm %s -o - | \

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
index babc16fcd3a7..c2a5d77343e6 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
@@ -1,3 +1,4 @@
+// REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
 // RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
 // RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c
index d11e94786a2c..073a5d1e2d25 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c
@@ -1,3 +1,4 @@
+// REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
 // RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-multiply.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-multiply.c
index e6d329f3d9e1..739248db7813 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-multiply.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-multiply.c
@@ -1,3 +1,4 @@
+// REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
 // RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
index 6dd96f4e2f88..99558a46bde7 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
@@ -1,3 +1,4 @@
+// REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm %s \
 // RUN:   -target-cpu pwr9 -o - | FileCheck %s
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -emit-llvm %s \

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
index bdce26a82dd2..b1fd4ff03c8f 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
@@ -1,3 +1,4 @@
+// REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm %s \
 // RUN:   -target-cpu pwr9 -o - | FileCheck %s
 // RUN: %clan

[clang] 4eb107c - [PowerPC] Add PowerPC population count, reversed load and store related builtins and instrinsics for XL compatibility

2021-07-15 Thread Victor Huang via cfe-commits 

Author: Victor Huang
Date: 2021-07-15T17:23:56-05:00
New Revision: 4eb107ccbad791098494c26dfc1d423ecf558ef7

URL: 
https://github.com/llvm/llvm-project/commit/4eb107ccbad791098494c26dfc1d423ecf558ef7
DIFF: 
https://github.com/llvm/llvm-project/commit/4eb107ccbad791098494c26dfc1d423ecf558ef7.diff

LOG: [PowerPC] Add PowerPC population count, reversed load and store related 
builtins and instrinsics for XL compatibility

This patch is in a series of patches to provide builtins for compatibility
with the XL compiler. This patch adds the builtins and instrisics for population
count, reversed load and store related operations.

Reviewed By: nemanjai, #powerpc

Differential revision: https://reviews.llvm.org/D106021

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed-64bit-only.c
clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c
clang/test/CodeGen/builtins-ppc-xlcompat-popcnt.c

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed-64bit-only.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-popcnt.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 6bbd70c8368e..f7f34122f17d 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -31,6 +31,8 @@
 
 // builtins for compatibility with the XL compiler
 BUILTIN(__builtin_ppc_popcntb, "ULiULi", "")
+BUILTIN(__builtin_ppc_poppar4, "iUi", "")
+BUILTIN(__builtin_ppc_poppar8, "iULLi", "")
 BUILTIN(__builtin_ppc_eieio, "v", "")
 BUILTIN(__builtin_ppc_iospace_eieio, "v", "")
 BUILTIN(__builtin_ppc_isync, "v", "")
@@ -87,6 +89,14 @@ BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "")
 BUILTIN(__builtin_ppc_rlwnm, "UiUiIUiIUi", "")
 BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "")
 BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi", "")
+// load
+BUILTIN(__builtin_ppc_load2r, "UiUs*", "")
+BUILTIN(__builtin_ppc_load4r, "UiUi*", "")
+BUILTIN(__builtin_ppc_load8r, "ULLiULLi*", "")
+// store
+BUILTIN(__builtin_ppc_store2r, "vUiUs*", "")
+BUILTIN(__builtin_ppc_store4r, "vUiUi*", "")
+BUILTIN(__builtin_ppc_store8r, "vULLiULLi*", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 947e8c945c88..84cd3d4db028 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -89,6 +89,8 @@ bool 
PPCTargetInfo::handleTargetFeatures(std::vector &Features,
 
 static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__popcntb", "__builtin_ppc_popcntb");
+  Builder.defineMacro("__poppar4", "__builtin_ppc_poppar4");
+  Builder.defineMacro("__poppar8", "__builtin_ppc_poppar8");
   Builder.defineMacro("__eieio", "__builtin_ppc_eieio");
   Builder.defineMacro("__iospace_eieio", "__builtin_ppc_iospace_eieio");
   Builder.defineMacro("__isync", "__builtin_ppc_isync");
@@ -143,6 +145,12 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__rlwnm", "__builtin_ppc_rlwnm");
   Builder.defineMacro("__rlwimi", "__builtin_ppc_rlwimi");
   Builder.defineMacro("__rldimi", "__builtin_ppc_rldimi");
+  Builder.defineMacro("__load2r", "__builtin_ppc_load2r");
+  Builder.defineMacro("__load4r", "__builtin_ppc_load4r");
+  Builder.defineMacro("__load8r", "__builtin_ppc_load8r");
+  Builder.defineMacro("__store2r", "__builtin_ppc_store2r");
+  Builder.defineMacro("__store4r", "__builtin_ppc_store4r");
+  Builder.defineMacro("__store8r", "__builtin_ppc_store8r");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 4091b6cc62ce..ce238d7ee937 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15197,6 +15197,20 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 Value *Shift = Builder.CreateCall(F, {Ops[0], Ops[0], Ops[1]});
 return Builder.CreateAnd(Shift, Ops[2]);
   }
+  case PPC::BI__builtin_ppc_poppar4:
+  case PPC::BI__builtin_ppc_poppar8: {
+llvm::Type *ArgType = Ops[0]->getType();
+Function *F = CGM.getIntrinsic(Intrinsic::ctpop, ArgType);
+Value *Tmp = Builder.CreateCall(F, Ops[0]);
+
+llvm::Type *ResultType = ConvertType(E->getType());
+Value *Result = Builder.CreateAnd(Tmp, llvm::ConstantInt::get(ArgType, 1));
+if (Result->getType() != ResultType)
+  Result = Builder.CreateIntCast(Result, ResultTy

[clang] 1a762f9 - [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

2021-07-20 Thread Victor Huang via cfe-commits 

Author: Victor Huang
Date: 2021-07-20T13:06:22-05:00
New Revision: 1a762f93f81640768dc9e9d933780fff32cfa639

URL: 
https://github.com/llvm/llvm-project/commit/1a762f93f81640768dc9e9d933780fff32cfa639
DIFF: 
https://github.com/llvm/llvm-project/commit/1a762f93f81640768dc9e9d933780fff32cfa639.diff

LOG: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL 
compatibility

This patch is in a series of patches to provide builtins for compatibility
with the XL compiler. This patch add the builtin and emit target independent
code for __cmpb.

Reviewed By: nemanjai, #powerpc

Differential revision: https://reviews.llvm.org/D105194

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-32.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-64.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 07e000d4f710..5f8bbf6adb87 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -81,6 +81,7 @@ BUILTIN(__builtin_ppc_rdlam, "UWiUWiUWiUWIi", "nc")
 BUILTIN(__builtin_ppc_cmpeqb, "LLiLLiLLi", "")
 BUILTIN(__builtin_ppc_cmprb, "iCIiii", "")
 BUILTIN(__builtin_ppc_setb, "LLiLLiLLi", "")
+BUILTIN(__builtin_ppc_cmpb, "LLiLLiLLi", "")
 // Multiply
 BUILTIN(__builtin_ppc_mulhd, "LLiLiLi", "")
 BUILTIN(__builtin_ppc_mulhdu, "ULLiULiULi", "")

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index b713fce8906c..f4e646a7417f 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -135,6 +135,7 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__cmpeqb", "__builtin_ppc_cmpeqb");
   Builder.defineMacro("__cmprb", "__builtin_ppc_cmprb");
   Builder.defineMacro("__setb", "__builtin_ppc_setb");
+  Builder.defineMacro("__cmpb", "__builtin_ppc_cmpb");
   Builder.defineMacro("__mulhd", "__builtin_ppc_mulhd");
   Builder.defineMacro("__mulhdu", "__builtin_ppc_mulhdu");
   Builder.defineMacro("__mulhw", "__builtin_ppc_mulhw");

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 44aabfd47735..2bc194e1c795 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15212,7 +15212,42 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
  "cast");
 return Result;
   }
-
+  case PPC::BI__builtin_ppc_cmpb: {
+if (getTarget().getTriple().isPPC64()) {
+  Function *F =
+  CGM.getIntrinsic(Intrinsic::ppc_cmpb, {Int64Ty, Int64Ty, Int64Ty});
+  return Builder.CreateCall(F, Ops, "cmpb");
+}
+// For 32 bit, emit the code as below:
+// %conv = trunc i64 %a to i32
+// %conv1 = trunc i64 %b to i32
+// %shr = lshr i64 %a, 32
+// %conv2 = trunc i64 %shr to i32
+// %shr3 = lshr i64 %b, 32
+// %conv4 = trunc i64 %shr3 to i32
+// %0 = tail call i32 @llvm.ppc.cmpb32(i32 %conv, i32 %conv1)
+// %conv5 = zext i32 %0 to i64
+// %1 = tail call i32 @llvm.ppc.cmpb32(i32 %conv2, i32 %conv4)
+// %conv614 = zext i32 %1 to i64
+// %shl = shl nuw i64 %conv614, 32
+// %or = or i64 %shl, %conv5
+// ret i64 %or
+Function *F =
+CGM.getIntrinsic(Intrinsic::ppc_cmpb, {Int32Ty, Int32Ty, Int32Ty});
+Value *ArgOneLo = Builder.CreateTrunc(Ops[0], Int32Ty);
+Value *ArgTwoLo = Builder.CreateTrunc(Ops[1], Int32Ty);
+Constant *ShiftAmt = ConstantInt::get(Int64Ty, 32);
+Value *ArgOneHi =
+Builder.CreateTrunc(Builder.CreateLShr(Ops[0], ShiftAmt), Int32Ty);
+Value *ArgTwoHi =
+Builder.CreateTrunc(Builder.CreateLShr(Ops[1], ShiftAmt), Int32Ty);
+Value *ResLo = Builder.CreateZExt(
+Builder.CreateCall(F, {ArgOneLo, ArgTwoLo}, "cmpb"), Int64Ty);
+Value *ResHiShift = Builder.CreateZExt(
+Builder.CreateCall(F, {ArgOneHi, ArgTwoHi}, "cmpb"), Int64Ty);
+Value *ResHi = Builder.CreateShl(ResHiShift, ShiftAmt);
+return Builder.CreateOr(ResLo, ResHi);
+  }
   // Copy sign
   case PPC::BI__builtin_vsx_xvcpsgnsp:
   case PPC::BI__builtin_vsx_xvcpsgndp: {

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-compare.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
new file mode 100644
index ..35f08bf33f51
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
@@ -0,0 +1,44 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s 
--check-prefix=CHE

[clang] 26ea4a4 - [PowerPC] Add PowerPC "__stbcx" builtin and intrinsic for XL compatibility

2021-07-22 Thread Victor Huang via cfe-commits 

Author: Victor Huang
Date: 2021-07-22T10:48:46-05:00
New Revision: 26ea4a4432431ce581e46746fa93981ad7f891d0

URL: 
https://github.com/llvm/llvm-project/commit/26ea4a4432431ce581e46746fa93981ad7f891d0
DIFF: 
https://github.com/llvm/llvm-project/commit/26ea4a4432431ce581e46746fa93981ad7f891d0.diff

LOG: [PowerPC] Add PowerPC "__stbcx" builtin and intrinsic for XL compatibility

This patch is in a series of patches to provide builtins for compatibility
with the XL compiler. This patch adds the builtin and intrinsic for "__stbcx".

Reviewed By: nemanjai, #powerpc

Differential revision: https://reviews.llvm.org/D106484

Added: 


Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 1c68eaf2ec78e..5d0093434566c 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -79,6 +79,7 @@ BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "")
 BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
 BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
 BUILTIN(__builtin_ppc_sthcx, "isD*s", "")
+BUILTIN(__builtin_ppc_stbcx, "icD*i", "")
 BUILTIN(__builtin_ppc_tdw, "vLLiLLiIUi", "")
 BUILTIN(__builtin_ppc_tw, "viiIUi", "")
 BUILTIN(__builtin_ppc_trap, "vi", "")

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 86096dc0743b6..409504d054f14 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -124,6 +124,7 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
   Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
   Builder.defineMacro("__sthcx", "__builtin_ppc_sthcx");
+  Builder.defineMacro("__stbcx", "__builtin_ppc_stbcx");
   Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
   Builder.defineMacro("__tw", "__builtin_ppc_tw");
   Builder.defineMacro("__trap", "__builtin_ppc_trap");

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 02da39c11d7f9..76f34f6a65556 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3434,9 +3434,8 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo 
&TI, unsigned BuiltinID,
   case PPC::BI__builtin_ppc_rdlam:
 return SemaValueIsRunOfOnes(TheCall, 2);
   case PPC::BI__builtin_ppc_icbt:
-return SemaFeatureCheck(*this, TheCall, "isa-v207-instructions",
-diag::err_ppc_builtin_only_on_arch, "8");
   case PPC::BI__builtin_ppc_sthcx:
+  case PPC::BI__builtin_ppc_stbcx:
   case PPC::BI__builtin_ppc_lharx:
   case PPC::BI__builtin_ppc_lbarx:
 return SemaFeatureCheck(*this, TheCall, "isa-v207-instructions",

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
index d05d5ef2b3abb..df6659b843ab9 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
@@ -15,6 +15,8 @@
 // RUN:   -target-cpu pwr7 -o - 2>&1 | FileCheck %s -check-prefix=CHECK-NOPWR8
 
 extern void *a;
+extern volatile char *c_addr;
+extern char c;
 
 void test_icbt() {
 // CHECK-LABEL: @test_icbt(
@@ -31,3 +33,14 @@ void test_builtin_ppc_icbt() {
 // CHECK-PWR8: call void @llvm.ppc.icbt(i8* %0)
 // CHECK-NOPWR8: error: this builtin is only valid on POWER8 or later CPUs
 }
+
+int test_builtin_ppc_stbcx() {
+// CHECK-PWR8-LABEL: @test_builtin_ppc_stbcx(
+// CHECK-PWR8: [[TMP0:%.*]] = load i8*, i8** @c_addr, align {{[0-9]+}}
+// CHECK-PWR8-NEXT:[[TMP1:%.*]] = load i8, i8* @c, align 1
+// CHECK-PWR8-NEXT:[[TMP2:%.*]] = sext i8 [[TMP1]] to i32
+// CHECK-PWR8-NEXT:[[TMP3:%.*]] = call i32 @llvm.ppc.stbcx(i8* [[TMP0]], 
i32 [[TMP2]])
+// CHECK-PWR8-NEXT:ret i32 [[TMP3]]
+// CHECK-NOPWR8: error: this builtin is only valid on POWER8 or later CPUs
+  return __builtin_ppc_stbcx(c_addr, c);
+}

diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index a3a42b0489ccc..92d3bdea37edf 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1566,6 +1566,9 @@ let TargetPrefix = "ppc" in {
 [IntrWriteMem]>;
   def int_ppc_sthcx
   : Intrinsic<[llvm_i32_ty], [ llvm_ptr_ty, llvm_i32_ty ], [IntrWriteMem]>;
+  def int_ppc_stbcx : GCCBuiltin<"__builtin_ppc_stbcx">,
+  Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
+[IntrWriteMem]>;
   def int_ppc_dcbtstt : GCCBuiltin<"__

[clang] 10e0cdf - [PowerPC][NFC] Power ISA features for Semachecking

2021-07-13 Thread Victor Huang via cfe-commits 

Author: Victor Huang
Date: 2021-07-13T10:51:25-05:00
New Revision: 10e0cdfc6526578c8892d895c0448e77cb9ba876

URL: 
https://github.com/llvm/llvm-project/commit/10e0cdfc6526578c8892d895c0448e77cb9ba876
DIFF: 
https://github.com/llvm/llvm-project/commit/10e0cdfc6526578c8892d895c0448e77cb9ba876.diff

LOG: [PowerPC][NFC] Power ISA features for Semachecking

[NFC] This patch adds features for pwr7, pwr8, and pwr9 that can be
used for semachecking builtin functions that are only valid for certain
versions of ppc.

Reviewed By: nemanjai, #powerpc
Authored By: Quinn Pham 

Differential revision: https://reviews.llvm.org/D105501

Added: 


Modified: 
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/lib/Sema/SemaChecking.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h

Removed: 




diff  --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td 
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 2d62163e3dcc0..422507cd2842b 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -9757,8 +9757,8 @@ def err_mips_builtin_requires_dspr2 : Error<
   "this builtin requires 'dsp r2' ASE, please use -mdspr2">;
 def err_mips_builtin_requires_msa : Error<
   "this builtin requires 'msa' ASE, please use -mmsa">;
-def err_ppc_builtin_only_on_pwr7 : Error<
-  "this builtin is only valid on POWER7 or later CPUs">;
+def err_ppc_builtin_only_on_arch : Error<
+  "this builtin is only valid on POWER%0 or later CPUs">;
 def err_ppc_invalid_use_mma_type : Error<
   "invalid use of PPC MMA type">;
 def err_x86_builtin_invalid_rounding : Error<

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index b77b4a38bc46f..514f1a031ae79 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -73,6 +73,12 @@ bool 
PPCTargetInfo::handleTargetFeatures(std::vector &Features,
   HasROPProtect = true;
 } else if (Feature == "+privileged") {
   HasPrivileged = true;
+} else if (Feature == "+isa-v207-instructions") {
+  IsISA2_07 = true;
+} else if (Feature == "+isa-v30-instructions") {
+  IsISA3_0 = true;
+} else if (Feature == "+isa-v31-instructions") {
+  IsISA3_1 = true;
 }
 // TODO: Finish this list and add an assert that we've handled them
 // all.
@@ -390,6 +396,15 @@ bool PPCTargetInfo::initFeatureMap(
 .Case("e500", true)
 .Default(false);
 
+  Features["isa-v207-instructions"] = llvm::StringSwitch(CPU)
+  .Case("ppc64le", true)
+  .Case("pwr9", true)
+  .Case("pwr8", true)
+  .Default(false);
+
+  Features["isa-v30-instructions"] =
+  llvm::StringSwitch(CPU).Case("pwr9", true).Default(false);
+
   // Power10 includes all the same features as Power9 plus any features 
specific
   // to the Power10 core.
   if (CPU == "pwr10" || CPU == "power10") {
@@ -446,6 +461,7 @@ void PPCTargetInfo::addP10SpecificFeatures(
   Features["power10-vector"] = true;
   Features["pcrelative-memops"] = true;
   Features["prefix-instrs"] = true;
+  Features["isa-v31-instructions"] = true;
   return;
 }
 
@@ -476,6 +492,9 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const {
   .Case("mma", HasMMA)
   .Case("rop-protect", HasROPProtect)
   .Case("privileged", HasPrivileged)
+  .Case("isa-v207-instructions", IsISA2_07)
+  .Case("isa-v30-instructions", IsISA3_0)
+  .Case("isa-v31-instructions", IsISA3_1)
   .Default(false);
 }
 

diff  --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index bd79c68ce3f71..7c14a4eb9410c 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -74,6 +74,9 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public 
TargetInfo {
   bool HasP10Vector = false;
   bool HasPCRelativeMemops = false;
   bool HasPrefixInstrs = false;
+  bool IsISA2_07 = false;
+  bool IsISA3_0 = false;
+  bool IsISA3_1 = false;
 
 protected:
   std::string ABI;

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 99621a226dea6..062c7eb4a12e5 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3275,10 +3275,18 @@ static bool isPPC_64Builtin(unsigned BuiltinID) {
 }
 
 static bool SemaFeatureCheck(Sema &S, CallExpr *TheCall,
- StringRef FeatureToCheck, unsigned DiagID) {
-  if (!S.Context.getTargetInfo().hasFeature(FeatureToCheck))
-return S.Diag(TheCall->getBeginLoc(), DiagID) << TheCall->getSourceRange();
-  return f

[clang] e4585d3 - Revert "[PowerPC][NFC] Power ISA features for Semachecking"

2021-07-13 Thread Victor Huang via cfe-commits 

Author: Victor Huang
Date: 2021-07-13T13:13:34-05:00
New Revision: e4585d3f4e1f076ff12db65259924492f5912b19

URL: 
https://github.com/llvm/llvm-project/commit/e4585d3f4e1f076ff12db65259924492f5912b19
DIFF: 
https://github.com/llvm/llvm-project/commit/e4585d3f4e1f076ff12db65259924492f5912b19.diff

LOG: Revert "[PowerPC][NFC] Power ISA features for Semachecking"

This reverts commit 10e0cdfc6526578c8892d895c0448e77cb9ba876.

Added: 


Modified: 
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/lib/Sema/SemaChecking.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h

Removed: 




diff  --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td 
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 422507cd2842..2d62163e3dcc 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -9757,8 +9757,8 @@ def err_mips_builtin_requires_dspr2 : Error<
   "this builtin requires 'dsp r2' ASE, please use -mdspr2">;
 def err_mips_builtin_requires_msa : Error<
   "this builtin requires 'msa' ASE, please use -mmsa">;
-def err_ppc_builtin_only_on_arch : Error<
-  "this builtin is only valid on POWER%0 or later CPUs">;
+def err_ppc_builtin_only_on_pwr7 : Error<
+  "this builtin is only valid on POWER7 or later CPUs">;
 def err_ppc_invalid_use_mma_type : Error<
   "invalid use of PPC MMA type">;
 def err_x86_builtin_invalid_rounding : Error<

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 514f1a031ae7..b77b4a38bc46 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -73,12 +73,6 @@ bool 
PPCTargetInfo::handleTargetFeatures(std::vector &Features,
   HasROPProtect = true;
 } else if (Feature == "+privileged") {
   HasPrivileged = true;
-} else if (Feature == "+isa-v207-instructions") {
-  IsISA2_07 = true;
-} else if (Feature == "+isa-v30-instructions") {
-  IsISA3_0 = true;
-} else if (Feature == "+isa-v31-instructions") {
-  IsISA3_1 = true;
 }
 // TODO: Finish this list and add an assert that we've handled them
 // all.
@@ -396,15 +390,6 @@ bool PPCTargetInfo::initFeatureMap(
 .Case("e500", true)
 .Default(false);
 
-  Features["isa-v207-instructions"] = llvm::StringSwitch(CPU)
-  .Case("ppc64le", true)
-  .Case("pwr9", true)
-  .Case("pwr8", true)
-  .Default(false);
-
-  Features["isa-v30-instructions"] =
-  llvm::StringSwitch(CPU).Case("pwr9", true).Default(false);
-
   // Power10 includes all the same features as Power9 plus any features 
specific
   // to the Power10 core.
   if (CPU == "pwr10" || CPU == "power10") {
@@ -461,7 +446,6 @@ void PPCTargetInfo::addP10SpecificFeatures(
   Features["power10-vector"] = true;
   Features["pcrelative-memops"] = true;
   Features["prefix-instrs"] = true;
-  Features["isa-v31-instructions"] = true;
   return;
 }
 
@@ -492,9 +476,6 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const {
   .Case("mma", HasMMA)
   .Case("rop-protect", HasROPProtect)
   .Case("privileged", HasPrivileged)
-  .Case("isa-v207-instructions", IsISA2_07)
-  .Case("isa-v30-instructions", IsISA3_0)
-  .Case("isa-v31-instructions", IsISA3_1)
   .Default(false);
 }
 

diff  --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 7c14a4eb9410..bd79c68ce3f7 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -74,9 +74,6 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public 
TargetInfo {
   bool HasP10Vector = false;
   bool HasPCRelativeMemops = false;
   bool HasPrefixInstrs = false;
-  bool IsISA2_07 = false;
-  bool IsISA3_0 = false;
-  bool IsISA3_1 = false;
 
 protected:
   std::string ABI;

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 062c7eb4a12e..99621a226dea 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3275,18 +3275,10 @@ static bool isPPC_64Builtin(unsigned BuiltinID) {
 }
 
 static bool SemaFeatureCheck(Sema &S, CallExpr *TheCall,
- StringRef FeatureToCheck, unsigned DiagID,
- StringRef DiagArg = "") {
-  if (S.Context.getTargetInfo().hasFeature(FeatureToCheck))
-return false;
-
-  if (DiagArg.empty())
-S.Diag(TheCall->getBeginLoc(), DiagID) << TheCall->getSourceRange();
-  else
-S.Diag(TheCall->getBeginLoc(), DiagID)
-<< DiagArg << TheCall->getSourceRange();
-
-  return true;
+

[clang] 781929b - [PowerPC][NFC] Power ISA features for Semachecking

2021-07-13 Thread Victor Huang via cfe-commits 

Author: Victor Huang
Date: 2021-07-13T13:13:34-05:00
New Revision: 781929b4236bc34681fb0783cf7b6021109fe28b

URL: 
https://github.com/llvm/llvm-project/commit/781929b4236bc34681fb0783cf7b6021109fe28b
DIFF: 
https://github.com/llvm/llvm-project/commit/781929b4236bc34681fb0783cf7b6021109fe28b.diff

LOG: [PowerPC][NFC] Power ISA features for Semachecking

[NFC] This patch adds features for pwr7, pwr8, and pwr9 that can be
used for semachecking builtin functions that are only valid for certain
versions of ppc.

Reviewed By: nemanjai, #powerpc
Authored By: Quinn Pham 

Differential revision: https://reviews.llvm.org/D105501

Added: 
clang/test/Driver/ppc-isa-features.cpp

Modified: 
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/lib/Sema/SemaChecking.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h

Removed: 




diff  --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td 
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 2d62163e3dcc..422507cd2842 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -9757,8 +9757,8 @@ def err_mips_builtin_requires_dspr2 : Error<
   "this builtin requires 'dsp r2' ASE, please use -mdspr2">;
 def err_mips_builtin_requires_msa : Error<
   "this builtin requires 'msa' ASE, please use -mmsa">;
-def err_ppc_builtin_only_on_pwr7 : Error<
-  "this builtin is only valid on POWER7 or later CPUs">;
+def err_ppc_builtin_only_on_arch : Error<
+  "this builtin is only valid on POWER%0 or later CPUs">;
 def err_ppc_invalid_use_mma_type : Error<
   "invalid use of PPC MMA type">;
 def err_x86_builtin_invalid_rounding : Error<

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index b77b4a38bc46..514f1a031ae7 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -73,6 +73,12 @@ bool 
PPCTargetInfo::handleTargetFeatures(std::vector &Features,
   HasROPProtect = true;
 } else if (Feature == "+privileged") {
   HasPrivileged = true;
+} else if (Feature == "+isa-v207-instructions") {
+  IsISA2_07 = true;
+} else if (Feature == "+isa-v30-instructions") {
+  IsISA3_0 = true;
+} else if (Feature == "+isa-v31-instructions") {
+  IsISA3_1 = true;
 }
 // TODO: Finish this list and add an assert that we've handled them
 // all.
@@ -390,6 +396,15 @@ bool PPCTargetInfo::initFeatureMap(
 .Case("e500", true)
 .Default(false);
 
+  Features["isa-v207-instructions"] = llvm::StringSwitch(CPU)
+  .Case("ppc64le", true)
+  .Case("pwr9", true)
+  .Case("pwr8", true)
+  .Default(false);
+
+  Features["isa-v30-instructions"] =
+  llvm::StringSwitch(CPU).Case("pwr9", true).Default(false);
+
   // Power10 includes all the same features as Power9 plus any features 
specific
   // to the Power10 core.
   if (CPU == "pwr10" || CPU == "power10") {
@@ -446,6 +461,7 @@ void PPCTargetInfo::addP10SpecificFeatures(
   Features["power10-vector"] = true;
   Features["pcrelative-memops"] = true;
   Features["prefix-instrs"] = true;
+  Features["isa-v31-instructions"] = true;
   return;
 }
 
@@ -476,6 +492,9 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const {
   .Case("mma", HasMMA)
   .Case("rop-protect", HasROPProtect)
   .Case("privileged", HasPrivileged)
+  .Case("isa-v207-instructions", IsISA2_07)
+  .Case("isa-v30-instructions", IsISA3_0)
+  .Case("isa-v31-instructions", IsISA3_1)
   .Default(false);
 }
 

diff  --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index bd79c68ce3f7..7c14a4eb9410 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -74,6 +74,9 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public 
TargetInfo {
   bool HasP10Vector = false;
   bool HasPCRelativeMemops = false;
   bool HasPrefixInstrs = false;
+  bool IsISA2_07 = false;
+  bool IsISA3_0 = false;
+  bool IsISA3_1 = false;
 
 protected:
   std::string ABI;

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 99621a226dea..062c7eb4a12e 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3275,10 +3275,18 @@ static bool isPPC_64Builtin(unsigned BuiltinID) {
 }
 
 static bool SemaFeatureCheck(Sema &S, CallExpr *TheCall,
- StringRef FeatureToCheck, unsigned DiagID) {
-  if (!S.Context.getTargetInfo().hasFeature(FeatureToCheck))
-return S.Diag(TheCall->getBeginLoc(), DiagID) << TheCall-

[clang] 18c1941 - [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

2021-07-13 Thread Victor Huang via cfe-commits 

Author: Victor Huang
Date: 2021-07-13T16:55:09-05:00
New Revision: 18c19414eb70578d4c487d6f4b0f438aead71d6a

URL: 
https://github.com/llvm/llvm-project/commit/18c19414eb70578d4c487d6f4b0f438aead71d6a
DIFF: 
https://github.com/llvm/llvm-project/commit/18c19414eb70578d4c487d6f4b0f438aead71d6a.diff

LOG: [PowerPC] Add PowerPC compare and multiply related builtins and 
instrinsics for XL compatibility

This patch is in a series of patches to provide builtins for compatibility
with the XL compiler. This patch adds the builtins and instrisics for compare
and multiply related operations.

Reviewed By: nemanjai, #powerpc

Differential revision: https://reviews.llvm.org/D102875

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c
clang/test/CodeGen/builtins-ppc-xlcompat-multiply.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare-64bit-only.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 6a72cc089df7e..09769b3f974eb 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -71,6 +71,18 @@ BUILTIN(__builtin_ppc_fctiw, "dd", "")
 BUILTIN(__builtin_ppc_fctiwz, "dd", "")
 BUILTIN(__builtin_ppc_fctudz, "dd", "")
 BUILTIN(__builtin_ppc_fctuwz, "dd", "")
+// Compare
+BUILTIN(__builtin_ppc_cmpeqb, "LLiLLiLLi", "")
+BUILTIN(__builtin_ppc_cmprb, "iCIiii", "")
+BUILTIN(__builtin_ppc_setb, "LLiLLiLLi", "")
+// Multiply
+BUILTIN(__builtin_ppc_mulhd, "LLiLiLi", "")
+BUILTIN(__builtin_ppc_mulhdu, "ULLiULiULi", "")
+BUILTIN(__builtin_ppc_mulhw, "iii", "")
+BUILTIN(__builtin_ppc_mulhwu, "UiUiUi", "")
+BUILTIN(__builtin_ppc_maddhd, "LLiLLiLLiLLi", "")
+BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "")
+BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 514f1a031ae79..b79b30d7a4cdb 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -130,6 +130,16 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
   Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
   Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
+  Builder.defineMacro("__cmpeqb", "__builtin_ppc_cmpeqb");
+  Builder.defineMacro("__cmprb", "__builtin_ppc_cmprb");
+  Builder.defineMacro("__setb", "__builtin_ppc_setb");
+  Builder.defineMacro("__mulhd", "__builtin_ppc_mulhd");
+  Builder.defineMacro("__mulhdu", "__builtin_ppc_mulhdu");
+  Builder.defineMacro("__mulhw", "__builtin_ppc_mulhw");
+  Builder.defineMacro("__mulhwu", "__builtin_ppc_mulhwu");
+  Builder.defineMacro("__maddhd", "__builtin_ppc_maddhd");
+  Builder.defineMacro("__maddhdu", "__builtin_ppc_maddhdu");
+  Builder.defineMacro("__maddld", "__builtin_ppc_maddld");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 062c7eb4a12e5..6c6f284d1f6e5 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3269,6 +3269,13 @@ static bool isPPC_64Builtin(unsigned BuiltinID) {
   case PPC::BI__builtin_ppc_stdcx:
   case PPC::BI__builtin_ppc_tdw:
   case PPC::BI__builtin_ppc_trapd:
+  case PPC::BI__builtin_ppc_cmpeqb:
+  case PPC::BI__builtin_ppc_setb:
+  case PPC::BI__builtin_ppc_mulhd:
+  case PPC::BI__builtin_ppc_mulhdu:
+  case PPC::BI__builtin_ppc_maddhd:
+  case PPC::BI__builtin_ppc_maddhdu:
+  case PPC::BI__builtin_ppc_maddld:
 return true;
   }
   return false;
@@ -3360,6 +3367,17 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo 
&TI, unsigned BuiltinID,
   case PPC::BI__builtin_ppc_tw:
   case PPC::BI__builtin_ppc_tdw:
 return SemaBuiltinConstantArgRange(TheCall, 2, 0, 31);
+  case PPC::BI__builtin_ppc_cmpeqb:
+  case PPC::BI__builtin_ppc_setb:
+  case PPC::BI__builtin_ppc_maddhd:
+  case PPC::BI__builtin_ppc_maddhdu:
+  case PPC::BI__builtin_ppc_maddld:
+return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions",
+diag::err_ppc_builtin_only_on_arch, "9");
+  case PPC::BI__builtin_ppc_cmprb:
+re

[clang] 46475a7 - [AIX][TLS] Diagnose use of unimplemented TLS models

2021-05-11 Thread Victor Huang via cfe-commits 

Author: Victor Huang
Date: 2021-05-11T17:21:08-05:00
New Revision: 46475a79f85b230fde3e7de8966c96bef14f0d24

URL: 
https://github.com/llvm/llvm-project/commit/46475a79f85b230fde3e7de8966c96bef14f0d24
DIFF: 
https://github.com/llvm/llvm-project/commit/46475a79f85b230fde3e7de8966c96bef14f0d24.diff

LOG: [AIX][TLS] Diagnose use of unimplemented TLS models

Add front end diagnostics to report error for unimplemented TLS models set by
- compiler option `-ftls-model`
- attributes like `__thread int __attribute__((tls_model("local-exec"))) 
var_name;`

Reviewed by: aaron.ballman, nemanjai, PowerPC

Differential Revision: https://reviews.llvm.org/D102070

Added: 
clang/test/CodeGen/aix-tls-model.cpp
clang/test/Sema/aix-attr-tls_model.c

Modified: 
clang/include/clang/Basic/DiagnosticDriverKinds.td
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/lib/Frontend/CompilerInvocation.cpp
clang/lib/Sema/SemaDeclAttr.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td 
b/clang/include/clang/Basic/DiagnosticDriverKinds.td
index d090afa516c75..6e4a60156fef7 100644
--- a/clang/include/clang/Basic/DiagnosticDriverKinds.td
+++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td
@@ -545,6 +545,8 @@ def err_drv_invalid_object_mode : Error<"OBJECT_MODE 
setting %0 is not recognize
 def err_aix_default_altivec_abi : Error<
   "The default Altivec ABI on AIX is not yet supported, use '-mabi=vec-extabi' 
for the extended Altivec ABI">;
 
+def err_aix_unsupported_tls_model : Error<"TLS model '%0' is not yet supported 
on AIX">;
+
 def err_invalid_cxx_abi : Error<"Invalid C++ ABI name '%0'">;
 def err_unsupported_cxx_abi : Error<"C++ ABI '%0' is not supported on target 
triple '%1'">;
 

diff  --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td 
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 3d665cc76c539..fef8bafad9656 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -3151,6 +3151,8 @@ def warn_objc_redundant_literal_use : Warning<
 def err_attr_tlsmodel_arg : Error<"tls_model must be \"global-dynamic\", "
   "\"local-dynamic\", \"initial-exec\" or \"local-exec\"">;
 
+def err_aix_attr_unsupported_tls_model : Error<"TLS model '%0' is not yet 
supported on AIX">;
+
 def err_tls_var_aligned_over_maximum : Error<
   "alignment (%0) of thread-local variable %1 is greater than the maximum 
supported "
   "alignment (%2) for a thread-local variable on this target">;

diff  --git a/clang/lib/Frontend/CompilerInvocation.cpp 
b/clang/lib/Frontend/CompilerInvocation.cpp
index 4b0bd30556451..0c5066a2f8cd3 100644
--- a/clang/lib/Frontend/CompilerInvocation.cpp
+++ b/clang/lib/Frontend/CompilerInvocation.cpp
@@ -1808,6 +1808,14 @@ bool CompilerInvocation::ParseCodeGenArgs(CodeGenOptions 
&Opts, ArgList &Args,
 Opts.ExplicitEmulatedTLS = true;
   }
 
+  if (Arg *A = Args.getLastArg(OPT_ftlsmodel_EQ)) {
+if (T.isOSAIX()) {
+  StringRef Name = A->getValue();
+  if (Name != "global-dynamic")
+Diags.Report(diag::err_aix_unsupported_tls_model) << Name;
+}
+  }
+
   if (Arg *A = Args.getLastArg(OPT_fdenormal_fp_math_EQ)) {
 StringRef Val = A->getValue();
 Opts.FPDenormalMode = llvm::parseDenormalFPAttribute(Val);

diff  --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp
index f961076421b5b..72868224cf539 100644
--- a/clang/lib/Sema/SemaDeclAttr.cpp
+++ b/clang/lib/Sema/SemaDeclAttr.cpp
@@ -1935,6 +1935,12 @@ static void handleTLSModelAttr(Sema &S, Decl *D, const 
ParsedAttr &AL) {
 return;
   }
 
+  if (S.Context.getTargetInfo().getTriple().isOSAIX() &&
+  Model != "global-dynamic") {
+S.Diag(LiteralLoc, diag::err_aix_attr_unsupported_tls_model) << Model;
+return;
+  }
+
   D->addAttr(::new (S.Context) TLSModelAttr(S.Context, AL, Model));
 }
 

diff  --git a/clang/test/CodeGen/aix-tls-model.cpp 
b/clang/test/CodeGen/aix-tls-model.cpp
new file mode 100644
index 0..a531f558ac796
--- /dev/null
+++ b/clang/test/CodeGen/aix-tls-model.cpp
@@ -0,0 +1,26 @@
+// RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -emit-llvm 
-o - | FileCheck %s -check-prefix=CHECK-GD
+// RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=global-dynamic -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
+// RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=local-dynamic -emit-llvm 2>&1 | FileCheck %s 
-check-prefix=CHECK-LD-ERROR
+// RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=initial-exec -emit-llvm  2>&1 | FileCheck %s 
-check-prefix=CHECK-IE-ERROR
+// RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=local-exec -emit-llvm 2>&1 | FileCheck %s 
-check-prefix=CHECK-LE-ERROR
+// RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -t

[clang] 2e5c17d - [PowerPC][NFC] Rename P10 builtins vec_clrl, vec_clrr to vec_clr_first and vec_clr_last

2021-08-30 Thread Victor Huang via cfe-commits 

Author: Victor Huang
Date: 2021-08-30T09:52:15-05:00
New Revision: 2e5c17d19e370c4d4f17ee89ca645113692f5407

URL: 
https://github.com/llvm/llvm-project/commit/2e5c17d19e370c4d4f17ee89ca645113692f5407
DIFF: 
https://github.com/llvm/llvm-project/commit/2e5c17d19e370c4d4f17ee89ca645113692f5407.diff

LOG: [PowerPC][NFC] Rename P10 builtins vec_clrl, vec_clrr to vec_clr_first and 
vec_clr_last

This patch renames the vector clear left/right builtins vec_clrl, vec_clrr to
vec_clr_first and vec_clr_last to avoid the ambiguities when dealing with 
endianness.

Reviewed By: amyk, lei

Differential revision: https://reviews.llvm.org/D108702

Added: 


Modified: 
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c

Removed: 




diff  --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index d548d8a0dd75e..fa9100a2639db 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -18312,10 +18312,10 @@ vec_cfuge(vector unsigned long long __a, vector 
unsigned long long __b) {
: __builtin_vsx_xxgenpcvdm((__a), (int)(__imm)))
 #endif /* __VSX__ */
 
-/* vec_clrl */
+/* vec_clr_first */
 
 static __inline__ vector signed char __ATTRS_o_ai
-vec_clrl(vector signed char __a, unsigned int __n) {
+vec_clr_first(vector signed char __a, unsigned int __n) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vclrrb(__a, __n);
 #else
@@ -18324,7 +18324,7 @@ vec_clrl(vector signed char __a, unsigned int __n) {
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
-vec_clrl(vector unsigned char __a, unsigned int __n) {
+vec_clr_first(vector unsigned char __a, unsigned int __n) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vclrrb((vector signed char)__a, __n);
 #else
@@ -18332,10 +18332,10 @@ vec_clrl(vector unsigned char __a, unsigned int __n) {
 #endif
 }
 
-/* vec_clrr */
+/* vec_clr_last */
 
 static __inline__ vector signed char __ATTRS_o_ai
-vec_clrr(vector signed char __a, unsigned int __n) {
+vec_clr_last(vector signed char __a, unsigned int __n) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vclrlb(__a, __n);
 #else
@@ -18344,7 +18344,7 @@ vec_clrr(vector signed char __a, unsigned int __n) {
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
-vec_clrr(vector unsigned char __a, unsigned int __n) {
+vec_clr_last(vector unsigned char __a, unsigned int __n) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vclrlb((vector signed char)__a, __n);
 #else

diff  --git a/clang/test/CodeGen/builtins-ppc-p10vector.c 
b/clang/test/CodeGen/builtins-ppc-p10vector.c
index b0dda0bc29e94..f97b445509267 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -732,36 +732,36 @@ vector unsigned long long test_xxgenpcvdm(void) {
   return vec_genpcvm(vulla, 0);
 }
 
-vector signed char test_vec_vclrl_sc(void) {
+vector signed char test_vec_clr_first_sc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vclrrb(<16 x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
-  return vec_clrl(vsca, uia);
+  return vec_clr_first(vsca, uia);
 }
 
-vector unsigned char test_vec_clrl_uc(void) {
+vector unsigned char test_vec_clr_first_uc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vclrrb(<16 x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
-  return vec_clrl(vuca, uia);
+  return vec_clr_first(vuca, uia);
 }
 
-vector signed char test_vec_vclrr_sc(void) {
+vector signed char test_vec_clr_last_sc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrrb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
-  return vec_clrr(vsca, uia);
+  return vec_clr_last(vsca, uia);
 }
 
-vector unsigned char test_vec_clrr_uc(void) {
+vector unsigned char test_vec_clr_last_uc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrrb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
-  return vec_clrr(vuca, uia);
+  return vec_clr_last(vuca, uia);
 }
 
 vector unsigned long long test_vclzdm(void) {



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