r303753 - Generalize two diagnostic messages to take function name as parameter.

2017-05-24 Thread Tony Jiang via cfe-commits 
Author: jtony
Date: Wed May 24 09:45:57 2017
New Revision: 303753

URL: http://llvm.org/viewvc/llvm-project?rev=303753&view=rev
Log:
Generalize two diagnostic messages to take function name as parameter.

Modified:
cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td
cfe/trunk/lib/Sema/SemaChecking.cpp

Modified: cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td?rev=303753&r1=303752&r2=303753&view=diff
==
--- cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td (original)
+++ cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td Wed May 24 09:45:57 
2017
@@ -8012,10 +8012,10 @@ def err_block_on_nonlocal : Error<
 def err_block_on_vm : Error<
   "__block attribute not allowed on declaration with a variably modified 
type">;
 
-def err_shufflevector_non_vector : Error<
-  "first two arguments to __builtin_shufflevector must be vectors">;
-def err_shufflevector_incompatible_vector : Error<
-  "first two arguments to __builtin_shufflevector must have the same type">;
+def err_vec_builtin_non_vector : Error<
+ "first two arguments to %0 must be vectors">;
+def err_vec_builtin_incompatible_vector : Error<
+  "first two arguments to %0 must have the same type">;
 def err_shufflevector_nonconstant_argument : Error<
   "index for __builtin_shufflevector must be a constant integer">;
 def err_shufflevector_argument_too_large : Error<

Modified: cfe/trunk/lib/Sema/SemaChecking.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Sema/SemaChecking.cpp?rev=303753&r1=303752&r2=303753&view=diff
==
--- cfe/trunk/lib/Sema/SemaChecking.cpp (original)
+++ cfe/trunk/lib/Sema/SemaChecking.cpp Wed May 24 09:45:57 2017
@@ -3914,7 +3914,8 @@ ExprResult Sema::SemaBuiltinShuffleVecto
 
 if (!LHSType->isVectorType() || !RHSType->isVectorType())
   return ExprError(Diag(TheCall->getLocStart(),
-diag::err_shufflevector_non_vector)
+diag::err_vec_builtin_non_vector)
+   << TheCall->getDirectCallee()
<< SourceRange(TheCall->getArg(0)->getLocStart(),
   TheCall->getArg(1)->getLocEnd()));
 
@@ -3928,12 +3929,14 @@ ExprResult Sema::SemaBuiltinShuffleVecto
   if (!RHSType->hasIntegerRepresentation() ||
   RHSType->getAs()->getNumElements() != numElements)
 return ExprError(Diag(TheCall->getLocStart(),
-  diag::err_shufflevector_incompatible_vector)
+  diag::err_vec_builtin_incompatible_vector)
+ << TheCall->getDirectCallee()
  << SourceRange(TheCall->getArg(1)->getLocStart(),
 TheCall->getArg(1)->getLocEnd()));
 } else if (!Context.hasSameUnqualifiedType(LHSType, RHSType)) {
   return ExprError(Diag(TheCall->getLocStart(),
-diag::err_shufflevector_incompatible_vector)
+diag::err_vec_builtin_incompatible_vector)
+   << TheCall->getDirectCallee()
<< SourceRange(TheCall->getArg(0)->getLocStart(),
   TheCall->getArg(1)->getLocEnd()));
 } else if (numElements != numResElements) {


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r303760 - [PowerPC] Implement vec_xxpermdi builtin.

2017-05-24 Thread Tony Jiang via cfe-commits 
Author: jtony
Date: Wed May 24 10:13:32 2017
New Revision: 303760

URL: http://llvm.org/viewvc/llvm-project?rev=303760&view=rev
Log:
[PowerPC] Implement vec_xxpermdi builtin.

The vec_xxpermdi builtin is missing from altivec.h. This has been requested by
developers working on libvpx for VP9 support for Google.

The patch fixes PR: https://bugs.llvm.org/show_bug.cgi?id=32653
Differential Revision: https://reviews.llvm.org/D33053

Modified:
cfe/trunk/include/clang/Basic/BuiltinsPPC.def
cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td
cfe/trunk/include/clang/Sema/Sema.h
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
cfe/trunk/lib/Headers/altivec.h
cfe/trunk/lib/Sema/SemaChecking.cpp
cfe/trunk/test/CodeGen/builtins-ppc-error.c
cfe/trunk/test/CodeGen/builtins-ppc-vsx.c

Modified: cfe/trunk/include/clang/Basic/BuiltinsPPC.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsPPC.def?rev=303760&r1=303759&r2=303760&view=diff
==
--- cfe/trunk/include/clang/Basic/BuiltinsPPC.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsPPC.def Wed May 24 10:13:32 2017
@@ -420,6 +420,8 @@ BUILTIN(__builtin_vsx_xvtstdcsp, "V4UiV4
 BUILTIN(__builtin_vsx_insertword, "V16UcV4UiV16UcIi", "")
 BUILTIN(__builtin_vsx_extractuword, "V2ULLiV16UcIi", "")
 
+BUILTIN(__builtin_vsx_xxpermdi, "v.", "t")
+
 // HTM builtins
 BUILTIN(__builtin_tbegin, "UiUIi", "")
 BUILTIN(__builtin_tend, "UiUIi", "")

Modified: cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td?rev=303760&r1=303759&r2=303760&view=diff
==
--- cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td (original)
+++ cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td Wed May 24 10:13:32 
2017
@@ -8016,6 +8016,9 @@ def err_vec_builtin_non_vector : Error<
  "first two arguments to %0 must be vectors">;
 def err_vec_builtin_incompatible_vector : Error<
   "first two arguments to %0 must have the same type">;
+def err_vsx_builtin_nonconstant_argument : Error<
+  "argument %0 to %1 must be a 2-bit unsigned literal (i.e. 0, 1, 2 or 3)">;
+
 def err_shufflevector_nonconstant_argument : Error<
   "index for __builtin_shufflevector must be a constant integer">;
 def err_shufflevector_argument_too_large : Error<

Modified: cfe/trunk/include/clang/Sema/Sema.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Sema/Sema.h?rev=303760&r1=303759&r2=303760&view=diff
==
--- cfe/trunk/include/clang/Sema/Sema.h (original)
+++ cfe/trunk/include/clang/Sema/Sema.h Wed May 24 10:13:32 2017
@@ -10124,6 +10124,7 @@ private:
   bool SemaBuiltinVAStartARM(CallExpr *Call);
   bool SemaBuiltinUnorderedCompare(CallExpr *TheCall);
   bool SemaBuiltinFPClassification(CallExpr *TheCall, unsigned NumArgs);
+  bool SemaBuiltinVSX(CallExpr *TheCall);
   bool SemaBuiltinOSLogFormat(CallExpr *TheCall);
 
 public:

Modified: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=303760&r1=303759&r2=303760&view=diff
==
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp Wed May 24 10:13:32 2017
@@ -8442,6 +8442,39 @@ Value *CodeGenFunction::EmitPPCBuiltinEx
   return Builder.CreateCall(F, Ops);
 }
   }
+
+  case PPC::BI__builtin_vsx_xxpermdi: {
+ConstantInt *ArgCI = dyn_cast(Ops[2]);
+assert(ArgCI && "Third arg must be constant integer!");
+
+unsigned Index = ArgCI->getZExtValue();
+Ops[0] = Builder.CreateBitCast(Ops[0], llvm::VectorType::get(Int64Ty, 2));
+Ops[1] = Builder.CreateBitCast(Ops[1], llvm::VectorType::get(Int64Ty, 2));
+
+// Element zero comes from the first input vector and element one comes 
from
+// the second. The element indices within each vector are numbered in big
+// endian order so the shuffle mask must be adjusted for this on little
+// endian platforms (i.e. index is complemented and source vector 
reversed).
+unsigned ElemIdx0;
+unsigned ElemIdx1;
+if (getTarget().isLittleEndian()) {
+  ElemIdx0 = (~Index & 1) + 2;
+  ElemIdx1 = (~Index & 2) >> 1;
+} else { // BigEndian
+  ElemIdx0 = (Index & 2) >> 1;
+  ElemIdx1 = 2 + (Index & 1);
+}
+
+Constant *ShuffleElts[2] = {ConstantInt::get(Int32Ty, ElemIdx0),
+ConstantInt::get(Int32Ty, ElemIdx1)};
+Constant *ShuffleMask = llvm::ConstantVector::get(ShuffleElts);
+
+Value *ShuffleCall =
+Builder.CreateShuffleVector(Ops[0], Ops[1], ShuffleMask);
+QualType BIRetType = E->getType();
+auto RetTy = ConvertType(BIRetType);
+return Builder.CreateBitCast(Shu

r303766 - [PowerPC] Implement vec_xxsldwi builtin.

2017-05-24 Thread Tony Jiang via cfe-commits 
Author: jtony
Date: Wed May 24 10:54:13 2017
New Revision: 303766

URL: http://llvm.org/viewvc/llvm-project?rev=303766&view=rev
Log:
[PowerPC] Implement vec_xxsldwi builtin.

The vec_xxsldwi builtin is missing from altivec.h. This has been requested by
developers working on libvpx for VP9 support for Google.

The patch fixes PR: https://bugs.llvm.org/show_bug.cgi?id=32653
Differential Revision: https://reviews.llvm.org/D33236

Modified:
cfe/trunk/include/clang/Basic/BuiltinsPPC.def
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
cfe/trunk/lib/Headers/altivec.h
cfe/trunk/lib/Sema/SemaChecking.cpp
cfe/trunk/test/CodeGen/builtins-ppc-error.c
cfe/trunk/test/CodeGen/builtins-ppc-vsx.c

Modified: cfe/trunk/include/clang/Basic/BuiltinsPPC.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsPPC.def?rev=303766&r1=303765&r2=303766&view=diff
==
--- cfe/trunk/include/clang/Basic/BuiltinsPPC.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsPPC.def Wed May 24 10:54:13 2017
@@ -421,6 +421,7 @@ BUILTIN(__builtin_vsx_insertword, "V16Uc
 BUILTIN(__builtin_vsx_extractuword, "V2ULLiV16UcIi", "")
 
 BUILTIN(__builtin_vsx_xxpermdi, "v.", "t")
+BUILTIN(__builtin_vsx_xxsldwi, "v.", "t")
 
 // HTM builtins
 BUILTIN(__builtin_tbegin, "UiUIi", "")

Modified: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=303766&r1=303765&r2=303766&view=diff
==
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp Wed May 24 10:54:13 2017
@@ -8475,6 +8475,47 @@ Value *CodeGenFunction::EmitPPCBuiltinEx
 auto RetTy = ConvertType(BIRetType);
 return Builder.CreateBitCast(ShuffleCall, RetTy);
   }
+
+  case PPC::BI__builtin_vsx_xxsldwi: {
+ConstantInt *ArgCI = dyn_cast(Ops[2]);
+assert(ArgCI && "Third argument must be a compile time constant");
+unsigned Index = ArgCI->getZExtValue() & 0x3;
+Ops[0] = Builder.CreateBitCast(Ops[0], llvm::VectorType::get(Int32Ty, 4));
+Ops[1] = Builder.CreateBitCast(Ops[1], llvm::VectorType::get(Int32Ty, 4));
+
+// Create a shuffle mask
+unsigned ElemIdx0;
+unsigned ElemIdx1;
+unsigned ElemIdx2;
+unsigned ElemIdx3;
+if (getTarget().isLittleEndian()) {
+  // Little endian element N comes from element 8+N-Index of the
+  // concatenated wide vector (of course, using modulo arithmetic on
+  // the total number of elements).
+  ElemIdx0 = (8 - Index) % 8;
+  ElemIdx1 = (9 - Index) % 8;
+  ElemIdx2 = (10 - Index) % 8;
+  ElemIdx3 = (11 - Index) % 8;
+} else {
+  // Big endian ElemIdx = Index + N
+  ElemIdx0 = Index;
+  ElemIdx1 = Index + 1;
+  ElemIdx2 = Index + 2;
+  ElemIdx3 = Index + 3;
+}
+
+Constant *ShuffleElts[4] = {ConstantInt::get(Int32Ty, ElemIdx0),
+ConstantInt::get(Int32Ty, ElemIdx1),
+ConstantInt::get(Int32Ty, ElemIdx2),
+ConstantInt::get(Int32Ty, ElemIdx3)};
+
+Constant *ShuffleMask = llvm::ConstantVector::get(ShuffleElts);
+Value *ShuffleCall =
+Builder.CreateShuffleVector(Ops[0], Ops[1], ShuffleMask);
+QualType BIRetType = E->getType();
+auto RetTy = ConvertType(BIRetType);
+return Builder.CreateBitCast(ShuffleCall, RetTy);
+  }
   }
 }
 

Modified: cfe/trunk/lib/Headers/altivec.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/altivec.h?rev=303766&r1=303765&r2=303766&view=diff
==
--- cfe/trunk/lib/Headers/altivec.h (original)
+++ cfe/trunk/lib/Headers/altivec.h Wed May 24 10:54:13 2017
@@ -12158,6 +12158,7 @@ static __inline__ void __ATTRS_o_ai vec_
 
 #ifdef __VSX__
 #define vec_xxpermdi __builtin_vsx_xxpermdi
+#define vec_xxsldwi __builtin_vsx_xxsldwi
 #endif
 
 /* vec_xor */

Modified: cfe/trunk/lib/Sema/SemaChecking.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Sema/SemaChecking.cpp?rev=303766&r1=303765&r2=303766&view=diff
==
--- cfe/trunk/lib/Sema/SemaChecking.cpp (original)
+++ cfe/trunk/lib/Sema/SemaChecking.cpp Wed May 24 10:54:13 2017
@@ -1697,6 +1697,7 @@ bool Sema::CheckPPCBuiltinFunctionCall(u
 return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31) ||
SemaBuiltinConstantArgRange(TheCall, 2, 0, 31);
   case PPC::BI__builtin_vsx_xxpermdi:
+  case PPC::BI__builtin_vsx_xxsldwi:
 return SemaBuiltinVSX(TheCall);
   }
   return SemaBuiltinConstantArgRange(TheCall, i, l, u);

Modified: cfe/trunk/test/CodeGen/builtins-ppc-error.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-ppc-error.c?rev=303766&r1=303765&r2=303766&view=diff

r303786 - Fix one test case faiulre in commit 303766.

2017-05-24 Thread Tony Jiang via cfe-commits 
Author: jtony
Date: Wed May 24 13:12:11 2017
New Revision: 303786

URL: http://llvm.org/viewvc/llvm-project?rev=303786&view=rev
Log:
Fix one test case faiulre in commit 303766.

It is clean when I build boostrap and run make checkall on my machine, I guess
it could be I only build bootstrap with assert, while the buildbots may build
without asserts, which could cause the difference.

Modified:
cfe/trunk/test/CodeGen/builtins-ppc-vsx.c

Modified: cfe/trunk/test/CodeGen/builtins-ppc-vsx.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-ppc-vsx.c?rev=303786&r1=303785&r2=303786&view=diff
==
--- cfe/trunk/test/CodeGen/builtins-ppc-vsx.c (original)
+++ cfe/trunk/test/CodeGen/builtins-ppc-vsx.c Wed May 24 13:12:11 2017
@@ -1793,13 +1793,13 @@ vector int xxpermdi_should_not_assert(ve
 vector double xxsldwi_should_not_assert(vector double a, vector double b) {
   return vec_xxsldwi(a, b, 0);
 // CHECK-LABEL: xxsldwi_should_not_assert
-// CHECK:  bitcast <2 x double> %0 to <4 x i32>
-// CHECK-NEXT:  bitcast <2 x double> %1 to <4 x i32>
-// CHECK-NEXT:  shufflevector <4 x i32> %2, <4 x i32> %3, <4 x i32> 
-// CHECK-NEXT:  bitcast <4 x i32> %4 to <2 x double>
+// CHECK:  bitcast <2 x double> %{{[0-9]+}} to <4 x i32>
+// CHECK-NEXT:  bitcast <2 x double> %{{[0-9]+}} to <4 x i32>
+// CHECK-NEXT:  shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 
x i32> 
+// CHECK-NEXT:  bitcast <4 x i32> %{{[0-9]+}} to <2 x double>
 
-// CHECK-LE:  bitcast <2 x double> %0 to <4 x i32>
-// CHECK-NEXT-LE:  bitcast <2 x double> %1 to <4 x i32>
-// CHECK-NEXT-LE:  shufflevector <4 x i32> %2, <4 x i32> %3, <4 x i32> 
-// CHECK-NEXT-LE:  bitcast <4 x i32> %4 to <2 x double>
+// CHECK-LE:  bitcast <2 x double> %{{[0-9]+}} to <4 x i32>
+// CHECK-NEXT-LE:  bitcast <2 x double> %{{[0-9]+}} to <4 x i32>
+// CHECK-NEXT-LE:  shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, 
<4 x i32> 
+// CHECK-NEXT-LE:  bitcast <4 x i32> %{{[0-9]+}} to <2 x double>
 }


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r305401 - [PPC] Enhance altivec conversion function macros implementation.

2017-06-14 Thread Tony Jiang via cfe-commits 
Author: jtony
Date: Wed Jun 14 12:23:43 2017
New Revision: 305401

URL: http://llvm.org/viewvc/llvm-project?rev=305401&view=rev
Log:
[PPC] Enhance altivec conversion function macros implementation.

Add checking for the second parameter of altivec conversion builtin to make sure
it is compile-time constant int.

This patch fixes PR33212: PPC vec_cst useless at -O0
Differential Revision: https://reviews.llvm.org/D34092

Modified:
cfe/trunk/include/clang/Basic/BuiltinsPPC.def
cfe/trunk/test/CodeGen/builtins-ppc-error.c

Modified: cfe/trunk/include/clang/Basic/BuiltinsPPC.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsPPC.def?rev=305401&r1=305400&r2=305401&view=diff
==
--- cfe/trunk/include/clang/Basic/BuiltinsPPC.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsPPC.def Wed Jun 14 12:23:43 2017
@@ -51,10 +51,10 @@ BUILTIN(__builtin_altivec_vavguw, "V4UiV
 
 BUILTIN(__builtin_altivec_vrfip, "V4fV4f", "")
 
-BUILTIN(__builtin_altivec_vcfsx, "V4fV4ii", "")
-BUILTIN(__builtin_altivec_vcfux, "V4fV4ii", "")
-BUILTIN(__builtin_altivec_vctsxs, "V4SiV4fi", "")
-BUILTIN(__builtin_altivec_vctuxs, "V4UiV4fi", "")
+BUILTIN(__builtin_altivec_vcfsx, "V4fV4iIi", "")
+BUILTIN(__builtin_altivec_vcfux, "V4fV4iIi", "")
+BUILTIN(__builtin_altivec_vctsxs, "V4SiV4fIi", "")
+BUILTIN(__builtin_altivec_vctuxs, "V4UiV4fIi", "")
 
 BUILTIN(__builtin_altivec_dss, "vUi", "")
 BUILTIN(__builtin_altivec_dssall, "v", "")

Modified: cfe/trunk/test/CodeGen/builtins-ppc-error.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-ppc-error.c?rev=305401&r1=305400&r2=305401&view=diff
==
--- cfe/trunk/test/CodeGen/builtins-ppc-error.c (original)
+++ cfe/trunk/test/CodeGen/builtins-ppc-error.c Wed Jun 14 12:23:43 2017
@@ -11,6 +11,8 @@
 #include 
 
 extern vector signed int vsi;
+extern vector signed int vui;
+extern vector float vf;
 extern vector unsigned char vuc;
 
 void testInsertWord(void) {
@@ -34,3 +36,34 @@ void testXXSLDWI(int index) {
   vec_xxsldwi(1, 2, 3); //expected-error {{first two arguments to 
'__builtin_vsx_xxsldwi' must be vectors}}
   vec_xxsldwi(vsi, vuc, 2); //expected-error {{first two arguments to 
'__builtin_vsx_xxsldwi' must have the same type}}
 }
+
+void testCTF(int index) {
+  vec_ctf(vsi, index); //expected-error {{argument to 
'__builtin_altivec_vcfsx' must be a constant integer}}
+  vec_ctf(vui, index); //expected-error {{argument to 
'__builtin_altivec_vcfsx' must be a constant integer}}
+}
+
+void testVCFSX(int index) {
+  vec_vcfsx(vsi, index); //expected-error {{argument to 
'__builtin_altivec_vcfsx' must be a constant integer}}
+}
+
+void testVCFUX(int index) {
+  vec_vcfux(vui, index); //expected-error {{argument to 
'__builtin_altivec_vcfux' must be a constant integer}}
+}
+
+void testCTS(int index) {
+  vec_cts(vf, index); //expected-error {{argument to 
'__builtin_altivec_vctsxs' must be a constant integer}}
+
+}
+
+void testVCTSXS(int index) {
+  vec_vctsxs(vf, index); //expected-error {{argument to 
'__builtin_altivec_vctsxs' must be a constant integer}}
+}
+
+void testCTU(int index) {
+  vec_ctu(vf, index); //expected-error {{argument to 
'__builtin_altivec_vctuxs' must be a constant integer}}
+
+}
+
+void testVCTUXS(int index) {
+  vec_vctuxs(vf, index); //expected-error {{argument to 
'__builtin_altivec_vctuxs' must be a constant integer}}
+}


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r291702 - [PowerPC] Fix the wrong implementation of builtin vec_rlnm.

2017-01-11 Thread Tony Jiang via cfe-commits 
Author: jtony
Date: Wed Jan 11 14:59:42 2017
New Revision: 291702

URL: http://llvm.org/viewvc/llvm-project?rev=291702&view=rev
Log:
[PowerPC] Fix the wrong implementation of builtin vec_rlnm.

Modified:
cfe/trunk/lib/Headers/altivec.h
cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c

Modified: cfe/trunk/lib/Headers/altivec.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/altivec.h?rev=291702&r1=291701&r2=291702&view=diff
==
--- cfe/trunk/lib/Headers/altivec.h (original)
+++ cfe/trunk/lib/Headers/altivec.h Wed Jan 11 14:59:42 2017
@@ -7664,13 +7664,15 @@ vec_rlmi(vector unsigned long long __a,
 static __inline__ vector unsigned int __ATTRS_o_ai
 vec_rlnm(vector unsigned int __a, vector unsigned int __b,
  vector unsigned int __c) {
-  return __builtin_altivec_vrlwnm(__a, __b) & __c;
+  vector unsigned int OneByte = { 0x8, 0x8, 0x8, 0x8 };
+  return __builtin_altivec_vrlwnm(__a, ((__c << OneByte) | __b));
 }
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_rlnm(vector unsigned long long __a, vector unsigned long long __b,
  vector unsigned long long __c) {
-  return __builtin_altivec_vrldnm(__a, __b) & __c;
+  vector unsigned long long OneByte = { 0x8, 0x8 };
+  return __builtin_altivec_vrldnm(__a, ((__c << OneByte) | __b));
 }
 #endif
 

Modified: cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c?rev=291702&r1=291701&r2=291702&view=diff
==
--- cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c (original)
+++ cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c Wed Jan 11 14:59:42 2017
@@ -868,20 +868,24 @@ vector unsigned long long test76(void) {
   return vec_rlmi(vula, vula, vula);
 }
 vector unsigned int test77(void) {
+// CHECK-BE: %[[RES1:.+]] = shl <4 x i32
+// CHECK-BE: %[[RES2:.+]] = or <4 x i32> %[[RES1]]
 // CHECK-BE: @llvm.ppc.altivec.vrlwnm(<4 x i32
-// CHECK-BE: and <4 x i32
 // CHECK-BE: ret <4 x i32>
+// CHECK: %[[RES1:.+]] = shl <4 x i32
+// CHECK: %[[RES2:.+]] = or <4 x i32> %[[RES1]]
 // CHECK: @llvm.ppc.altivec.vrlwnm(<4 x i32
-// CHECK: and <4 x i32
 // CHECK: ret <4 x i32>
   return vec_rlnm(vuia, vuia, vuia);
 }
 vector unsigned long long test78(void) {
+// CHECK-BE: %[[RES1:.+]] = shl <2 x i64
+// CHECK-BE: %[[RES2:.+]] = or <2 x i64> %[[RES1]]
 // CHECK-BE: @llvm.ppc.altivec.vrldnm(<2 x i64
-// CHECK-BE: and <2 x i64
 // CHECK-BE-NEXT: ret <2 x i64>
+// CHECK: %[[RES1:.+]] = shl <2 x i64
+// CHECK: %[[RES2:.+]] = or <2 x i64> %[[RES1]]
 // CHECK: @llvm.ppc.altivec.vrldnm(<2 x i64
-// CHECK: and <2 x i64
 // CHECK-NEXT: ret <2 x i64>
   return vec_rlnm(vula, vula, vula);
 }


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r286971 - [PowerPC] Implement BE VSX load/store builtins - clang portion.

2016-11-15 Thread Tony Jiang via cfe-commits 
Author: jtony
Date: Tue Nov 15 08:30:56 2016
New Revision: 286971

URL: http://llvm.org/viewvc/llvm-project?rev=286971&view=rev
Log:
[PowerPC] Implement BE VSX load/store builtins - clang portion.

This patch implements all the overloads for vec_xl_be and vec_xst_be. On BE,
they behaves exactly the same with vec_xl and vec_xst, therefore they are
simply implemented by defining a matching macro. On LE, they are implemented
by defining new builtins and intrinsics. For int/float/long long/double, it
is just a load (lxvw4x/lxvd2x) or store(stxvw4x/stxvd2x). For char/char/short,
we also need some extra shuffling before or after call the builtins to get the
desired BE order. For int128, simply call vec_xl or vec_xst.

Modified:
cfe/trunk/include/clang/Basic/BuiltinsPPC.def
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
cfe/trunk/lib/Headers/altivec.h
cfe/trunk/test/CodeGen/builtins-ppc-altivec.c
cfe/trunk/test/CodeGen/builtins-ppc-quadword.c
cfe/trunk/test/CodeGen/builtins-ppc-vsx.c

Modified: cfe/trunk/include/clang/Basic/BuiltinsPPC.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsPPC.def?rev=286971&r1=286970&r2=286971&view=diff
==
--- cfe/trunk/include/clang/Basic/BuiltinsPPC.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsPPC.def Tue Nov 15 08:30:56 2016
@@ -303,9 +303,13 @@ BUILTIN(__builtin_altivec_vrldnm, "V2ULL
 
 BUILTIN(__builtin_vsx_lxvd2x, "V2divC*", "")
 BUILTIN(__builtin_vsx_lxvw4x, "V4iivC*", "")
+BUILTIN(__builtin_vsx_lxvd2x_be, "V2dSLLivC*", "")
+BUILTIN(__builtin_vsx_lxvw4x_be, "V4iSLLivC*", "")
 
 BUILTIN(__builtin_vsx_stxvd2x, "vV2div*", "")
 BUILTIN(__builtin_vsx_stxvw4x, "vV4iiv*", "")
+BUILTIN(__builtin_vsx_stxvd2x_be, "vV2dSLLivC*", "")
+BUILTIN(__builtin_vsx_stxvw4x_be, "vV4iSLLivC*", "")
 
 BUILTIN(__builtin_vsx_xvmaxdp, "V2dV2dV2d", "")
 BUILTIN(__builtin_vsx_xvmaxsp, "V4fV4fV4f", "")

Modified: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=286971&r1=286970&r2=286971&view=diff
==
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp Tue Nov 15 08:30:56 2016
@@ -7911,7 +7911,7 @@ Value *CodeGenFunction::EmitPPCBuiltinEx
   case PPC::BI__builtin_ppc_get_timebase:
 return Builder.CreateCall(CGM.getIntrinsic(Intrinsic::readcyclecounter));
 
-  // vec_ld, vec_lvsl, vec_lvsr
+  // vec_ld, vec_xl_be, vec_lvsl, vec_lvsr
   case PPC::BI__builtin_altivec_lvx:
   case PPC::BI__builtin_altivec_lvxl:
   case PPC::BI__builtin_altivec_lvebx:
@@ -7921,6 +7921,8 @@ Value *CodeGenFunction::EmitPPCBuiltinEx
   case PPC::BI__builtin_altivec_lvsr:
   case PPC::BI__builtin_vsx_lxvd2x:
   case PPC::BI__builtin_vsx_lxvw4x:
+  case PPC::BI__builtin_vsx_lxvd2x_be:
+  case PPC::BI__builtin_vsx_lxvw4x_be:
   {
 Ops[1] = Builder.CreateBitCast(Ops[1], Int8PtrTy);
 
@@ -7956,12 +7958,18 @@ Value *CodeGenFunction::EmitPPCBuiltinEx
 case PPC::BI__builtin_vsx_lxvw4x:
   ID = Intrinsic::ppc_vsx_lxvw4x;
   break;
+case PPC::BI__builtin_vsx_lxvd2x_be:
+  ID = Intrinsic::ppc_vsx_lxvd2x_be;
+  break;
+case PPC::BI__builtin_vsx_lxvw4x_be:
+  ID = Intrinsic::ppc_vsx_lxvw4x_be;
+  break;
 }
 llvm::Function *F = CGM.getIntrinsic(ID);
 return Builder.CreateCall(F, Ops, "");
   }
 
-  // vec_st
+  // vec_st, vec_xst_be
   case PPC::BI__builtin_altivec_stvx:
   case PPC::BI__builtin_altivec_stvxl:
   case PPC::BI__builtin_altivec_stvebx:
@@ -7969,6 +7977,8 @@ Value *CodeGenFunction::EmitPPCBuiltinEx
   case PPC::BI__builtin_altivec_stvewx:
   case PPC::BI__builtin_vsx_stxvd2x:
   case PPC::BI__builtin_vsx_stxvw4x:
+  case PPC::BI__builtin_vsx_stxvd2x_be:
+  case PPC::BI__builtin_vsx_stxvw4x_be:
   {
 Ops[2] = Builder.CreateBitCast(Ops[2], Int8PtrTy);
 Ops[1] = Builder.CreateGEP(Ops[2], Ops[1]);
@@ -7997,6 +8007,12 @@ Value *CodeGenFunction::EmitPPCBuiltinEx
 case PPC::BI__builtin_vsx_stxvw4x:
   ID = Intrinsic::ppc_vsx_stxvw4x;
   break;
+case PPC::BI__builtin_vsx_stxvd2x_be:
+  ID = Intrinsic::ppc_vsx_stxvd2x_be;
+  break;
+case PPC::BI__builtin_vsx_stxvw4x_be:
+  ID = Intrinsic::ppc_vsx_stxvw4x_be;
+  break;
 }
 llvm::Function *F = CGM.getIntrinsic(ID);
 return Builder.CreateCall(F, Ops, "");

Modified: cfe/trunk/lib/Headers/altivec.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/altivec.h?rev=286971&r1=286970&r2=286971&view=diff
==
--- cfe/trunk/lib/Headers/altivec.h (original)
+++ cfe/trunk/lib/Headers/altivec.h Tue Nov 15 08:30:56 2016
@@ -16133,6 +16133,82 @@ vec_xl(signed long long __offset, unsign
 }
 #endif
 
+/* vec_xl_be */
+
+#ifdef __LITTLE_ENDIAN__
+static __inline__ vector signed char __ATTRS_o_ai
+vec

[PATCH] D26160: [PowerPC] Implement remaining vector comparison builtins

2016-11-03 Thread Tony Jiang via cfe-commits 
jtony updated this revision to Diff 76862.
jtony marked 2 inline comments as done.
jtony added a comment.

Fix a few format and layout issues.

Format: clang-format is not always correct, sometimes separate parameters in 
different lines is better.
Layout: put the overloaded builtin functions  in such order:  signed version, 
unsigned version and bool version.


https://reviews.llvm.org/D26160

Files:
  lib/Headers/altivec.h
  test/CodeGen/builtins-ppc-altivec.c
  test/CodeGen/builtins-ppc-p8vector.c

Index: test/CodeGen/builtins-ppc-p8vector.c
===
--- test/CodeGen/builtins-ppc-p8vector.c
+++ test/CodeGen/builtins-ppc-p8vector.c
@@ -151,6 +151,11 @@
 // CHECK-PPC: warning: implicit declaration of function 'vec_mergeo'
   
   /* vec_cmpeq */
+  res_vbll = vec_cmpeq(vbll, vbll);
+// CHECK: @llvm.ppc.altivec.vcmpequd
+// CHECK-LE: @llvm.ppc.altivec.vcmpequd
+// CHECK-PPC: error: call to 'vec_cmpeq' is ambiguous
+
   res_vbll = vec_cmpeq(vsll, vsll);
 // CHECK: @llvm.ppc.altivec.vcmpequd
 // CHECK-LE: @llvm.ppc.altivec.vcmpequd
Index: test/CodeGen/builtins-ppc-altivec.c
===
--- test/CodeGen/builtins-ppc-altivec.c
+++ test/CodeGen/builtins-ppc-altivec.c
@@ -938,22 +938,34 @@
 // CHECK: @llvm.ppc.altivec.vcmpequb
 // CHECK-LE: @llvm.ppc.altivec.vcmpequb
 
+  res_vbc = vec_cmpeq(vbc, vbc);
+// CHECK: @llvm.ppc.altivec.vcmpequb
+// CHECK-LE: @llvm.ppc.altivec.vcmpequb
+
   res_vbs = vec_cmpeq(vs, vs);
 // CHECK: @llvm.ppc.altivec.vcmpequh
 // CHECK-LE: @llvm.ppc.altivec.vcmpequh
 
   res_vbs = vec_cmpeq(vus, vus);
 // CHECK: @llvm.ppc.altivec.vcmpequh
 // CHECK-LE: @llvm.ppc.altivec.vcmpequh
 
+  res_vbs = vec_cmpeq(vbs, vbs);
+// CHECK: @llvm.ppc.altivec.vcmpequh
+// CHECK-LE: @llvm.ppc.altivec.vcmpequh
+
   res_vbi = vec_cmpeq(vi, vi);
 // CHECK: @llvm.ppc.altivec.vcmpequw
 // CHECK-LE: @llvm.ppc.altivec.vcmpequw
 
   res_vbi = vec_cmpeq(vui, vui);
 // CHECK: @llvm.ppc.altivec.vcmpequw
 // CHECK-LE: @llvm.ppc.altivec.vcmpequw
 
+  res_vbi = vec_cmpeq(vbi, vbi);
+// CHECK: @llvm.ppc.altivec.vcmpequw
+// CHECK-LE: @llvm.ppc.altivec.vcmpequw
+
   res_vbi = vec_cmpeq(vf, vf);
 // CHECK: @llvm.ppc.altivec.vcmpeqfp
 // CHECK-LE: @llvm.ppc.altivec.vcmpeqfp
Index: lib/Headers/altivec.h
===
--- lib/Headers/altivec.h
+++ lib/Headers/altivec.h
@@ -1564,6 +1564,12 @@
   (vector char)__b);
 }
 
+static __inline__ vector bool char __ATTRS_o_ai
+vec_cmpeq(vector bool char __a, vector bool char __b) {
+  return (vector bool char)__builtin_altivec_vcmpequb((vector char)__a,
+  (vector char)__b);
+}
+
 static __inline__ vector bool short __ATTRS_o_ai vec_cmpeq(vector short __a,
vector short __b) {
   return (vector bool short)__builtin_altivec_vcmpequh(__a, __b);
@@ -1575,6 +1581,12 @@
(vector short)__b);
 }
 
+static __inline__ vector bool short __ATTRS_o_ai
+vec_cmpeq(vector bool short __a, vector bool short __b) {
+  return (vector bool short)__builtin_altivec_vcmpequh((vector short)__a,
+   (vector short)__b);
+}
+
 static __inline__ vector bool int __ATTRS_o_ai vec_cmpeq(vector int __a,
  vector int __b) {
   return (vector bool int)__builtin_altivec_vcmpequw(__a, __b);
@@ -1586,6 +1598,12 @@
  (vector int)__b);
 }
 
+static __inline__ vector bool int __ATTRS_o_ai vec_cmpeq(vector bool int __a,
+ vector bool int __b) {
+  return (vector bool int)__builtin_altivec_vcmpequw((vector int)__a,
+ (vector int)__b);
+}
+
 #ifdef __POWER8_VECTOR__
 static __inline__ vector bool long long __ATTRS_o_ai
 vec_cmpeq(vector signed long long __a, vector signed long long __b) {
@@ -1597,6 +1615,13 @@
   return (vector bool long long)__builtin_altivec_vcmpequd(
   (vector long long)__a, (vector long long)__b);
 }
+
+static __inline__ vector bool long long __ATTRS_o_ai
+vec_cmpeq(vector bool long long __a, vector bool long long __b) {
+  return (vector bool long long)__builtin_altivec_vcmpequd(
+  (vector long long)__a, (vector long long)__b);
+}
+
 #endif
 
 static __inline__ vector bool int __ATTRS_o_ai vec_cmpeq(vector float __a,
@@ -2298,14 +2323,15 @@
  result if either is zero.
   */
   vector bool char __tmp1 = vec_cmpeq(__a, __b);
-  vector bool char __tmp2 = __tmp1 | vec_cmpeq(__tmp1, __a) |
-vec_cmpeq(__tmp1, __b);
+  vector bool char __tmp2 = __tmp1 |
+vec_cmpeq((vector signed char)__tmp1, __a) |
+

[PATCH] D26282: [PowerPC] Implement plain VSX load/store builtins.

2016-11-03 Thread Tony Jiang via cfe-commits 
jtony created this revision.
jtony added reviewers: nemanjai, amehsan, kbarton, sfertile, syzaara, lei.
jtony added subscribers: llvm-commits, cfe-commits, echristo.

Implement all the different 24 overloads for vec_xl and vec_xst.

Signatures:
vector signed char vec_xl (signed long long, signed char *);
vector unsigned char vec_xl (signed long long, unsigned char *);
vector signed int vec_xl (signed long long, signed int *);
vector unsigned int vec_xl (signed long long, unsigned int *);
vector signed __int128 vec_xl (signed long long, signed __int128 *);
vector unsigned __int128 vec_xl (signed long long, unsigned __int128 *);
vector signed long long vec_xl (signed long long, signed long long *);
vector unsigned long long vec_xl (signed long long, unsigned long long *);
vector signed short vec_xl (signed long long, signed short *);
vector unsigned short vec_xl (signed long long, unsigned short *);
vector double vec_xl (signed long long, double *);
vector float vec_xl (signed long long, float *);
void vec_xst (vector signed char, signed long long, signed char *);
void vec_xst (vector unsigned char, signed long long, unsigned char *);
void vec_xst (vector signed int, signed long long, signed int *);
void vec_xst (vector unsigned int, signed long long, unsigned int *);
void vec_xst (vector signed __int128, signed long long, signed __int128 *);
void vec_xst (vector unsigned __int128, signed long long, unsigned __int128 *);
void vec_xst (vector signed long long, signed long long, signed long long *);
void vec_xst (vector unsigned long long, signed long long, unsigned long long 
*);
void vec_xst (vector signed short, signed long long, signed short *);
void vec_xst (vector unsigned short, signed long long, unsigned short *);
void vec_xst (vector double, signed long long, double *);
void vec_xst (vector float, signed long long, float *);


https://reviews.llvm.org/D26282

Files:
  lib/Headers/altivec.h
  test/CodeGen/builtins-ppc-altivec.c
  test/CodeGen/builtins-ppc-quadword.c
  test/CodeGen/builtins-ppc-vsx.c

Index: test/CodeGen/builtins-ppc-vsx.c
===
--- test/CodeGen/builtins-ppc-vsx.c
+++ test/CodeGen/builtins-ppc-vsx.c
@@ -21,6 +21,7 @@
 vector signed long long vsll = { 255LL, -937LL };
 vector unsigned long long vull = { 1447LL, 2894LL };
 double d = 23.4;
+signed long long sll = 618LL;
 float af[4] = {23.4f, 56.7f, 89.0f, 12.3f};
 double ad[2] = {23.4, 56.7};
 signed char asc[16] = { -8,  9, -10, 11, -12, 13, -14, 15,
@@ -31,8 +32,8 @@
 unsigned short aus[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
 signed int asi[4] = { -1, 2, -3, 4 };
 unsigned int aui[4] = { 0, 1, 2, 3 };
-signed long asl[2] = { -1L, 2L };
-unsigned long aul[2] = { 1L, 2L };
+signed long long asll[2] = { -1L, 2L };
+unsigned long long aull[2] = { 1L, 2L };
 
 vector float res_vf;
 vector double res_vd;
@@ -1248,4 +1249,28 @@
   res_vull = vec_sro(vull, vuc);
 // CHECK: @llvm.ppc.altivec.vsro
 // CHECK-LE: @llvm.ppc.altivec.vsro
+
+res_vsll = vec_xl(sll, asll);
+// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
+// CHECK-LE: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
+
+res_vull = vec_xl(sll, aull);
+// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
+// CHECK-LE: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
+
+res_vd = vec_xl(sll, ad);
+// CHECK: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 16
+// CHECK-LE: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 16
+
+vec_xst(vsll, sll, asll);
+// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
+// CHECK-LE: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
+
+vec_xst(vull, sll, aull);
+// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
+// CHECK-LE: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
+
+vec_xst(vd, sll, ad);
+// CHECK: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 16
+// CHECK-LE: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 16
 }
Index: test/CodeGen/builtins-ppc-quadword.c
===
--- test/CodeGen/builtins-ppc-quadword.c
+++ test/CodeGen/builtins-ppc-quadword.c
@@ -15,6 +15,12 @@
 // CHECK-PPC: error: __int128 is not supported on this target
 vector unsigned __int128 vulll = { 1 };
 
+signed long long param_sll;
+// CHECK-PPC: error: __int128 is not supported on this target
+signed __int128 param_lll;
+// CHECK-PPC: error: __int128 is not supported on this target
+unsigned __int128 param_ulll;
+
 // CHECK-PPC: error: __int128 is not supported on this target
 vector signed __int128 res_vlll;
 // CHECK-PPC: error: __int128 is not supported on this target
@@ -165,4 +171,26 @@
 // CHECK-LE: xor <16 x i8>
 // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
 // CHECK_PPC: error: call to 'vec_revb' is ambiguous
+
+  /* vec_xl */
+  res_vlll = vec_xl(param_sll, ¶m_lll);
+  // C

[PATCH] D26282: [PowerPC] Implement plain VSX load/store builtins.

2016-11-05 Thread Tony Jiang via cfe-commits 
jtony updated this revision to Diff 76945.
jtony added a comment.

Reorder the overloads according to their size.


https://reviews.llvm.org/D26282

Files:
  lib/Headers/altivec.h
  test/CodeGen/builtins-ppc-altivec.c
  test/CodeGen/builtins-ppc-quadword.c
  test/CodeGen/builtins-ppc-vsx.c

Index: test/CodeGen/builtins-ppc-vsx.c
===
--- test/CodeGen/builtins-ppc-vsx.c
+++ test/CodeGen/builtins-ppc-vsx.c
@@ -21,6 +21,7 @@
 vector signed long long vsll = { 255LL, -937LL };
 vector unsigned long long vull = { 1447LL, 2894LL };
 double d = 23.4;
+signed long long sll = 618LL;
 float af[4] = {23.4f, 56.7f, 89.0f, 12.3f};
 double ad[2] = {23.4, 56.7};
 signed char asc[16] = { -8,  9, -10, 11, -12, 13, -14, 15,
@@ -31,8 +32,8 @@
 unsigned short aus[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
 signed int asi[4] = { -1, 2, -3, 4 };
 unsigned int aui[4] = { 0, 1, 2, 3 };
-signed long asl[2] = { -1L, 2L };
-unsigned long aul[2] = { 1L, 2L };
+signed long long asll[2] = { -1L, 2L };
+unsigned long long aull[2] = { 1L, 2L };
 
 vector float res_vf;
 vector double res_vd;
@@ -1248,4 +1249,28 @@
   res_vull = vec_sro(vull, vuc);
 // CHECK: @llvm.ppc.altivec.vsro
 // CHECK-LE: @llvm.ppc.altivec.vsro
+
+res_vsll = vec_xl(sll, asll);
+// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
+// CHECK-LE: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
+
+res_vull = vec_xl(sll, aull);
+// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
+// CHECK-LE: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
+
+res_vd = vec_xl(sll, ad);
+// CHECK: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 16
+// CHECK-LE: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 16
+
+vec_xst(vsll, sll, asll);
+// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
+// CHECK-LE: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
+
+vec_xst(vull, sll, aull);
+// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
+// CHECK-LE: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
+
+vec_xst(vd, sll, ad);
+// CHECK: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 16
+// CHECK-LE: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 16
 }
Index: test/CodeGen/builtins-ppc-quadword.c
===
--- test/CodeGen/builtins-ppc-quadword.c
+++ test/CodeGen/builtins-ppc-quadword.c
@@ -15,6 +15,12 @@
 // CHECK-PPC: error: __int128 is not supported on this target
 vector unsigned __int128 vulll = { 1 };
 
+signed long long param_sll;
+// CHECK-PPC: error: __int128 is not supported on this target
+signed __int128 param_lll;
+// CHECK-PPC: error: __int128 is not supported on this target
+unsigned __int128 param_ulll;
+
 // CHECK-PPC: error: __int128 is not supported on this target
 vector signed __int128 res_vlll;
 // CHECK-PPC: error: __int128 is not supported on this target
@@ -165,4 +171,26 @@
 // CHECK-LE: xor <16 x i8>
 // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
 // CHECK_PPC: error: call to 'vec_revb' is ambiguous
+
+  /* vec_xl */
+  res_vlll = vec_xl(param_sll, ¶m_lll);
+  // CHECK: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-LE: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-PPC: error: call to 'vec_xl' is ambiguous
+
+  res_vulll = vec_xl(param_sll, ¶m_ulll);
+  // CHECK: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-LE: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-PPC: error: call to 'vec_xl' is ambiguous
+
+  /* vec_xst */
+   vec_xst(vlll, param_sll, ¶m_lll);
+  // CHECK: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-LE: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-PPC: error: call to 'vec_xst' is ambiguous
+
+   vec_xst(vulll, param_sll, ¶m_ulll);
+  // CHECK: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-LE: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-PPC: error: call to 'vec_xst' is ambiguous
 }
Index: test/CodeGen/builtins-ppc-altivec.c
===
--- test/CodeGen/builtins-ppc-altivec.c
+++ test/CodeGen/builtins-ppc-altivec.c
@@ -45,6 +45,7 @@
 int param_i;
 unsigned int param_ui;
 float param_f;
+signed long long param_sll;
 
 int res_sc;
 int res_uc;
@@ -9200,3 +9201,69 @@
 // CHECK-LE: xor <16 x i8>
 // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
 }
+
+/* -- vec_xl  */
+void test9() {
+  // CHECK-LABEL: define void @test9
+  // CHECK-LE-LABEL: define void @test9
+  res_vsc = vec_xl(param_sll, ¶m_sc);
+  // CHECK: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 16
+  // CHECK-LE: load <16 x i8>, <16 x i8>* %{{[0-9

[PATCH] D26160: [PowerPC] Implement remaining vector comparison builtins

2016-11-07 Thread Tony Jiang via cfe-commits 
jtony updated this revision to Diff 77036.
jtony added a comment.

I migrated the commit from the old anonymous repository to the new jtony 
repository to prepare for committing upstream (use git svn dcommit).  Should 
not have any difference with the previous patches, update it just in case.


https://reviews.llvm.org/D26160

Files:
  lib/Headers/altivec.h
  test/CodeGen/builtins-ppc-altivec.c
  test/CodeGen/builtins-ppc-p8vector.c

Index: test/CodeGen/builtins-ppc-p8vector.c
===
--- test/CodeGen/builtins-ppc-p8vector.c
+++ test/CodeGen/builtins-ppc-p8vector.c
@@ -151,6 +151,11 @@
 // CHECK-PPC: warning: implicit declaration of function 'vec_mergeo'
   
   /* vec_cmpeq */
+  res_vbll = vec_cmpeq(vbll, vbll);
+// CHECK: @llvm.ppc.altivec.vcmpequd
+// CHECK-LE: @llvm.ppc.altivec.vcmpequd
+// CHECK-PPC: error: call to 'vec_cmpeq' is ambiguous
+
   res_vbll = vec_cmpeq(vsll, vsll);
 // CHECK: @llvm.ppc.altivec.vcmpequd
 // CHECK-LE: @llvm.ppc.altivec.vcmpequd
Index: test/CodeGen/builtins-ppc-altivec.c
===
--- test/CodeGen/builtins-ppc-altivec.c
+++ test/CodeGen/builtins-ppc-altivec.c
@@ -938,6 +938,14 @@
 // CHECK: @llvm.ppc.altivec.vcmpequb
 // CHECK-LE: @llvm.ppc.altivec.vcmpequb
 
+  res_vbc = vec_cmpeq(vbc, vbc);
+// CHECK: @llvm.ppc.altivec.vcmpequb
+// CHECK-LE: @llvm.ppc.altivec.vcmpequb
+
+  res_vbc = vec_cmpeq(vbc, vbc);
+// CHECK: @llvm.ppc.altivec.vcmpequb
+// CHECK-LE: @llvm.ppc.altivec.vcmpequb
+
   res_vbs = vec_cmpeq(vs, vs);
 // CHECK: @llvm.ppc.altivec.vcmpequh
 // CHECK-LE: @llvm.ppc.altivec.vcmpequh
@@ -946,6 +954,14 @@
 // CHECK: @llvm.ppc.altivec.vcmpequh
 // CHECK-LE: @llvm.ppc.altivec.vcmpequh
 
+  res_vbs = vec_cmpeq(vbs, vbs);
+// CHECK: @llvm.ppc.altivec.vcmpequh
+// CHECK-LE: @llvm.ppc.altivec.vcmpequh
+
+  res_vbs = vec_cmpeq(vbs, vbs);
+// CHECK: @llvm.ppc.altivec.vcmpequh
+// CHECK-LE: @llvm.ppc.altivec.vcmpequh
+
   res_vbi = vec_cmpeq(vi, vi);
 // CHECK: @llvm.ppc.altivec.vcmpequw
 // CHECK-LE: @llvm.ppc.altivec.vcmpequw
@@ -954,6 +970,14 @@
 // CHECK: @llvm.ppc.altivec.vcmpequw
 // CHECK-LE: @llvm.ppc.altivec.vcmpequw
 
+  res_vbi = vec_cmpeq(vbi, vbi);
+// CHECK: @llvm.ppc.altivec.vcmpequw
+// CHECK-LE: @llvm.ppc.altivec.vcmpequw
+
+  res_vbi = vec_cmpeq(vbi, vbi);
+// CHECK: @llvm.ppc.altivec.vcmpequw
+// CHECK-LE: @llvm.ppc.altivec.vcmpequw
+
   res_vbi = vec_cmpeq(vf, vf);
 // CHECK: @llvm.ppc.altivec.vcmpeqfp
 // CHECK-LE: @llvm.ppc.altivec.vcmpeqfp
Index: lib/Headers/altivec.h
===
--- lib/Headers/altivec.h
+++ lib/Headers/altivec.h
@@ -1564,6 +1564,12 @@
   (vector char)__b);
 }
 
+static __inline__ vector bool char __ATTRS_o_ai
+vec_cmpeq(vector bool char __a, vector bool char __b) {
+  return (vector bool char)__builtin_altivec_vcmpequb((vector char)__a,
+  (vector char)__b);
+}
+
 static __inline__ vector bool short __ATTRS_o_ai vec_cmpeq(vector short __a,
vector short __b) {
   return (vector bool short)__builtin_altivec_vcmpequh(__a, __b);
@@ -1575,6 +1581,12 @@
(vector short)__b);
 }
 
+static __inline__ vector bool short __ATTRS_o_ai
+vec_cmpeq(vector bool short __a, vector bool short __b) {
+  return (vector bool short)__builtin_altivec_vcmpequh((vector short)__a,
+   (vector short)__b);
+}
+
 static __inline__ vector bool int __ATTRS_o_ai vec_cmpeq(vector int __a,
  vector int __b) {
   return (vector bool int)__builtin_altivec_vcmpequw(__a, __b);
@@ -1586,6 +1598,12 @@
  (vector int)__b);
 }
 
+static __inline__ vector bool int __ATTRS_o_ai vec_cmpeq(vector bool int __a,
+ vector bool int __b) {
+  return (vector bool int)__builtin_altivec_vcmpequw((vector int)__a,
+ (vector int)__b);
+}
+
 #ifdef __POWER8_VECTOR__
 static __inline__ vector bool long long __ATTRS_o_ai
 vec_cmpeq(vector signed long long __a, vector signed long long __b) {
@@ -1597,6 +1615,13 @@
   return (vector bool long long)__builtin_altivec_vcmpequd(
   (vector long long)__a, (vector long long)__b);
 }
+
+static __inline__ vector bool long long __ATTRS_o_ai
+vec_cmpeq(vector bool long long __a, vector bool long long __b) {
+  return (vector bool long long)__builtin_altivec_vcmpequd(
+  (vector long long)__a, (vector long long)__b);
+}
+
 #endif
 
 static __inline__ vector bool int __ATTRS_o_ai vec_cmpeq(vector float __a,
@@ -2298,14 +2323,15 @@
  result if either is zero.
   */
   vector bool char __tmp1 = vec_cm

[PATCH] D26282: [PowerPC] Implement plain VSX load/store builtins.

2016-11-07 Thread Tony Jiang via cfe-commits 
jtony updated this revision to Diff 77037.
jtony added a comment.

I also migrated this commit from the old anonymous repository to the new jtony 
repository to prepare for committing upstream (use git svn dcommit). Should not 
have any difference with the previous patch, update it just in case.


https://reviews.llvm.org/D26282

Files:
  lib/Headers/altivec.h
  test/CodeGen/builtins-ppc-altivec.c
  test/CodeGen/builtins-ppc-quadword.c
  test/CodeGen/builtins-ppc-vsx.c

Index: test/CodeGen/builtins-ppc-vsx.c
===
--- test/CodeGen/builtins-ppc-vsx.c
+++ test/CodeGen/builtins-ppc-vsx.c
@@ -21,6 +21,7 @@
 vector signed long long vsll = { 255LL, -937LL };
 vector unsigned long long vull = { 1447LL, 2894LL };
 double d = 23.4;
+signed long long sll = 618LL;
 float af[4] = {23.4f, 56.7f, 89.0f, 12.3f};
 double ad[2] = {23.4, 56.7};
 signed char asc[16] = { -8,  9, -10, 11, -12, 13, -14, 15,
@@ -31,8 +32,8 @@
 unsigned short aus[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
 signed int asi[4] = { -1, 2, -3, 4 };
 unsigned int aui[4] = { 0, 1, 2, 3 };
-signed long asl[2] = { -1L, 2L };
-unsigned long aul[2] = { 1L, 2L };
+signed long long asll[2] = { -1L, 2L };
+unsigned long long aull[2] = { 1L, 2L };
 
 vector float res_vf;
 vector double res_vd;
@@ -1248,4 +1249,28 @@
   res_vull = vec_sro(vull, vuc);
 // CHECK: @llvm.ppc.altivec.vsro
 // CHECK-LE: @llvm.ppc.altivec.vsro
+
+res_vsll = vec_xl(sll, asll);
+// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
+// CHECK-LE: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
+
+res_vull = vec_xl(sll, aull);
+// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
+// CHECK-LE: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
+
+res_vd = vec_xl(sll, ad);
+// CHECK: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 16
+// CHECK-LE: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 16
+
+vec_xst(vsll, sll, asll);
+// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
+// CHECK-LE: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
+
+vec_xst(vull, sll, aull);
+// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
+// CHECK-LE: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
+
+vec_xst(vd, sll, ad);
+// CHECK: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 16
+// CHECK-LE: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 16
 }
Index: test/CodeGen/builtins-ppc-quadword.c
===
--- test/CodeGen/builtins-ppc-quadword.c
+++ test/CodeGen/builtins-ppc-quadword.c
@@ -15,6 +15,12 @@
 // CHECK-PPC: error: __int128 is not supported on this target
 vector unsigned __int128 vulll = { 1 };
 
+signed long long param_sll;
+// CHECK-PPC: error: __int128 is not supported on this target
+signed __int128 param_lll;
+// CHECK-PPC: error: __int128 is not supported on this target
+unsigned __int128 param_ulll;
+
 // CHECK-PPC: error: __int128 is not supported on this target
 vector signed __int128 res_vlll;
 // CHECK-PPC: error: __int128 is not supported on this target
@@ -165,4 +171,26 @@
 // CHECK-LE: xor <16 x i8>
 // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
 // CHECK_PPC: error: call to 'vec_revb' is ambiguous
+
+  /* vec_xl */
+  res_vlll = vec_xl(param_sll, ¶m_lll);
+  // CHECK: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-LE: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-PPC: error: call to 'vec_xl' is ambiguous
+
+  res_vulll = vec_xl(param_sll, ¶m_ulll);
+  // CHECK: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-LE: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-PPC: error: call to 'vec_xl' is ambiguous
+
+  /* vec_xst */
+   vec_xst(vlll, param_sll, ¶m_lll);
+  // CHECK: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-LE: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-PPC: error: call to 'vec_xst' is ambiguous
+
+   vec_xst(vulll, param_sll, ¶m_ulll);
+  // CHECK: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-LE: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-PPC: error: call to 'vec_xst' is ambiguous
 }
Index: test/CodeGen/builtins-ppc-altivec.c
===
--- test/CodeGen/builtins-ppc-altivec.c
+++ test/CodeGen/builtins-ppc-altivec.c
@@ -45,6 +45,7 @@
 int param_i;
 unsigned int param_ui;
 float param_f;
+signed long long param_sll;
 
 int res_sc;
 int res_uc;
@@ -9224,3 +9225,69 @@
 // CHECK-LE: xor <16 x i8>
 // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
 }
+
+/* -- vec_xl  */
+void test9() {
+  // CHECK-LABEL: define void @test9
+  // CHE

r286205 - [PowerPC] Implement remaining vector comparison builtins.

2016-11-08 Thread Tony Jiang via cfe-commits 
Author: jtony
Date: Mon Nov  7 22:15:45 2016
New Revision: 286205

URL: http://llvm.org/viewvc/llvm-project?rev=286205&view=rev
Log:
[PowerPC] Implement remaining vector comparison builtins.

vector bool char vec_cmpeq (vector bool char, vector bool char);
vector bool int vec_cmpeq (vector bool int, vector bool int);
vector bool long long vec_cmpeq (vector bool long long, vector bool long lon
vector bool short vec_cmpeq (vector bool short, vector bool short);

Modified:
cfe/trunk/lib/Headers/altivec.h
cfe/trunk/test/CodeGen/builtins-ppc-altivec.c
cfe/trunk/test/CodeGen/builtins-ppc-p8vector.c

Modified: cfe/trunk/lib/Headers/altivec.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/altivec.h?rev=286205&r1=286204&r2=286205&view=diff
==
--- cfe/trunk/lib/Headers/altivec.h (original)
+++ cfe/trunk/lib/Headers/altivec.h Mon Nov  7 22:15:45 2016
@@ -1564,6 +1564,12 @@ vec_cmpeq(vector unsigned char __a, vect
   (vector char)__b);
 }
 
+static __inline__ vector bool char __ATTRS_o_ai
+vec_cmpeq(vector bool char __a, vector bool char __b) {
+  return (vector bool char)__builtin_altivec_vcmpequb((vector char)__a,
+  (vector char)__b);
+}
+
 static __inline__ vector bool short __ATTRS_o_ai vec_cmpeq(vector short __a,
vector short __b) {
   return (vector bool short)__builtin_altivec_vcmpequh(__a, __b);
@@ -1575,6 +1581,12 @@ vec_cmpeq(vector unsigned short __a, vec
(vector short)__b);
 }
 
+static __inline__ vector bool short __ATTRS_o_ai
+vec_cmpeq(vector bool short __a, vector bool short __b) {
+  return (vector bool short)__builtin_altivec_vcmpequh((vector short)__a,
+   (vector short)__b);
+}
+
 static __inline__ vector bool int __ATTRS_o_ai vec_cmpeq(vector int __a,
  vector int __b) {
   return (vector bool int)__builtin_altivec_vcmpequw(__a, __b);
@@ -1586,6 +1598,12 @@ vec_cmpeq(vector unsigned int __a, vecto
  (vector int)__b);
 }
 
+static __inline__ vector bool int __ATTRS_o_ai vec_cmpeq(vector bool int __a,
+ vector bool int __b) {
+  return (vector bool int)__builtin_altivec_vcmpequw((vector int)__a,
+ (vector int)__b);
+}
+
 #ifdef __POWER8_VECTOR__
 static __inline__ vector bool long long __ATTRS_o_ai
 vec_cmpeq(vector signed long long __a, vector signed long long __b) {
@@ -1597,6 +1615,13 @@ vec_cmpeq(vector unsigned long long __a,
   return (vector bool long long)__builtin_altivec_vcmpequd(
   (vector long long)__a, (vector long long)__b);
 }
+
+static __inline__ vector bool long long __ATTRS_o_ai
+vec_cmpeq(vector bool long long __a, vector bool long long __b) {
+  return (vector bool long long)__builtin_altivec_vcmpequd(
+  (vector long long)__a, (vector long long)__b);
+}
+
 #endif
 
 static __inline__ vector bool int __ATTRS_o_ai vec_cmpeq(vector float __a,
@@ -2298,14 +2323,15 @@ vec_first_match_or_eos_index(vector sign
  result if either is zero.
   */
   vector bool char __tmp1 = vec_cmpeq(__a, __b);
-  vector bool char __tmp2 = __tmp1 | vec_cmpeq(__tmp1, __a) |
-vec_cmpeq(__tmp1, __b);
+  vector bool char __tmp2 = __tmp1 |
+vec_cmpeq((vector signed char)__tmp1, __a) |
+vec_cmpeq((vector signed char)__tmp1, __b);
 
   vector unsigned long long __res =
 #ifdef __LITTLE_ENDIAN__
-vec_cnttz((vector unsigned long long)__tmp2);
+  vec_cnttz((vector unsigned long long)__tmp2);
 #else
-vec_cntlz((vector unsigned long long)__tmp2);
+  vec_cntlz((vector unsigned long long)__tmp2);
 #endif
   if (__res[0] == 64) {
 return (__res[1] + 64) >> 3;
@@ -2317,14 +2343,15 @@ static __inline__ unsigned __ATTRS_o_ai
 vec_first_match_or_eos_index(vector unsigned char __a,
  vector unsigned char __b) {
   vector bool char __tmp1 = vec_cmpeq(__a, __b);
-  vector bool char __tmp2 = __tmp1 | vec_cmpeq(__tmp1, __a) |
-vec_cmpeq(__tmp1, __b);
+  vector bool char __tmp2 = __tmp1 |
+vec_cmpeq((vector unsigned char)__tmp1, __a) |
+vec_cmpeq((vector unsigned char)__tmp1, __b);
 
   vector unsigned long long __res =
 #ifdef __LITTLE_ENDIAN__
-vec_cnttz((vector unsigned long long)__tmp2);
+  vec_cnttz((vector unsigned long long)__tmp2);
 #else
-vec_cntlz((vector unsigned long long)__tmp2);
+  vec_cntlz((vector unsigned long long)__tmp2);
 #endif
   if (__res[0] == 64) {
 return (__res[1] + 64) >> 3;
@@ -2335,14 +2362,15 @@ vec_first_match_or_eos_

[PATCH] D26271: [PPC} add extract significand/ extract exponent/test data class for vector float and vector double -- clang portion

2016-11-08 Thread Tony Jiang via cfe-commits 
jtony added a comment.

A very small nit,  the bracket does not match in the title, do you mean [PPC] 
instead of [PPC}?


Repository:
  rL LLVM

https://reviews.llvm.org/D26271



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[PATCH] D26282: [PowerPC] Implement plain VSX load/store builtins.

2016-11-08 Thread Tony Jiang via cfe-commits 
jtony updated this revision to Diff 77190.
jtony added a comment.

Add -U99 option to git diff to show context for this patch.


https://reviews.llvm.org/D26282

Files:
  lib/Headers/altivec.h
  test/CodeGen/builtins-ppc-altivec.c
  test/CodeGen/builtins-ppc-quadword.c
  test/CodeGen/builtins-ppc-vsx.c

Index: test/CodeGen/builtins-ppc-vsx.c
===
--- test/CodeGen/builtins-ppc-vsx.c
+++ test/CodeGen/builtins-ppc-vsx.c
@@ -21,6 +21,7 @@
 vector signed long long vsll = { 255LL, -937LL };
 vector unsigned long long vull = { 1447LL, 2894LL };
 double d = 23.4;
+signed long long sll = 618LL;
 float af[4] = {23.4f, 56.7f, 89.0f, 12.3f};
 double ad[2] = {23.4, 56.7};
 signed char asc[16] = { -8,  9, -10, 11, -12, 13, -14, 15,
@@ -31,8 +32,8 @@
 unsigned short aus[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
 signed int asi[4] = { -1, 2, -3, 4 };
 unsigned int aui[4] = { 0, 1, 2, 3 };
-signed long asl[2] = { -1L, 2L };
-unsigned long aul[2] = { 1L, 2L };
+signed long long asll[2] = { -1L, 2L };
+unsigned long long aull[2] = { 1L, 2L };
 
 vector float res_vf;
 vector double res_vd;
@@ -1248,4 +1249,28 @@
   res_vull = vec_sro(vull, vuc);
 // CHECK: @llvm.ppc.altivec.vsro
 // CHECK-LE: @llvm.ppc.altivec.vsro
+
+res_vsll = vec_xl(sll, asll);
+// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
+// CHECK-LE: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
+
+res_vull = vec_xl(sll, aull);
+// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
+// CHECK-LE: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
+
+res_vd = vec_xl(sll, ad);
+// CHECK: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 16
+// CHECK-LE: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 16
+
+vec_xst(vsll, sll, asll);
+// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
+// CHECK-LE: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
+
+vec_xst(vull, sll, aull);
+// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
+// CHECK-LE: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
+
+vec_xst(vd, sll, ad);
+// CHECK: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 16
+// CHECK-LE: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 16
 }
Index: test/CodeGen/builtins-ppc-quadword.c
===
--- test/CodeGen/builtins-ppc-quadword.c
+++ test/CodeGen/builtins-ppc-quadword.c
@@ -15,6 +15,12 @@
 // CHECK-PPC: error: __int128 is not supported on this target
 vector unsigned __int128 vulll = { 1 };
 
+signed long long param_sll;
+// CHECK-PPC: error: __int128 is not supported on this target
+signed __int128 param_lll;
+// CHECK-PPC: error: __int128 is not supported on this target
+unsigned __int128 param_ulll;
+
 // CHECK-PPC: error: __int128 is not supported on this target
 vector signed __int128 res_vlll;
 // CHECK-PPC: error: __int128 is not supported on this target
@@ -165,4 +171,26 @@
 // CHECK-LE: xor <16 x i8>
 // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
 // CHECK_PPC: error: call to 'vec_revb' is ambiguous
+
+  /* vec_xl */
+  res_vlll = vec_xl(param_sll, ¶m_lll);
+  // CHECK: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-LE: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-PPC: error: call to 'vec_xl' is ambiguous
+
+  res_vulll = vec_xl(param_sll, ¶m_ulll);
+  // CHECK: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-LE: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-PPC: error: call to 'vec_xl' is ambiguous
+
+  /* vec_xst */
+   vec_xst(vlll, param_sll, ¶m_lll);
+  // CHECK: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-LE: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-PPC: error: call to 'vec_xst' is ambiguous
+
+   vec_xst(vulll, param_sll, ¶m_ulll);
+  // CHECK: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-LE: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-PPC: error: call to 'vec_xst' is ambiguous
 }
Index: test/CodeGen/builtins-ppc-altivec.c
===
--- test/CodeGen/builtins-ppc-altivec.c
+++ test/CodeGen/builtins-ppc-altivec.c
@@ -45,6 +45,7 @@
 int param_i;
 unsigned int param_ui;
 float param_f;
+signed long long param_sll;
 
 int res_sc;
 int res_uc;
@@ -9224,3 +9225,69 @@
 // CHECK-LE: xor <16 x i8>
 // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
 }
+
+/* -- vec_xl  */
+void test9() {
+  // CHECK-LABEL: define void @test9
+  // CHECK-LE-LABEL: define void @test9
+  res_vsc = vec_xl(param_sll, ¶m_sc);
+  // CHECK: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 16
+  // CHECK-LE: load <16 x i8>, <

r286455 - [PowerPC] Implement plain VSX load/store builtins.

2016-11-10 Thread Tony Jiang via cfe-commits 
Author: jtony
Date: Thu Nov 10 08:39:56 2016
New Revision: 286455

URL: http://llvm.org/viewvc/llvm-project?rev=286455&view=rev
Log:
[PowerPC] Implement plain VSX load/store builtins.

Implement all the different 24 overloads for vec_xl and vec_xst.

Modified:
cfe/trunk/lib/Headers/altivec.h
cfe/trunk/test/CodeGen/builtins-ppc-altivec.c
cfe/trunk/test/CodeGen/builtins-ppc-quadword.c
cfe/trunk/test/CodeGen/builtins-ppc-vsx.c

Modified: cfe/trunk/lib/Headers/altivec.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/altivec.h?rev=286455&r1=286454&r2=286455&view=diff
==
--- cfe/trunk/lib/Headers/altivec.h (original)
+++ cfe/trunk/lib/Headers/altivec.h Thu Nov 10 08:39:56 2016
@@ -15606,6 +15606,150 @@ vec_revb(vector unsigned __int128 __a) {
 }
 #endif /* END __POWER8_VECTOR__ && __powerpc64__ */
 
+
+/* vec_xl */
+
+static inline __ATTRS_o_ai vector signed char vec_xl(signed long long __offset,
+ signed char *__ptr) {
+  return *(vector signed char *)(__ptr + __offset);
+}
+
+static inline __ATTRS_o_ai vector unsigned char
+vec_xl(signed long long __offset, unsigned char *__ptr) {
+  return *(vector unsigned char *)(__ptr + __offset);
+}
+
+static inline __ATTRS_o_ai vector signed short vec_xl(signed long long 
__offset,
+  signed short *__ptr) {
+  return *(vector signed short *)(__ptr + __offset);
+}
+
+static inline __ATTRS_o_ai vector unsigned short
+vec_xl(signed long long __offset, unsigned short *__ptr) {
+  return *(vector unsigned short *)(__ptr + __offset);
+}
+
+static inline __ATTRS_o_ai vector signed int vec_xl(signed long long __offset,
+signed int *__ptr) {
+  return *(vector signed int *)(__ptr + __offset);
+}
+
+static inline __ATTRS_o_ai vector unsigned int vec_xl(signed long long 
__offset,
+  unsigned int *__ptr) {
+  return *(vector unsigned int *)(__ptr + __offset);
+}
+
+static inline __ATTRS_o_ai vector float vec_xl(signed long long __offset,
+   float *__ptr) {
+  return *(vector float *)(__ptr + __offset);
+}
+
+#ifdef __VSX__
+static inline __ATTRS_o_ai vector signed long long
+vec_xl(signed long long __offset, signed long long *__ptr) {
+  return *(vector signed long long *)(__ptr + __offset);
+}
+
+static inline __ATTRS_o_ai vector unsigned long long
+vec_xl(signed long long __offset, unsigned long long *__ptr) {
+  return *(vector unsigned long long *)(__ptr + __offset);
+}
+
+static inline __ATTRS_o_ai vector double vec_xl(signed long long __offset,
+double *__ptr) {
+  return *(vector double *)(__ptr + __offset);
+}
+#endif
+
+#if defined(__POWER8_VECTOR__) && defined(__powerpc64__)
+static inline __ATTRS_o_ai vector signed __int128
+vec_xl(signed long long __offset, signed __int128 *__ptr) {
+  return *(vector signed __int128 *)(__ptr + __offset);
+}
+
+static inline __ATTRS_o_ai vector unsigned __int128
+vec_xl(signed long long __offset, unsigned __int128 *__ptr) {
+  return *(vector unsigned __int128 *)(__ptr + __offset);
+}
+#endif
+
+/* vec_xst */
+
+static inline __ATTRS_o_ai void vec_xst(vector signed char __vec,
+signed long long __offset,
+signed char *__ptr) {
+  *(vector signed char *)(__ptr + __offset) = __vec;
+}
+
+static inline __ATTRS_o_ai void vec_xst(vector unsigned char __vec,
+signed long long __offset,
+unsigned char *__ptr) {
+  *(vector unsigned char *)(__ptr + __offset) = __vec;
+}
+
+static inline __ATTRS_o_ai void vec_xst(vector signed short __vec,
+signed long long __offset,
+signed short *__ptr) {
+  *(vector signed short *)(__ptr + __offset) = __vec;
+}
+
+static inline __ATTRS_o_ai void vec_xst(vector unsigned short __vec,
+signed long long __offset,
+unsigned short *__ptr) {
+  *(vector unsigned short *)(__ptr + __offset) = __vec;
+}
+
+static inline __ATTRS_o_ai void vec_xst(vector signed int __vec,
+signed long long __offset,
+signed int *__ptr) {
+  *(vector signed int *)(__ptr + __offset) = __vec;
+}
+
+static inline __ATTRS_o_ai void vec_xst(vector unsigned int __vec,
+signed long long __offset,
+unsigned int *__ptr) {
+  *(vector unsigned int *)(__ptr + __offset) = __vec;
+}
+
+static inline __ATTRS_o_ai void vec_xst(vector float __vec,
+

[PATCH] D26519: [PowerPC] Implement BE VSX load/store builtins - clang portion.

2016-11-10 Thread Tony Jiang via cfe-commits 
jtony created this revision.
jtony added reviewers: nemanjai, amehsan, kbarton, sfertile, syzaara, lei.
jtony added subscribers: cfe-commits, echristo, llvm-commits.

This patch implements all the overloads for vec_xl_be and vec_xst_be. On BE,
they behaves exactly the same with vec_xl and vec_xst, therefore they are
simply implemented by defining a matching macro. On LE, they are implemented
by defining new builtins and intrinsics. For int/float/long long/double, it
is just a load (lxvw4x/lxvd2x) or store(stxvw4x/stxvd2x). For char/char/short,
we also need some extra shuffling before or after call the builtins to get the
desired BE order. For int128, simply call vec_xl or vec_xst.

Signatures:
vector signed char vec_xl_be (signed long long, signed char *);
vector unsigned char vec_xl_be (signed long long, unsigned char *);
vector signed int vec_xl_be (signed long long, signed int *);
vector unsigned int vec_xl_be (signed long long, unsigned int *);
vector signed __int128 vec_xl_be (signed long long, signed __int128 *);
vector unsigned __int128 vec_xl_be (signed long long, unsigned __int128 *);
vector signed long long vec_xl_be (signed long long, signed long long *);
vector unsigned long long vec_xl_be (signed long long, unsigned long long *);
vector signed short vec_xl_be (signed long long, signed short *);
vector unsigned short vec_xl_be (signed long long, unsigned short *);
vector double vec_xl_be (signed long long, double *);
vector float vec_xl_be (signed long long, float *);
void vec_xst_be (vector signed char, signed long long, signed char *);
void vec_xst_be (vector unsigned char, signed long long, unsigned char *);
void vec_xst_be (vector signed int, signed long long, signed int *);
void vec_xst_be (vector unsigned int, signed long long, unsigned int *);
void vec_xst_be (vector signed __int128, signed long long, signed __int128 *);
void vec_xst_be (vector unsigned __int128, signed long long, unsigned __int128 
*);
void vec_xst_be (vector signed long long, signed long long, signed long long *);
void vec_xst_be (vector unsigned long long, signed long long, unsigned long 
long *);
void vec_xst_be (vector signed short, signed long long, signed short *);
void vec_xst_be (vector unsigned short, signed long long, unsigned short *);
void vec_xst_be (vector double, signed long long, double *);
void vec_xst_be (vector float, signed long long, float *);


https://reviews.llvm.org/D26519

Files:
  include/clang/Basic/BuiltinsPPC.def
  lib/CodeGen/CGBuiltin.cpp
  lib/Headers/altivec.h
  test/CodeGen/builtins-ppc-altivec.c
  test/CodeGen/builtins-ppc-quadword.c
  test/CodeGen/builtins-ppc-vsx.c

Index: test/CodeGen/builtins-ppc-vsx.c
===
--- test/CodeGen/builtins-ppc-vsx.c
+++ test/CodeGen/builtins-ppc-vsx.c
@@ -1273,4 +1273,28 @@
 vec_xst(vd, sll, ad);
 // CHECK: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 16
 // CHECK-LE: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 16
+
+res_vsll = vec_xl_be(sll, asll);
+// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
+// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}})
+
+res_vull = vec_xl_be(sll, aull);
+// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 16
+// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}})
+
+res_vd = vec_xl_be(sll, ad);
+// CHECK: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 16
+// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}})
+
+vec_xst_be(vsll, sll, asll);
+// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
+// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}})
+
+vec_xst_be(vull, sll, aull);
+// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 16
+// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}})
+
+vec_xst_be(vd, sll, ad);
+// CHECK: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 16
+// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}})
 }
Index: test/CodeGen/builtins-ppc-quadword.c
===
--- test/CodeGen/builtins-ppc-quadword.c
+++ test/CodeGen/builtins-ppc-quadword.c
@@ -193,4 +193,26 @@
   // CHECK: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16
   // CHECK-LE: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 16
   // CHECK-PPC: error: call to 'vec_xst' is ambiguous
+
+  /* vec_xl_be */
+  res_vlll = vec_xl_be(param_sll, ¶m_lll);
+  // CHECK: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-LE: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-PPC: error: call to 'vec_xl' is ambiguous
+
+  res_vulll = vec_xl_be(param_sll, ¶m_ulll);
+  // CHECK: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-LE: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 16
+  // CHECK-PPC

[PATCH] D26520: [PowerPC] Implement BE VSX load/store builtins - llvm portion.

2016-11-10 Thread Tony Jiang via cfe-commits 
jtony created this revision.
jtony added reviewers: nemanjai, sfertile, syzaara, lei, kbarton, amehsan.
jtony added subscribers: llvm-commits, cfe-commits, echristo.

This patch implements all the overloads for vec_xl_be and vec_xst_be. On BE,
they behaves exactly the same with vec_xl and vec_xst, therefore they are
simply implemented by defining a matching macro. On LE, they are implemented
by defining new builtins and intrinsics. For int/float/long long/double, it
is just a load (lxvw4x/lxvd2x) or store(stxvw4x/stxvd2x). For char/char/short,
we also need some extra shuffling before or after call the builtins to get the
desired BE order. For int128, simply call vec_xl or vec_xst.

Signatures:
vector signed char vec_xl_be (signed long long, signed char *);
vector unsigned char vec_xl_be (signed long long, unsigned char *);
vector signed int vec_xl_be (signed long long, signed int *);
vector unsigned int vec_xl_be (signed long long, unsigned int *);
vector signed int128 vec_xl_be (signed long long, signed int128 *);
vector unsigned int128 vec_xl_be (signed long long, unsigned int128 *);
vector signed long long vec_xl_be (signed long long, signed long long *);
vector unsigned long long vec_xl_be (signed long long, unsigned long long *);
vector signed short vec_xl_be (signed long long, signed short *);
vector unsigned short vec_xl_be (signed long long, unsigned short *);
vector double vec_xl_be (signed long long, double *);
vector float vec_xl_be (signed long long, float *);
void vec_xst_be (vector signed char, signed long long, signed char *);
void vec_xst_be (vector unsigned char, signed long long, unsigned char *);
void vec_xst_be (vector signed int, signed long long, signed int *);
void vec_xst_be (vector unsigned int, signed long long, unsigned int *);
void vec_xst_be (vector signed int128, signed long long, signed int128 *);
void vec_xst_be (vector unsigned int128, signed long long, unsigned int128 *);
void vec_xst_be (vector signed long long, signed long long, signed long long *);
void vec_xst_be (vector unsigned long long, signed long long, unsigned long 
long *);
void vec_xst_be (vector signed short, signed long long, signed short *);
void vec_xst_be (vector unsigned short, signed long long, unsigned short *);
void vec_xst_be (vector double, signed long long, double *);
void vec_xst_be (vector float, signed long long, float *);


https://reviews.llvm.org/D26520

Files:
  include/llvm/IR/IntrinsicsPowerPC.td
  lib/Target/PowerPC/PPCISelLowering.cpp
  lib/Target/PowerPC/PPCInstrVSX.td
  test/CodeGen/PowerPC/vsx.ll

Index: test/CodeGen/PowerPC/vsx.ll
===
--- test/CodeGen/PowerPC/vsx.ll
+++ test/CodeGen/PowerPC/vsx.ll
@@ -1190,3 +1190,51 @@
 ; CHECK-LE: xscmpudp [[REG:[0-9]+]], 3, 4
 ; CHECK-LE: beqlr [[REG]]
 }
+
+; Function Attrs: nounwind readnone
+define <4 x i32> @test83(i8* %a) {
+  entry:
+%0 = tail call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8* %a)
+  ret <4 x i32> %0
+  ; CHECK-LABEL: test83
+  ; CHECK: lxvw4x 34, 0, 3
+  ; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8*)
+
+; Function Attrs: nounwind readnone
+define <2 x double> @test84(i8* %a) {
+  entry:
+%0 = tail call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %a)
+  ret <2 x double> %0
+  ; CHECK-LABEL: test84
+  ; CHECK: lxvd2x 34, 0, 3
+  ; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8*)
+
+; Function Attrs: nounwind readnone
+define void @test85(<4 x i32> %a, i8* %b) {
+  entry:
+tail call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %a, i8* %b)
+ret void
+  ; CHECK-LABEL: test85
+  ; CHECK: stxvw4x 34, 0, 5
+  ; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare void @llvm.ppc.vsx.stxvw4x.be(<4 x i32>, i8*)
+
+; Function Attrs: nounwind readnone
+define void @test86(<2 x double> %a, i8* %b) {
+  entry:
+tail call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %a, i8* %b)
+ret void
+  ; CHECK-LABEL: test86
+  ; CHECK: stxvd2x 34, 0, 5
+  ; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare void @llvm.ppc.vsx.stxvd2x.be(<2 x double>, i8*)
Index: lib/Target/PowerPC/PPCInstrVSX.td
===
--- lib/Target/PowerPC/PPCInstrVSX.td
+++ lib/Target/PowerPC/PPCInstrVSX.td
@@ -1012,6 +1012,10 @@
 (STXVD2X $rS, xoaddr:$dst)>;
   def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, xoaddr:$dst),
 (STXVW4X $rS, xoaddr:$dst)>;
+  def : Pat<(int_ppc_vsx_stxvd2x_be v2f64:$rS, xoaddr:$dst),
+(STXVD2X $rS, xoaddr:$dst)>;
+  def : Pat<(int_ppc_vsx_stxvw4x_be v4i32:$rS, xoaddr:$dst),
+(STXVW4X $rS, xoaddr:$dst)>;
   def : Pat<(PPCstxvd2x v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
 }
 let Predicates = [IsBigEndian, HasVSX, HasOnlySwappingMemOps] in {
@@ -1840,6 +1844,9 @@
   def : Pat<(f64 (vector_extract v