[PATCH] D46871: [AMDGPU] Add interpolation builtins

2018-05-15 Thread Tim Corringham via Phabricator via cfe-commits 
timcorringham created this revision.
Herald added subscribers: cfe-commits, t-tye, tpr, dstuttard, yaxunl, nhaehnle, 
wdng, kzhuravl.

Added builtins for the interpolation intrinsics, and related LIT
test.


Repository:
  rC Clang

https://reviews.llvm.org/D46871

Files:
  include/clang/Basic/BuiltinsAMDGPU.def
  test/CodeGenOpenCL/builtins-amdgcn-interp.cl


Index: test/CodeGenOpenCL/builtins-amdgcn-interp.cl
===
--- /dev/null
+++ test/CodeGenOpenCL/builtins-amdgcn-interp.cl
@@ -0,0 +1,44 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx900 -S -o - 
%s | FileCheck %s --check-prefixes=CHECK,GFX9,BANK32
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu fiji -S -o - %s 
| FileCheck %s --check-prefixes=CHECK,GFX8,BANK32
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx810 -S -o - 
%s | FileCheck %s --check-prefixes=CHECK,GFX8,BANK16
+
+#pragma OPENCL EXTENSION cl_khr_fp16 : enable
+
+// CHECK-LABEL: test_interp_f16
+// CHECK: s_mov_b32 m0, s{{[0-9]}}
+// BANK32: v_interp_p1ll_f16 v{{[0-9]}}, v{{[0-9]}}, attr3.z{{$}}
+// BANK32: v_interp_p1ll_f16 v{{[0-9]}}, v{{[0-9]}}, attr3.z high
+// BANK16: v_interp_mov_f32_e32 v4, p0, attr3.z
+// BANK16: v_interp_p1lv_f16 v{{[0-9]}}, v{{[0-9]}}, attr3.z, v{{[0-9]}}{{$}}
+// BANK16: v_interp_p1lv_f16 v{{[0-9]}}, v{{[0-9]}}, attr3.z, v{{[0-9]}} high
+// GFX9: _interp_p2_legacy_f16 v{{[0-9]}}, v{{[0-9]}}, attr3.z, v{{[0-9]}}{{$}}
+// GFX9: v_interp_p2_legacy_f16 v{{[0-9]}}, v{{[0-9]}}, attr3.z, v{{[0-9]}} 
high
+// GFX8: _interp_p2_f16 v{{[0-9]}}, v{{[0-9]}}, attr3.z, v{{[0-9]}}{{$}}
+// GFX8: v_interp_p2_f16 v{{[0-9]}}, v{{[0-9]}}, attr3.z, v{{[0-9]}} high
+// CHECK: v_add_f16_e32 v{{[0-9]}}, v{{[0-9]}}, v{{[0-9]}}
+void test_interp_f16(global half* out, float i, float j, int m0)
+{
+  float p1_0 = __builtin_amdgcn_interp_p1_f16(i, 2, 3, false, m0);
+  half p2_0 = __builtin_amdgcn_interp_p2_f16(p1_0, j, 2, 3, false, m0);
+  float p1_1 = __builtin_amdgcn_interp_p1_f16(i, 2, 3, true, m0);
+  half p2_1 = __builtin_amdgcn_interp_p2_f16(p1_1, j, 2, 3, true, m0);
+  *out = p2_0 + p2_1;
+}
+
+// CHECK-LABEL: test_interp_f32
+// CHECK: s_mov_b32 m0, s{{[0-9]}}
+// CHECK: v_interp_p1_f32_e32 v{{[0-9]}}, v{{[0-9]}}, attr4.y
+// CHECK: v_interp_p2_f32_e32 v{{[0-9]}}, v{{[0-9]}}, attr4.y
+void test_interp_f32(global float* out, float i, float j, int m0)
+{
+  float p1 = __builtin_amdgcn_interp_p1(i, 1, 4, m0);
+  *out = __builtin_amdgcn_interp_p2(p1, j, 1, 4, m0);
+}
+
+// CHECK-LABEL: test_interp_mov
+// CHECK: v_interp_mov_f32_e32 v{{[0-9]}}, p0, attr4.w
+void test_interp_mov(global float* out, float i, float j, int m0)
+{
+  *out = __builtin_amdgcn_interp_mov(2, 3, 4, m0);
+}
Index: include/clang/Basic/BuiltinsAMDGPU.def
===
--- include/clang/Basic/BuiltinsAMDGPU.def
+++ include/clang/Basic/BuiltinsAMDGPU.def
@@ -98,6 +98,15 @@
 BUILTIN(__builtin_amdgcn_ds_fmax, "ff*3fiib", "n")
 
 
//===--===//
+// Interpolation builtins.
+//===--===//
+BUILTIN(__builtin_amdgcn_interp_p1_f16, "ffUiUibUi", "nc")
+BUILTIN(__builtin_amdgcn_interp_p2_f16, "hffUiUibUi", "nc")
+BUILTIN(__builtin_amdgcn_interp_p1, "ffUiUiUi", "nc")
+BUILTIN(__builtin_amdgcn_interp_p2, "fffUiUiUi", "nc")
+BUILTIN(__builtin_amdgcn_interp_mov, "fUiUiUiUi", "nc")
+
+//===--===//
 // VI+ only builtins.
 
//===--===//
 


Index: test/CodeGenOpenCL/builtins-amdgcn-interp.cl
===
--- /dev/null
+++ test/CodeGenOpenCL/builtins-amdgcn-interp.cl
@@ -0,0 +1,44 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx900 -S -o - %s | FileCheck %s --check-prefixes=CHECK,GFX9,BANK32
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu fiji -S -o - %s | FileCheck %s --check-prefixes=CHECK,GFX8,BANK32
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx810 -S -o - %s | FileCheck %s --check-prefixes=CHECK,GFX8,BANK16
+
+#pragma OPENCL EXTENSION cl_khr_fp16 : enable
+
+// CHECK-LABEL: test_interp_f16
+// CHECK: s_mov_b32 m0, s{{[0-9]}}
+// BANK32: v_interp_p1ll_f16 v{{[0-9]}}, v{{[0-9]}}, attr3.z{{$}}
+// BANK32: v_interp_p1ll_f16 v{{[0-9]}}, v{{[0-9]}}, attr3.z high
+// BANK16: v_interp_mov_f32_e32 v4, p0, attr3.z
+// BANK16: v_interp_p1lv_f16 v{{[0-9]}}, v{{[0-9]}}, attr3.z, v{{[0-9]}}{{$}}
+// BANK16: v_interp_p1lv_f16 v{{[0-9]}}, v{{[0-9]}}, attr3.z, v{{[0-9]}} high
+// GFX9: _interp_p2_legacy_f16 v{{[0-9]}}, v{{[0-9]}}, attr3.z, v{{[0-9]}}{{$}}
+// GFX9: v_interp_p2_legacy_f16 v{{[0-9]}}, v{{[0-9]}}, attr3.z, v{{[0-9]}} h

[PATCH] D46871: [AMDGPU] Add interpolation builtins

2018-05-15 Thread Tim Corringham via Phabricator via cfe-commits 
timcorringham added inline comments.



Comment at: include/clang/Basic/BuiltinsAMDGPU.def:103-107
+BUILTIN(__builtin_amdgcn_interp_p1_f16, "ffUiUibUi", "nc")
+BUILTIN(__builtin_amdgcn_interp_p2_f16, "hffUiUibUi", "nc")
+BUILTIN(__builtin_amdgcn_interp_p1, "ffUiUiUi", "nc")
+BUILTIN(__builtin_amdgcn_interp_p2, "fffUiUiUi", "nc")
+BUILTIN(__builtin_amdgcn_interp_mov, "fUiUiUiUi", "nc")

arsenm wrote:
> You will also need C++ handling for these when the intrinsics are fixed to 
> use name mangling
Can you expand on that please, I don't know what needs to be done here?



Comment at: test/CodeGenOpenCL/builtins-amdgcn-interp.cl:2-28
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx900 -S -o - 
%s | FileCheck %s --check-prefixes=CHECK,GFX9,BANK32
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu fiji -S -o - %s 
| FileCheck %s --check-prefixes=CHECK,GFX8,BANK32
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx810 -S -o - 
%s | FileCheck %s --check-prefixes=CHECK,GFX8,BANK16
+
+#pragma OPENCL EXTENSION cl_khr_fp16 : enable
+
+// CHECK-LABEL: test_interp_f16

arsenm wrote:
> These should be emitting / checking the IR, not the output asm
Checking the IR doesn't allow you to check the behavior very well, as there are 
differences depending on the target-cpu which are not apparent in the IR.


Repository:
  rC Clang

https://reviews.llvm.org/D46871



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[PATCH] D46871: [AMDGPU] Add interpolation builtins

2018-05-18 Thread Tim Corringham via Phabricator via cfe-commits 
timcorringham updated this revision to Diff 147460.
timcorringham added a comment.

[AMDGPU] Add interpolation builtins

Updated LIT test so that it only tests for the existence of the builtins
by checking the IR.


Repository:
  rC Clang

https://reviews.llvm.org/D46871

Files:
  include/clang/Basic/BuiltinsAMDGPU.def
  test/CodeGenOpenCL/builtins-amdgcn-interp.cl


Index: test/CodeGenOpenCL/builtins-amdgcn-interp.cl
===
--- /dev/null
+++ test/CodeGenOpenCL/builtins-amdgcn-interp.cl
@@ -0,0 +1,34 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx900 -S 
-emit-llvm -o - %s | FileCheck %s
+
+#pragma OPENCL EXTENSION cl_khr_fp16 : enable
+
+// CHECK-LABEL: test_interp_f16
+// CHECK: call float @llvm.amdgcn.interp.p1.f16
+// CHECK: call half @llvm.amdgcn.interp.p2.f16
+// CHECK: call float @llvm.amdgcn.interp.p1.f16
+// CHECK: call half @llvm.amdgcn.interp.p2.f16
+void test_interp_f16(global half* out, float i, float j, int m0)
+{
+  float p1_0 = __builtin_amdgcn_interp_p1_f16(i, 2, 3, false, m0);
+  half p2_0 = __builtin_amdgcn_interp_p2_f16(p1_0, j, 2, 3, false, m0);
+  float p1_1 = __builtin_amdgcn_interp_p1_f16(i, 2, 3, true, m0);
+  half p2_1 = __builtin_amdgcn_interp_p2_f16(p1_1, j, 2, 3, true, m0);
+  *out = p2_0 + p2_1;
+}
+
+// CHECK-LABEL: test_interp_f32
+// CHECK: call float @llvm.amdgcn.interp.p1
+// CHECK: call float @llvm.amdgcn.interp.p2
+void test_interp_f32(global float* out, float i, float j, int m0)
+{
+  float p1 = __builtin_amdgcn_interp_p1(i, 1, 4, m0);
+  *out = __builtin_amdgcn_interp_p2(p1, j, 1, 4, m0);
+}
+
+// CHECK-LABEL: test_interp_mov
+// CHECK: call float @llvm.amdgcn.interp.mov
+void test_interp_mov(global float* out, float i, float j, int m0)
+{
+  *out = __builtin_amdgcn_interp_mov(2, 3, 4, m0);
+}
Index: include/clang/Basic/BuiltinsAMDGPU.def
===
--- include/clang/Basic/BuiltinsAMDGPU.def
+++ include/clang/Basic/BuiltinsAMDGPU.def
@@ -98,6 +98,15 @@
 BUILTIN(__builtin_amdgcn_ds_fmax, "ff*3fiib", "n")
 
 
//===--===//
+// Interpolation builtins.
+//===--===//
+BUILTIN(__builtin_amdgcn_interp_p1_f16, "ffUiUibUi", "nc")
+BUILTIN(__builtin_amdgcn_interp_p2_f16, "hffUiUibUi", "nc")
+BUILTIN(__builtin_amdgcn_interp_p1, "ffUiUiUi", "nc")
+BUILTIN(__builtin_amdgcn_interp_p2, "fffUiUiUi", "nc")
+BUILTIN(__builtin_amdgcn_interp_mov, "fUiUiUiUi", "nc")
+
+//===--===//
 // VI+ only builtins.
 
//===--===//
 


Index: test/CodeGenOpenCL/builtins-amdgcn-interp.cl
===
--- /dev/null
+++ test/CodeGenOpenCL/builtins-amdgcn-interp.cl
@@ -0,0 +1,34 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx900 -S -emit-llvm -o - %s | FileCheck %s
+
+#pragma OPENCL EXTENSION cl_khr_fp16 : enable
+
+// CHECK-LABEL: test_interp_f16
+// CHECK: call float @llvm.amdgcn.interp.p1.f16
+// CHECK: call half @llvm.amdgcn.interp.p2.f16
+// CHECK: call float @llvm.amdgcn.interp.p1.f16
+// CHECK: call half @llvm.amdgcn.interp.p2.f16
+void test_interp_f16(global half* out, float i, float j, int m0)
+{
+  float p1_0 = __builtin_amdgcn_interp_p1_f16(i, 2, 3, false, m0);
+  half p2_0 = __builtin_amdgcn_interp_p2_f16(p1_0, j, 2, 3, false, m0);
+  float p1_1 = __builtin_amdgcn_interp_p1_f16(i, 2, 3, true, m0);
+  half p2_1 = __builtin_amdgcn_interp_p2_f16(p1_1, j, 2, 3, true, m0);
+  *out = p2_0 + p2_1;
+}
+
+// CHECK-LABEL: test_interp_f32
+// CHECK: call float @llvm.amdgcn.interp.p1
+// CHECK: call float @llvm.amdgcn.interp.p2
+void test_interp_f32(global float* out, float i, float j, int m0)
+{
+  float p1 = __builtin_amdgcn_interp_p1(i, 1, 4, m0);
+  *out = __builtin_amdgcn_interp_p2(p1, j, 1, 4, m0);
+}
+
+// CHECK-LABEL: test_interp_mov
+// CHECK: call float @llvm.amdgcn.interp.mov
+void test_interp_mov(global float* out, float i, float j, int m0)
+{
+  *out = __builtin_amdgcn_interp_mov(2, 3, 4, m0);
+}
Index: include/clang/Basic/BuiltinsAMDGPU.def
===
--- include/clang/Basic/BuiltinsAMDGPU.def
+++ include/clang/Basic/BuiltinsAMDGPU.def
@@ -98,6 +98,15 @@
 BUILTIN(__builtin_amdgcn_ds_fmax, "ff*3fiib", "n")
 
 //===--===//
+// Interpolation builtins.
+//===--===//
+BUILTIN(__builtin_amdgcn_interp_p1_f16, "ffUiUibUi", "nc")
+BUILTIN(__builtin_amdgcn_interp_p2_f16, "hffUiUibUi", "nc")
+BUILTIN(__builtin_amdgcn_interp_p1, "ffUiUiUi", "nc")
+BUILTIN(__b

[PATCH] D46871: [AMDGPU] Add interpolation builtins

2019-01-28 Thread Tim Corringham via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rC352358: [AMDGPU] Add interpolation builtins (authored by 
timcorringham, committed by ).
Herald added a subscriber: jvesely.

Changed prior to commit:
  https://reviews.llvm.org/D46871?vs=147460&id=183837#toc

Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D46871/new/

https://reviews.llvm.org/D46871

Files:
  include/clang/Basic/BuiltinsAMDGPU.def
  test/CodeGenOpenCL/builtins-amdgcn-interp.cl


Index: test/CodeGenOpenCL/builtins-amdgcn-interp.cl
===
--- test/CodeGenOpenCL/builtins-amdgcn-interp.cl
+++ test/CodeGenOpenCL/builtins-amdgcn-interp.cl
@@ -0,0 +1,34 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx900 -S 
-emit-llvm -o - %s | FileCheck %s
+
+#pragma OPENCL EXTENSION cl_khr_fp16 : enable
+
+// CHECK-LABEL: test_interp_f16
+// CHECK: call float @llvm.amdgcn.interp.p1.f16
+// CHECK: call half @llvm.amdgcn.interp.p2.f16
+// CHECK: call float @llvm.amdgcn.interp.p1.f16
+// CHECK: call half @llvm.amdgcn.interp.p2.f16
+void test_interp_f16(global half* out, float i, float j, int m0)
+{
+  float p1_0 = __builtin_amdgcn_interp_p1_f16(i, 2, 3, false, m0);
+  half p2_0 = __builtin_amdgcn_interp_p2_f16(p1_0, j, 2, 3, false, m0);
+  float p1_1 = __builtin_amdgcn_interp_p1_f16(i, 2, 3, true, m0);
+  half p2_1 = __builtin_amdgcn_interp_p2_f16(p1_1, j, 2, 3, true, m0);
+  *out = p2_0 + p2_1;
+}
+
+// CHECK-LABEL: test_interp_f32
+// CHECK: call float @llvm.amdgcn.interp.p1
+// CHECK: call float @llvm.amdgcn.interp.p2
+void test_interp_f32(global float* out, float i, float j, int m0)
+{
+  float p1 = __builtin_amdgcn_interp_p1(i, 1, 4, m0);
+  *out = __builtin_amdgcn_interp_p2(p1, j, 1, 4, m0);
+}
+
+// CHECK-LABEL: test_interp_mov
+// CHECK: call float @llvm.amdgcn.interp.mov
+void test_interp_mov(global float* out, float i, float j, int m0)
+{
+  *out = __builtin_amdgcn_interp_mov(2, 3, 4, m0);
+}
Index: include/clang/Basic/BuiltinsAMDGPU.def
===
--- include/clang/Basic/BuiltinsAMDGPU.def
+++ include/clang/Basic/BuiltinsAMDGPU.def
@@ -106,6 +106,15 @@
 TARGET_BUILTIN(__builtin_amdgcn_buffer_wbinvl1_vol, "v", "n", "ci-insts")
 
 
//===--===//
+// Interpolation builtins.
+//===--===//
+BUILTIN(__builtin_amdgcn_interp_p1_f16, "ffUiUibUi", "nc")
+BUILTIN(__builtin_amdgcn_interp_p2_f16, "hffUiUibUi", "nc")
+BUILTIN(__builtin_amdgcn_interp_p1, "ffUiUiUi", "nc")
+BUILTIN(__builtin_amdgcn_interp_p2, "fffUiUiUi", "nc")
+BUILTIN(__builtin_amdgcn_interp_mov, "fUiUiUiUi", "nc")
+
+//===--===//
 // VI+ only builtins.
 
//===--===//
 


Index: test/CodeGenOpenCL/builtins-amdgcn-interp.cl
===
--- test/CodeGenOpenCL/builtins-amdgcn-interp.cl
+++ test/CodeGenOpenCL/builtins-amdgcn-interp.cl
@@ -0,0 +1,34 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx900 -S -emit-llvm -o - %s | FileCheck %s
+
+#pragma OPENCL EXTENSION cl_khr_fp16 : enable
+
+// CHECK-LABEL: test_interp_f16
+// CHECK: call float @llvm.amdgcn.interp.p1.f16
+// CHECK: call half @llvm.amdgcn.interp.p2.f16
+// CHECK: call float @llvm.amdgcn.interp.p1.f16
+// CHECK: call half @llvm.amdgcn.interp.p2.f16
+void test_interp_f16(global half* out, float i, float j, int m0)
+{
+  float p1_0 = __builtin_amdgcn_interp_p1_f16(i, 2, 3, false, m0);
+  half p2_0 = __builtin_amdgcn_interp_p2_f16(p1_0, j, 2, 3, false, m0);
+  float p1_1 = __builtin_amdgcn_interp_p1_f16(i, 2, 3, true, m0);
+  half p2_1 = __builtin_amdgcn_interp_p2_f16(p1_1, j, 2, 3, true, m0);
+  *out = p2_0 + p2_1;
+}
+
+// CHECK-LABEL: test_interp_f32
+// CHECK: call float @llvm.amdgcn.interp.p1
+// CHECK: call float @llvm.amdgcn.interp.p2
+void test_interp_f32(global float* out, float i, float j, int m0)
+{
+  float p1 = __builtin_amdgcn_interp_p1(i, 1, 4, m0);
+  *out = __builtin_amdgcn_interp_p2(p1, j, 1, 4, m0);
+}
+
+// CHECK-LABEL: test_interp_mov
+// CHECK: call float @llvm.amdgcn.interp.mov
+void test_interp_mov(global float* out, float i, float j, int m0)
+{
+  *out = __builtin_amdgcn_interp_mov(2, 3, 4, m0);
+}
Index: include/clang/Basic/BuiltinsAMDGPU.def
===
--- include/clang/Basic/BuiltinsAMDGPU.def
+++ include/clang/Basic/BuiltinsAMDGPU.def
@@ -106,6 +106,15 @@
 TARGET_BUILTIN(__builtin_amdgcn_buffer_wbinvl1_vol, "v", "n", "ci-insts")
 
 //===--===//
+// Interpolation builtin