[PATCH] D79710: [clang][BFloat] add create/set/get/dup intrinsics

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Comment at: clang/include/clang/Basic/arm_neon.td:1845
+
+// V8.2-A BFloat intrinsics
+let ArchGuard = "defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC)" in {

labrinea wrote:
> v8.6-A ?
Yes V8.2-A, the feature has been added to the 8.2 architecture, but in a later 
release.

For example, the section on BFloat in the  Arm ARM reads:
`ARMv8.2-BF16, Armv8.2 AArch64 BFloat16 Extension` 


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[PATCH] D79710: [clang][BFloat] add create/set/get/dup intrinsics

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stuij added a comment.

In D79710#2041418 , @LukeGeeson wrote:

> Can you update the commit message in this differential as well please? Same 
> for the other commits :)


done


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[PATCH] D79708: [clang][BFloat] add NEON emitter for bfloat

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stuij added inline comments.



Comment at: clang/include/clang/Basic/arm_bf16.td:1
+//===--- arm_fp16.td - ARM FP16 compiler interface 
===//
+//

SjoerdMeijer wrote:
> typo: fp16 - > bf16?
> Here, and a few more places, or is it intentional? If so, I guess that can be 
> a bit confusing?
> 
Thanks for that. I went through the patch and I only found the mistake in this 
file.



Comment at: clang/include/clang/Basic/arm_neon_incl.td:293
+
+  string CartesianProductWith = "";
 }

fpetrogalli wrote:
> What is this for?
Thanks, that is actually part of another patch. I will remove.



Comment at: clang/utils/TableGen/NeonEmitter.cpp:2198
 
+static void emitNeonTypeDefs(const std::string& types, raw_ostream &OS) {
+  std::string TypedefTypes(types);

fpetrogalli wrote:
> Is this related to the changes for bfloat? Or is it a just a refactoring that 
> it is nice to have? If the latter, please consider submitting it as a 
> separate patch. If both refactoring and BF16 related, at the moment it is not 
> possible to see clearly which changes are BF16 specific, so please do submit 
> the refactoring first.
Yes, related to bfloat. We're emitting that code twice now.

I can make a new patch, but I'm not sure if the effort justifies the in my mind 
small amount of gain in clarity. It's basically just pasting the removed part 
on the left into this function. If you disagree, tell me, and I will create the 
extra patch.



Comment at: clang/utils/TableGen/NeonEmitter.cpp:2411
+/// is comprised of type definitions and function declarations.
+void NeonEmitter::runFP16(raw_ostream &OS) {
+  OS << "/*=== arm_fp16.h - ARM FP16 intrinsics "

SjoerdMeijer wrote:
> I am a bit confused here, we already have a runFP16, I am missing something?
The fairly similar runBF16 fn was added. The way git interprets this is 
probably a bit confusing. There's still just one runFP16 function.



Comment at: clang/utils/TableGen/NeonEmitter.cpp:2416
+" *\n"
+" * Permission is hereby granted, free of charge, to any person "
+"obtaining a copy\n"

SjoerdMeijer wrote:
> I can't remember the outcome, but I had a discussion with @sdesmalen about 
> this license, if this should be the new or old copyright notice. I believe, 
> but am not certain, that this should be the new one.
I'll change it, and will ping @sdesmalen to be sure.


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[PATCH] D79708: [clang][BFloat] add NEON emitter for bfloat

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stuij updated this revision to Diff 265524.
stuij added a comment.

addressed review comments, most of all changed license header on the generated 
bfloat file


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Files:
  clang/include/clang/Basic/arm_bf16.td
  clang/include/clang/Basic/arm_neon_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/Preprocessor/aarch64-target-features.c
  clang/test/Preprocessor/arm-target-features.c
  clang/utils/TableGen/NeonEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -85,6 +85,7 @@
 
 void EmitNeon(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitFP16(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitBF16(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeonSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeonTest(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeon2(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -63,6 +63,7 @@
   GenClangOpenCLBuiltins,
   GenArmNeon,
   GenArmFP16,
+  GenArmBF16,
   GenArmNeonSema,
   GenArmNeonTest,
   GenArmMveHeader,
@@ -186,6 +187,7 @@
"Generate OpenCL builtin declaration handlers"),
 clEnumValN(GenArmNeon, "gen-arm-neon", "Generate arm_neon.h for clang"),
 clEnumValN(GenArmFP16, "gen-arm-fp16", "Generate arm_fp16.h for clang"),
+clEnumValN(GenArmBF16, "gen-arm-bf16", "Generate arm_bf16.h for clang"),
 clEnumValN(GenArmNeonSema, "gen-arm-neon-sema",
"Generate ARM NEON sema support for clang"),
 clEnumValN(GenArmNeonTest, "gen-arm-neon-test",
@@ -360,6 +362,9 @@
   case GenArmFP16:
 EmitFP16(Records, OS);
 break;
+  case GenArmBF16:
+EmitBF16(Records, OS);
+break;
   case GenArmNeonSema:
 EmitNeonSema(Records, OS);
 break;
Index: clang/utils/TableGen/NeonEmitter.cpp
===
--- clang/utils/TableGen/NeonEmitter.cpp
+++ clang/utils/TableGen/NeonEmitter.cpp
@@ -99,7 +99,8 @@
   Poly128,
   Float16,
   Float32,
-  Float64
+  Float64,
+  BFloat16
 };
 
 } // end namespace NeonTypeFlags
@@ -147,6 +148,7 @@
 SInt,
 UInt,
 Poly,
+BFloat16,
   };
   TypeKind Kind;
   bool Immediate, Constant, Pointer;
@@ -199,6 +201,7 @@
   bool isInt() const { return isInteger() && ElementBitwidth == 32; }
   bool isLong() const { return isInteger() && ElementBitwidth == 64; }
   bool isVoid() const { return Kind == Void; }
+  bool isBFloat16() const { return Kind == BFloat16; }
   unsigned getNumElements() const { return Bitwidth / ElementBitwidth; }
   unsigned getSizeInBits() const { return Bitwidth; }
   unsigned getElementSizeInBits() const { return ElementBitwidth; }
@@ -585,8 +588,11 @@
   // runFP16 - Emit arm_fp16.h.inc
   void runFP16(raw_ostream &o);
 
-  // runHeader - Emit all the __builtin prototypes used in arm_neon.h
-	// and arm_fp16.h
+  // runBF16 - Emit arm_bf16.h.inc
+  void runBF16(raw_ostream &o);
+
+  // runHeader - Emit all the __builtin prototypes used in arm_neon.h,
+  // arm_fp16.h and arm_bf16.h
   void runHeader(raw_ostream &o);
 
   // runTests - Emit tests for all the Neon intrinsics.
@@ -611,6 +617,8 @@
 S += "poly";
   else if (isFloating())
 S += "float";
+  else if (isBFloat16())
+S += "bfloat";
   else
 S += "int";
 
@@ -650,7 +658,10 @@
 case 128: S += "LLLi"; break;
 default: llvm_unreachable("Unhandled case!");
 }
-  else
+  else if (isBFloat16()) {
+assert(ElementBitwidth == 16 && "BFloat16 can only be 16 bits");
+S += "y";
+  } else
 switch (ElementBitwidth) {
 case 16: S += "h"; break;
 case 32: S += "f"; break;
@@ -704,6 +715,11 @@
 Base = (unsigned)NeonTypeFlags::Float16 + (Addend - 1);
   }
 
+  if (isBFloat16()) {
+assert(Addend == 1 && "BFloat16 is only 16 bit");
+Base = (unsigned)NeonTypeFlags::BFloat16;
+  }
+
   if (Bitwidth == 128)
 Base |= (unsigned)NeonTypeFlags::QuadFlag;
   if (isInteger() && !isSigned())
@@ -727,6 +743,9 @@
   } else if (Name.startswith("poly")) {
 T.Kind = Poly;
 Name = Name.drop_front(4);
+  } else if (Name.startswith("bfloat")) {
+T.Kind = BFloat16;
+Name = Name.drop_front(6);
   } else {
 assert(Name.startswith("int"));
 Name = Name.drop_front(3);
@@ -825,6 +844,10 @@
   if (isPoly())
 NumVectors = 0;
   break;
+case 'b':
+

[PATCH] D79708: [clang][BFloat] add NEON emitter for bfloat

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Comment at: clang/utils/TableGen/NeonEmitter.cpp:2416
+" *\n"
+" * Permission is hereby granted, free of charge, to any person "
+"obtaining a copy\n"

stuij wrote:
> SjoerdMeijer wrote:
> > I can't remember the outcome, but I had a discussion with @sdesmalen about 
> > this license, if this should be the new or old copyright notice. I believe, 
> > but am not certain, that this should be the new one.
> I'll change it, and will ping @sdesmalen to be sure.
Just to be clear: I've changed the BF16 text, not the FP16 text, which should 
stay the same.


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[PATCH] D76077: [ARM] Add __bf16 as new Bfloat16 C Type

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stuij updated this revision to Diff 265753.
stuij marked an inline comment as done.
stuij added a comment.

no explicit float-abi cmdline arg should default to softfp


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Files:
  clang/docs/LanguageExtensions.rst
  clang/include/clang-c/Index.h
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/BuiltinTypes.def
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/Specifiers.h
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Sema/DeclSpec.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/Basic/TargetInfo.cpp
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/CodeGenTypeCache.h
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Format/FormatToken.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Parse/ParseDecl.cpp
  clang/lib/Parse/ParseExpr.cpp
  clang/lib/Parse/ParseExprCXX.cpp
  clang/lib/Parse/ParseTentative.cpp
  clang/lib/Sema/DeclSpec.cpp
  clang/lib/Sema/SemaCast.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/lib/Sema/SemaTemplateVariadic.cpp
  clang/lib/Sema/SemaType.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/CodeGen/arm-bf16-params-returns.c
  clang/test/CodeGen/arm-mangle-16bit-float.cpp
  clang/test/Sema/arm-bf16-forbidden-ops.c
  clang/test/Sema/arm-bf16-forbidden-ops.cpp
  clang/test/Sema/arm-bfloat.cpp
  clang/tools/libclang/CXType.cpp

Index: clang/tools/libclang/CXType.cpp
===
--- clang/tools/libclang/CXType.cpp
+++ clang/tools/libclang/CXType.cpp
@@ -608,6 +608,7 @@
 TKIND(Elaborated);
 TKIND(Pipe);
 TKIND(Attributed);
+TKIND(BFloat16);
 #define IMAGE_TYPE(ImgType, Id, SingletonId, Access, Suffix) TKIND(Id);
 #include "clang/Basic/OpenCLImageTypes.def"
 #undef IMAGE_TYPE
Index: clang/test/Sema/arm-bfloat.cpp
===
--- /dev/null
+++ clang/test/Sema/arm-bfloat.cpp
@@ -0,0 +1,29 @@
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple aarch64-arm-none-eabi -target-cpu cortex-a75 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple arm-arm-none-eabi -target-cpu cortex-a53 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+
+void test(bool b) {
+  __bf16 bf16;
+
+  bf16 + bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 - bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 * bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 / bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+
+  __fp16 fp16;
+
+  bf16 + fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 + bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 - fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 - bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 * fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 * bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 / fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 / bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 = fp16; // expected-error {{assigning to '__bf16' from incompatible type '__fp16'}}
+  fp16 = bf16; // expected-error {{assigning to '__fp16' from incompatible type '__bf16'}}
+  bf16 + (b ? fp16 : bf16); // expected-error {{incompatible operand types ('__fp16' and '__bf16')}}
+}
Index: clang/test/Sema/arm-bf16-forbidden-ops.cpp
===
--- /dev/null
+++ clang/test/Sema/arm-bf16-forbidden-ops.cpp
@@ -0,0 +1,71 @@
+// RUN: %clang_cc1 -fsyntax-only -verify -triple aarch64 

[PATCH] D79710: [clang][BFloat] add create/set/get/dup intrinsics

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stuij updated this revision to Diff 265764.
stuij added a comment.

moving 'CartesianProductWith' to more apt patch


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Files:
  clang/include/clang/Basic/arm_neon.td
  clang/include/clang/Basic/arm_neon_incl.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-bf16-getset-intrinsics.c

Index: clang/test/CodeGen/aarch64-bf16-getset-intrinsics.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-bf16-getset-intrinsics.c
@@ -0,0 +1,120 @@
+// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +neon -target-feature +bf16 \
+// RUN:  -O2 -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK64
+// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi hard \
+// RUN:  -O2 -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK32
+
+#include 
+
+bfloat16x4_t test_vcreate_bf16(uint64_t a) {
+  return vcreate_bf16(a);
+}
+// CHECK-LABEL: test_vcreate_bf16
+// CHECK64: %0 = bitcast i64 %a to <4 x bfloat>
+// CHECK32: %0 = bitcast i64 %a to <4 x bfloat>
+
+bfloat16x4_t test_vdup_n_bf16(bfloat16_t v) {
+  return vdup_n_bf16(v);
+}
+// CHECK-LABEL: test_vdup_n_bf16
+// CHECK64: %vecinit.i = insertelement <4 x bfloat> undef, bfloat %v, i32 0
+// CHECK32: %vecinit.i = insertelement <4 x bfloat> undef, bfloat %v, i32 0
+// CHECK: %vecinit{{.*}} = shufflevector <4 x bfloat> %vecinit.i, <4 x bfloat> undef, <4 x i32> zeroinitializer
+
+bfloat16x8_t test_vdupq_n_bf16(bfloat16_t v) {
+  return vdupq_n_bf16(v);
+}
+// CHECK-LABEL: test_vdupq_n_bf16
+// CHECK64: %vecinit.i = insertelement <8 x bfloat> undef, bfloat %v, i32 0
+// CHECK32: %vecinit.i = insertelement <8 x bfloat> undef, bfloat %v, i32 0
+// CHECK:   %vecinit{{.*}} = shufflevector <8 x bfloat> %vecinit.i, <8 x bfloat> undef, <8 x i32> zeroinitializer
+
+bfloat16x4_t test_vdup_lane_bf16(bfloat16x4_t v) {
+  return vdup_lane_bf16(v, 1);
+}
+// CHECK-LABEL: test_vdup_lane_bf16
+// CHECK64: %lane = shufflevector <4 x bfloat> %v, <4 x bfloat> undef, <4 x i32> 
+// CHECK32: %lane = shufflevector <4 x bfloat> %v, <4 x bfloat> undef, <4 x i32> 
+
+bfloat16x8_t test_vdupq_lane_bf16(bfloat16x4_t v) {
+  return vdupq_lane_bf16(v, 1);
+}
+// CHECK-LABEL: test_vdupq_lane_bf16
+// CHECK64: %lane = shufflevector <4 x bfloat> %v, <4 x bfloat> undef, <8 x i32> 
+// CHECK32: %lane = shufflevector <4 x bfloat> %v, <4 x bfloat> undef, <8 x i32> 
+
+bfloat16x4_t test_vdup_laneq_bf16(bfloat16x8_t v) {
+  return vdup_laneq_bf16(v, 7);
+}
+// CHECK-LABEL: test_vdup_laneq_bf16
+// CHECK64: %lane = shufflevector <8 x bfloat> %v, <8 x bfloat> undef, <4 x i32> 
+// CHECK32: %lane = shufflevector <8 x bfloat> %v, <8 x bfloat> undef, <4 x i32> 
+
+bfloat16x8_t test_vdupq_laneq_bf16(bfloat16x8_t v) {
+  return vdupq_laneq_bf16(v, 7);
+}
+// CHECK-LABEL: test_vdupq_laneq_bf16
+// CHECK64: %lane = shufflevector <8 x bfloat> %v, <8 x bfloat> undef, <8 x i32> 
+// CHECK32: %lane = shufflevector <8 x bfloat> %v, <8 x bfloat> undef, <8 x i32> 
+
+bfloat16x8_t test_vcombine_bf16(bfloat16x4_t low, bfloat16x4_t high) {
+  return vcombine_bf16(low, high);
+}
+// CHECK-LABEL: test_vcombine_bf16
+// CHECK64: %shuffle.i = shufflevector <4 x bfloat> %low, <4 x bfloat> %high, <8 x i32> 
+// CHECK32: %shuffle.i = shufflevector <4 x bfloat> %low, <4 x bfloat> %high, <8 x i32> 
+
+bfloat16x4_t test_vget_high_bf16(bfloat16x8_t a) {
+  return vget_high_bf16(a);
+}
+// CHECK-LABEL: test_vget_high_bf16
+// CHECK64: %shuffle.i = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> 
+// CHECK32: %shuffle.i = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> 
+
+bfloat16x4_t test_vget_low_bf16(bfloat16x8_t a) {
+  return vget_low_bf16(a);
+}
+// CHECK-LABEL: test_vget_low_bf16
+// CHECK64: %shuffle.i = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> 
+// CHECK32: %shuffle.i = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> 
+
+bfloat16_t test_vget_lane_bf16(bfloat16x4_t v) {
+  return vget_lane_bf16(v, 1);
+}
+// CHECK-LABEL: test_vget_lane_bf16
+// CHECK64: %vget_lane = extractelement <4 x bfloat> %v, i32 1
+// CHECK32: %vget_lane = extractelement <4 x bfloat> %v, i32 1
+
+bfloat16_t test_vgetq_lane_bf16(bfloat16x8_t v) {
+  return vgetq_lane_bf16(v, 7);
+}
+// CHECK-LABEL: test_vgetq_lane_bf16
+// CHECK64: %vgetq_lane = extractelement <8 x bfloat> %v, i32 7
+// CHECK32: %vget_lane = extractelement <8 x bfloat> %v, i32 7
+
+bfloat16x4_t test_vset_lane_bf16(bfloat16_t a, bfloat16x4_t v) {
+  return vset_lane_bf16(a, v, 1);
+}
+// CHECK-LABEL: test_vset_lane_bf16
+// CHECK64: %vset_lane = insertelement <4 x bfloat> %v, bfloat %a, i32 1
+// CHECK32: %vset_lane = insertelement <4 x bfloat> %v, bfloat %a, i32 1
+
+bfloat16x8_t test_vsetq_lane_bf16(bfloat16_t a, bfloat16x8_t v) {
+  return vsetq_lane

[PATCH] D76077: [ARM] Add __bf16 as new Bfloat16 C Type

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 265985.
stuij marked 14 inline comments as done.
stuij added a comment.

addressed review comments and some related general changes:

- renamed IsSoftFloatABI -> IsFloatABISoftFP
- split bfloat tests out of arm-mangle-16bit-float.cpp
- bfloat shouldn't be checking for NativeHalfType
- err_cast_(from|to)_bfloat -> err_cast_(from|to)_bfloat16
- reworded comments and other minor fixes


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76077/new/

https://reviews.llvm.org/D76077

Files:
  clang/docs/LanguageExtensions.rst
  clang/include/clang-c/Index.h
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/BuiltinTypes.def
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/Specifiers.h
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Sema/DeclSpec.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/Basic/TargetInfo.cpp
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/CodeGenTypeCache.h
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Format/FormatToken.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Parse/ParseDecl.cpp
  clang/lib/Parse/ParseExpr.cpp
  clang/lib/Parse/ParseExprCXX.cpp
  clang/lib/Parse/ParseTentative.cpp
  clang/lib/Sema/DeclSpec.cpp
  clang/lib/Sema/SemaCast.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/lib/Sema/SemaTemplateVariadic.cpp
  clang/lib/Sema/SemaType.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/CodeGen/arm-bf16-params-returns.c
  clang/test/CodeGen/arm-mangle-16bit-float.cpp
  clang/test/CodeGen/arm-mangle-bf16.cpp
  clang/test/Sema/arm-bf16-forbidden-ops.c
  clang/test/Sema/arm-bf16-forbidden-ops.cpp
  clang/test/Sema/arm-bfloat.cpp
  clang/tools/libclang/CXType.cpp

Index: clang/tools/libclang/CXType.cpp
===
--- clang/tools/libclang/CXType.cpp
+++ clang/tools/libclang/CXType.cpp
@@ -608,6 +608,7 @@
 TKIND(Elaborated);
 TKIND(Pipe);
 TKIND(Attributed);
+TKIND(BFloat16);
 #define IMAGE_TYPE(ImgType, Id, SingletonId, Access, Suffix) TKIND(Id);
 #include "clang/Basic/OpenCLImageTypes.def"
 #undef IMAGE_TYPE
Index: clang/test/Sema/arm-bfloat.cpp
===
--- /dev/null
+++ clang/test/Sema/arm-bfloat.cpp
@@ -0,0 +1,29 @@
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple aarch64-arm-none-eabi -target-cpu cortex-a75 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple arm-arm-none-eabi -target-cpu cortex-a53 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+
+void test(bool b) {
+  __bf16 bf16;
+
+  bf16 + bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 - bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 * bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 / bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+
+  __fp16 fp16;
+
+  bf16 + fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 + bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 - fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 - bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 * fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 * bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 / fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 / bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 = fp16; // expected-error {{assigning to '__bf16' from incompatible type '__fp16'}}
+  fp16 = bf16; // expected-error {{assigning to '__fp16' from incompatible type '__bf16'}}
+  bf16 + (b ? fp16 : bf16); // expected-error {{incompatible op

[PATCH] D79708: [clang][BFloat] add NEON emitter for bfloat

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 265988.
stuij added a comment.

replanted arg passing test from other patch


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79708/new/

https://reviews.llvm.org/D79708

Files:
  clang/include/clang/Basic/arm_bf16.td
  clang/include/clang/Basic/arm_neon_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/arm-bf16-params-returns.c
  clang/test/Preprocessor/aarch64-target-features.c
  clang/test/Preprocessor/arm-target-features.c
  clang/utils/TableGen/NeonEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -85,6 +85,7 @@
 
 void EmitNeon(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitFP16(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitBF16(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeonSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeonTest(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeon2(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -63,6 +63,7 @@
   GenClangOpenCLBuiltins,
   GenArmNeon,
   GenArmFP16,
+  GenArmBF16,
   GenArmNeonSema,
   GenArmNeonTest,
   GenArmMveHeader,
@@ -186,6 +187,7 @@
"Generate OpenCL builtin declaration handlers"),
 clEnumValN(GenArmNeon, "gen-arm-neon", "Generate arm_neon.h for clang"),
 clEnumValN(GenArmFP16, "gen-arm-fp16", "Generate arm_fp16.h for clang"),
+clEnumValN(GenArmBF16, "gen-arm-bf16", "Generate arm_bf16.h for clang"),
 clEnumValN(GenArmNeonSema, "gen-arm-neon-sema",
"Generate ARM NEON sema support for clang"),
 clEnumValN(GenArmNeonTest, "gen-arm-neon-test",
@@ -360,6 +362,9 @@
   case GenArmFP16:
 EmitFP16(Records, OS);
 break;
+  case GenArmBF16:
+EmitBF16(Records, OS);
+break;
   case GenArmNeonSema:
 EmitNeonSema(Records, OS);
 break;
Index: clang/utils/TableGen/NeonEmitter.cpp
===
--- clang/utils/TableGen/NeonEmitter.cpp
+++ clang/utils/TableGen/NeonEmitter.cpp
@@ -99,7 +99,8 @@
   Poly128,
   Float16,
   Float32,
-  Float64
+  Float64,
+  BFloat16
 };
 
 } // end namespace NeonTypeFlags
@@ -147,6 +148,7 @@
 SInt,
 UInt,
 Poly,
+BFloat16,
   };
   TypeKind Kind;
   bool Immediate, Constant, Pointer;
@@ -199,6 +201,7 @@
   bool isInt() const { return isInteger() && ElementBitwidth == 32; }
   bool isLong() const { return isInteger() && ElementBitwidth == 64; }
   bool isVoid() const { return Kind == Void; }
+  bool isBFloat16() const { return Kind == BFloat16; }
   unsigned getNumElements() const { return Bitwidth / ElementBitwidth; }
   unsigned getSizeInBits() const { return Bitwidth; }
   unsigned getElementSizeInBits() const { return ElementBitwidth; }
@@ -585,8 +588,11 @@
   // runFP16 - Emit arm_fp16.h.inc
   void runFP16(raw_ostream &o);
 
-  // runHeader - Emit all the __builtin prototypes used in arm_neon.h
-	// and arm_fp16.h
+  // runBF16 - Emit arm_bf16.h.inc
+  void runBF16(raw_ostream &o);
+
+  // runHeader - Emit all the __builtin prototypes used in arm_neon.h,
+  // arm_fp16.h and arm_bf16.h
   void runHeader(raw_ostream &o);
 
   // runTests - Emit tests for all the Neon intrinsics.
@@ -611,6 +617,8 @@
 S += "poly";
   else if (isFloating())
 S += "float";
+  else if (isBFloat16())
+S += "bfloat";
   else
 S += "int";
 
@@ -650,7 +658,10 @@
 case 128: S += "LLLi"; break;
 default: llvm_unreachable("Unhandled case!");
 }
-  else
+  else if (isBFloat16()) {
+assert(ElementBitwidth == 16 && "BFloat16 can only be 16 bits");
+S += "y";
+  } else
 switch (ElementBitwidth) {
 case 16: S += "h"; break;
 case 32: S += "f"; break;
@@ -704,6 +715,11 @@
 Base = (unsigned)NeonTypeFlags::Float16 + (Addend - 1);
   }
 
+  if (isBFloat16()) {
+assert(Addend == 1 && "BFloat16 is only 16 bit");
+Base = (unsigned)NeonTypeFlags::BFloat16;
+  }
+
   if (Bitwidth == 128)
 Base |= (unsigned)NeonTypeFlags::QuadFlag;
   if (isInteger() && !isSigned())
@@ -727,6 +743,9 @@
   } else if (Name.startswith("poly")) {
 T.Kind = Poly;
 Name = Name.drop_front(4);
+  } else if (Name.startswith("bfloat")) {
+T.Kind = BFloat16;
+Name = Name.drop_front(6);
   } else {
 assert(Name.startswith("int"));
 Name = Name.drop_front(3);
@@ -825,6 +844,10 @@
   if (isPoly())
 NumVectors = 0;
   break;
+case 'b':
+ 

[PATCH] D79711: [ARM][BFloat] Add poly64_t on AArch32.

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 265987.
stuij added a comment.

added testing


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79711/new/

https://reviews.llvm.org/D79711

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/CodeGen/arm-poly64.c
  clang/utils/TableGen/NeonEmitter.cpp


Index: clang/utils/TableGen/NeonEmitter.cpp
===
--- clang/utils/TableGen/NeonEmitter.cpp
+++ clang/utils/TableGen/NeonEmitter.cpp
@@ -2235,6 +2235,7 @@
   OS << "#else\n";
   OS << "typedef int8_t poly8_t;\n";
   OS << "typedef int16_t poly16_t;\n";
+  OS << "typedef int64_t poly64_t;\n";
   OS << "#endif\n";
 
   // Emit Neon vector typedefs.
@@ -2247,7 +2248,7 @@
   for (auto &TS : TDTypeVec) {
 bool IsA64 = false;
 Type T(TS, ".");
-if (T.isDouble() || (T.isPoly() && T.getElementSizeInBits() == 64))
+if (T.isDouble())
   IsA64 = true;
 
 if (InIfdef && !IsA64) {
@@ -2280,7 +2281,7 @@
 for (auto &TS : TDTypeVec) {
   bool IsA64 = false;
   Type T(TS, ".");
-  if (T.isDouble() || (T.isPoly() && T.getElementSizeInBits() == 64))
+  if (T.isDouble())
 IsA64 = true;
 
   if (InIfdef && !IsA64) {
Index: clang/test/CodeGen/arm-poly64.c
===
--- /dev/null
+++ clang/test/CodeGen/arm-poly64.c
@@ -0,0 +1,12 @@
+// RUN: %clang_cc1 -triple armv8.2a-arm-none-eabi -target-feature +neon \
+// RUN:  -emit-llvm -o - %s | FileCheck %s
+
+// Test that we can use the poly64 type on AArch32
+
+#include 
+
+// CHECK-LABEL: @test_poly64
+// CHECK: ret i64 %0
+poly64_t test_poly64(poly64_t a) {
+  return a;
+}
Index: clang/lib/Sema/SemaType.cpp
===
--- clang/lib/Sema/SemaType.cpp
+++ clang/lib/Sema/SemaType.cpp
@@ -7649,15 +7649,16 @@
 Triple.getArch() == llvm::Triple::aarch64_be;
   if (VecKind == VectorType::NeonPolyVector) {
 if (IsPolyUnsigned) {
-  // AArch64 polynomial vectors are unsigned and support poly64.
+  // AArch64 polynomial vectors are unsigned.
   return BTy->getKind() == BuiltinType::UChar ||
  BTy->getKind() == BuiltinType::UShort ||
  BTy->getKind() == BuiltinType::ULong ||
  BTy->getKind() == BuiltinType::ULongLong;
 } else {
-  // AArch32 polynomial vector are signed.
+  // AArch32 polynomial vectors are signed.
   return BTy->getKind() == BuiltinType::SChar ||
- BTy->getKind() == BuiltinType::Short;
+ BTy->getKind() == BuiltinType::Short ||
+ BTy->getKind() == BuiltinType::LongLong;
 }
   }
 
Index: clang/lib/AST/ItaniumMangle.cpp
===
--- clang/lib/AST/ItaniumMangle.cpp
+++ clang/lib/AST/ItaniumMangle.cpp
@@ -3167,6 +3167,7 @@
 case BuiltinType::UShort:
   EltName = "poly16_t";
   break;
+case BuiltinType::LongLong:
 case BuiltinType::ULongLong:
   EltName = "poly64_t";
   break;
Index: clang/include/clang/Basic/TargetBuiltins.h
===
--- clang/include/clang/Basic/TargetBuiltins.h
+++ clang/include/clang/Basic/TargetBuiltins.h
@@ -157,7 +157,7 @@
 EltType getEltType() const { return (EltType)(Flags & EltTypeMask); }
 bool isPoly() const {
   EltType ET = getEltType();
-  return ET == Poly8 || ET == Poly16;
+  return ET == Poly8 || ET == Poly16 || ET == Poly64;
 }
 bool isUnsigned() const { return (Flags & UnsignedFlag) != 0; }
 bool isQuad() const { return (Flags & QuadFlag) != 0; }


Index: clang/utils/TableGen/NeonEmitter.cpp
===
--- clang/utils/TableGen/NeonEmitter.cpp
+++ clang/utils/TableGen/NeonEmitter.cpp
@@ -2235,6 +2235,7 @@
   OS << "#else\n";
   OS << "typedef int8_t poly8_t;\n";
   OS << "typedef int16_t poly16_t;\n";
+  OS << "typedef int64_t poly64_t;\n";
   OS << "#endif\n";
 
   // Emit Neon vector typedefs.
@@ -2247,7 +2248,7 @@
   for (auto &TS : TDTypeVec) {
 bool IsA64 = false;
 Type T(TS, ".");
-if (T.isDouble() || (T.isPoly() && T.getElementSizeInBits() == 64))
+if (T.isDouble())
   IsA64 = true;
 
 if (InIfdef && !IsA64) {
@@ -2280,7 +2281,7 @@
 for (auto &TS : TDTypeVec) {
   bool IsA64 = false;
   Type T(TS, ".");
-  if (T.isDouble() || (T.isPoly() && T.getElementSizeInBits() == 64))
+  if (T.isDouble())
 IsA64 = true;
 
   if (InIfdef && !IsA64) {
Index: clang/test/CodeGen/arm-poly64.c
===
--- /dev/null
+++ clang/test/CodeGen/arm-poly64.c
@@ -0,0 +1,12 @@
+// RUN: %clang_cc1 -triple armv8.2a-arm-none-eabi -target-feature +neon \
+// RUN:  -e

[PATCH] D76077: [ARM] Add __bf16 as new Bfloat16 C Type

[Ties Stuij via Phabricator via cfe-commits]

stuij added inline comments.



Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:8111
   "pointer cannot be cast to type %0">;
+def err_cast_to_bfloat : Error<"cannot type-cast to __bf16">;
+def err_cast_from_bfloat : Error<"cannot type-cast from __bf16">;

SjoerdMeijer wrote:
> Nit: was wondering if `err_cast_to_bfloat16` would be more consistent
agree



Comment at: clang/lib/AST/ASTContext.cpp:2052
+  Width = Target->getBFloat16Width();
+  Align = Target->getBFloat16Align();
 case BuiltinType::Float16:

SjoerdMeijer wrote:
> Is a `break` missing here?
tnx



Comment at: clang/lib/AST/ASTContext.cpp:6007
 case Float16Rank:
 case HalfRank: llvm_unreachable("Complex half is not supported");
 case FloatRank:  return FloatComplexTy;

SjoerdMeijer wrote:
> nit: perhaps this error message is not entirely accurate for bfloat16?
tnx



Comment at: clang/lib/AST/ItaniumMangle.cpp:3186
+case BuiltinType::Half:  EltName = "float16_t"; break;
+case BuiltinType::BFloat16:  EltName = "bfloat16x1_t"; break;
 default:

stuij wrote:
> majnemer wrote:
> > Why is this x1?
> Yes, that does look odd. The original author of this code has left the 
> company, but I'll ask around.
I'm not sure it's 100% wrong, but it's not consistent with GCC. Changing to 
`bfloat16_t`.



Comment at: clang/lib/Basic/Targets/AArch64.cpp:74
+  BFloat16Width = BFloat16Align = 16;
+  BFloat16Format = &llvm::APFloat::BFloat();
+

SjoerdMeijer wrote:
> Nit: we use bfloat16 everywhere, would `llvm::APFloat::BFloat16()` be better 
> for consistency?
In the IR world bfloat is consistently called bfloat, without the 16. I think 
this might turn into bikeshedding to justify if either one or both sides of the 
divide should or should not include the '16'. I can think of arguments to 
support the various options.

As I think there's no clear winner, I'd like to take the route of less effort 
and keep things as is.



Comment at: clang/lib/CodeGen/CodeGenModule.cpp:115
   HalfTy = llvm::Type::getHalfTy(LLVMContext);
+  BFloatTy = llvm::Type::getBFloatTy(LLVMContext);
   FloatTy = llvm::Type::getFloatTy(LLVMContext);

SjoerdMeijer wrote:
> nit: perhaps `getBFloat16Ty()`
see previous C - IR divide comment



Comment at: clang/lib/CodeGen/CodeGenTypeCache.h:39
+  /// half, bfloat, float, double
+  llvm::Type *HalfTy, *BFloatTy, *FloatTy, *DoubleTy;
 

SjoerdMeijer wrote:
> And so here too, BFloat16Ty?
see previous C - IR divide comment



Comment at: clang/lib/CodeGen/CodeGenTypes.cpp:307
+else
+  return llvm::Type::getInt16Ty(VMContext);
+  }

SjoerdMeijer wrote:
> Is this covered in tests?
Thanks. That code doesn't make sense to me. We are not expecting to emulate 
bfloat operations, and we shouldn't conflate bfloat with half. I'll remove the 
UseNativeHalf clause, and the one call-site of this fn.



Comment at: clang/lib/CodeGen/TargetInfo.cpp:5844
   ABIKind Kind;
+  bool IsSoftFloatABI;
 

SjoerdMeijer wrote:
> Nit: to distinguish the unfortunate float ABI names, I was wondering whether 
> `IsFloatABISoftFP` is clearer, or something along those lines, just to make 
> clear it is not the "soft" but the "softfp" variant
Yes, good idea. Done.



Comment at: clang/test/CodeGen/arm-mangle-16bit-float.cpp:2
+// RUN: %clang_cc1 -triple aarch64-arm-none-eabi 
-fallow-half-arguments-and-returns -target-feature +bf16 -target-feature 
+fullfp16 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK64
+// RUN: %clang_cc1 -triple arm-arm-none-eabi 
-fallow-half-arguments-and-returns -target-feature +bf16 -target-feature 
+fullfp16 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK32
+

SjoerdMeijer wrote:
> Do you need to pass `+fullfp16`?
I'm splitting out bf16 and fp16 tests. I don't think we should be testing with 
the union of cmdline options to accommodate testing multiple types in one file.


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[PATCH] D79708: [clang][BFloat] add NEON emitter for bfloat

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 266085.
stuij added a comment.

add bfloat header test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79708/new/

https://reviews.llvm.org/D79708

Files:
  clang/include/clang/Basic/arm_bf16.td
  clang/include/clang/Basic/arm_neon_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/arm-bf16-params-returns.c
  clang/test/Headers/arm-bf16-header.c
  clang/test/Preprocessor/aarch64-target-features.c
  clang/test/Preprocessor/arm-target-features.c
  clang/utils/TableGen/NeonEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -85,6 +85,7 @@
 
 void EmitNeon(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitFP16(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitBF16(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeonSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeonTest(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeon2(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -63,6 +63,7 @@
   GenClangOpenCLBuiltins,
   GenArmNeon,
   GenArmFP16,
+  GenArmBF16,
   GenArmNeonSema,
   GenArmNeonTest,
   GenArmMveHeader,
@@ -186,6 +187,7 @@
"Generate OpenCL builtin declaration handlers"),
 clEnumValN(GenArmNeon, "gen-arm-neon", "Generate arm_neon.h for clang"),
 clEnumValN(GenArmFP16, "gen-arm-fp16", "Generate arm_fp16.h for clang"),
+clEnumValN(GenArmBF16, "gen-arm-bf16", "Generate arm_bf16.h for clang"),
 clEnumValN(GenArmNeonSema, "gen-arm-neon-sema",
"Generate ARM NEON sema support for clang"),
 clEnumValN(GenArmNeonTest, "gen-arm-neon-test",
@@ -360,6 +362,9 @@
   case GenArmFP16:
 EmitFP16(Records, OS);
 break;
+  case GenArmBF16:
+EmitBF16(Records, OS);
+break;
   case GenArmNeonSema:
 EmitNeonSema(Records, OS);
 break;
Index: clang/utils/TableGen/NeonEmitter.cpp
===
--- clang/utils/TableGen/NeonEmitter.cpp
+++ clang/utils/TableGen/NeonEmitter.cpp
@@ -99,7 +99,8 @@
   Poly128,
   Float16,
   Float32,
-  Float64
+  Float64,
+  BFloat16
 };
 
 } // end namespace NeonTypeFlags
@@ -147,6 +148,7 @@
 SInt,
 UInt,
 Poly,
+BFloat16,
   };
   TypeKind Kind;
   bool Immediate, Constant, Pointer;
@@ -199,6 +201,7 @@
   bool isInt() const { return isInteger() && ElementBitwidth == 32; }
   bool isLong() const { return isInteger() && ElementBitwidth == 64; }
   bool isVoid() const { return Kind == Void; }
+  bool isBFloat16() const { return Kind == BFloat16; }
   unsigned getNumElements() const { return Bitwidth / ElementBitwidth; }
   unsigned getSizeInBits() const { return Bitwidth; }
   unsigned getElementSizeInBits() const { return ElementBitwidth; }
@@ -585,8 +588,11 @@
   // runFP16 - Emit arm_fp16.h.inc
   void runFP16(raw_ostream &o);
 
-  // runHeader - Emit all the __builtin prototypes used in arm_neon.h
-	// and arm_fp16.h
+  // runBF16 - Emit arm_bf16.h.inc
+  void runBF16(raw_ostream &o);
+
+  // runHeader - Emit all the __builtin prototypes used in arm_neon.h,
+  // arm_fp16.h and arm_bf16.h
   void runHeader(raw_ostream &o);
 
   // runTests - Emit tests for all the Neon intrinsics.
@@ -611,6 +617,8 @@
 S += "poly";
   else if (isFloating())
 S += "float";
+  else if (isBFloat16())
+S += "bfloat";
   else
 S += "int";
 
@@ -650,7 +658,10 @@
 case 128: S += "LLLi"; break;
 default: llvm_unreachable("Unhandled case!");
 }
-  else
+  else if (isBFloat16()) {
+assert(ElementBitwidth == 16 && "BFloat16 can only be 16 bits");
+S += "y";
+  } else
 switch (ElementBitwidth) {
 case 16: S += "h"; break;
 case 32: S += "f"; break;
@@ -704,6 +715,11 @@
 Base = (unsigned)NeonTypeFlags::Float16 + (Addend - 1);
   }
 
+  if (isBFloat16()) {
+assert(Addend == 1 && "BFloat16 is only 16 bit");
+Base = (unsigned)NeonTypeFlags::BFloat16;
+  }
+
   if (Bitwidth == 128)
 Base |= (unsigned)NeonTypeFlags::QuadFlag;
   if (isInteger() && !isSigned())
@@ -727,6 +743,9 @@
   } else if (Name.startswith("poly")) {
 T.Kind = Poly;
 Name = Name.drop_front(4);
+  } else if (Name.startswith("bfloat")) {
+T.Kind = BFloat16;
+Name = Name.drop_front(6);
   } else {
 assert(Name.startswith("int"));
 Name = Name.drop_front(3);
@@ -825,6 +844,10 @@
   if (isPoly())
 NumVectors = 0;
   break;
+  

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stuij added a comment.
This revision now requires changes to proceed.

We need testing for the backend code.


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[PATCH] D76077: [ARM] Add __bf16 as new Bfloat16 C Type

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stuij marked 9 inline comments as done.
stuij added inline comments.



Comment at: clang/lib/Basic/Targets/AArch64.cpp:74
+  BFloat16Width = BFloat16Align = 16;
+  BFloat16Format = &llvm::APFloat::BFloat();
+

SjoerdMeijer wrote:
> stuij wrote:
> > SjoerdMeijer wrote:
> > > Nit: we use bfloat16 everywhere, would `llvm::APFloat::BFloat16()` be 
> > > better for consistency?
> > In the IR world bfloat is consistently called bfloat, without the 16. I 
> > think this might turn into bikeshedding to justify if either one or both 
> > sides of the divide should or should not include the '16'. I can think of 
> > arguments to support the various options.
> > 
> > As I think there's no clear winner, I'd like to take the route of less 
> > effort and keep things as is.
> ah, I couldn't remember on which patch I commented on the bfloat16 vs bfloat 
> naming.
> Since everything is called bfloat16, from the architecture extension to the 
> source language type, I find this a bit of a missed opportunity to get the 
> names consistent. And I wouldn't say that naming of types is bikeshedding. 
> But maybe that's just me...
In general naming isn't bikeshedding. And I appreciate discussions on naming. 
I'm just afraid it might turn into bikeshedding. I do agree that such a remark 
isn't a very constructive to a conversation. Sorry.



Comment at: clang/test/CodeGen/arm-bf16-params-returns.c:5
+// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs -mfloat-abi 
softfp -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt 
-S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK64-SOFTFP
+
+// function return types

SjoerdMeijer wrote:
> what happens with `-mfloat-abi=soft`. Does that deserve a test?
Yes, this one is interesting. I think we shouldn't support bfloat at all in 
combination with -mfloat-abi=soft. We don't support software emulation of 
bfloat instructions and all operations on bfloat are simd instructions.

It turns out cc1 will accept -mfloat-abi=soft with neon intrinsics, which will 
happily churn out neon instructions. This doesn't sound very soft. The driver 
will ignore -mfloat-abi=soft in certain combinations of cmdline instructions, 
but I haven't delved deep enough to know what's what.

GCC doesn't allow soft+neon combination. Unfortunately it will actually crash 
for just a bfloat type by itself, which is quite useless without intrinsics. 
The Arm GCC folks will raise a ticket on this with as proposed solution to not 
allow this combination.

As this issue seems bigger than just bfloat, and potentially there's driver 
code involved as well I thought it'd make sense to handle this in a separate 
patch.



Comment at: clang/test/CodeGen/arm-mangle-16bit-float.cpp:4
+
+// CHECK64: define {{.*}}void @_Z3foou6__bf16(half %b)
+// CHECK32: define {{.*}}void @_Z3foou6__bf16(i32 %b.coerce)

SjoerdMeijer wrote:
> LukeGeeson wrote:
> > SjoerdMeijer wrote:
> > > LukeGeeson wrote:
> > > > craig.topper wrote:
> > > > > How can bfloat16 be passed as half? Don't they have a different 
> > > > > format?
> > > > see the above comment about soft-abis
> > > Probably I am bit confused too now... are the three possible types that 
> > > we are expecing not bfloat, i32, or i16? 
> > Hi Sjoerd, Good spot here I forgot to add a default case somewhere, which 
> > means AArch32 didn't observe `-mfloat-abi softfp` by default - and hence 
> > used bfloat where i32 was expected. 
> > 
> > I have a local patch for this and will send to Ties to merge into this one 
> > :) 
> > 
> > 
> > We're not sure what you mean by i16 however?
> Ah, as I said, got confused. Now I see we use i16 for targets that don't 
> support bfloat16. So we probably need a test for that.
As I wrote above, I think we currently should not allow it as long as there are 
no targets that support bfloat and have use for this combination.



Comment at: clang/test/CodeGen/arm-mangle-bf16.cpp:3
+// RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi 
hard -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK32-HARD
+// RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi 
softfp -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK32-SOFTFP
+

SjoerdMeijer wrote:
> SjoerdMeijer wrote:
> > nit: if the name mangling is Independent of the float ABI, then you might 
> > as well one runline and the abi option.
> -> ...  then you might as well have only one runline and remove the abi 
> option.
yes, I thought it's better to be defensive here, in case the implementation 
changes.


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[PATCH] D76077: [ARM] Add __bf16 as new Bfloat16 C Type

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stuij added inline comments.



Comment at: clang/lib/Basic/Targets/ARM.cpp:80
 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
+  BFloat16Width = BFloat16Align = 16;
+  BFloat16Format = &llvm::APFloat::BFloat();

SjoerdMeijer wrote:
> Is this tested? Can it be tested?
Yes, I think it's a bit tricky to test this all by itself. Right now this is 
used when return a TypeInfo, which is used in all kinds of different contexts. 
I think alignment is better tested where it is eventually expressed.


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[PATCH] D76077: [ARM] Add __bf16 as new Bfloat16 C Type

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stuij added a comment.

In D76077#2066323 , @SjoerdMeijer 
wrote:

> Can you summarise where we are? I.e.,
>
> - float-abi=soft doesn't work. But what is the problem? Are we not simply 
> passing i16s, is that not what we are supposed to do?


At the moment when going through the GCC compatibility driver (standard 
interface), we get `__bf16 is not supported on this target`.
When using -cc1, we can pass `-mfloat-abi=soft`, we can compile source-code 
that contains `__bf16`, and we can also compile neon intrinsics in general. It 
looks like we just ignore soft was passed and instead we use the hard 
float-abi. For intrinsics we should error.

In general we pass i32's btw, not i16's. Also for `__fp16`.

> Can you also update the description of this patch, I got totally confused by:
> 
> - "introduces an opaque, storage-only C-type __bf16, which does not introduce 
> a new LLVM IR type, but maps it to either i16 or half type."

willdo


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[PATCH] D76077: [ARM] Add __bf16 as new Bfloat16 C Type

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stuij added a comment.

In D76077#2066520 , @SjoerdMeijer 
wrote:

> > At the moment when going through the GCC compatibility driver (standard 
> > interface), we get __bf16 is not supported on this target.
>
> If this is the current behaviour, and consistent with GCC, that sounds 
> reasonable.


Unfortunately, this is not consistent with GCC. GCC will happily compile.


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[PATCH] D79710: [clang][BFloat] add create/set/get/dup intrinsics

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Comment at: clang/include/clang/Basic/arm_neon.td:1854
+  def VDUP_LANE_BF : WOpInst<"vdup_lane", ".qI", "bQb", OP_DUP_LN>;
+  def VDUP_LANEQ_BF: WOpInst<"vdup_laneq", ".QI", "bQb", OP_DUP_LN> {
+let isLaneQ = 1;

labrinea wrote:
> My local build points here with:
> `arm_neon.td:1926:3: error: No compatible intrinsic found - looking up 
> intrinsic 'splat_laneq(bfloat16x8_t, int32_t)'`
> 
> 
Thanks, yes we need to upstream another patch to match the upstreamed work 
already done for other types.


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[PATCH] D76077: [ARM] Add __bf16 as new Bfloat16 C Type

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stuij commandeered this revision.
stuij edited reviewers, added: LukeGeeson; removed: stuij.
stuij added a comment.

commandeering as I've got some changes to push


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[PATCH] D78194: [ARM] Add __bf16 as new Bfloat16 C Type

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stuij created this revision.
Herald added subscribers: cfe-commits, danielkiss, arphaman, kristof.beyls.
Herald added a project: clang.

This patch upstreams support for a new storage only bfloat16 C type.
This type is used to implement primitive support for bfloat16 data, in
line with the Bfloat16 extension of the Armv8.6-a architecture, as
detailed here:

https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a

The bfloat type, and its properties is specified in the Arm C language
extension specification:

https://developer.arm.com/docs/ihi0055/d/procedure-call-standard-for-the-arm-64-bit-architecture

In detail this patch:

  introduces an opaque, storage-only C-type __bf16, which does not introduce a 
new LLVM IR type, but maps it to either i16 or half type.

This is part of a patch series, starting with command-line and Bfloat16
assembly support. The subsequent patches will upstream intrinsics
support for BFloat16, followed by Matrix Multiplication and the
remaining Virtualization features of the armv8.6-a architecture.

Based on work by:

- Luke Cheeseman
- Momchil Velikov
- labrinea
- Luke Geeson


Repository:
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https://reviews.llvm.org/D78194

Files:
  clang/docs/LanguageExtensions.rst
  clang/include/clang-c/Index.h
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/BuiltinTypes.def
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/Specifiers.h
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Sema/DeclSpec.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/Basic/TargetInfo.cpp
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenTypeCache.h
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Format/FormatToken.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Parse/ParseDecl.cpp
  clang/lib/Parse/ParseExpr.cpp
  clang/lib/Parse/ParseExprCXX.cpp
  clang/lib/Parse/ParseTentative.cpp
  clang/lib/Sema/DeclSpec.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/lib/Sema/SemaTemplateVariadic.cpp
  clang/lib/Sema/SemaType.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/CodeGen/arm-mangle-16bit-float.cpp
  clang/test/Sema/arm-bfloat.cpp
  clang/tools/libclang/CXType.cpp

Index: clang/tools/libclang/CXType.cpp
===
--- clang/tools/libclang/CXType.cpp
+++ clang/tools/libclang/CXType.cpp
@@ -607,6 +607,7 @@
 TKIND(Elaborated);
 TKIND(Pipe);
 TKIND(Attributed);
+TKIND(Bfloat16);
 #define IMAGE_TYPE(ImgType, Id, SingletonId, Access, Suffix) TKIND(Id);
 #include "clang/Basic/OpenCLImageTypes.def"
 #undef IMAGE_TYPE
Index: clang/test/Sema/arm-bfloat.cpp
===
--- /dev/null
+++ clang/test/Sema/arm-bfloat.cpp
@@ -0,0 +1,29 @@
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple aarch64-arm-none-eabi -target-cpu cortex-a75 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple arm-arm-none-eabi -target-cpu cortex-a53 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+
+void test(bool b) {
+  __bf16 bf16;
+
+  bf16 + bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 - bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 * bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 / bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+
+  __fp16 fp16;
+
+  bf16 + fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 + bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 - fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 - bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 * fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 * bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 / fp16; // expected-error {{invalid operands to binary expres

[PATCH] D76077: [ARM] Add __bf16 as new Bfloat16 C Type

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stuij added a comment.

changes in the last patch: depend on bfloat IR type, and resolve some conflicts 
that crept in


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[PATCH] D76077: [ARM] Add __bf16 as new Bfloat16 C Type

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stuij updated this revision to Diff 268335.
stuij added a comment.

Addressed review comments. Notably what to do in combination with 
-mfloat-abi=soft.


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Files:
  clang/docs/LanguageExtensions.rst
  clang/include/clang-c/Index.h
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/BuiltinTypes.def
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/Specifiers.h
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Sema/DeclSpec.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/Basic/TargetInfo.cpp
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/ABIInfo.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/CodeGenTypeCache.h
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Format/FormatToken.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Parse/ParseDecl.cpp
  clang/lib/Parse/ParseExpr.cpp
  clang/lib/Parse/ParseExprCXX.cpp
  clang/lib/Parse/ParseTentative.cpp
  clang/lib/Sema/DeclSpec.cpp
  clang/lib/Sema/SemaCast.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/lib/Sema/SemaTemplateVariadic.cpp
  clang/lib/Sema/SemaType.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/CodeGen/arm-bf16-params-returns.c
  clang/test/CodeGen/arm-bf16-softfloat.c
  clang/test/CodeGen/arm-mangle-bf16.cpp
  clang/test/Sema/arm-bf16-forbidden-ops.c
  clang/test/Sema/arm-bf16-forbidden-ops.cpp
  clang/test/Sema/arm-bfloat.cpp
  clang/tools/libclang/CXType.cpp

Index: clang/tools/libclang/CXType.cpp
===
--- clang/tools/libclang/CXType.cpp
+++ clang/tools/libclang/CXType.cpp
@@ -608,6 +608,7 @@
 TKIND(Elaborated);
 TKIND(Pipe);
 TKIND(Attributed);
+TKIND(BFloat16);
 #define IMAGE_TYPE(ImgType, Id, SingletonId, Access, Suffix) TKIND(Id);
 #include "clang/Basic/OpenCLImageTypes.def"
 #undef IMAGE_TYPE
Index: clang/test/Sema/arm-bfloat.cpp
===
--- /dev/null
+++ clang/test/Sema/arm-bfloat.cpp
@@ -0,0 +1,29 @@
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple aarch64-arm-none-eabi -target-cpu cortex-a75 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple arm-arm-none-eabi -target-cpu cortex-a53 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+
+void test(bool b) {
+  __bf16 bf16;
+
+  bf16 + bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 - bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 * bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 / bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+
+  __fp16 fp16;
+
+  bf16 + fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 + bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 - fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 - bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 * fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 * bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 / fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 / bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 = fp16; // expected-error {{assigning to '__bf16' from incompatible type '__fp16'}}
+  fp16 = bf16; // expected-error {{assigning to '__fp16' from incompatible type '__bf16'}}
+  bf16 + (b ? fp16 : bf16); // expected-error {{incompatible operand types ('__fp16' and '__bf16')}}
+}
Index: clang/test/Sema/arm-bf16-forbidden-ops.cpp
===
--- /dev/null
+++ clang/test/Sema/arm-bf16-forbidden-ops.cpp
@@ -0,0 +1,71 @@
+// RUN

cfe-commits@lists.llvm.org

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stuij added a comment.

For the backend tests, I suggest using `-asm-verbose=0` with llc to only print 
instructions and get rid of `// kill: ..` and friends. Use 
`update_cc_test_checks.py` again to regenerate the testing.


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stuij added a comment.

In D80716#2073251 , @LukeGeeson wrote:

> Besides from rebasing to get @pratlucas changes upstream.
>
> @stuij  please could you confirm if you are happy with this, so I can merge


Hi Luke,

For the backend tests it would be good if you would use `CHECK-NEXT` from label 
to ret, like I believe you did in the other patch, using `-asm-verbose=0` to 
get rid of the cruft.


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[PATCH] D76077: [ARM] Add __bf16 as new Bfloat16 C Type

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stuij marked 2 inline comments as done.
stuij added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:6989
+  false,
+  getTarget().hasBFloat16Type());
   llvm::Type *Ty = VTy;

labrinea wrote:
> shouldn't this be `getTargetHooks().getABIInfo().allowBFloatArgsAndRet()` ?
thanks, done


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[PATCH] D79708: [clang][BFloat] add NEON emitter for bfloat

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stuij updated this revision to Diff 268616.
stuij marked 7 inline comments as done.
stuij added a comment.

addressed remaining nits


Repository:
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Files:
  clang/include/clang/Basic/arm_bf16.td
  clang/include/clang/Basic/arm_neon_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/arm-bf16-params-returns.c
  clang/test/Preprocessor/aarch64-target-features.c
  clang/test/Preprocessor/arm-target-features.c
  clang/utils/TableGen/NeonEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -85,6 +85,7 @@
 
 void EmitNeon(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitFP16(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitBF16(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeonSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeonTest(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeon2(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -63,6 +63,7 @@
   GenClangOpenCLBuiltins,
   GenArmNeon,
   GenArmFP16,
+  GenArmBF16,
   GenArmNeonSema,
   GenArmNeonTest,
   GenArmMveHeader,
@@ -186,6 +187,7 @@
"Generate OpenCL builtin declaration handlers"),
 clEnumValN(GenArmNeon, "gen-arm-neon", "Generate arm_neon.h for clang"),
 clEnumValN(GenArmFP16, "gen-arm-fp16", "Generate arm_fp16.h for clang"),
+clEnumValN(GenArmBF16, "gen-arm-bf16", "Generate arm_bf16.h for clang"),
 clEnumValN(GenArmNeonSema, "gen-arm-neon-sema",
"Generate ARM NEON sema support for clang"),
 clEnumValN(GenArmNeonTest, "gen-arm-neon-test",
@@ -360,6 +362,9 @@
   case GenArmFP16:
 EmitFP16(Records, OS);
 break;
+  case GenArmBF16:
+EmitBF16(Records, OS);
+break;
   case GenArmNeonSema:
 EmitNeonSema(Records, OS);
 break;
Index: clang/utils/TableGen/NeonEmitter.cpp
===
--- clang/utils/TableGen/NeonEmitter.cpp
+++ clang/utils/TableGen/NeonEmitter.cpp
@@ -99,7 +99,8 @@
   Poly128,
   Float16,
   Float32,
-  Float64
+  Float64,
+  BFloat16
 };
 
 } // end namespace NeonTypeFlags
@@ -147,6 +148,7 @@
 SInt,
 UInt,
 Poly,
+BFloat16,
   };
   TypeKind Kind;
   bool Immediate, Constant, Pointer;
@@ -199,6 +201,7 @@
   bool isInt() const { return isInteger() && ElementBitwidth == 32; }
   bool isLong() const { return isInteger() && ElementBitwidth == 64; }
   bool isVoid() const { return Kind == Void; }
+  bool isBFloat16() const { return Kind == BFloat16; }
   unsigned getNumElements() const { return Bitwidth / ElementBitwidth; }
   unsigned getSizeInBits() const { return Bitwidth; }
   unsigned getElementSizeInBits() const { return ElementBitwidth; }
@@ -583,8 +586,11 @@
   // runFP16 - Emit arm_fp16.h.inc
   void runFP16(raw_ostream &o);
 
-  // runHeader - Emit all the __builtin prototypes used in arm_neon.h
-	// and arm_fp16.h
+  // runBF16 - Emit arm_bf16.h.inc
+  void runBF16(raw_ostream &o);
+
+  // runHeader - Emit all the __builtin prototypes used in arm_neon.h,
+  // arm_fp16.h and arm_bf16.h
   void runHeader(raw_ostream &o);
 
   // runTests - Emit tests for all the Neon intrinsics.
@@ -609,6 +615,8 @@
 S += "poly";
   else if (isFloating())
 S += "float";
+  else if (isBFloat16())
+S += "bfloat";
   else
 S += "int";
 
@@ -648,7 +656,10 @@
 case 128: S += "LLLi"; break;
 default: llvm_unreachable("Unhandled case!");
 }
-  else
+  else if (isBFloat16()) {
+assert(ElementBitwidth == 16 && "BFloat16 can only be 16 bits");
+S += "y";
+  } else
 switch (ElementBitwidth) {
 case 16: S += "h"; break;
 case 32: S += "f"; break;
@@ -702,6 +713,11 @@
 Base = (unsigned)NeonTypeFlags::Float16 + (Addend - 1);
   }
 
+  if (isBFloat16()) {
+assert(Addend == 1 && "BFloat16 is only 16 bit");
+Base = (unsigned)NeonTypeFlags::BFloat16;
+  }
+
   if (Bitwidth == 128)
 Base |= (unsigned)NeonTypeFlags::QuadFlag;
   if (isInteger() && !isSigned())
@@ -725,6 +741,9 @@
   } else if (Name.startswith("poly")) {
 T.Kind = Poly;
 Name = Name.drop_front(4);
+  } else if (Name.startswith("bfloat")) {
+T.Kind = BFloat16;
+Name = Name.drop_front(6);
   } else {
 assert(Name.startswith("int"));
 Name = Name.drop_front(3);
@@ -823,6 +842,10 @@
   if (isPoly())
 NumVectors = 0;
   break;

[PATCH] D76077: [ARM] Add __bf16 as new Bfloat16 C Type

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stuij updated this revision to Diff 268614.
stuij marked an inline comment as done.
stuij added a comment.

Resolved merge conflicts with head. Fixed minor oversight.


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Files:
  clang/docs/LanguageExtensions.rst
  clang/include/clang-c/Index.h
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/BuiltinTypes.def
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/Specifiers.h
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Sema/DeclSpec.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/Basic/TargetInfo.cpp
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/ABIInfo.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/CodeGenTypeCache.h
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Format/FormatToken.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Parse/ParseDecl.cpp
  clang/lib/Parse/ParseExpr.cpp
  clang/lib/Parse/ParseExprCXX.cpp
  clang/lib/Parse/ParseTentative.cpp
  clang/lib/Sema/DeclSpec.cpp
  clang/lib/Sema/SemaCast.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/lib/Sema/SemaTemplateVariadic.cpp
  clang/lib/Sema/SemaType.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/CodeGen/arm-bf16-params-returns.c
  clang/test/CodeGen/arm-bf16-softfloat.c
  clang/test/CodeGen/arm-mangle-bf16.cpp
  clang/test/Sema/arm-bf16-forbidden-ops.c
  clang/test/Sema/arm-bf16-forbidden-ops.cpp
  clang/test/Sema/arm-bfloat.cpp
  clang/tools/libclang/CXType.cpp

Index: clang/tools/libclang/CXType.cpp
===
--- clang/tools/libclang/CXType.cpp
+++ clang/tools/libclang/CXType.cpp
@@ -608,6 +608,7 @@
 TKIND(Elaborated);
 TKIND(Pipe);
 TKIND(Attributed);
+TKIND(BFloat16);
 #define IMAGE_TYPE(ImgType, Id, SingletonId, Access, Suffix) TKIND(Id);
 #include "clang/Basic/OpenCLImageTypes.def"
 #undef IMAGE_TYPE
Index: clang/test/Sema/arm-bfloat.cpp
===
--- /dev/null
+++ clang/test/Sema/arm-bfloat.cpp
@@ -0,0 +1,29 @@
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple aarch64-arm-none-eabi -target-cpu cortex-a75 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple arm-arm-none-eabi -target-cpu cortex-a53 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+
+void test(bool b) {
+  __bf16 bf16;
+
+  bf16 + bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 - bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 * bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 / bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+
+  __fp16 fp16;
+
+  bf16 + fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 + bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 - fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 - bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 * fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 * bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 / fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 / bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 = fp16; // expected-error {{assigning to '__bf16' from incompatible type '__fp16'}}
+  fp16 = bf16; // expected-error {{assigning to '__fp16' from incompatible type '__bf16'}}
+  bf16 + (b ? fp16 : bf16); // expected-error {{incompatible operand types ('__fp16' and '__bf16')}}
+}
Index: clang/test/Sema/arm-bf16-forbidden-ops.cpp
===
--- /dev/null
+++ clang/test/Sema/arm-bf16-forbidden-ops.cpp
@@ -0,0 +1

[PATCH] D76077: [ARM] Add __bf16 as new Bfloat16 C Type

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This revision was automatically updated to reflect the committed changes.
Closed by commit rGecd682bbf5e6: [ARM] Add __bf16 as new Bfloat16 C Type 
(authored by stuij).

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Files:
  clang/docs/LanguageExtensions.rst
  clang/include/clang-c/Index.h
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/BuiltinTypes.def
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/Specifiers.h
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Sema/DeclSpec.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/Basic/TargetInfo.cpp
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/ABIInfo.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/CodeGenTypeCache.h
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Format/FormatToken.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Parse/ParseDecl.cpp
  clang/lib/Parse/ParseExpr.cpp
  clang/lib/Parse/ParseExprCXX.cpp
  clang/lib/Parse/ParseTentative.cpp
  clang/lib/Sema/DeclSpec.cpp
  clang/lib/Sema/SemaCast.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/lib/Sema/SemaTemplateVariadic.cpp
  clang/lib/Sema/SemaType.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/CodeGen/arm-bf16-params-returns.c
  clang/test/CodeGen/arm-bf16-softfloat.c
  clang/test/CodeGen/arm-mangle-bf16.cpp
  clang/test/Sema/arm-bf16-forbidden-ops.c
  clang/test/Sema/arm-bf16-forbidden-ops.cpp
  clang/test/Sema/arm-bfloat.cpp
  clang/tools/libclang/CXType.cpp

Index: clang/tools/libclang/CXType.cpp
===
--- clang/tools/libclang/CXType.cpp
+++ clang/tools/libclang/CXType.cpp
@@ -608,6 +608,7 @@
 TKIND(Elaborated);
 TKIND(Pipe);
 TKIND(Attributed);
+TKIND(BFloat16);
 #define IMAGE_TYPE(ImgType, Id, SingletonId, Access, Suffix) TKIND(Id);
 #include "clang/Basic/OpenCLImageTypes.def"
 #undef IMAGE_TYPE
Index: clang/test/Sema/arm-bfloat.cpp
===
--- /dev/null
+++ clang/test/Sema/arm-bfloat.cpp
@@ -0,0 +1,29 @@
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple aarch64-arm-none-eabi -target-cpu cortex-a75 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple arm-arm-none-eabi -target-cpu cortex-a53 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+
+void test(bool b) {
+  __bf16 bf16;
+
+  bf16 + bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 - bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 * bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 / bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+
+  __fp16 fp16;
+
+  bf16 + fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 + bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 - fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 - bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 * fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 * bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 / fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 / bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 = fp16; // expected-error {{assigning to '__bf16' from incompatible type '__fp16'}}
+  fp16 = bf16; // expected-error {{assigning to '__fp16' from incompatible type '__bf16'}}
+  bf16 + (b ? fp16 : bf16); // expected-error {{incompatible operand types ('__fp16' and '__bf16')}}
+}
Index: clang/test/Sema/arm-bf16-forbidden-ops.cpp
===
--- /dev/null
+++ clang/test/Sema/arm-bf16-forbidden-ops.cpp
@@ -0,0 +

[PATCH] D79711: [ARM] Add poly64_t on AArch32.

[Ties Stuij via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG1e447318339a: [ARM] Add poly64_t on AArch32. (authored by 
stuij).

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Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/CodeGen/arm-poly64.c
  clang/utils/TableGen/NeonEmitter.cpp


Index: clang/utils/TableGen/NeonEmitter.cpp
===
--- clang/utils/TableGen/NeonEmitter.cpp
+++ clang/utils/TableGen/NeonEmitter.cpp
@@ -2233,6 +2233,7 @@
   OS << "#else\n";
   OS << "typedef int8_t poly8_t;\n";
   OS << "typedef int16_t poly16_t;\n";
+  OS << "typedef int64_t poly64_t;\n";
   OS << "#endif\n";
 
   // Emit Neon vector typedefs.
@@ -2245,7 +2246,7 @@
   for (auto &TS : TDTypeVec) {
 bool IsA64 = false;
 Type T(TS, ".");
-if (T.isDouble() || (T.isPoly() && T.getElementSizeInBits() == 64))
+if (T.isDouble())
   IsA64 = true;
 
 if (InIfdef && !IsA64) {
@@ -2278,7 +2279,7 @@
 for (auto &TS : TDTypeVec) {
   bool IsA64 = false;
   Type T(TS, ".");
-  if (T.isDouble() || (T.isPoly() && T.getElementSizeInBits() == 64))
+  if (T.isDouble())
 IsA64 = true;
 
   if (InIfdef && !IsA64) {
Index: clang/test/CodeGen/arm-poly64.c
===
--- /dev/null
+++ clang/test/CodeGen/arm-poly64.c
@@ -0,0 +1,12 @@
+// RUN: %clang_cc1 -triple armv8.2a-arm-none-eabi -target-feature +neon \
+// RUN:  -emit-llvm -o - %s | FileCheck %s
+
+// Test that we can use the poly64 type on AArch32
+
+#include 
+
+// CHECK-LABEL: @test_poly64
+// CHECK: ret i64 %0
+poly64_t test_poly64(poly64_t a) {
+  return a;
+}
Index: clang/lib/Sema/SemaType.cpp
===
--- clang/lib/Sema/SemaType.cpp
+++ clang/lib/Sema/SemaType.cpp
@@ -7650,15 +7650,16 @@
 Triple.getArch() == llvm::Triple::aarch64_be;
   if (VecKind == VectorType::NeonPolyVector) {
 if (IsPolyUnsigned) {
-  // AArch64 polynomial vectors are unsigned and support poly64.
+  // AArch64 polynomial vectors are unsigned.
   return BTy->getKind() == BuiltinType::UChar ||
  BTy->getKind() == BuiltinType::UShort ||
  BTy->getKind() == BuiltinType::ULong ||
  BTy->getKind() == BuiltinType::ULongLong;
 } else {
-  // AArch32 polynomial vector are signed.
+  // AArch32 polynomial vectors are signed.
   return BTy->getKind() == BuiltinType::SChar ||
- BTy->getKind() == BuiltinType::Short;
+ BTy->getKind() == BuiltinType::Short ||
+ BTy->getKind() == BuiltinType::LongLong;
 }
   }
 
Index: clang/lib/AST/ItaniumMangle.cpp
===
--- clang/lib/AST/ItaniumMangle.cpp
+++ clang/lib/AST/ItaniumMangle.cpp
@@ -3167,6 +3167,7 @@
 case BuiltinType::UShort:
   EltName = "poly16_t";
   break;
+case BuiltinType::LongLong:
 case BuiltinType::ULongLong:
   EltName = "poly64_t";
   break;
Index: clang/include/clang/Basic/TargetBuiltins.h
===
--- clang/include/clang/Basic/TargetBuiltins.h
+++ clang/include/clang/Basic/TargetBuiltins.h
@@ -157,7 +157,7 @@
 EltType getEltType() const { return (EltType)(Flags & EltTypeMask); }
 bool isPoly() const {
   EltType ET = getEltType();
-  return ET == Poly8 || ET == Poly16;
+  return ET == Poly8 || ET == Poly16 || ET == Poly64;
 }
 bool isUnsigned() const { return (Flags & UnsignedFlag) != 0; }
 bool isQuad() const { return (Flags & QuadFlag) != 0; }


Index: clang/utils/TableGen/NeonEmitter.cpp
===
--- clang/utils/TableGen/NeonEmitter.cpp
+++ clang/utils/TableGen/NeonEmitter.cpp
@@ -2233,6 +2233,7 @@
   OS << "#else\n";
   OS << "typedef int8_t poly8_t;\n";
   OS << "typedef int16_t poly16_t;\n";
+  OS << "typedef int64_t poly64_t;\n";
   OS << "#endif\n";
 
   // Emit Neon vector typedefs.
@@ -2245,7 +2246,7 @@
   for (auto &TS : TDTypeVec) {
 bool IsA64 = false;
 Type T(TS, ".");
-if (T.isDouble() || (T.isPoly() && T.getElementSizeInBits() == 64))
+if (T.isDouble())
   IsA64 = true;
 
 if (InIfdef && !IsA64) {
@@ -2278,7 +2279,7 @@
 for (auto &TS : TDTypeVec) {
   bool IsA64 = false;
   Type T(TS, ".");
-  if (T.isDouble() || (T.isPoly() && T.getElementSizeInBits() == 64))
+  if (T.isDouble())
 IsA64 = true;
 
   if (InIfdef && !IsA64) {
Index: clang/test/CodeGen/arm-poly64.c
===
--- /dev/null
+++ clang/test/CodeGen/arm-poly64.c
@@ -0,0 +1,12 @@
+// RUN: %

[PATCH] D79708: [clang][BFloat] add NEON emitter for bfloat

[Ties Stuij via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGa6fcf5ca033a: [clang][BFloat] add NEON emitter for bfloat 
(authored by stuij).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79708/new/

https://reviews.llvm.org/D79708

Files:
  clang/include/clang/Basic/arm_bf16.td
  clang/include/clang/Basic/arm_neon_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/arm-bf16-params-returns.c
  clang/test/Preprocessor/aarch64-target-features.c
  clang/test/Preprocessor/arm-target-features.c
  clang/utils/TableGen/NeonEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -85,6 +85,7 @@
 
 void EmitNeon(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitFP16(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitBF16(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeonSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeonTest(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeon2(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -63,6 +63,7 @@
   GenClangOpenCLBuiltins,
   GenArmNeon,
   GenArmFP16,
+  GenArmBF16,
   GenArmNeonSema,
   GenArmNeonTest,
   GenArmMveHeader,
@@ -186,6 +187,7 @@
"Generate OpenCL builtin declaration handlers"),
 clEnumValN(GenArmNeon, "gen-arm-neon", "Generate arm_neon.h for clang"),
 clEnumValN(GenArmFP16, "gen-arm-fp16", "Generate arm_fp16.h for clang"),
+clEnumValN(GenArmBF16, "gen-arm-bf16", "Generate arm_bf16.h for clang"),
 clEnumValN(GenArmNeonSema, "gen-arm-neon-sema",
"Generate ARM NEON sema support for clang"),
 clEnumValN(GenArmNeonTest, "gen-arm-neon-test",
@@ -360,6 +362,9 @@
   case GenArmFP16:
 EmitFP16(Records, OS);
 break;
+  case GenArmBF16:
+EmitBF16(Records, OS);
+break;
   case GenArmNeonSema:
 EmitNeonSema(Records, OS);
 break;
Index: clang/utils/TableGen/NeonEmitter.cpp
===
--- clang/utils/TableGen/NeonEmitter.cpp
+++ clang/utils/TableGen/NeonEmitter.cpp
@@ -99,7 +99,8 @@
   Poly128,
   Float16,
   Float32,
-  Float64
+  Float64,
+  BFloat16
 };
 
 } // end namespace NeonTypeFlags
@@ -147,6 +148,7 @@
 SInt,
 UInt,
 Poly,
+BFloat16,
   };
   TypeKind Kind;
   bool Immediate, Constant, Pointer;
@@ -199,6 +201,7 @@
   bool isInt() const { return isInteger() && ElementBitwidth == 32; }
   bool isLong() const { return isInteger() && ElementBitwidth == 64; }
   bool isVoid() const { return Kind == Void; }
+  bool isBFloat16() const { return Kind == BFloat16; }
   unsigned getNumElements() const { return Bitwidth / ElementBitwidth; }
   unsigned getSizeInBits() const { return Bitwidth; }
   unsigned getElementSizeInBits() const { return ElementBitwidth; }
@@ -583,8 +586,11 @@
   // runFP16 - Emit arm_fp16.h.inc
   void runFP16(raw_ostream &o);
 
-  // runHeader - Emit all the __builtin prototypes used in arm_neon.h
-	// and arm_fp16.h
+  // runBF16 - Emit arm_bf16.h.inc
+  void runBF16(raw_ostream &o);
+
+  // runHeader - Emit all the __builtin prototypes used in arm_neon.h,
+  // arm_fp16.h and arm_bf16.h
   void runHeader(raw_ostream &o);
 
   // runTests - Emit tests for all the Neon intrinsics.
@@ -609,6 +615,8 @@
 S += "poly";
   else if (isFloating())
 S += "float";
+  else if (isBFloat16())
+S += "bfloat";
   else
 S += "int";
 
@@ -648,7 +656,10 @@
 case 128: S += "LLLi"; break;
 default: llvm_unreachable("Unhandled case!");
 }
-  else
+  else if (isBFloat16()) {
+assert(ElementBitwidth == 16 && "BFloat16 can only be 16 bits");
+S += "y";
+  } else
 switch (ElementBitwidth) {
 case 16: S += "h"; break;
 case 32: S += "f"; break;
@@ -702,6 +713,11 @@
 Base = (unsigned)NeonTypeFlags::Float16 + (Addend - 1);
   }
 
+  if (isBFloat16()) {
+assert(Addend == 1 && "BFloat16 is only 16 bit");
+Base = (unsigned)NeonTypeFlags::BFloat16;
+  }
+
   if (Bitwidth == 128)
 Base |= (unsigned)NeonTypeFlags::QuadFlag;
   if (isInteger() && !isSigned())
@@ -725,6 +741,9 @@
   } else if (Name.startswith("poly")) {
 T.Kind = Poly;
 Name = Name.drop_front(4);
+  } else if (Name.startswith("bfloat")) {
+T.Kind = BFloat16;
+Name = Name.drop_front(6);
   } else {
 assert(Name.startswith("int"));
 Name = Name.drop_front(3);
@@ -823,6 +842,10 @@
   if (isPoly())

[PATCH] D79710: [clang][BFloat] Add create/set/get/dup intrinsics

[Ties Stuij via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG8b137a430636: [clang][BFloat] Add create/set/get/dup 
intrinsics (authored by stuij).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79710/new/

https://reviews.llvm.org/D79710

Files:
  clang/include/clang/Basic/arm_neon.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-bf16-getset-intrinsics.c
  clang/test/CodeGen/arm-bf16-getset-intrinsics.c

Index: clang/test/CodeGen/arm-bf16-getset-intrinsics.c
===
--- /dev/null
+++ clang/test/CodeGen/arm-bf16-getset-intrinsics.c
@@ -0,0 +1,151 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi hard \
+// RUN:  -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg -instcombine | FileCheck %s
+
+#include 
+
+// CHECK-LABEL: @test_vcreate_bf16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast i64 [[A:%.*]] to <4 x bfloat>
+// CHECK-NEXT:ret <4 x bfloat> [[TMP0]]
+//
+bfloat16x4_t test_vcreate_bf16(uint64_t a) {
+  return vcreate_bf16(a);
+}
+
+// CHECK-LABEL: @test_vdup_n_bf16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[VECINIT_I:%.*]] = insertelement <4 x bfloat> undef, bfloat [[V:%.*]], i32 0
+// CHECK-NEXT:[[VECINIT3_I:%.*]] = shufflevector <4 x bfloat> [[VECINIT_I]], <4 x bfloat> undef, <4 x i32> zeroinitializer
+// CHECK-NEXT:ret <4 x bfloat> [[VECINIT3_I]]
+//
+bfloat16x4_t test_vdup_n_bf16(bfloat16_t v) {
+  return vdup_n_bf16(v);
+}
+
+// CHECK-LABEL: @test_vdupq_n_bf16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[VECINIT_I:%.*]] = insertelement <8 x bfloat> undef, bfloat [[V:%.*]], i32 0
+// CHECK-NEXT:[[VECINIT7_I:%.*]] = shufflevector <8 x bfloat> [[VECINIT_I]], <8 x bfloat> undef, <8 x i32> zeroinitializer
+// CHECK-NEXT:ret <8 x bfloat> [[VECINIT7_I]]
+//
+bfloat16x8_t test_vdupq_n_bf16(bfloat16_t v) {
+  return vdupq_n_bf16(v);
+}
+
+// CHECK-LABEL: @test_vdup_lane_bf16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[LANE:%.*]] = shufflevector <4 x bfloat> [[V:%.*]], <4 x bfloat> undef, <4 x i32> 
+// CHECK-NEXT:ret <4 x bfloat> [[LANE]]
+//
+bfloat16x4_t test_vdup_lane_bf16(bfloat16x4_t v) {
+  return vdup_lane_bf16(v, 1);
+}
+
+// CHECK-LABEL: @test_vdupq_lane_bf16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[LANE:%.*]] = shufflevector <4 x bfloat> [[V:%.*]], <4 x bfloat> undef, <8 x i32> 
+// CHECK-NEXT:ret <8 x bfloat> [[LANE]]
+//
+bfloat16x8_t test_vdupq_lane_bf16(bfloat16x4_t v) {
+  return vdupq_lane_bf16(v, 1);
+}
+
+// CHECK-LABEL: @test_vdup_laneq_bf16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[LANE:%.*]] = shufflevector <8 x bfloat> [[V:%.*]], <8 x bfloat> undef, <4 x i32> 
+// CHECK-NEXT:ret <4 x bfloat> [[LANE]]
+//
+bfloat16x4_t test_vdup_laneq_bf16(bfloat16x8_t v) {
+  return vdup_laneq_bf16(v, 7);
+}
+
+// CHECK-LABEL: @test_vdupq_laneq_bf16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[LANE:%.*]] = shufflevector <8 x bfloat> [[V:%.*]], <8 x bfloat> undef, <8 x i32> 
+// CHECK-NEXT:ret <8 x bfloat> [[LANE]]
+//
+bfloat16x8_t test_vdupq_laneq_bf16(bfloat16x8_t v) {
+  return vdupq_laneq_bf16(v, 7);
+}
+
+// CHECK-LABEL: @test_vcombine_bf16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[SHUFFLE_I:%.*]] = shufflevector <4 x bfloat> [[LOW:%.*]], <4 x bfloat> [[HIGH:%.*]], <8 x i32> 
+// CHECK-NEXT:ret <8 x bfloat> [[SHUFFLE_I]]
+//
+bfloat16x8_t test_vcombine_bf16(bfloat16x4_t low, bfloat16x4_t high) {
+  return vcombine_bf16(low, high);
+}
+
+// CHECK-LABEL: @test_vget_high_bf16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[SHUFFLE_I:%.*]] = shufflevector <8 x bfloat> [[A:%.*]], <8 x bfloat> undef, <4 x i32> 
+// CHECK-NEXT:ret <4 x bfloat> [[SHUFFLE_I]]
+//
+bfloat16x4_t test_vget_high_bf16(bfloat16x8_t a) {
+  return vget_high_bf16(a);
+}
+
+// CHECK-LABEL: @test_vget_low_bf16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[SHUFFLE_I:%.*]] = shufflevector <8 x bfloat> [[A:%.*]], <8 x bfloat> undef, <4 x i32> 
+// CHECK-NEXT:ret <4 x bfloat> [[SHUFFLE_I]]
+//
+bfloat16x4_t test_vget_low_bf16(bfloat16x8_t a) {
+  return vget_low_bf16(a);
+}
+
+// CHECK-LABEL: @test_vget_lane_bf16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[DOTCAST1:%.*]] = extractelement <4 x bfloat> [[V:%.*]], i32 1
+// CHECK-NEXT:ret bfloat [[DOTCAST1]]
+//
+bfloat16_t test_vget_lane_bf16(bfloat16x4_t v) {
+  return vget_lane_bf16(v, 1);
+}
+
+// CHECK-LABEL: @test_vgetq_lane_bf16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[DOTCAST1:%.*]] = extractelement <8 x bfloat> [[V:%.*]], i32 7
+// CHECK-NEXT:ret bfloat [[DOTCAST1]]
+//
+bfloat16_t test_vgetq_lane_bf16(bfloat16x8_t v) {
+  return vgetq_lane_bf16(v, 7);
+}
+
+// CHECK-LABEL: @test_vset_lane_bf16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = insertelement <4 x bfloat> [[V:%.

[PATCH] D79869: [clang][BFloat] Add reinterpret cast intrinsics

[Ties Stuij via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG5945e9799e77: [clang][BFloat] Add reinterpret cast 
intrinsics (authored by stuij).

Changed prior to commit:
  https://reviews.llvm.org/D79869?vs=264590&id=269052#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79869/new/

https://reviews.llvm.org/D79869

Files:
  clang/include/clang/Basic/arm_neon.td
  clang/include/clang/Basic/arm_neon_incl.td
  clang/test/CodeGen/aarch64-bf16-reinterpret-intrinsics.c
  clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
  clang/utils/TableGen/NeonEmitter.cpp

Index: clang/utils/TableGen/NeonEmitter.cpp
===
--- clang/utils/TableGen/NeonEmitter.cpp
+++ clang/utils/TableGen/NeonEmitter.cpp
@@ -311,7 +311,7 @@
   /// The unmangled name.
   std::string Name;
   /// The input and output typespecs. InTS == OutTS except when
-  /// CartesianProductOfTypes is 1 - this is the case for vreinterpret.
+  /// CartesianProductWith is non-empty - this is the case for vreinterpret.
   TypeSpec OutTS, InTS;
   /// The base class kind. Most intrinsics use ClassS, which has full type
   /// info for integers (s32/u32). Some use ClassI, which doesn't care about
@@ -344,7 +344,7 @@
   /// The set of intrinsics that this intrinsic uses/requires.
   std::set Dependencies;
   /// The "base type", which is Type('d', OutTS). InBaseType is only
-  /// different if CartesianProductOfTypes = 1 (for vreinterpret).
+  /// different if CartesianProductWith is non-empty (for vreinterpret).
   Type BaseType, InBaseType;
   /// The return variable.
   Variable RetVar;
@@ -1936,10 +1936,10 @@
   std::string Proto = std::string(R->getValueAsString("Prototype"));
   std::string Types = std::string(R->getValueAsString("Types"));
   Record *OperationRec = R->getValueAsDef("Operation");
-  bool CartesianProductOfTypes = R->getValueAsBit("CartesianProductOfTypes");
   bool BigEndianSafe  = R->getValueAsBit("BigEndianSafe");
   std::string Guard = std::string(R->getValueAsString("ArchGuard"));
   bool IsUnavailable = OperationRec->getValueAsBit("Unavailable");
+  std::string CartesianProductWith = std::string(R->getValueAsString("CartesianProductWith"));
 
   // Set the global current record. This allows assert_with_loc to produce
   // decent location information even when highly nested.
@@ -1954,17 +1954,20 @@
 CK = ClassMap[R->getSuperClasses()[1].first];
 
   std::vector> NewTypeSpecs;
-  for (auto TS : TypeSpecs) {
-if (CartesianProductOfTypes) {
+  if (!CartesianProductWith.empty()) {
+std::vector ProductTypeSpecs = TypeSpec::fromTypeSpecs(CartesianProductWith);
+for (auto TS : TypeSpecs) {
   Type DefaultT(TS, ".");
-  for (auto SrcTS : TypeSpecs) {
+  for (auto SrcTS : ProductTypeSpecs) {
 Type DefaultSrcT(SrcTS, ".");
 if (TS == SrcTS ||
 DefaultSrcT.getSizeInBits() != DefaultT.getSizeInBits())
   continue;
 NewTypeSpecs.push_back(std::make_pair(TS, SrcTS));
   }
-} else {
+}
+  } else {
+for (auto TS : TypeSpecs) {
   NewTypeSpecs.push_back(std::make_pair(TS, TS));
 }
   }
Index: clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
===
--- /dev/null
+++ clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
@@ -0,0 +1,314 @@
+// RUN: %clang_cc1 -triple armv8.2a-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi hard \
+// RUN: -disable-O0-optnone -S -emit-llvm -o - %s \
+// RUN: | opt -S -instcombine \
+// RUN: | FileCheck %s
+
+// REQUIRES: arm-registered-target
+
+#include 
+
+// CHECK-LABEL: @test_vreinterpret_bf16_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <8 x i8> [[A:%.*]] to <4 x bfloat>
+// CHECK-NEXT:ret <4 x bfloat> [[TMP0]]
+//
+bfloat16x4_t test_vreinterpret_bf16_s8(int8x8_t a)  { return vreinterpret_bf16_s8(a);}
+// CHECK-LABEL: @test_vreinterpret_bf16_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <4 x i16> [[A:%.*]] to <4 x bfloat>
+// CHECK-NEXT:ret <4 x bfloat> [[TMP0]]
+//
+bfloat16x4_t test_vreinterpret_bf16_s16(int16x4_t a){ return vreinterpret_bf16_s16(a);   }
+// CHECK-LABEL: @test_vreinterpret_bf16_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <2 x i32> [[A:%.*]] to <4 x bfloat>
+// CHECK-NEXT:ret <4 x bfloat> [[A:%.*]]
+//
+bfloat16x4_t test_vreinterpret_bf16_s32(int32x2_t a){ return vreinterpret_bf16_s32(a);   }
+// CHECK-LABEL: @test_vreinterpret_bf16_f32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <2 x float> [[A:%.*]] to <4 x bfloat>
+// CHECK-NEXT:ret <4 x bfloat> [[TMP0]]
+//
+bfloat16x4_t test_vreinterpret_bf16_f32(float32x2_t a)  { return vreinterpret_bf16_f32(a);   }
+// CHECK-LABEL: @test_vreinterpret_bf16_u8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*

cfe-commits@lists.llvm.org

[Ties Stuij via Phabricator via cfe-commits]

stuij added inline comments.



Comment at: llvm/test/CodeGen/AArch64/aarch64-bf16-ldst-intrinsics.ll:264
+; Function Attrs: argmemonly nounwind readonly
+declare { <8 x bfloat>, <8 x bfloat> } 
@llvm.aarch64.neon.ld2lane.v8bf16.p0i8(<8 x bfloat>, <8 x bfloat>, i64, i8*) #3
+

chill wrote:
> SjoerdMeijer wrote:
> > chill wrote:
> > > SjoerdMeijer wrote:
> > > > chill wrote:
> > > > > LukeGeeson wrote:
> > > > > > SjoerdMeijer wrote:
> > > > > > > LukeGeeson wrote:
> > > > > > > > arsenm wrote:
> > > > > > > > > Why is the IR type name bfloat and not bfloat16?
> > > > > > > > The naming for the IR type was agreed upon here after quite a 
> > > > > > > > big discussion. 
> > > > > > > > https://reviews.llvm.org/D78190
> > > > > > > I regret very much that I didn't notice this earlier... I.e., I 
> > > > > > > noticed this in D76077 and wrote that I am relatively unhappy 
> > > > > > > about this (I think I mentioned this on another ticket too).
> > > > > > > Because like @arsenm , I would expect the IR type name to be 
> > > > > > > bfloat16.
> > > > > > > 
> > > > > > > Correct me if I am wrong, but I don't see a big discussion about 
> > > > > > > this in D78190. I only see 1 or 2 comments about `BFloat` vs 
> > > > > > > `Bfloat`.
> > > > > > I cannot see a discussion about the IR type name per-se but I can 
> > > > > > see you were both involved in the discussion more generally.
> > > > > > 
> > > > > > I am concerned that this patch is the wrong place to discuss such 
> > > > > > issues, and that we should bring this up in a more appropriate 
> > > > > > place as you mention so that this patch isn't held back.
> > > > > I don't see a compelling reason for the name to be `bfloat16` or 
> > > > > `bfloat3`, etc. Like other floating-point types (`float`, `double`, 
> > > > > and `half`), the name denotes a specific externally defined format, 
> > > > > unlike `iN`.
> > > > > Like other floating-point types (float, double, and half), the name 
> > > > > denotes a specific externally defined format, 
> > > > 
> > > > Is the defined format not called bfloat16?
> > > Indeed, people use the name "bfloat16". But then the `half`, `float`, and 
> > > `double` also differ from the official `binary16`, `binarty32`, and 
> > > `binary64`.
> > > IMHO `bfloat` fits better in the LLVM IR naming convention.
> > yeah, so that's exactly why I don't follow your logic. If there's any logic 
> > in the names here, the mapping from source-language type to IR type seems 
> > the most plausible one. And I just don't see the benefit of dropping the 
> > 16, and how that would fit better in some naming scheme or how that makes 
> > things clearer here.
> What source language?
> 
> That said, I'm resigning from the bikeshedding here.
Just as a house-keeping note: If we would change the naming, I think we can all 
agree that this ticket itself shouldn't be the place where we want to do this. 
I'm happy for the conversation to carry on here, but I think we can move the 
ticket forward at the same time.



Comment at: llvm/test/CodeGen/AArch64/aarch64-bf16-ldst-intrinsics.ll:916
+
+attributes #0 = { norecurse nounwind readonly 
"correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" 
"frame-pointer"="none" "less-precise-fpmad"="false" 
"min-legal-vector-width"="64" "no-infs-fp-math"="false" 
"no-jump-tables"="false" "no-nans-fp-math"="false" 
"no-signed-zeros-fp-math"="false" "no-trapping-math"="false" 
"stack-protector-buffer-size"="8" "target-features"="+bf16,+neon" 
"unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { norecurse nounwind readonly 
"correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" 
"frame-pointer"="none" "less-precise-fpmad"="false" 
"min-legal-vector-width"="128" "no-infs-fp-math"="false" 
"no-jump-tables"="false" "no-nans-fp-math"="false" 
"no-signed-zeros-fp-math"="false" "no-trapping-math"="false" 
"stack-protector-buffer-size"="8" "target-features"="+bf16,+neon" 
"unsafe-fp-math"="false" "use-soft-float"="false" }

You should be able to do without all these big blocks of attributes which I 
guess were generated from C -> IR conversion. Just remove it and the `#x`s 
after the function declarations (maybe replace them with `nounwind`).


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stuij accepted this revision.
stuij added a comment.

LGTM. Thanks!


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stuij accepted this revision.
stuij added a comment.
This revision is now accepted and ready to land.

LGTM. Thanks!


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[PATCH] D81837: [ARM][bfloat] Removing lowering of bfloat arguments and returns from Clang's CodeGen

[Ties Stuij via Phabricator via cfe-commits]

stuij created this revision.
Herald added subscribers: cfe-commits, danielkiss, kristof.beyls.
Herald added a project: clang.
stuij added a child revision: D81373: [WIP] Basic bfloat support on Arm.

As part of moving the argument lowering handling for bfloat arguments and
returns to the backend, this patch removes the code that was responsible for
handling the coercion of those arguments in Clang's Codegen.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81837

Files:
  clang/lib/CodeGen/ABIInfo.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/arm-bf16-getset-intrinsics.c
  clang/test/CodeGen/arm-bf16-params-returns.c
  clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c

Index: clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
===
--- clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
+++ clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
@@ -1,7 +1,7 @@
 // RUN: %clang_cc1 -triple armv8.2a-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi hard \
-// RUN: -disable-O0-optnone -S -emit-llvm -o - %s \
-// RUN: | opt -S -instcombine \
-// RUN: | FileCheck %s
+// RUN: -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -instcombine | FileCheck %s
+// RUN: %clang_cc1 -triple armv8.2a-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi softfp \
+// RUN: -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -instcombine | FileCheck %s
 
 // REQUIRES: arm-registered-target
 
Index: clang/test/CodeGen/arm-bf16-params-returns.c
===
--- clang/test/CodeGen/arm-bf16-params-returns.c
+++ clang/test/CodeGen/arm-bf16-params-returns.c
@@ -1,7 +1,7 @@
-// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK32-HARD
-// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK64-HARD
-// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi softfp -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK32-SOFTFP
-// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs -mfloat-abi softfp -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK64-SOFTFP
+// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s
+// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi softfp -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs -mfloat-abi softfp -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s
 
 #include 
 
@@ -9,24 +9,11 @@
 __bf16 test_ret_bf16(__bf16 v) {
   return v;
 }
-// CHECK32-HARD: define arm_aapcs_vfpcc bfloat @test_ret_bf16(bfloat returned %v) {{.*}} {
-// CHECK32-HARD: ret bfloat %v
-// CHECK64-HARD: define bfloat @test_ret_bf16(bfloat returned %v) {{.*}} {
-// CHECK64-HARD: ret bfloat %v
-// CHECK32-SOFTFP: define i32 @test_ret_bf16(i32 [[V0:.*]]) {{.*}} {
-// CHECK32-SOFTFP: %tmp2.0.insert.ext = and i32 [[V0]], 65535
-// CHECK32-SOFTFP: ret i32 %tmp2.0.insert.ext
-// CHECK64-SOFTFP: define bfloat @test_ret_bf16(bfloat returned %v) {{.*}} {
-// CHECK64-SOFTFP: ret bfloat %v
+// CHECK: define {{.*}}bfloat @test_ret_bf16(bfloat returned %v) {{.*}} {
+// CHECK: ret bfloat %v
 
 bfloat16x4_t test_ret_bf16x4_t(bfloat16x4_t v) {
   return v;
 }
-// CHECK32-HARD: define arm_aapcs_vfpcc <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> returned %v) {{.*}} {
-// CHECK32-HARD: ret <4 x bfloat> %v
-// CHECK64-HARD: define <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> returned %v) {{.*}} {
-// CHECK64-HARD: ret <4 x bfloat> %v
-// CHECK32-SOFTFP: define <2 x i32> @test_ret_bf16x4_t(<2 x i32> [[V0:.*]]) {{.*}} {
-// CHECK32-SOFTFP: ret <2 x i32> %v
-// CHECK64-SOFTFP: define <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> returned %v) {{.*}} {
-// CHECK64-SOFTFP: ret <4 x bfloat> %v
+// CHECK: define {{.*}}<4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> returned %v) {{.*}} {
+// CHECK: ret <4 x bfloat> %v
Index: clang/test/CodeGen/arm-bf16-getset-intrinsics.c
=

[PATCH] D81837: [ARM][bfloat] Removing lowering of bfloat arguments and returns from Clang's CodeGen

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 270721.
stuij added a comment.

adjust arm bfloat mangle tests for these changes


Repository:
  rG LLVM Github Monorepo

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Files:
  clang/lib/CodeGen/ABIInfo.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/arm-bf16-getset-intrinsics.c
  clang/test/CodeGen/arm-bf16-params-returns.c
  clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
  clang/test/CodeGen/arm-mangle-bf16.cpp

Index: clang/test/CodeGen/arm-mangle-bf16.cpp
===
--- clang/test/CodeGen/arm-mangle-bf16.cpp
+++ clang/test/CodeGen/arm-mangle-bf16.cpp
@@ -1,8 +1,6 @@
-// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +bf16 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK64
-// RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi hard -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK32-HARD
-// RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi softfp -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK32-SOFTFP
+// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +bf16 -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi hard -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi softfp -emit-llvm -o - %s | FileCheck %s
 
-// CHECK64: define {{.*}}void @_Z3foou6__bf16(bfloat %b)
-// CHECK32-HARD: define {{.*}}void @_Z3foou6__bf16(bfloat %b)
-// CHECK32-SOFTFP: define {{.*}}void @_Z3foou6__bf16(i32 %b.coerce)
+// CHECK: define {{.*}}void @_Z3foou6__bf16(bfloat %b)
 void foo(__bf16 b) {}
Index: clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
===
--- clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
+++ clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
@@ -1,7 +1,7 @@
 // RUN: %clang_cc1 -triple armv8.2a-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi hard \
-// RUN: -disable-O0-optnone -S -emit-llvm -o - %s \
-// RUN: | opt -S -instcombine \
-// RUN: | FileCheck %s
+// RUN: -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -instcombine | FileCheck %s
+// RUN: %clang_cc1 -triple armv8.2a-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi softfp \
+// RUN: -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -instcombine | FileCheck %s
 
 // REQUIRES: arm-registered-target
 
Index: clang/test/CodeGen/arm-bf16-params-returns.c
===
--- clang/test/CodeGen/arm-bf16-params-returns.c
+++ clang/test/CodeGen/arm-bf16-params-returns.c
@@ -1,7 +1,7 @@
-// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK32-HARD
-// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK64-HARD
-// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi softfp -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK32-SOFTFP
-// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs -mfloat-abi softfp -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK64-SOFTFP
+// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s
+// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi softfp -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs -mfloat-abi softfp -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s
 
 #include 
 
@@ -9,24 +9,11 @@
 __bf16 test_ret_bf16(__bf16 v) {
   return v;
 }
-// CHECK32-HARD: define arm_aapcs_vfpcc bfloat @test_ret_bf16(bfloat returned %v) {{.*}} {
-// CHECK32-HARD: ret bfloat %v
-// CHECK64-HARD: define bfloat @test_ret_bf16(bfloat returned %v) {{.*}} {
-// CHECK64-HARD: ret bfloat %v
-// CHECK32-SOFTFP: define i32 @test_ret_bf16(i32 [[V0:.*]]) {{.*}} {
-// CHECK32-SOFTFP: %tmp2.0.insert.ext = and i32 [[V0]], 65535
-// CHECK32-SOFTFP: ret i32 %t

[PATCH] D81451: [ARM][Clang] Removing lowering of half-precision FP arguments and returns from Clang's CodeGen

[Ties Stuij via Phabricator via cfe-commits]

stuij added a comment.

I would have expected changes for neon as well.

Can't we now also get rid of the HasLegalHalfType argument to GetNeonType in 
CGBuiltin.(h|cpp). And also similar code in TargetInfo.cpp 
(ARMABIInfo::classifyReturnType, ARMABIInfo::isIllegalVectorType)?


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[PATCH] D81304: [llvm][SveEmitter] Emit the bfloat version of `svld1ro`.

[Ties Stuij via Phabricator via cfe-commits]

stuij added inline comments.



Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c:1
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE -triple 
aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | 
FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE 
-DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s

There should be no dependency on `-fallow-half-arguments-and-returns`. For 
bfloat we should use `-mfloat-abi hard`. Does this work for `-mfloat-abi 
softfp`?


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[PATCH] D81837: [ARM][bfloat] Removing lowering of bfloat arguments and returns from Clang's CodeGen

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 271130.
stuij added a comment.

We only remove clang-side lowering for non-vector bfloat types.


Repository:
  rG LLVM Github Monorepo

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Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/arm-bf16-params-returns.c
  clang/test/CodeGen/arm-mangle-bf16.cpp


Index: clang/test/CodeGen/arm-mangle-bf16.cpp
===
--- clang/test/CodeGen/arm-mangle-bf16.cpp
+++ clang/test/CodeGen/arm-mangle-bf16.cpp
@@ -1,8 +1,6 @@
-// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +bf16 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK64
-// RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi 
hard -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK32-HARD
-// RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi 
softfp -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK32-SOFTFP
+// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +bf16 
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi 
hard -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi 
softfp -emit-llvm -o - %s | FileCheck %s
 
-// CHECK64: define {{.*}}void @_Z3foou6__bf16(bfloat %b)
-// CHECK32-HARD: define {{.*}}void @_Z3foou6__bf16(bfloat %b)
-// CHECK32-SOFTFP: define {{.*}}void @_Z3foou6__bf16(i32 %b.coerce)
+// CHECK: define {{.*}}void @_Z3foou6__bf16(bfloat %b)
 void foo(__bf16 b) {}
Index: clang/test/CodeGen/arm-bf16-params-returns.c
===
--- clang/test/CodeGen/arm-bf16-params-returns.c
+++ clang/test/CodeGen/arm-bf16-params-returns.c
@@ -13,9 +13,8 @@
 // CHECK32-HARD: ret bfloat %v
 // CHECK64-HARD: define bfloat @test_ret_bf16(bfloat returned %v) {{.*}} {
 // CHECK64-HARD: ret bfloat %v
-// CHECK32-SOFTFP: define i32 @test_ret_bf16(i32 [[V0:.*]]) {{.*}} {
-// CHECK32-SOFTFP: %tmp2.0.insert.ext = and i32 [[V0]], 65535
-// CHECK32-SOFTFP: ret i32 %tmp2.0.insert.ext
+// CHECK32-SOFTFP: define bfloat @test_ret_bf16(bfloat returned %v) {{.*}} {
+// CHECK32-SOFTFP: ret bfloat %v
 // CHECK64-SOFTFP: define bfloat @test_ret_bf16(bfloat returned %v) {{.*}} {
 // CHECK64-SOFTFP: ret bfloat %v
 
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -6276,13 +6276,6 @@
 return ABIArgInfo::getDirect(ResType);
   }
 
-  // __bf16 gets passed using the bfloat IR type, or using i32 but
-  // with the top 16 bits unspecified.
-  if (Ty->isBFloat16Type() && IsFloatABISoftFP) {
-llvm::Type *ResType = llvm::Type::getInt32Ty(getVMContext());
-return ABIArgInfo::getDirect(ResType);
-  }
-
   if (!isAggregateTypeForABI(Ty)) {
 // Treat an enum type as its underlying type.
 if (const EnumType *EnumTy = Ty->getAs()) {
@@ -6497,15 +6490,6 @@
 return ABIArgInfo::getDirect(ResType);
   }
 
-  // if we're using the softfp float abi, __bf16 get returned as if it were an
-  // int but with the top 16 bits unspecified.
-  if (RetTy->isBFloat16Type()) {
-llvm::Type *ResType = IsAAPCS_VFP ?
-  llvm::Type::getBFloatTy(getVMContext()) :
-  llvm::Type::getInt32Ty(getVMContext());
-return ABIArgInfo::getDirect(ResType);
-  }
-
   if (!isAggregateTypeForABI(RetTy)) {
 // Treat an enum type as its underlying type.
 if (const EnumType *EnumTy = RetTy->getAs())


Index: clang/test/CodeGen/arm-mangle-bf16.cpp
===
--- clang/test/CodeGen/arm-mangle-bf16.cpp
+++ clang/test/CodeGen/arm-mangle-bf16.cpp
@@ -1,8 +1,6 @@
-// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +bf16 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK64
-// RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi hard -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK32-HARD
-// RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi softfp -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK32-SOFTFP
+// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +bf16 -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi hard -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi softfp -emit-llvm -o - %s | FileCheck %s
 
-// CHECK64: define {{.*}}void @_Z3foou6__bf16(bfloat %b)
-// CHECK32-HARD: define {{.*}}void @_Z3foou6__bf16(bfloat %b)
-// CHECK32-SOFTFP: define {{.*}}void @_Z3foou6__bf16(i32 %b.coerce)
+// CHECK: define {{.*}}void @_Z3foou6__bf16(bfloat %b)
 void foo(__bf16 b) {}
Index: clang/test/CodeGen/arm-bf16-params-returns.

[PATCH] D81451: [ARM][Clang] Removing lowering of half-precision FP arguments and returns from Clang's CodeGen

[Ties Stuij via Phabricator via cfe-commits]

stuij added a comment.

In D81451#2092997 , @pratlucas wrote:

> Hi @stuij,
>
> The changes to the backend only handle the half (f16) type itself, not 
> vectors that have it as their base type.
>
> From what I've checked on the AAPCS, the rules for handling those types are a 
> bit different and they would require their own handling in the backend's 
> calling convention lowering.
>  I haven't looked into the backend's handling of those types in detail, but I 
> believe a similar approach to the one taken for f16 would be possible for the 
> vector types as well.


Fair enough. Thanks.


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[PATCH] D81304: [llvm][SveEmitter] Emit the bfloat version of `svld1ro`.

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stuij added inline comments.



Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c:1
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE -triple 
aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | 
FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE 
-DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s

sdesmalen wrote:
> fpetrogalli wrote:
> > sdesmalen wrote:
> > > stuij wrote:
> > > > There should be no dependency on `-fallow-half-arguments-and-returns`. 
> > > > For bfloat we should use `-mfloat-abi hard`. Does this work for 
> > > > `-mfloat-abi softfp`?
> > > `-fallow-half-arguments-and-returns` isn't strictly needed for this test, 
> > > we just use the same RUN line for all the ACLE tests and we needed this 
> > > for `__fp16` in some of the tests.
> > > 
> > > I don't believe that `-mfloat-abi softfp` is supported for AArch64.
> > @stuij - the following lines work, one with `softfp` and one with `hard`:
> > 
> > ```
> > // RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 
> > -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE 
> > -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve 
> > -target\
> > -feature +bf16 -mfloat-abi softfp -fallow-half-arguments-and-returns -S -O1 
> > -Werror -Wall -emit-llvm -o - %s | FileCheck %s
> > // RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 
> > -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE 
> > -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve 
> > -target\
> > -feature +bf16 -mfloat-abi hard -fallow-half-arguments-and-returns -S -O1 
> > -Werror -Wall -emit-llvm -o - %s | FileCheck %s
> > ```
> > 
> > @sdesmalen I am not an experer here, but there is a test which targets 
> > aarch64 that uses `softfp` (see 
> > `clang/test/CodeGen/arm-bf16-params-returns.c`). The following line in that 
> > test clearly targets `aarch64`:
> > 
> > ```
> > // RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs 
> > -mfloat-abi softfp -target-feature +bf16 -target-feature +neon -emit-llvm 
> > -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s \
> > --check-prefix=CHECK64-SOFTFP
> > ```
> > 
> > @both - should I update the test with the two extra RUN lines mentioned up 
> > in the message?
> > @sdesmalen I am not an experer here, but there is a test which targets 
> > aarch64 that uses softfp (see 
> > clang/test/CodeGen/arm-bf16-params-returns.c). The following line in that 
> > test clearly targets aarch64:
> `clang/test/CodeGen/arm-bf16-params-returns.c` also shows that setting 
> `softfp` has no effect for AArch64.
> 
> > @both - should I update the test with the two extra RUN lines mentioned up 
> > in the message?
> No, I think the extra RUN lines aren't necessary.
@fpetrogalli: @sdesmalen is totally right. Softfp doesn't make sense on AArch64 
as fp isn't optional. I think the original intent of that AArch64 line in 
`arm-bf16-params-returns.c` was to make sure AArch64 indeed doesn't change, but 
then the option should of course never be passed in the first place. I guess 
this is a bit of over-defensive coding against the way clang isn't stellar at 
argument passing.


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[PATCH] D81304: [llvm][SveEmitter] Emit the bfloat version of `svld1ro`.

[Ties Stuij via Phabricator via cfe-commits]

stuij accepted this revision.
stuij added a comment.

LGTM


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[PATCH] D78190: Add Bfloat IR type

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stuij marked an inline comment as done.
stuij added inline comments.



Comment at: llvm/include/llvm-c/Core.h:149
   LLVMHalfTypeKind,/**< 16 bit floating point type */
+  LLVMBFloatTypeKind,  /**< 16 bit brain floating point type */
   LLVMFloatTypeKind,   /**< 32 bit floating point type */

tstellar wrote:
> Can you move this new enum value to the end of enum definition?  Adding it 
> here changes the C ABI.
Yes, np. Will make a patch today.


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[PATCH] D81837: [ARM][bfloat] Removing lowering of bfloat arguments and returns from Clang's CodeGen

[Ties Stuij via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG035795659b60: [ARM][bfloat] Do not coerce bfloat arguments 
and returns to integers (authored by stuij).

Changed prior to commit:
  https://reviews.llvm.org/D81837?vs=271130&id=271775#toc

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Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/arm-bf16-params-returns.c
  clang/test/CodeGen/arm-mangle-bf16.cpp


Index: clang/test/CodeGen/arm-mangle-bf16.cpp
===
--- clang/test/CodeGen/arm-mangle-bf16.cpp
+++ clang/test/CodeGen/arm-mangle-bf16.cpp
@@ -1,8 +1,6 @@
-// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +bf16 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK64
-// RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi 
hard -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK32-HARD
-// RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi 
softfp -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK32-SOFTFP
+// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +bf16 
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi 
hard -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi 
softfp -emit-llvm -o - %s | FileCheck %s
 
-// CHECK64: define {{.*}}void @_Z3foou6__bf16(bfloat %b)
-// CHECK32-HARD: define {{.*}}void @_Z3foou6__bf16(bfloat %b)
-// CHECK32-SOFTFP: define {{.*}}void @_Z3foou6__bf16(i32 %b.coerce)
+// CHECK: define {{.*}}void @_Z3foou6__bf16(bfloat %b)
 void foo(__bf16 b) {}
Index: clang/test/CodeGen/arm-bf16-params-returns.c
===
--- clang/test/CodeGen/arm-bf16-params-returns.c
+++ clang/test/CodeGen/arm-bf16-params-returns.c
@@ -1,7 +1,6 @@
 // RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-abi aapcs 
-mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o 
- %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK32-HARD
-// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs -mfloat-abi 
hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt 
-S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK64-HARD
 // RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-abi aapcs 
-mfloat-abi softfp -target-feature +bf16 -target-feature +neon -emit-llvm -O2 
-o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK32-SOFTFP
-// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs -mfloat-abi 
softfp -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt 
-S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK64-SOFTFP
+// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs 
-target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S 
-mem2reg -sroa | FileCheck %s --check-prefix=CHECK64
 
 #include 
 
@@ -11,22 +10,17 @@
 }
 // CHECK32-HARD: define arm_aapcs_vfpcc bfloat @test_ret_bf16(bfloat returned 
%v) {{.*}} {
 // CHECK32-HARD: ret bfloat %v
-// CHECK64-HARD: define bfloat @test_ret_bf16(bfloat returned %v) {{.*}} {
-// CHECK64-HARD: ret bfloat %v
-// CHECK32-SOFTFP: define i32 @test_ret_bf16(i32 [[V0:.*]]) {{.*}} {
-// CHECK32-SOFTFP: %tmp2.0.insert.ext = and i32 [[V0]], 65535
-// CHECK32-SOFTFP: ret i32 %tmp2.0.insert.ext
-// CHECK64-SOFTFP: define bfloat @test_ret_bf16(bfloat returned %v) {{.*}} {
-// CHECK64-SOFTFP: ret bfloat %v
+// CHECK32-SOFTFP: define bfloat @test_ret_bf16(bfloat returned %v) {{.*}} {
+// CHECK32-SOFTFP: ret bfloat %v
+// CHECK64: define bfloat @test_ret_bf16(bfloat returned %v) {{.*}} {
+// CHECK64: ret bfloat %v
 
 bfloat16x4_t test_ret_bf16x4_t(bfloat16x4_t v) {
   return v;
 }
 // CHECK32-HARD: define arm_aapcs_vfpcc <4 x bfloat> @test_ret_bf16x4_t(<4 x 
bfloat> returned %v) {{.*}} {
 // CHECK32-HARD: ret <4 x bfloat> %v
-// CHECK64-HARD: define <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> returned 
%v) {{.*}} {
-// CHECK64-HARD: ret <4 x bfloat> %v
 // CHECK32-SOFTFP: define <2 x i32> @test_ret_bf16x4_t(<2 x i32> [[V0:.*]]) 
{{.*}} {
 // CHECK32-SOFTFP: ret <2 x i32> %v
-// CHECK64-SOFTFP: define <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> 
returned %v) {{.*}} {
-// CHECK64-SOFTFP: ret <4 x bfloat> %v
+// CHECK64: define <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> returned %v) 
{{.*}} {
+// CHECK64: ret <4 x bfloat> %v
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -6265,13 +6265,6 @@
   if (isIllegalVectorType(Ty))
 return coerceIllegalVector(Ty);
 
-  // __bf16 gets passed using the bfloat IR type, or using i32 but
-  // with

[PATCH] D78190: Add Bfloat IR type

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stuij added inline comments.



Comment at: llvm/include/llvm-c/Core.h:149
   LLVMHalfTypeKind,/**< 16 bit floating point type */
+  LLVMBFloatTypeKind,  /**< 16 bit brain floating point type */
   LLVMFloatTypeKind,   /**< 32 bit floating point type */

stuij wrote:
> tstellar wrote:
> > Can you move this new enum value to the end of enum definition?  Adding it 
> > here changes the C ABI.
> Yes, np. Will make a patch today.
patch up for review: https://reviews.llvm.org/D82135


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[PATCH] D82206: [ARM][BFloat] Implement bf16 get/set_lane without casts to i16 vectors

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stuij accepted this revision.
stuij added a comment.
This revision is now accepted and ready to land.

LGTM. Thanks!


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[PATCH] D80928: [BFloat] Add convert/copy instrinsic support

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stuij accepted this revision.
stuij added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D78194: [ARM] Add __bf16 as new Bfloat16 C Type

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 258017.
stuij added a comment.

changes: depend on bfloat IR type, and resolve some conflicts that crept in


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Files:
  clang/docs/LanguageExtensions.rst
  clang/include/clang-c/Index.h
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/BuiltinTypes.def
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/Specifiers.h
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Sema/DeclSpec.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/Basic/TargetInfo.cpp
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenTypeCache.h
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Format/FormatToken.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Parse/ParseDecl.cpp
  clang/lib/Parse/ParseExpr.cpp
  clang/lib/Parse/ParseExprCXX.cpp
  clang/lib/Parse/ParseTentative.cpp
  clang/lib/Sema/DeclSpec.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/lib/Sema/SemaTemplateVariadic.cpp
  clang/lib/Sema/SemaType.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/CodeGen/arm-mangle-16bit-float.cpp
  clang/test/Sema/arm-bfloat.cpp
  clang/tools/libclang/CXType.cpp

Index: clang/tools/libclang/CXType.cpp
===
--- clang/tools/libclang/CXType.cpp
+++ clang/tools/libclang/CXType.cpp
@@ -607,6 +607,7 @@
 TKIND(Elaborated);
 TKIND(Pipe);
 TKIND(Attributed);
+TKIND(Bfloat16);
 #define IMAGE_TYPE(ImgType, Id, SingletonId, Access, Suffix) TKIND(Id);
 #include "clang/Basic/OpenCLImageTypes.def"
 #undef IMAGE_TYPE
Index: clang/test/Sema/arm-bfloat.cpp
===
--- /dev/null
+++ clang/test/Sema/arm-bfloat.cpp
@@ -0,0 +1,29 @@
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple aarch64-arm-none-eabi -target-cpu cortex-a75 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple arm-arm-none-eabi -target-cpu cortex-a53 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+
+void test(bool b) {
+  __bf16 bf16;
+
+  bf16 + bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 - bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 * bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 / bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+
+  __fp16 fp16;
+
+  bf16 + fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 + bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 - fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 - bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 * fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 * bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 / fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 / bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 = fp16; // expected-error {{assigning to '__bf16' from incompatible type '__fp16'}}
+  fp16 = bf16; // expected-error {{assigning to '__fp16' from incompatible type '__bf16'}}
+  bf16 + (b ? fp16 : bf16); // expected-error {{incompatible operand types ('__fp16' and '__bf16')}}
+}
Index: clang/test/CodeGen/arm-mangle-16bit-float.cpp
===
--- /dev/null
+++ clang/test/CodeGen/arm-mangle-16bit-float.cpp
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -fallow-half-arguments-and-returns -target-feature +bf16 -target-feature +fullfp16 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK64
+// RUN: %clang_cc1 -triple arm-arm-none-eabi -fallow-half-arguments-and-returns -target-feature +bf16 -target-feature +fullfp16 -emit-llvm -o - %s | FileCheck %s --

[PATCH] D76077: [ARM] Add __bf16 as new Bfloat16 C Type

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 258018.
stuij added a comment.

changes: depend on bfloat IR type, and resolve some conflicts that crept in


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Files:
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  clang/include/clang-c/Index.h
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/BuiltinTypes.def
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/Specifiers.h
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Sema/DeclSpec.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/Basic/TargetInfo.cpp
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenTypeCache.h
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Format/FormatToken.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Parse/ParseDecl.cpp
  clang/lib/Parse/ParseExpr.cpp
  clang/lib/Parse/ParseExprCXX.cpp
  clang/lib/Parse/ParseTentative.cpp
  clang/lib/Sema/DeclSpec.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/lib/Sema/SemaTemplateVariadic.cpp
  clang/lib/Sema/SemaType.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/CodeGen/arm-mangle-16bit-float.cpp
  clang/test/Sema/arm-bfloat.cpp
  clang/tools/libclang/CXType.cpp

Index: clang/tools/libclang/CXType.cpp
===
--- clang/tools/libclang/CXType.cpp
+++ clang/tools/libclang/CXType.cpp
@@ -607,6 +607,7 @@
 TKIND(Elaborated);
 TKIND(Pipe);
 TKIND(Attributed);
+TKIND(Bfloat16);
 #define IMAGE_TYPE(ImgType, Id, SingletonId, Access, Suffix) TKIND(Id);
 #include "clang/Basic/OpenCLImageTypes.def"
 #undef IMAGE_TYPE
Index: clang/test/Sema/arm-bfloat.cpp
===
--- /dev/null
+++ clang/test/Sema/arm-bfloat.cpp
@@ -0,0 +1,29 @@
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple aarch64-arm-none-eabi -target-cpu cortex-a75 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple arm-arm-none-eabi -target-cpu cortex-a53 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+
+void test(bool b) {
+  __bf16 bf16;
+
+  bf16 + bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 - bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 * bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 / bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+
+  __fp16 fp16;
+
+  bf16 + fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 + bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 - fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 - bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 * fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 * bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 / fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 / bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 = fp16; // expected-error {{assigning to '__bf16' from incompatible type '__fp16'}}
+  fp16 = bf16; // expected-error {{assigning to '__fp16' from incompatible type '__bf16'}}
+  bf16 + (b ? fp16 : bf16); // expected-error {{incompatible operand types ('__fp16' and '__bf16')}}
+}
Index: clang/test/CodeGen/arm-mangle-16bit-float.cpp
===
--- /dev/null
+++ clang/test/CodeGen/arm-mangle-16bit-float.cpp
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -fallow-half-arguments-and-returns -target-feature +bf16 -target-feature +fullfp16 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK64
+// RUN: %clang_cc1 -triple arm-arm-none-eabi -fallow-half-arguments-and-returns -target-feature +bf16 -target-feature +fullfp16 -emit-llvm -o - %s | FileCheck %s --

[PATCH] D78194: [ARM] Add __bf16 as new Bfloat16 C Type

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stuij added a comment.

This should not have been it's own revision. I wrongly trusted arc to update 
https://reviews.llvm.org/D76077.


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[PATCH] D78190: Add Bfloat IR type

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stuij updated this revision to Diff 258036.
stuij marked 2 inline comments as done.
stuij added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

addressing review comments


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Files:
  clang/lib/Sema/SemaOpenMP.cpp
  llvm/docs/BitCodeFormat.rst
  llvm/docs/LangRef.rst
  llvm/include/llvm-c/Core.h
  llvm/include/llvm/ADT/APFloat.h
  llvm/include/llvm/Bitcode/LLVMBitCodes.h
  llvm/include/llvm/IR/Constants.h
  llvm/include/llvm/IR/DataLayout.h
  llvm/include/llvm/IR/Type.h
  llvm/lib/AsmParser/LLLexer.cpp
  llvm/lib/AsmParser/LLParser.cpp
  llvm/lib/Bitcode/Reader/BitcodeReader.cpp
  llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
  llvm/lib/CodeGen/MIRParser/MILexer.cpp
  llvm/lib/IR/AsmWriter.cpp
  llvm/lib/IR/Constants.cpp
  llvm/lib/IR/Core.cpp
  llvm/lib/IR/DataLayout.cpp
  llvm/lib/IR/Function.cpp
  llvm/lib/IR/LLVMContextImpl.cpp
  llvm/lib/IR/LLVMContextImpl.h
  llvm/lib/IR/Type.cpp
  llvm/lib/Support/APFloat.cpp
  llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/Assembler/bfloat-constprop.ll
  llvm/test/Assembler/bfloat-conv.ll
  llvm/test/Assembler/bfloat.ll
  llvm/tools/llvm-c-test/echo.cpp

Index: llvm/tools/llvm-c-test/echo.cpp
===
--- llvm/tools/llvm-c-test/echo.cpp
+++ llvm/tools/llvm-c-test/echo.cpp
@@ -72,6 +72,8 @@
 return LLVMVoidTypeInContext(Ctx);
   case LLVMHalfTypeKind:
 return LLVMHalfTypeInContext(Ctx);
+  case LLVMBfloatTypeKind:
+return LLVMHalfTypeInContext(Ctx);
   case LLVMFloatTypeKind:
 return LLVMFloatTypeInContext(Ctx);
   case LLVMDoubleTypeKind:
Index: llvm/test/Assembler/bfloat.ll
===
--- /dev/null
+++ llvm/test/Assembler/bfloat.ll
@@ -0,0 +1,15 @@
+; RUN: llvm-as < %s | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+; Basic smoke test for bfloat type.
+
+; CHECK: define bfloat @check_bfloat
+define bfloat @check_bfloat(bfloat %A) {
+; CHECK: ret bfloat %A
+ret bfloat %A
+}
+
+; CHECK: define bfloat @check_bfloat_literal
+define bfloat @check_bfloat_literal() {
+; CHECK: ret bfloat 0xR3149
+ret bfloat 0xR3149
+}
Index: llvm/test/Assembler/bfloat-conv.ll
===
--- /dev/null
+++ llvm/test/Assembler/bfloat-conv.ll
@@ -0,0 +1,14 @@
+; RUN: opt < %s -O3 -S | FileCheck %s
+; RUN: verify-uselistorder %s
+; Testing bfloat to float conversion.
+
+define float @abc() nounwind {
+entry:
+  %a = alloca bfloat, align 2
+  %.compoundliteral = alloca float, align 4
+  store bfloat 0xR4C8D, bfloat* %a, align 2
+  %tmp = load bfloat, bfloat* %a, align 2
+  %conv = fpext bfloat %tmp to float
+; CHECK: 0x4191A000
+  ret float %conv
+}
Index: llvm/test/Assembler/bfloat-constprop.ll
===
--- /dev/null
+++ llvm/test/Assembler/bfloat-constprop.ll
@@ -0,0 +1,17 @@
+; RUN: opt < %s -O3 -S | FileCheck %s
+; RUN: verify-uselistorder %s
+; Testing bfloat constant propagation.
+
+define bfloat @abc() nounwind {
+entry:
+  %a = alloca bfloat, align 2
+  %b = alloca bfloat, align 2
+  %.compoundliteral = alloca float, align 4
+  store bfloat 0xR40C0, bfloat* %a, align 2
+  store bfloat 0xR40C0, bfloat* %b, align 2
+  %tmp = load bfloat, bfloat* %a, align 2
+  %tmp1 = load bfloat, bfloat* %b, align 2
+  %add = fadd bfloat %tmp, %tmp1
+; CHECK: 0xR4140
+  ret bfloat %add
+}
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -11438,8 +11438,9 @@
   MVT LogicVT = VT;
   if (EltVT == MVT::f32 || EltVT == MVT::f64) {
 Zero = DAG.getConstantFP(0.0, DL, EltVT);
-AllOnes = DAG.getConstantFP(
-APFloat::getAllOnesValue(EltVT.getSizeInBits(), true), DL, EltVT);
+APFloat AllOnesValue = APFloat::getAllOnesValue(
+SelectionDAG::EVTToAPFloatSemantics(EltVT), EltVT.getSizeInBits());
+AllOnes = DAG.getConstantFP(AllOnesValue, DL, EltVT);
 LogicVT =
 MVT::getVectorVT(EltVT == MVT::f64 ? MVT::i64 : MVT::i32, Mask.size());
   } else {
Index: llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
===
--- llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
+++ llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
@@ -322,6 +322,7 @@
   }
   case Type::FunctionTyID:
   case Type::VoidTyID:
+  case Type::BfloatTyID:
   case Type::X86_FP80TyID:
   case Type::FP128TyID:
   case Type::PPC_FP128TyID:
Index: llvm/lib/Support/APFloat.cpp
===
--- llvm/lib/Support/APFloat.cpp
+++ l

[PATCH] D78190: Add Bfloat IR type

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stuij added a comment.

@craig.topper : Yes, I thought to keep this patch confined to IR. Codegen and 
intrinsics patches are still to come.




Comment at: llvm/docs/LangRef.rst:2896
+   * - ``bfloat``
+ - 16-bit brain floating-point value (10-bit mantissa)
+

craig.topper wrote:
> bfloat doesn't have 10-bits of mantissa. its 1 bit of sign, 8-bits of 
> exponent and 7-bits of mantissa.
Ai, such a fail. Thanks!



Comment at: llvm/lib/Support/APFloat.cpp:4837
 
 APFloat APFloat::getAllOnesValue(unsigned BitWidth, bool isIEEE) {
   if (isIEEE) {

craig.topper wrote:
> This is a bit of strange interace. I wonder if it wouldn't be possible to 
> have the callers pass the semantics instead of the bitwidth and then this 
> function could get the bitwidth from the semantics. It looks like there 
> aren't many callers. I believe the one in Constants.cpp could get the 
> semantics from getFltSemantics on the Type. Probably similar could be done at 
> other callers?
Yes, I wholeheartedly concur. Turns out the function was also used in both 
front- and backend, but luckily there were already similar getters available 
for FltSemantics. I hoped to get also get rid of the BitWidth argument, but it 
turns out that it's not guaranteed that that FltSemantics has that filled in 
properly. Hardcoding exceptions didn't feel very nice and would make this a fn 
that can easily be overlooked to update for new types.


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stuij added inline comments.



Comment at: llvm/include/llvm/IR/Constants.h:790
+  static Constant *getFP(Type *ElementType, ArrayRef Elts);
 
   /// Return a ConstantVector with the specified constant in each element.

jdoerfert wrote:
> Drive by: The documentation of these functions need to be changed and it 
> needs to be clarified what would happen if you pass `double` to the 
> `uint16_y` version.
Thanks. I changed the documentation and added type asserts to guard against 
passing unfit types.



Comment at: llvm/test/Assembler/bfloat-constprop.ll:1
+; RUN: opt < %s -O3 -S | FileCheck %s
+; RUN: verify-uselistorder %s

arsenm wrote:
> This test is doing way too much. You can reduce the to just ret fadd K0, K1
Fair to all the testcase comments.


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[PATCH] D78190: Add Bfloat IR type

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stuij updated this revision to Diff 258185.
stuij marked 4 inline comments as done.
stuij added a comment.

added some type constraints to the various getFP containter methods, adjusted 
getFP documentation, and simplified test cases


Repository:
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Files:
  clang/lib/Sema/SemaOpenMP.cpp
  llvm/docs/BitCodeFormat.rst
  llvm/docs/LangRef.rst
  llvm/include/llvm-c/Core.h
  llvm/include/llvm/ADT/APFloat.h
  llvm/include/llvm/Bitcode/LLVMBitCodes.h
  llvm/include/llvm/IR/Constants.h
  llvm/include/llvm/IR/DataLayout.h
  llvm/include/llvm/IR/Type.h
  llvm/lib/AsmParser/LLLexer.cpp
  llvm/lib/AsmParser/LLParser.cpp
  llvm/lib/Bitcode/Reader/BitcodeReader.cpp
  llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
  llvm/lib/CodeGen/MIRParser/MILexer.cpp
  llvm/lib/IR/AsmWriter.cpp
  llvm/lib/IR/Constants.cpp
  llvm/lib/IR/Core.cpp
  llvm/lib/IR/DataLayout.cpp
  llvm/lib/IR/Function.cpp
  llvm/lib/IR/LLVMContextImpl.cpp
  llvm/lib/IR/LLVMContextImpl.h
  llvm/lib/IR/Type.cpp
  llvm/lib/Support/APFloat.cpp
  llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/Assembler/bfloat.ll
  llvm/tools/llvm-c-test/echo.cpp

Index: llvm/tools/llvm-c-test/echo.cpp
===
--- llvm/tools/llvm-c-test/echo.cpp
+++ llvm/tools/llvm-c-test/echo.cpp
@@ -72,6 +72,8 @@
 return LLVMVoidTypeInContext(Ctx);
   case LLVMHalfTypeKind:
 return LLVMHalfTypeInContext(Ctx);
+  case LLVMBfloatTypeKind:
+return LLVMHalfTypeInContext(Ctx);
   case LLVMFloatTypeKind:
 return LLVMFloatTypeInContext(Ctx);
   case LLVMDoubleTypeKind:
Index: llvm/test/Assembler/bfloat.ll
===
--- /dev/null
+++ llvm/test/Assembler/bfloat.ll
@@ -0,0 +1,26 @@
+; RUN: llvm-as < %s | llvm-dis | FileCheck %s --check-prefix=ASSEM-DISASS
+; RUN: opt < %s -O3 -S | FileCheck %s --check-prefix=OPT
+; RUN: verify-uselistorder %s
+; Basic smoke tests for bfloat type.
+
+define bfloat @check_bfloat(bfloat %A) {
+; ASSEM-DISASS: ret bfloat %A
+ret bfloat %A
+}
+
+define bfloat @check_bfloat_literal() {
+; ASSEM-DISASS: ret bfloat 0xR3149
+ret bfloat 0xR3149
+}
+
+define bfloat @check_bfloat_constprop() {
+  %tmp = fadd bfloat 0xR40C0, 0xR40C0
+; OPT: 0xR4140
+  ret bfloat %tmp
+}
+
+define float @check_bfloat_convert() {
+  %tmp = fpext bfloat 0xR4C8D to float
+; OPT: 0x4191A000
+  ret float %tmp
+}
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -11438,8 +11438,9 @@
   MVT LogicVT = VT;
   if (EltVT == MVT::f32 || EltVT == MVT::f64) {
 Zero = DAG.getConstantFP(0.0, DL, EltVT);
-AllOnes = DAG.getConstantFP(
-APFloat::getAllOnesValue(EltVT.getSizeInBits(), true), DL, EltVT);
+APFloat AllOnesValue = APFloat::getAllOnesValue(
+SelectionDAG::EVTToAPFloatSemantics(EltVT), EltVT.getSizeInBits());
+AllOnes = DAG.getConstantFP(AllOnesValue, DL, EltVT);
 LogicVT =
 MVT::getVectorVT(EltVT == MVT::f64 ? MVT::i64 : MVT::i32, Mask.size());
   } else {
Index: llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
===
--- llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
+++ llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
@@ -322,6 +322,7 @@
   }
   case Type::FunctionTyID:
   case Type::VoidTyID:
+  case Type::BfloatTyID:
   case Type::X86_FP80TyID:
   case Type::FP128TyID:
   case Type::PPC_FP128TyID:
Index: llvm/lib/Support/APFloat.cpp
===
--- llvm/lib/Support/APFloat.cpp
+++ llvm/lib/Support/APFloat.cpp
@@ -69,6 +69,7 @@
   };
 
   static const fltSemantics semIEEEhalf = {15, -14, 11, 16};
+  static const fltSemantics semBfloat = {127, -126, 8, 16};
   static const fltSemantics semIEEEsingle = {127, -126, 24, 32};
   static const fltSemantics semIEEEdouble = {1023, -1022, 53, 64};
   static const fltSemantics semIEEEquad = {16383, -16382, 113, 128};
@@ -117,6 +118,8 @@
 switch (S) {
 case S_IEEEhalf:
   return IEEEhalf();
+case S_Bfloat:
+  return Bfloat();
 case S_IEEEsingle:
   return IEEEsingle();
 case S_IEEEdouble:
@@ -135,6 +138,8 @@
   APFloatBase::SemanticsToEnum(const llvm::fltSemantics &Sem) {
 if (&Sem == &llvm::APFloat::IEEEhalf())
   return S_IEEEhalf;
+else if (&Sem == &llvm::APFloat::Bfloat())
+  return S_Bfloat;
 else if (&Sem == &llvm::APFloat::IEEEsingle())
   return S_IEEEsingle;
 else if (&Sem == &llvm::APFloat::IEEEdouble())
@@ -152,6 +157,9 @@
   const fltSemantics &APFloatBase::IEEEhalf() {
 return semIEEEhalf;
   }
+  const fltSemantics

[PATCH] D78190: Add Bfloat IR type

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Marked all comments as having been addressed.


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[PATCH] D78190: Add Bfloat IR type

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stuij updated this revision to Diff 260326.
stuij added a comment.

addressed comments: throughout the patch changed the string `Bfloat` to 
`BFloat`, expanded description of bfloat in the documentation, addressed misc 
comments.

also added `Type *getBFloatTy()` to IRBuilder.h

thanks for the comments


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Files:
  clang/lib/Sema/SemaOpenMP.cpp
  llvm/docs/BitCodeFormat.rst
  llvm/docs/LangRef.rst
  llvm/include/llvm-c/Core.h
  llvm/include/llvm/ADT/APFloat.h
  llvm/include/llvm/Bitcode/LLVMBitCodes.h
  llvm/include/llvm/IR/Constants.h
  llvm/include/llvm/IR/DataLayout.h
  llvm/include/llvm/IR/IRBuilder.h
  llvm/include/llvm/IR/Type.h
  llvm/lib/AsmParser/LLLexer.cpp
  llvm/lib/AsmParser/LLParser.cpp
  llvm/lib/Bitcode/Reader/BitcodeReader.cpp
  llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
  llvm/lib/CodeGen/MIRParser/MILexer.cpp
  llvm/lib/IR/AsmWriter.cpp
  llvm/lib/IR/Constants.cpp
  llvm/lib/IR/Core.cpp
  llvm/lib/IR/DataLayout.cpp
  llvm/lib/IR/Function.cpp
  llvm/lib/IR/LLVMContextImpl.cpp
  llvm/lib/IR/LLVMContextImpl.h
  llvm/lib/IR/Type.cpp
  llvm/lib/Support/APFloat.cpp
  llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/Assembler/bfloat.ll
  llvm/tools/llvm-c-test/echo.cpp

Index: llvm/tools/llvm-c-test/echo.cpp
===
--- llvm/tools/llvm-c-test/echo.cpp
+++ llvm/tools/llvm-c-test/echo.cpp
@@ -72,6 +72,8 @@
 return LLVMVoidTypeInContext(Ctx);
   case LLVMHalfTypeKind:
 return LLVMHalfTypeInContext(Ctx);
+  case LLVMBFloatTypeKind:
+return LLVMHalfTypeInContext(Ctx);
   case LLVMFloatTypeKind:
 return LLVMFloatTypeInContext(Ctx);
   case LLVMDoubleTypeKind:
Index: llvm/test/Assembler/bfloat.ll
===
--- /dev/null
+++ llvm/test/Assembler/bfloat.ll
@@ -0,0 +1,26 @@
+; RUN: llvm-as < %s | llvm-dis | FileCheck %s --check-prefix=ASSEM-DISASS
+; RUN: opt < %s -O3 -S | FileCheck %s --check-prefix=OPT
+; RUN: verify-uselistorder %s
+; Basic smoke tests for bfloat type.
+
+define bfloat @check_bfloat(bfloat %A) {
+; ASSEM-DISASS: ret bfloat %A
+ret bfloat %A
+}
+
+define bfloat @check_bfloat_literal() {
+; ASSEM-DISASS: ret bfloat 0xR3149
+ret bfloat 0xR3149
+}
+
+define bfloat @check_bfloat_constprop() {
+  %tmp = fadd bfloat 0xR40C0, 0xR40C0
+; OPT: 0xR4140
+  ret bfloat %tmp
+}
+
+define float @check_bfloat_convert() {
+  %tmp = fpext bfloat 0xR4C8D to float
+; OPT: 0x4191A000
+  ret float %tmp
+}
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -11460,8 +11460,9 @@
   MVT LogicVT = VT;
   if (EltVT == MVT::f32 || EltVT == MVT::f64) {
 Zero = DAG.getConstantFP(0.0, DL, EltVT);
-AllOnes = DAG.getConstantFP(
-APFloat::getAllOnesValue(EltVT.getSizeInBits(), true), DL, EltVT);
+APFloat AllOnesValue = APFloat::getAllOnesValue(
+SelectionDAG::EVTToAPFloatSemantics(EltVT), EltVT.getSizeInBits());
+AllOnes = DAG.getConstantFP(AllOnesValue, DL, EltVT);
 LogicVT =
 MVT::getVectorVT(EltVT == MVT::f64 ? MVT::i64 : MVT::i32, Mask.size());
   } else {
Index: llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
===
--- llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
+++ llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
@@ -323,6 +323,7 @@
   }
   case Type::FunctionTyID:
   case Type::VoidTyID:
+  case Type::BFloatTyID:
   case Type::X86_FP80TyID:
   case Type::FP128TyID:
   case Type::PPC_FP128TyID:
Index: llvm/lib/Support/APFloat.cpp
===
--- llvm/lib/Support/APFloat.cpp
+++ llvm/lib/Support/APFloat.cpp
@@ -69,6 +69,7 @@
   };
 
   static const fltSemantics semIEEEhalf = {15, -14, 11, 16};
+  static const fltSemantics semBFloat = {127, -126, 8, 16};
   static const fltSemantics semIEEEsingle = {127, -126, 24, 32};
   static const fltSemantics semIEEEdouble = {1023, -1022, 53, 64};
   static const fltSemantics semIEEEquad = {16383, -16382, 113, 128};
@@ -117,6 +118,8 @@
 switch (S) {
 case S_IEEEhalf:
   return IEEEhalf();
+case S_BFloat:
+  return BFloat();
 case S_IEEEsingle:
   return IEEEsingle();
 case S_IEEEdouble:
@@ -135,6 +138,8 @@
   APFloatBase::SemanticsToEnum(const llvm::fltSemantics &Sem) {
 if (&Sem == &llvm::APFloat::IEEEhalf())
   return S_IEEEhalf;
+else if (&Sem == &llvm::APFloat::BFloat())
+  return S_BFloat;
 else if (&Sem == &llvm::APFloat::IEEEsingle())
   return S_IEEEsingle;
 else if (&Sem == &llvm::APFloat::IEEEdouble())
@@ -152,6 +157,

[PATCH] D78190: Add Bfloat IR type

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stuij added inline comments.



Comment at: llvm/include/llvm-c/Core.h:149
   LLVMHalfTypeKind,/**< 16 bit floating point type */
+  LLVMBfloatTypeKind,  /**< 16 bit brain floating point type */
   LLVMFloatTypeKind,   /**< 32 bit floating point type */

scanon wrote:
> Throughout this, I think `BFloat` would be more consistent with other types 
> than `Bfloat` is.
Agreed. I continued the convention of the bfloat C type patch, but it did 
subconsciously grate a bit. I capitalized it everywhere where the B is 
capitalized.


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[PATCH] D78190: Add Bfloat IR type

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Comment at: llvm/docs/LangRef.rst:2896
+   * - ``bfloat``
+ - 16-bit brain floating-point value (8-bit mantissa)
+

scanon wrote:
> rjmccall wrote:
> > rjmccall wrote:
> > > scanon wrote:
> > > > bfloat and fp128 should agree w.r.t. whether or not the implicit bit 
> > > > counts. Either 7 and 112 or 8 and 113. Also, we should use 
> > > > "significand" instead of "mantissa". "Mantissa" has slipped in in a 
> > > > bunch of places, but "significand" is the IEEE 754 terminology, and we 
> > > > should follow it.
> > > I agree with Steve.  In general, there's no reason for these descriptions 
> > > to be as terse as they are, especially for the non-standard formats.  
> > > Someone reading IR and seeing `bfloat` for the first time is going to 
> > > come here and not be any wiser unless they figure out the right web 
> > > search.
> > Hmm, now this reads more like a rationale than documentation.  I would 
> > suggest:
> > 
> > > 16-bit "brain" floating-point value (7-bit significand).  Provides the 
> > > same number of exponent bits as ``float``, so that it matches its dynamic 
> > > range, just with greatly reduced precision.  Used in Intel's AVX-512 BF16 
> > > extensions and ARM's ARMv8.6-A extensions, among others.
> Yup, I agree. The important thing here is that someone can figure out what it 
> is (the top half of a float); it's ok for them to have to do some reading to 
> figure out *why* it is.
Does look cleaner. Done.


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[PATCH] D78190: Add Bfloat IR type

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stuij updated this revision to Diff 260373.
stuij marked an inline comment as done.
stuij added a comment.

updated bfloat documentation as per comments


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Files:
  clang/lib/Sema/SemaOpenMP.cpp
  llvm/docs/BitCodeFormat.rst
  llvm/docs/LangRef.rst
  llvm/include/llvm-c/Core.h
  llvm/include/llvm/ADT/APFloat.h
  llvm/include/llvm/Bitcode/LLVMBitCodes.h
  llvm/include/llvm/IR/Constants.h
  llvm/include/llvm/IR/DataLayout.h
  llvm/include/llvm/IR/IRBuilder.h
  llvm/include/llvm/IR/Type.h
  llvm/lib/AsmParser/LLLexer.cpp
  llvm/lib/AsmParser/LLParser.cpp
  llvm/lib/Bitcode/Reader/BitcodeReader.cpp
  llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
  llvm/lib/CodeGen/MIRParser/MILexer.cpp
  llvm/lib/IR/AsmWriter.cpp
  llvm/lib/IR/Constants.cpp
  llvm/lib/IR/Core.cpp
  llvm/lib/IR/DataLayout.cpp
  llvm/lib/IR/Function.cpp
  llvm/lib/IR/LLVMContextImpl.cpp
  llvm/lib/IR/LLVMContextImpl.h
  llvm/lib/IR/Type.cpp
  llvm/lib/Support/APFloat.cpp
  llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/Assembler/bfloat.ll
  llvm/tools/llvm-c-test/echo.cpp

Index: llvm/tools/llvm-c-test/echo.cpp
===
--- llvm/tools/llvm-c-test/echo.cpp
+++ llvm/tools/llvm-c-test/echo.cpp
@@ -72,6 +72,8 @@
 return LLVMVoidTypeInContext(Ctx);
   case LLVMHalfTypeKind:
 return LLVMHalfTypeInContext(Ctx);
+  case LLVMBFloatTypeKind:
+return LLVMHalfTypeInContext(Ctx);
   case LLVMFloatTypeKind:
 return LLVMFloatTypeInContext(Ctx);
   case LLVMDoubleTypeKind:
Index: llvm/test/Assembler/bfloat.ll
===
--- /dev/null
+++ llvm/test/Assembler/bfloat.ll
@@ -0,0 +1,26 @@
+; RUN: llvm-as < %s | llvm-dis | FileCheck %s --check-prefix=ASSEM-DISASS
+; RUN: opt < %s -O3 -S | FileCheck %s --check-prefix=OPT
+; RUN: verify-uselistorder %s
+; Basic smoke tests for bfloat type.
+
+define bfloat @check_bfloat(bfloat %A) {
+; ASSEM-DISASS: ret bfloat %A
+ret bfloat %A
+}
+
+define bfloat @check_bfloat_literal() {
+; ASSEM-DISASS: ret bfloat 0xR3149
+ret bfloat 0xR3149
+}
+
+define bfloat @check_bfloat_constprop() {
+  %tmp = fadd bfloat 0xR40C0, 0xR40C0
+; OPT: 0xR4140
+  ret bfloat %tmp
+}
+
+define float @check_bfloat_convert() {
+  %tmp = fpext bfloat 0xR4C8D to float
+; OPT: 0x4191A000
+  ret float %tmp
+}
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -11460,8 +11460,9 @@
   MVT LogicVT = VT;
   if (EltVT == MVT::f32 || EltVT == MVT::f64) {
 Zero = DAG.getConstantFP(0.0, DL, EltVT);
-AllOnes = DAG.getConstantFP(
-APFloat::getAllOnesValue(EltVT.getSizeInBits(), true), DL, EltVT);
+APFloat AllOnesValue = APFloat::getAllOnesValue(
+SelectionDAG::EVTToAPFloatSemantics(EltVT), EltVT.getSizeInBits());
+AllOnes = DAG.getConstantFP(AllOnesValue, DL, EltVT);
 LogicVT =
 MVT::getVectorVT(EltVT == MVT::f64 ? MVT::i64 : MVT::i32, Mask.size());
   } else {
Index: llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
===
--- llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
+++ llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
@@ -323,6 +323,7 @@
   }
   case Type::FunctionTyID:
   case Type::VoidTyID:
+  case Type::BFloatTyID:
   case Type::X86_FP80TyID:
   case Type::FP128TyID:
   case Type::PPC_FP128TyID:
Index: llvm/lib/Support/APFloat.cpp
===
--- llvm/lib/Support/APFloat.cpp
+++ llvm/lib/Support/APFloat.cpp
@@ -69,6 +69,7 @@
   };
 
   static const fltSemantics semIEEEhalf = {15, -14, 11, 16};
+  static const fltSemantics semBFloat = {127, -126, 8, 16};
   static const fltSemantics semIEEEsingle = {127, -126, 24, 32};
   static const fltSemantics semIEEEdouble = {1023, -1022, 53, 64};
   static const fltSemantics semIEEEquad = {16383, -16382, 113, 128};
@@ -117,6 +118,8 @@
 switch (S) {
 case S_IEEEhalf:
   return IEEEhalf();
+case S_BFloat:
+  return BFloat();
 case S_IEEEsingle:
   return IEEEsingle();
 case S_IEEEdouble:
@@ -135,6 +138,8 @@
   APFloatBase::SemanticsToEnum(const llvm::fltSemantics &Sem) {
 if (&Sem == &llvm::APFloat::IEEEhalf())
   return S_IEEEhalf;
+else if (&Sem == &llvm::APFloat::BFloat())
+  return S_BFloat;
 else if (&Sem == &llvm::APFloat::IEEEsingle())
   return S_IEEEsingle;
 else if (&Sem == &llvm::APFloat::IEEEdouble())
@@ -152,6 +157,9 @@
   const fltSemantics &APFloatBase::IEEEhalf() {
 return semIEEEhalf;
   }
+  const fltSemantics &APFloatBase::BFloat() {
+return semBFloa

[PATCH] D76077: [ARM] Add __bf16 as new Bfloat16 C Type

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stuij updated this revision to Diff 261851.
stuij added a comment.

I've amended this patch to conform to the general Bfloat -> BFloat convention
changes requested in the dependent BFloat IR patch (D78190 
).

I also folded in two other downstream patches, which allow for the ?: operator
on bf16 values and prohibit conversions between integer and __bf16.


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Files:
  clang/docs/LanguageExtensions.rst
  clang/include/clang-c/Index.h
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/BuiltinTypes.def
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/Specifiers.h
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Sema/DeclSpec.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/Basic/TargetInfo.cpp
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/CodeGenTypeCache.h
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Format/FormatToken.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Parse/ParseDecl.cpp
  clang/lib/Parse/ParseExpr.cpp
  clang/lib/Parse/ParseExprCXX.cpp
  clang/lib/Parse/ParseTentative.cpp
  clang/lib/Sema/DeclSpec.cpp
  clang/lib/Sema/SemaCast.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/lib/Sema/SemaTemplateVariadic.cpp
  clang/lib/Sema/SemaType.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/CodeGen/arm-mangle-16bit-float.cpp
  clang/test/Sema/arm-bf16-forbidden-ops.c
  clang/test/Sema/arm-bf16-forbidden-ops.cpp
  clang/test/Sema/arm-bfloat.cpp
  clang/tools/libclang/CXType.cpp

Index: clang/tools/libclang/CXType.cpp
===
--- clang/tools/libclang/CXType.cpp
+++ clang/tools/libclang/CXType.cpp
@@ -608,6 +608,7 @@
 TKIND(Elaborated);
 TKIND(Pipe);
 TKIND(Attributed);
+TKIND(BFloat16);
 #define IMAGE_TYPE(ImgType, Id, SingletonId, Access, Suffix) TKIND(Id);
 #include "clang/Basic/OpenCLImageTypes.def"
 #undef IMAGE_TYPE
Index: clang/test/Sema/arm-bfloat.cpp
===
--- /dev/null
+++ clang/test/Sema/arm-bfloat.cpp
@@ -0,0 +1,29 @@
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple aarch64-arm-none-eabi -target-cpu cortex-a75 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple arm-arm-none-eabi -target-cpu cortex-a53 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+
+void test(bool b) {
+  __bf16 bf16;
+
+  bf16 + bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 - bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 * bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 / bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+
+  __fp16 fp16;
+
+  bf16 + fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 + bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 - fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 - bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 * fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 * bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 / fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 / bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 = fp16; // expected-error {{assigning to '__bf16' from incompatible type '__fp16'}}
+  fp16 = bf16; // expected-error {{assigning to '__fp16' from incompatible type '__bf16'}}
+  bf16 + (b ? fp16 : bf16); // expected-error {{incompatible operand types ('__fp16' and '__bf16')}}
+}
Index: clang/test/Sema/arm-bf16-forbidden-ops.cpp

[PATCH] D78190: Add Bfloat IR type

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stuij added a comment.

Hi all. Are you OK for me to commit this change?

It was about a week ago since we resolved the last outstanding issues, and in 
general it looks like our noses have been pointing in the same direction on 
this patch.


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[PATCH] D78190: Add Bfloat IR type

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stuij updated this revision to Diff 262122.
stuij added a comment.

added vector tests


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Files:
  clang/lib/Sema/SemaOpenMP.cpp
  llvm/docs/BitCodeFormat.rst
  llvm/docs/LangRef.rst
  llvm/include/llvm-c/Core.h
  llvm/include/llvm/ADT/APFloat.h
  llvm/include/llvm/Bitcode/LLVMBitCodes.h
  llvm/include/llvm/IR/Constants.h
  llvm/include/llvm/IR/DataLayout.h
  llvm/include/llvm/IR/IRBuilder.h
  llvm/include/llvm/IR/Type.h
  llvm/lib/AsmParser/LLLexer.cpp
  llvm/lib/AsmParser/LLParser.cpp
  llvm/lib/Bitcode/Reader/BitcodeReader.cpp
  llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
  llvm/lib/CodeGen/MIRParser/MILexer.cpp
  llvm/lib/IR/AsmWriter.cpp
  llvm/lib/IR/Constants.cpp
  llvm/lib/IR/Core.cpp
  llvm/lib/IR/DataLayout.cpp
  llvm/lib/IR/Function.cpp
  llvm/lib/IR/LLVMContextImpl.cpp
  llvm/lib/IR/LLVMContextImpl.h
  llvm/lib/IR/Type.cpp
  llvm/lib/Support/APFloat.cpp
  llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/Assembler/bfloat.ll
  llvm/tools/llvm-c-test/echo.cpp

Index: llvm/tools/llvm-c-test/echo.cpp
===
--- llvm/tools/llvm-c-test/echo.cpp
+++ llvm/tools/llvm-c-test/echo.cpp
@@ -72,6 +72,8 @@
 return LLVMVoidTypeInContext(Ctx);
   case LLVMHalfTypeKind:
 return LLVMHalfTypeInContext(Ctx);
+  case LLVMBFloatTypeKind:
+return LLVMHalfTypeInContext(Ctx);
   case LLVMFloatTypeKind:
 return LLVMFloatTypeInContext(Ctx);
   case LLVMDoubleTypeKind:
Index: llvm/test/Assembler/bfloat.ll
===
--- /dev/null
+++ llvm/test/Assembler/bfloat.ll
@@ -0,0 +1,38 @@
+; RUN: llvm-as < %s | llvm-dis | FileCheck %s --check-prefix=ASSEM-DISASS
+; RUN: opt < %s -O3 -S | FileCheck %s --check-prefix=OPT
+; RUN: verify-uselistorder %s
+; Basic smoke tests for bfloat type.
+
+define bfloat @check_bfloat(bfloat %A) {
+; ASSEM-DISASS: ret bfloat %A
+ret bfloat %A
+}
+
+define bfloat @check_bfloat_literal() {
+; ASSEM-DISASS: ret bfloat 0xR3149
+ret bfloat 0xR3149
+}
+
+define <4 x bfloat> @check_fixed_vector() {
+; ASSEM-DISASS: ret <4 x bfloat> %tmp
+  %tmp = fadd <4 x bfloat> undef, undef
+  ret <4 x bfloat> %tmp
+}
+
+define  @check_vector() {
+; ASSEM-DISASS: ret  %tmp
+  %tmp = fadd  undef, undef
+  ret  %tmp
+}
+
+define bfloat @check_bfloat_constprop() {
+  %tmp = fadd bfloat 0xR40C0, 0xR40C0
+; OPT: 0xR4140
+  ret bfloat %tmp
+}
+
+define float @check_bfloat_convert() {
+  %tmp = fpext bfloat 0xR4C8D to float
+; OPT: 0x4191A000
+  ret float %tmp
+}
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -11458,8 +11458,9 @@
   MVT LogicVT = VT;
   if (EltVT == MVT::f32 || EltVT == MVT::f64) {
 Zero = DAG.getConstantFP(0.0, DL, EltVT);
-AllOnes = DAG.getConstantFP(
-APFloat::getAllOnesValue(EltVT.getSizeInBits(), true), DL, EltVT);
+APFloat AllOnesValue = APFloat::getAllOnesValue(
+SelectionDAG::EVTToAPFloatSemantics(EltVT), EltVT.getSizeInBits());
+AllOnes = DAG.getConstantFP(AllOnesValue, DL, EltVT);
 LogicVT =
 MVT::getVectorVT(EltVT == MVT::f64 ? MVT::i64 : MVT::i32, Mask.size());
   } else {
Index: llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
===
--- llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
+++ llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
@@ -323,6 +323,7 @@
   }
   case Type::FunctionTyID:
   case Type::VoidTyID:
+  case Type::BFloatTyID:
   case Type::X86_FP80TyID:
   case Type::FP128TyID:
   case Type::PPC_FP128TyID:
Index: llvm/lib/Support/APFloat.cpp
===
--- llvm/lib/Support/APFloat.cpp
+++ llvm/lib/Support/APFloat.cpp
@@ -69,6 +69,7 @@
   };
 
   static const fltSemantics semIEEEhalf = {15, -14, 11, 16};
+  static const fltSemantics semBFloat = {127, -126, 8, 16};
   static const fltSemantics semIEEEsingle = {127, -126, 24, 32};
   static const fltSemantics semIEEEdouble = {1023, -1022, 53, 64};
   static const fltSemantics semIEEEquad = {16383, -16382, 113, 128};
@@ -117,6 +118,8 @@
 switch (S) {
 case S_IEEEhalf:
   return IEEEhalf();
+case S_BFloat:
+  return BFloat();
 case S_IEEEsingle:
   return IEEEsingle();
 case S_IEEEdouble:
@@ -135,6 +138,8 @@
   APFloatBase::SemanticsToEnum(const llvm::fltSemantics &Sem) {
 if (&Sem == &llvm::APFloat::IEEEhalf())
   return S_IEEEhalf;
+else if (&Sem == &llvm::APFloat::BFloat())
+  return S_BFloat;
 else if (&Sem == &llvm::APFloat::IEEEsingle())
   return S_IEEEsingle;
 else if (&Sem == &llvm:

[PATCH] D78190: Add Bfloat IR type

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stuij added a comment.

In D78190#2018685 , @fpetrogalli wrote:

> 1. Shouldn't we test also that the parser is happy with the following 
> expressions?


Added. Thanks.

> 2. Would it make sense to to split this patch into 2 separate patches? One 
> that defines the enums and interfaces for `bfloat`, and one that does the 
> actual parsing/emission in the IR? I suspect there is much intertwine going 
> on, so probably not - in that case, I am happy for everything to go via a 
> single patch.

Yes, the parts are a bit intertwined. There are some lines along which we can 
cut the patch, but I personally don't feel we'd gain enough clarity to justify 
the cost. It's not a very sexy patch in my opinion, just a number of places to 
add the new type to. Also, this is also a nice unit of functionality to be able 
to test against. And lastly, I think we already had a good number of eyes on 
this patch. It seems like a duplication of effort to have people again review 
the different parts.

> 3. Do you need those changes in the Hexagon and x86 backend? Could they be 
> submitted separately, with some testing?

This is a backend agnostic patch. If the Hexagon and/or x86 communities want to 
make use of the IR type in some way, then yes, they can for sure submit the 
necessary patches.


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[PATCH] D78190: Add Bfloat IR type

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stuij added a comment.

So are we happy with the patch as it is? Anybody else wants to LGTM?


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[PATCH] D78190: Add Bfloat IR type

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stuij added a comment.

In D78190#2020701 , @stuij wrote:

> In D78190#2018685 , @fpetrogalli 
> wrote:
>
> > 3. Do you need those changes in the Hexagon and x86 backend? Could they be 
> > submitted separately, with some testing?
>
>
> This is a backend agnostic patch. If the Hexagon and/or x86 communities want 
> to make use of the IR type in some way, then yes, they can for sure submit 
> the necessary patches.


Ah sorry, I misread your comment. You're talking about the hexagon/x86 changes 
in this patch. They're there because of interface changes: the x86 change is 
because of the getAllOnesValue arguments have changed. The hexagon one is there 
to squash a warning because we added the bfloat Type.


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[PATCH] D78190: Add Bfloat IR type

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stuij added a comment.

Hi there, a gentle ping: does this look good to you?


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[PATCH] D79708: [clangd][BFloat] add NEON emitter for bfloat

[Ties Stuij via Phabricator via cfe-commits]

stuij created this revision.
Herald added subscribers: cfe-commits, usaxena95, kadircet, arphaman, jkorous, 
MaskRay, ilya-biryukov, kristof.beyls, mgorny.
Herald added a project: clang.
stuij added a parent revision: D76077: [ARM] Add __bf16 as new Bfloat16 C Type.
stuij edited parent revisions, added: D79711: [ARM][BFloat] Add poly64_t on 
AArch32.; removed: D76077: [ARM] Add __bf16 as new Bfloat16 C Type.

This patch adds the bfloat16_t struct typedefs (e.g. bfloat16x8x2_t) to
arm_neon.h

This patch is part of a series implementing the Bfloat16 extension of the
Armv8.6-a architecture, as detailed here:

https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a

The bfloat type, and its properties is specified in the Arm C language
extension specification:

https://developer.arm.com/docs/ihi0055/d/procedure-call-standard-for-the-arm-64-bit-architecture


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D79708

Files:
  clang/include/clang/Basic/arm_bf16.td
  clang/include/clang/Basic/arm_neon_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/Preprocessor/aarch64-target-features.c
  clang/test/Preprocessor/arm-target-features.c
  clang/utils/TableGen/NeonEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -85,6 +85,7 @@
 
 void EmitNeon(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitFP16(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitBF16(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeonSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeonTest(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeon2(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -63,6 +63,7 @@
   GenClangOpenCLBuiltins,
   GenArmNeon,
   GenArmFP16,
+  GenArmBF16,
   GenArmNeonSema,
   GenArmNeonTest,
   GenArmMveHeader,
@@ -186,6 +187,7 @@
"Generate OpenCL builtin declaration handlers"),
 clEnumValN(GenArmNeon, "gen-arm-neon", "Generate arm_neon.h for clang"),
 clEnumValN(GenArmFP16, "gen-arm-fp16", "Generate arm_fp16.h for clang"),
+clEnumValN(GenArmBF16, "gen-arm-bf16", "Generate arm_bf16.h for clang"),
 clEnumValN(GenArmNeonSema, "gen-arm-neon-sema",
"Generate ARM NEON sema support for clang"),
 clEnumValN(GenArmNeonTest, "gen-arm-neon-test",
@@ -360,6 +362,9 @@
   case GenArmFP16:
 EmitFP16(Records, OS);
 break;
+  case GenArmBF16:
+EmitBF16(Records, OS);
+break;
   case GenArmNeonSema:
 EmitNeonSema(Records, OS);
 break;
Index: clang/utils/TableGen/NeonEmitter.cpp
===
--- clang/utils/TableGen/NeonEmitter.cpp
+++ clang/utils/TableGen/NeonEmitter.cpp
@@ -99,7 +99,8 @@
   Poly128,
   Float16,
   Float32,
-  Float64
+  Float64,
+  BFloat16
 };
 
 } // end namespace NeonTypeFlags
@@ -147,6 +148,7 @@
 SInt,
 UInt,
 Poly,
+BFloat16,
   };
   TypeKind Kind;
   bool Immediate, Constant, Pointer;
@@ -199,6 +201,7 @@
   bool isInt() const { return isInteger() && ElementBitwidth == 32; }
   bool isLong() const { return isInteger() && ElementBitwidth == 64; }
   bool isVoid() const { return Kind == Void; }
+  bool isBFloat16() const { return Kind == BFloat16; }
   unsigned getNumElements() const { return Bitwidth / ElementBitwidth; }
   unsigned getSizeInBits() const { return Bitwidth; }
   unsigned getElementSizeInBits() const { return ElementBitwidth; }
@@ -585,8 +588,11 @@
   // runFP16 - Emit arm_fp16.h.inc
   void runFP16(raw_ostream &o);
 
-  // runHeader - Emit all the __builtin prototypes used in arm_neon.h
-	// and arm_fp16.h
+  // runBF16 - Emit arm_bf16.h.inc
+  void runBF16(raw_ostream &o);
+
+  // runHeader - Emit all the __builtin prototypes used in arm_neon.h,
+  // arm_fp16.h and arm_bf16.h
   void runHeader(raw_ostream &o);
 
   // runTests - Emit tests for all the Neon intrinsics.
@@ -611,12 +617,15 @@
 S += "poly";
   else if (isFloating())
 S += "float";
+  else if (isBFloat16())
+S += "bfloat";
   else
 S += "int";
 
   S += utostr(ElementBitwidth);
   if (isVector())
 S += "x" + utostr(getNumElements());
+
   if (NumVectors > 1)
 S += "x" + utostr(NumVectors);
   S += "_t";
@@ -650,7 +659,10 @@
 case 128: S += "LLLi"; break;
 default: llvm_unreachable("Unhandled case!");
 }
-  else
+  else if (isBFloat16()) {
+assert(ElementBitwidth == 

[PATCH] D79710: [clangd][BFloat] add create/set/get/dup intrinsics

[Ties Stuij via Phabricator via cfe-commits]

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Herald added a project: clang.

This patch is part of a series that adds support for the Bfloat16 extension of
the Armv8.6-a architecture, as detailed here:

https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a

The bfloat type, and its properties is specified in the Arm C language extension
specification:

https://developer.arm.com/docs/ihi0055/d/procedure-call-standard-for-the-arm-64-bit-architecture


Repository:
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Files:
  clang/include/clang/Basic/arm_neon.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-bf16-getset-intrinsics.c

Index: clang/test/CodeGen/aarch64-bf16-getset-intrinsics.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-bf16-getset-intrinsics.c
@@ -0,0 +1,120 @@
+// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +neon -target-feature +bf16 \
+// RUN:  -O2 -fallow-half-arguments-and-returns -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK64
+// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi hard \
+// RUN:  -O2 -fallow-half-arguments-and-returns -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK32
+
+#include 
+
+bfloat16x4_t test_vcreate_bf16(uint64_t a) {
+  return vcreate_bf16(a);
+}
+// CHECK-LABEL: test_vcreate_bf16
+// CHECK64: %0 = bitcast i64 %a to <4 x bfloat>
+// CHECK32: %0 = bitcast i64 %a to <4 x bfloat>
+
+bfloat16x4_t test_vdup_n_bf16(bfloat16_t v) {
+  return vdup_n_bf16(v);
+}
+// CHECK-LABEL: test_vdup_n_bf16
+// CHECK64: %vecinit.i = insertelement <4 x bfloat> undef, bfloat %v, i32 0
+// CHECK32: %vecinit.i = insertelement <4 x bfloat> undef, bfloat %v, i32 0
+// CHECK: %vecinit{{.*}} = shufflevector <4 x bfloat> %vecinit.i, <4 x bfloat> undef, <4 x i32> zeroinitializer
+
+bfloat16x8_t test_vdupq_n_bf16(bfloat16_t v) {
+  return vdupq_n_bf16(v);
+}
+// CHECK-LABEL: test_vdupq_n_bf16
+// CHECK64: %vecinit.i = insertelement <8 x bfloat> undef, bfloat %v, i32 0
+// CHECK32: %vecinit.i = insertelement <8 x bfloat> undef, bfloat %v, i32 0
+// CHECK:   %vecinit{{.*}} = shufflevector <8 x bfloat> %vecinit.i, <8 x bfloat> undef, <8 x i32> zeroinitializer
+
+bfloat16x4_t test_vdup_lane_bf16(bfloat16x4_t v) {
+  return vdup_lane_bf16(v, 1);
+}
+// CHECK-LABEL: test_vdup_lane_bf16
+// CHECK64: %lane = shufflevector <4 x bfloat> %v, <4 x bfloat> undef, <4 x i32> 
+// CHECK32: %lane = shufflevector <4 x bfloat> %v, <4 x bfloat> undef, <4 x i32> 
+
+bfloat16x8_t test_vdupq_lane_bf16(bfloat16x4_t v) {
+  return vdupq_lane_bf16(v, 1);
+}
+// CHECK-LABEL: test_vdupq_lane_bf16
+// CHECK64: %lane = shufflevector <4 x bfloat> %v, <4 x bfloat> undef, <8 x i32> 
+// CHECK32: %lane = shufflevector <4 x bfloat> %v, <4 x bfloat> undef, <8 x i32> 
+
+bfloat16x4_t test_vdup_laneq_bf16(bfloat16x8_t v) {
+  return vdup_laneq_bf16(v, 7);
+}
+// CHECK-LABEL: test_vdup_laneq_bf16
+// CHECK64: %lane = shufflevector <8 x bfloat> %v, <8 x bfloat> undef, <4 x i32> 
+// CHECK32: %lane = shufflevector <8 x bfloat> %v, <8 x bfloat> undef, <4 x i32> 
+
+bfloat16x8_t test_vdupq_laneq_bf16(bfloat16x8_t v) {
+  return vdupq_laneq_bf16(v, 7);
+}
+// CHECK-LABEL: test_vdupq_laneq_bf16
+// CHECK64: %lane = shufflevector <8 x bfloat> %v, <8 x bfloat> undef, <8 x i32> 
+// CHECK32: %lane = shufflevector <8 x bfloat> %v, <8 x bfloat> undef, <8 x i32> 
+
+bfloat16x8_t test_vcombine_bf16(bfloat16x4_t low, bfloat16x4_t high) {
+  return vcombine_bf16(low, high);
+}
+// CHECK-LABEL: test_vcombine_bf16
+// CHECK64: %shuffle.i = shufflevector <4 x bfloat> %low, <4 x bfloat> %high, <8 x i32> 
+// CHECK32: %shuffle.i = shufflevector <4 x bfloat> %low, <4 x bfloat> %high, <8 x i32> 
+
+bfloat16x4_t test_vget_high_bf16(bfloat16x8_t a) {
+  return vget_high_bf16(a);
+}
+// CHECK-LABEL: test_vget_high_bf16
+// CHECK64: %shuffle.i = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> 
+// CHECK32: %shuffle.i = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> 
+
+bfloat16x4_t test_vget_low_bf16(bfloat16x8_t a) {
+  return vget_low_bf16(a);
+}
+// CHECK-LABEL: test_vget_low_bf16
+// CHECK64: %shuffle.i = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> 
+// CHECK32: %shuffle.i = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> 
+
+bfloat16_t test_vget_lane_bf16(bfloat16x4_t v) {
+  return vget_lane_bf16(v, 1);
+}
+// CHECK-LABEL: test_vget_lane_bf16
+// CHECK64: %vget_lane = extractelement <4 x bfloat> %v, i32 1
+// CHECK32: %vget_lane = extractelement <4 x bfloat> %v, i32 1
+
+bfloat16_t test_vgetq_lane_bf16(bfloat16x8_t v) {
+  return vgetq_lane_bf16(v, 7);
+}
+// CHECK-LABEL: test_vgetq_lane_bf16
+// CHECK64: %vgetq_lane = extracteleme

[PATCH] D79711: [ARM][BFloat] Add poly64_t on AArch32.

[Ties Stuij via Phabricator via cfe-commits]

stuij created this revision.
Herald added subscribers: cfe-commits, danielkiss, kristof.beyls.
Herald added a project: clang.
stuij added a parent revision: D76077: [ARM] Add __bf16 as new Bfloat16 C Type.
stuij added a child revision: D79708: [clangd][BFloat] add NEON emitter for 
bfloat.

The poly64 types are guarded with ifdefs for AArch64 only. This is wrong. This
was also incorrectly documented in the ACLE spec, but this has been rectified in
the latest release. See paragraph 13.1.2 "Vector data types":

https://developer.arm.com/docs/101028/latest


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D79711

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/Sema/SemaType.cpp
  clang/utils/TableGen/NeonEmitter.cpp


Index: clang/utils/TableGen/NeonEmitter.cpp
===
--- clang/utils/TableGen/NeonEmitter.cpp
+++ clang/utils/TableGen/NeonEmitter.cpp
@@ -2235,6 +2235,7 @@
   OS << "#else\n";
   OS << "typedef int8_t poly8_t;\n";
   OS << "typedef int16_t poly16_t;\n";
+  OS << "typedef int64_t poly64_t;\n";
   OS << "#endif\n";
 
   // Emit Neon vector typedefs.
@@ -2247,7 +2248,7 @@
   for (auto &TS : TDTypeVec) {
 bool IsA64 = false;
 Type T(TS, ".");
-if (T.isDouble() || (T.isPoly() && T.getElementSizeInBits() == 64))
+if (T.isDouble())
   IsA64 = true;
 
 if (InIfdef && !IsA64) {
@@ -2280,7 +2281,7 @@
 for (auto &TS : TDTypeVec) {
   bool IsA64 = false;
   Type T(TS, ".");
-  if (T.isDouble() || (T.isPoly() && T.getElementSizeInBits() == 64))
+  if (T.isDouble())
 IsA64 = true;
 
   if (InIfdef && !IsA64) {
Index: clang/lib/Sema/SemaType.cpp
===
--- clang/lib/Sema/SemaType.cpp
+++ clang/lib/Sema/SemaType.cpp
@@ -7552,15 +7552,16 @@
 Triple.getArch() == llvm::Triple::aarch64_be;
   if (VecKind == VectorType::NeonPolyVector) {
 if (IsPolyUnsigned) {
-  // AArch64 polynomial vectors are unsigned and support poly64.
+  // AArch64 polynomial vectors are unsigned.
   return BTy->getKind() == BuiltinType::UChar ||
  BTy->getKind() == BuiltinType::UShort ||
  BTy->getKind() == BuiltinType::ULong ||
  BTy->getKind() == BuiltinType::ULongLong;
 } else {
-  // AArch32 polynomial vector are signed.
+  // AArch32 polynomial vectors are signed.
   return BTy->getKind() == BuiltinType::SChar ||
- BTy->getKind() == BuiltinType::Short;
+ BTy->getKind() == BuiltinType::Short ||
+ BTy->getKind() == BuiltinType::LongLong;
 }
   }
 
Index: clang/lib/AST/ItaniumMangle.cpp
===
--- clang/lib/AST/ItaniumMangle.cpp
+++ clang/lib/AST/ItaniumMangle.cpp
@@ -3165,6 +3165,7 @@
 case BuiltinType::UShort:
   EltName = "poly16_t";
   break;
+case BuiltinType::LongLong:
 case BuiltinType::ULongLong:
   EltName = "poly64_t";
   break;
Index: clang/include/clang/Basic/TargetBuiltins.h
===
--- clang/include/clang/Basic/TargetBuiltins.h
+++ clang/include/clang/Basic/TargetBuiltins.h
@@ -157,7 +157,7 @@
 EltType getEltType() const { return (EltType)(Flags & EltTypeMask); }
 bool isPoly() const {
   EltType ET = getEltType();
-  return ET == Poly8 || ET == Poly16;
+  return ET == Poly8 || ET == Poly16 || ET == Poly64;
 }
 bool isUnsigned() const { return (Flags & UnsignedFlag) != 0; }
 bool isQuad() const { return (Flags & QuadFlag) != 0; }


Index: clang/utils/TableGen/NeonEmitter.cpp
===
--- clang/utils/TableGen/NeonEmitter.cpp
+++ clang/utils/TableGen/NeonEmitter.cpp
@@ -2235,6 +2235,7 @@
   OS << "#else\n";
   OS << "typedef int8_t poly8_t;\n";
   OS << "typedef int16_t poly16_t;\n";
+  OS << "typedef int64_t poly64_t;\n";
   OS << "#endif\n";
 
   // Emit Neon vector typedefs.
@@ -2247,7 +2248,7 @@
   for (auto &TS : TDTypeVec) {
 bool IsA64 = false;
 Type T(TS, ".");
-if (T.isDouble() || (T.isPoly() && T.getElementSizeInBits() == 64))
+if (T.isDouble())
   IsA64 = true;
 
 if (InIfdef && !IsA64) {
@@ -2280,7 +2281,7 @@
 for (auto &TS : TDTypeVec) {
   bool IsA64 = false;
   Type T(TS, ".");
-  if (T.isDouble() || (T.isPoly() && T.getElementSizeInBits() == 64))
+  if (T.isDouble())
 IsA64 = true;
 
   if (InIfdef && !IsA64) {
Index: clang/lib/Sema/SemaType.cpp
===
--- clang/lib/Sema/SemaType.cpp
+++ clang/lib/Sema/SemaType.cpp
@@ -7552,15 +7552,16 @@
 Triple.getArch() == llvm::Triple::aarch64_be;
   if (VecKind == VectorType::NeonPolyVector) {
 if (IsPolyUnsigned) {
-  // AA

[PATCH] D76077: [ARM] Add __bf16 as new Bfloat16 C Type

[Ties Stuij via Phabricator via cfe-commits]

stuij marked 2 inline comments as done.
stuij added a comment.

@asmith: Thanks for reviewing :) Fixed your suggestions in the coming revision.




Comment at: clang/include/clang/AST/ASTContext.h:965
   CanQualType HalfTy; // [OpenCL 6.1.1.1], ARM NEON
+  CanQualType BFloat16Ty; // ARM NEON
   CanQualType Float16Ty; // C11 extension ISO/IEC TS 18661-3

asmith wrote:
> Maybe the comment is unnecessary. I can imagine other targets besides ARM 
> NEON using BFloat
fair



Comment at: clang/include/clang/AST/Type.h:1982
   bool isFloat16Type() const;  // C11 extension ISO/IEC TS 18661
+  bool isBFloat16Type() const; // ARM BFloat
   bool isFloat128Type() const;

asmith wrote:
> don't think this comment adds anything
> 
fair


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[PATCH] D76077: [ARM] Add __bf16 as new Bfloat16 C Type

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 263719.
stuij added a comment.

changes:

- addressed asmith's comments
- Bfloat doesn't depend on half cmdline options and correct code is generation 
for AArch32 hard and softfp CC


Repository:
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https://reviews.llvm.org/D76077

Files:
  clang/docs/LanguageExtensions.rst
  clang/include/clang-c/Index.h
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/BuiltinTypes.def
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/Specifiers.h
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Sema/DeclSpec.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/Basic/TargetInfo.cpp
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/CodeGenTypeCache.h
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Format/FormatToken.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Parse/ParseDecl.cpp
  clang/lib/Parse/ParseExpr.cpp
  clang/lib/Parse/ParseExprCXX.cpp
  clang/lib/Parse/ParseTentative.cpp
  clang/lib/Sema/DeclSpec.cpp
  clang/lib/Sema/SemaCast.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/lib/Sema/SemaTemplateVariadic.cpp
  clang/lib/Sema/SemaType.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/CodeGen/arm-bf16-params-returns.c
  clang/test/CodeGen/arm-mangle-16bit-float.cpp
  clang/test/Sema/arm-bf16-forbidden-ops.c
  clang/test/Sema/arm-bf16-forbidden-ops.cpp
  clang/test/Sema/arm-bfloat.cpp
  clang/tools/libclang/CXType.cpp

Index: clang/tools/libclang/CXType.cpp
===
--- clang/tools/libclang/CXType.cpp
+++ clang/tools/libclang/CXType.cpp
@@ -608,6 +608,7 @@
 TKIND(Elaborated);
 TKIND(Pipe);
 TKIND(Attributed);
+TKIND(BFloat16);
 #define IMAGE_TYPE(ImgType, Id, SingletonId, Access, Suffix) TKIND(Id);
 #include "clang/Basic/OpenCLImageTypes.def"
 #undef IMAGE_TYPE
Index: clang/test/Sema/arm-bfloat.cpp
===
--- /dev/null
+++ clang/test/Sema/arm-bfloat.cpp
@@ -0,0 +1,29 @@
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple aarch64-arm-none-eabi -target-cpu cortex-a75 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple arm-arm-none-eabi -target-cpu cortex-a53 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+
+void test(bool b) {
+  __bf16 bf16;
+
+  bf16 + bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 - bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 * bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 / bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+
+  __fp16 fp16;
+
+  bf16 + fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 + bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 - fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 - bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 * fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 * bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 / fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 / bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 = fp16; // expected-error {{assigning to '__bf16' from incompatible type '__fp16'}}
+  fp16 = bf16; // expected-error {{assigning to '__fp16' from incompatible type '__bf16'}}
+  bf16 + (b ? fp16 : bf16); // expected-error {{incompatible operand types ('__fp16' and '__bf16')}}
+}
Index: clang/test/Sema/arm-bf16-forbidden-ops.cpp
===
--- /dev/null
+++ clang/test/Sema/arm-bf16-forbidden-ops.cpp
@@ -0,0 +1,71 @@
+// RU

[PATCH] D79869: [clangd][BFloat] Add reinterpret cast intrinsics

[Ties Stuij via Phabricator via cfe-commits]

stuij created this revision.
Herald added subscribers: cfe-commits, usaxena95, kadircet, arphaman, jkorous, 
MaskRay, ilya-biryukov, kristof.beyls.
Herald added a project: clang.

This patch is part of a series implementing the Bfloat16 extension of the
Armv8.6-a architecture, as detailed here:

https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a

The bfloat type, and its properties is specified in the Arm C language
extension specification:

https://developer.arm.com/docs/ihi0055/d/procedure-call-standard-for-the-arm-64-bit-architecture


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D79869

Files:
  clang/include/clang/Basic/arm_neon.td
  clang/include/clang/Basic/arm_neon_incl.td
  clang/test/CodeGen/aarch64-bf16-reinterpret-intrinsics.c
  clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
  clang/utils/TableGen/NeonEmitter.cpp

Index: clang/utils/TableGen/NeonEmitter.cpp
===
--- clang/utils/TableGen/NeonEmitter.cpp
+++ clang/utils/TableGen/NeonEmitter.cpp
@@ -313,7 +313,7 @@
   /// The unmangled name.
   std::string Name;
   /// The input and output typespecs. InTS == OutTS except when
-  /// CartesianProductOfTypes is 1 - this is the case for vreinterpret.
+  /// CartesianProductWith is non-empty - this is the case for vreinterpret.
   TypeSpec OutTS, InTS;
   /// The base class kind. Most intrinsics use ClassS, which has full type
   /// info for integers (s32/u32). Some use ClassI, which doesn't care about
@@ -346,7 +346,7 @@
   /// The set of intrinsics that this intrinsic uses/requires.
   std::set Dependencies;
   /// The "base type", which is Type('d', OutTS). InBaseType is only
-  /// different if CartesianProductOfTypes = 1 (for vreinterpret).
+  /// different if CartesianProductWith is non-empty (for vreinterpret).
   Type BaseType, InBaseType;
   /// The return variable.
   Variable RetVar;
@@ -1939,10 +1939,10 @@
   std::string Proto = std::string(R->getValueAsString("Prototype"));
   std::string Types = std::string(R->getValueAsString("Types"));
   Record *OperationRec = R->getValueAsDef("Operation");
-  bool CartesianProductOfTypes = R->getValueAsBit("CartesianProductOfTypes");
   bool BigEndianSafe  = R->getValueAsBit("BigEndianSafe");
   std::string Guard = std::string(R->getValueAsString("ArchGuard"));
   bool IsUnavailable = OperationRec->getValueAsBit("Unavailable");
+  std::string CartesianProductWith = std::string(R->getValueAsString("CartesianProductWith"));
 
   // Set the global current record. This allows assert_with_loc to produce
   // decent location information even when highly nested.
@@ -1957,17 +1957,20 @@
 CK = ClassMap[R->getSuperClasses()[1].first];
 
   std::vector> NewTypeSpecs;
-  for (auto TS : TypeSpecs) {
-if (CartesianProductOfTypes) {
+  if (!CartesianProductWith.empty()) {
+std::vector ProductTypeSpecs = TypeSpec::fromTypeSpecs(CartesianProductWith);
+for (auto TS : TypeSpecs) {
   Type DefaultT(TS, ".");
-  for (auto SrcTS : TypeSpecs) {
+  for (auto SrcTS : ProductTypeSpecs) {
 Type DefaultSrcT(SrcTS, ".");
 if (TS == SrcTS ||
 DefaultSrcT.getSizeInBits() != DefaultT.getSizeInBits())
   continue;
 NewTypeSpecs.push_back(std::make_pair(TS, SrcTS));
   }
-} else {
+}
+  } else {
+for (auto TS : TypeSpecs) {
   NewTypeSpecs.push_back(std::make_pair(TS, TS));
 }
   }
Index: clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
===
--- /dev/null
+++ clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
@@ -0,0 +1,314 @@
+// RUN: %clang_cc1 -triple armv8.2a-arm-none-eabi -target-feature +neon -target-feature +bf16 \
+// RUN: -disable-O0-optnone -S -emit-llvm -o - %s \
+// RUN: | opt -S -instcombine \
+// RUN: | FileCheck %s
+
+// REQUIRES: arm-registered-target
+
+#include 
+
+// CHECK-LABEL: @test_vreinterpret_bf16_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <8 x i8> [[A:%.*]] to <4 x bfloat>
+// CHECK-NEXT:ret <4 x bfloat> [[TMP0]]
+//
+bfloat16x4_t test_vreinterpret_bf16_s8(int8x8_t a)  { return vreinterpret_bf16_s8(a);}
+// CHECK-LABEL: @test_vreinterpret_bf16_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <4 x i16> [[A:%.*]] to <4 x bfloat>
+// CHECK-NEXT:ret <4 x bfloat> [[TMP0]]
+//
+bfloat16x4_t test_vreinterpret_bf16_s16(int16x4_t a){ return vreinterpret_bf16_s16(a);   }
+// CHECK-LABEL: @test_vreinterpret_bf16_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <2 x i32> [[A:%.*]] to <4 x bfloat>
+// CHECK-NEXT:ret <4 x bfloat> [[A:%.*]]
+//
+bfloat16x4_t test_vreinterpret_bf16_s32(int32x2_t a){ return vreinterpret_bf16_s32(a);   }
+// CHECK-LABEL: @test_vreinterpret_bf16_f32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <2 x f

[PATCH] D78190: Add Bfloat IR type

[Ties Stuij via Phabricator via cfe-commits]

This revision was not accepted when it landed; it landed in state "Needs 
Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8c24f33158d8: [IR][BFloat] Add BFloat IR type (authored by 
stuij).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78190/new/

https://reviews.llvm.org/D78190

Files:
  clang/lib/Sema/SemaOpenMP.cpp
  llvm/docs/BitCodeFormat.rst
  llvm/docs/LangRef.rst
  llvm/include/llvm-c/Core.h
  llvm/include/llvm/ADT/APFloat.h
  llvm/include/llvm/Bitcode/LLVMBitCodes.h
  llvm/include/llvm/IR/Constants.h
  llvm/include/llvm/IR/DataLayout.h
  llvm/include/llvm/IR/IRBuilder.h
  llvm/include/llvm/IR/Type.h
  llvm/lib/AsmParser/LLLexer.cpp
  llvm/lib/AsmParser/LLParser.cpp
  llvm/lib/Bitcode/Reader/BitcodeReader.cpp
  llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
  llvm/lib/CodeGen/MIRParser/MILexer.cpp
  llvm/lib/IR/AsmWriter.cpp
  llvm/lib/IR/Constants.cpp
  llvm/lib/IR/Core.cpp
  llvm/lib/IR/DataLayout.cpp
  llvm/lib/IR/Function.cpp
  llvm/lib/IR/LLVMContextImpl.cpp
  llvm/lib/IR/LLVMContextImpl.h
  llvm/lib/IR/Type.cpp
  llvm/lib/Support/APFloat.cpp
  llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/Assembler/bfloat.ll
  llvm/tools/llvm-c-test/echo.cpp

Index: llvm/tools/llvm-c-test/echo.cpp
===
--- llvm/tools/llvm-c-test/echo.cpp
+++ llvm/tools/llvm-c-test/echo.cpp
@@ -72,6 +72,8 @@
 return LLVMVoidTypeInContext(Ctx);
   case LLVMHalfTypeKind:
 return LLVMHalfTypeInContext(Ctx);
+  case LLVMBFloatTypeKind:
+return LLVMHalfTypeInContext(Ctx);
   case LLVMFloatTypeKind:
 return LLVMFloatTypeInContext(Ctx);
   case LLVMDoubleTypeKind:
Index: llvm/test/Assembler/bfloat.ll
===
--- /dev/null
+++ llvm/test/Assembler/bfloat.ll
@@ -0,0 +1,38 @@
+; RUN: llvm-as < %s | llvm-dis | FileCheck %s --check-prefix=ASSEM-DISASS
+; RUN: opt < %s -O3 -S | FileCheck %s --check-prefix=OPT
+; RUN: verify-uselistorder %s
+; Basic smoke tests for bfloat type.
+
+define bfloat @check_bfloat(bfloat %A) {
+; ASSEM-DISASS: ret bfloat %A
+ret bfloat %A
+}
+
+define bfloat @check_bfloat_literal() {
+; ASSEM-DISASS: ret bfloat 0xR3149
+ret bfloat 0xR3149
+}
+
+define <4 x bfloat> @check_fixed_vector() {
+; ASSEM-DISASS: ret <4 x bfloat> %tmp
+  %tmp = fadd <4 x bfloat> undef, undef
+  ret <4 x bfloat> %tmp
+}
+
+define  @check_vector() {
+; ASSEM-DISASS: ret  %tmp
+  %tmp = fadd  undef, undef
+  ret  %tmp
+}
+
+define bfloat @check_bfloat_constprop() {
+  %tmp = fadd bfloat 0xR40C0, 0xR40C0
+; OPT: 0xR4140
+  ret bfloat %tmp
+}
+
+define float @check_bfloat_convert() {
+  %tmp = fpext bfloat 0xR4C8D to float
+; OPT: 0x4191A000
+  ret float %tmp
+}
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -11526,8 +11526,9 @@
   MVT LogicVT = VT;
   if (EltVT == MVT::f32 || EltVT == MVT::f64) {
 Zero = DAG.getConstantFP(0.0, DL, EltVT);
-AllOnes = DAG.getConstantFP(
-APFloat::getAllOnesValue(EltVT.getSizeInBits(), true), DL, EltVT);
+APFloat AllOnesValue = APFloat::getAllOnesValue(
+SelectionDAG::EVTToAPFloatSemantics(EltVT), EltVT.getSizeInBits());
+AllOnes = DAG.getConstantFP(AllOnesValue, DL, EltVT);
 LogicVT =
 MVT::getVectorVT(EltVT == MVT::f64 ? MVT::i64 : MVT::i32, Mask.size());
   } else {
Index: llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
===
--- llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
+++ llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
@@ -323,6 +323,7 @@
   }
   case Type::FunctionTyID:
   case Type::VoidTyID:
+  case Type::BFloatTyID:
   case Type::X86_FP80TyID:
   case Type::FP128TyID:
   case Type::PPC_FP128TyID:
Index: llvm/lib/Support/APFloat.cpp
===
--- llvm/lib/Support/APFloat.cpp
+++ llvm/lib/Support/APFloat.cpp
@@ -69,6 +69,7 @@
   };
 
   static const fltSemantics semIEEEhalf = {15, -14, 11, 16};
+  static const fltSemantics semBFloat = {127, -126, 8, 16};
   static const fltSemantics semIEEEsingle = {127, -126, 24, 32};
   static const fltSemantics semIEEEdouble = {1023, -1022, 53, 64};
   static const fltSemantics semIEEEquad = {16383, -16382, 113, 128};
@@ -117,6 +118,8 @@
 switch (S) {
 case S_IEEEhalf:
   return IEEEhalf();
+case S_BFloat:
+  return BFloat();
 case S_IEEEsingle:
   return IEEEsingle();
 case S_IEEEdouble:
@@ -135,6 +138,8 @@
   APFloatBase::SemanticsToEnum(const llvm::fltSemantics &Sem) {
 if (&Sem == &llvm::APFloat::IEEEhalf())
   return S_IEEEhalf;
+else if (&Sem == &l

[PATCH] D76077: [ARM] Add __bf16 as new Bfloat16 C Type

[Ties Stuij via Phabricator via cfe-commits]

stuij marked 4 inline comments as done.
stuij added a comment.

@LukeGeeson: you're already mentioned :) See the commits tab on this review. 
But Simon Tatham needs a mention as well. I shall add him.




Comment at: clang/docs/LanguageExtensions.rst:518
+Clang supports three half-precision (16-bit) floating point types: ``__fp16``,
+``_Float16`` and ``__bf16``.  These types are supported in all language modes.
 

SjoerdMeijer wrote:
> Not my field of expertise, and sorry if I've missed this somewhere, but was 
> wondering if this (i.e. all language modes) means we need C++ name mangling 
> support for bfloat? In the AArch64 backend I saw this:
> 
>   getBFloat16Mangling() const override { return "u6__bf16"; }
> 
> But that's something else I guess, and I was guessing a 2 letter mangling 
> needs to be added here?
> 
> https://itanium-cxx-abi.github.io/cxx-abi/abi.html#mangling-builtin
Yes, we need name-mangling support, and yes that method you mentioned does 
that. There's one for AArch32 as well. And yes we have documented it in the 
'C++ ABI for the latest Arm Architecture' docs:

aarch32: https://developer.arm.com/docs/ihi0041/latest
aarch64: https://developer.arm.com/docs/ihi0059/latest



Comment at: clang/include/clang-c/Index.h:3254
   CXType_FirstBuiltin = CXType_Void,
   CXType_LastBuiltin = CXType_ULongAccum,
 

majnemer wrote:
> Should this be:
>   CXType_LastBuiltin = CXType_BFloat16,
> 
thanks



Comment at: clang/lib/AST/ItaniumMangle.cpp:3186
+case BuiltinType::Half:  EltName = "float16_t"; break;
+case BuiltinType::BFloat16:  EltName = "bfloat16x1_t"; break;
 default:

majnemer wrote:
> Why is this x1?
Yes, that does look odd. The original author of this code has left the company, 
but I'll ask around.



Comment at: clang/lib/Sema/SemaOverload.cpp:1873-1874
 // We of course allow this conversion if long double is really double.
+if (FromType == S.Context.BFloat16Ty || ToType == S.Context.BFloat16Ty)
+  return false;
 if (&S.Context.getFloatTypeSemantics(FromType) !=

majnemer wrote:
> This probably needs an explanation.
done


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D76077



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[PATCH] D76077: [ARM] Add __bf16 as new Bfloat16 C Type

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 264560.
stuij added a comment.

addressing review comments and adding Simon Tatham to contributers


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76077/new/

https://reviews.llvm.org/D76077

Files:
  clang/include/clang/Basic/arm_neon.td


Index: clang/include/clang/Basic/arm_neon.td
===
--- clang/include/clang/Basic/arm_neon.td
+++ clang/include/clang/Basic/arm_neon.td
@@ -247,6 +247,12 @@

"UcUsUicsilPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUlhdQhQdPlQPl"> {
   let isLaneQ = 1;
 }
+let ArchGuard = "defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC)" in {
+  def SPLAT_BF  : WInst<"splat_lane", ".(!q)I", "bQb">;
+  def SPLATQ_BF : WInst<"splat_laneq", ".(!Q)I", "bQb"> {
+let isLaneQ = 1;
+  }
+}
 
 
//===--===//
 // Intrinsics


Index: clang/include/clang/Basic/arm_neon.td
===
--- clang/include/clang/Basic/arm_neon.td
+++ clang/include/clang/Basic/arm_neon.td
@@ -247,6 +247,12 @@
"UcUsUicsilPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUlhdQhQdPlQPl"> {
   let isLaneQ = 1;
 }
+let ArchGuard = "defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC)" in {
+  def SPLAT_BF  : WInst<"splat_lane", ".(!q)I", "bQb">;
+  def SPLATQ_BF : WInst<"splat_laneq", ".(!Q)I", "bQb"> {
+let isLaneQ = 1;
+  }
+}
 
 //===--===//
 // Intrinsics
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[PATCH] D76077: [ARM] Add __bf16 as new Bfloat16 C Type

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 264562.
stuij added a comment.

redo: addressing review comments and adding Simon Tatham to contributers


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76077/new/

https://reviews.llvm.org/D76077

Files:
  clang/docs/LanguageExtensions.rst
  clang/include/clang-c/Index.h
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/BuiltinTypes.def
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/Specifiers.h
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/TargetInfo.h
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Sema/DeclSpec.h
  clang/include/clang/Serialization/ASTBitCodes.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/AST/NSAPI.cpp
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypeLoc.cpp
  clang/lib/Basic/TargetInfo.cpp
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/CodeGenTypeCache.h
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/ItaniumCXXABI.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Format/FormatToken.cpp
  clang/lib/Index/USRGeneration.cpp
  clang/lib/Parse/ParseDecl.cpp
  clang/lib/Parse/ParseExpr.cpp
  clang/lib/Parse/ParseExprCXX.cpp
  clang/lib/Parse/ParseTentative.cpp
  clang/lib/Sema/DeclSpec.cpp
  clang/lib/Sema/SemaCast.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/lib/Sema/SemaTemplateVariadic.cpp
  clang/lib/Sema/SemaType.cpp
  clang/lib/Serialization/ASTCommon.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/test/CodeGen/arm-bf16-params-returns.c
  clang/test/CodeGen/arm-mangle-16bit-float.cpp
  clang/test/Sema/arm-bf16-forbidden-ops.c
  clang/test/Sema/arm-bf16-forbidden-ops.cpp
  clang/test/Sema/arm-bfloat.cpp
  clang/tools/libclang/CXType.cpp

Index: clang/tools/libclang/CXType.cpp
===
--- clang/tools/libclang/CXType.cpp
+++ clang/tools/libclang/CXType.cpp
@@ -608,6 +608,7 @@
 TKIND(Elaborated);
 TKIND(Pipe);
 TKIND(Attributed);
+TKIND(BFloat16);
 #define IMAGE_TYPE(ImgType, Id, SingletonId, Access, Suffix) TKIND(Id);
 #include "clang/Basic/OpenCLImageTypes.def"
 #undef IMAGE_TYPE
Index: clang/test/Sema/arm-bfloat.cpp
===
--- /dev/null
+++ clang/test/Sema/arm-bfloat.cpp
@@ -0,0 +1,29 @@
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple aarch64-arm-none-eabi -target-cpu cortex-a75 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 \
+// RUN: -triple arm-arm-none-eabi -target-cpu cortex-a53 \
+// RUN: -target-feature +bf16 -target-feature +neon %s
+
+void test(bool b) {
+  __bf16 bf16;
+
+  bf16 + bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 - bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 * bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+  bf16 / bf16; // expected-error {{invalid operands to binary expression ('__bf16' and '__bf16')}}
+
+  __fp16 fp16;
+
+  bf16 + fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 + bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 - fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 - bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 * fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 * bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 / fp16; // expected-error {{invalid operands to binary expression ('__bf16' and '__fp16')}}
+  fp16 / bf16; // expected-error {{invalid operands to binary expression ('__fp16' and '__bf16')}}
+  bf16 = fp16; // expected-error {{assigning to '__bf16' from incompatible type '__fp16'}}
+  fp16 = bf16; // expected-error {{assigning to '__fp16' from incompatible type '__bf16'}}
+  bf16 + (b ? fp16 : bf16); // expected-error {{incompatible operand types ('__fp16' and '__bf16')}}
+}
Index: clang/test/Sema/arm-bf16-forbidden-ops.cpp
===
--- /dev/null
+++ clang/test/Sema/arm-bf16-forbidden-ops.cpp
@@ -0,0 +1,71 @@
+// RUN: %clang_cc1 -fsyntax-only -verify -triple aarch64 -target-feature +bf16 %s
+

[PATCH] D79711: [ARM][BFloat] Add poly64_t on AArch32.

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 264586.
stuij added a comment.

adhere to attribution conventions


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79711/new/

https://reviews.llvm.org/D79711

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/Sema/SemaType.cpp
  clang/utils/TableGen/NeonEmitter.cpp


Index: clang/utils/TableGen/NeonEmitter.cpp
===
--- clang/utils/TableGen/NeonEmitter.cpp
+++ clang/utils/TableGen/NeonEmitter.cpp
@@ -2235,6 +2235,7 @@
   OS << "#else\n";
   OS << "typedef int8_t poly8_t;\n";
   OS << "typedef int16_t poly16_t;\n";
+  OS << "typedef int64_t poly64_t;\n";
   OS << "#endif\n";
 
   // Emit Neon vector typedefs.
@@ -2247,7 +2248,7 @@
   for (auto &TS : TDTypeVec) {
 bool IsA64 = false;
 Type T(TS, ".");
-if (T.isDouble() || (T.isPoly() && T.getElementSizeInBits() == 64))
+if (T.isDouble())
   IsA64 = true;
 
 if (InIfdef && !IsA64) {
@@ -2280,7 +2281,7 @@
 for (auto &TS : TDTypeVec) {
   bool IsA64 = false;
   Type T(TS, ".");
-  if (T.isDouble() || (T.isPoly() && T.getElementSizeInBits() == 64))
+  if (T.isDouble())
 IsA64 = true;
 
   if (InIfdef && !IsA64) {
Index: clang/lib/Sema/SemaType.cpp
===
--- clang/lib/Sema/SemaType.cpp
+++ clang/lib/Sema/SemaType.cpp
@@ -7649,15 +7649,16 @@
 Triple.getArch() == llvm::Triple::aarch64_be;
   if (VecKind == VectorType::NeonPolyVector) {
 if (IsPolyUnsigned) {
-  // AArch64 polynomial vectors are unsigned and support poly64.
+  // AArch64 polynomial vectors are unsigned.
   return BTy->getKind() == BuiltinType::UChar ||
  BTy->getKind() == BuiltinType::UShort ||
  BTy->getKind() == BuiltinType::ULong ||
  BTy->getKind() == BuiltinType::ULongLong;
 } else {
-  // AArch32 polynomial vector are signed.
+  // AArch32 polynomial vectors are signed.
   return BTy->getKind() == BuiltinType::SChar ||
- BTy->getKind() == BuiltinType::Short;
+ BTy->getKind() == BuiltinType::Short ||
+ BTy->getKind() == BuiltinType::LongLong;
 }
   }
 
Index: clang/lib/AST/ItaniumMangle.cpp
===
--- clang/lib/AST/ItaniumMangle.cpp
+++ clang/lib/AST/ItaniumMangle.cpp
@@ -3167,6 +3167,7 @@
 case BuiltinType::UShort:
   EltName = "poly16_t";
   break;
+case BuiltinType::LongLong:
 case BuiltinType::ULongLong:
   EltName = "poly64_t";
   break;
Index: clang/include/clang/Basic/TargetBuiltins.h
===
--- clang/include/clang/Basic/TargetBuiltins.h
+++ clang/include/clang/Basic/TargetBuiltins.h
@@ -157,7 +157,7 @@
 EltType getEltType() const { return (EltType)(Flags & EltTypeMask); }
 bool isPoly() const {
   EltType ET = getEltType();
-  return ET == Poly8 || ET == Poly16;
+  return ET == Poly8 || ET == Poly16 || ET == Poly64;
 }
 bool isUnsigned() const { return (Flags & UnsignedFlag) != 0; }
 bool isQuad() const { return (Flags & QuadFlag) != 0; }


Index: clang/utils/TableGen/NeonEmitter.cpp
===
--- clang/utils/TableGen/NeonEmitter.cpp
+++ clang/utils/TableGen/NeonEmitter.cpp
@@ -2235,6 +2235,7 @@
   OS << "#else\n";
   OS << "typedef int8_t poly8_t;\n";
   OS << "typedef int16_t poly16_t;\n";
+  OS << "typedef int64_t poly64_t;\n";
   OS << "#endif\n";
 
   // Emit Neon vector typedefs.
@@ -2247,7 +2248,7 @@
   for (auto &TS : TDTypeVec) {
 bool IsA64 = false;
 Type T(TS, ".");
-if (T.isDouble() || (T.isPoly() && T.getElementSizeInBits() == 64))
+if (T.isDouble())
   IsA64 = true;
 
 if (InIfdef && !IsA64) {
@@ -2280,7 +2281,7 @@
 for (auto &TS : TDTypeVec) {
   bool IsA64 = false;
   Type T(TS, ".");
-  if (T.isDouble() || (T.isPoly() && T.getElementSizeInBits() == 64))
+  if (T.isDouble())
 IsA64 = true;
 
   if (InIfdef && !IsA64) {
Index: clang/lib/Sema/SemaType.cpp
===
--- clang/lib/Sema/SemaType.cpp
+++ clang/lib/Sema/SemaType.cpp
@@ -7649,15 +7649,16 @@
 Triple.getArch() == llvm::Triple::aarch64_be;
   if (VecKind == VectorType::NeonPolyVector) {
 if (IsPolyUnsigned) {
-  // AArch64 polynomial vectors are unsigned and support poly64.
+  // AArch64 polynomial vectors are unsigned.
   return BTy->getKind() == BuiltinType::UChar ||
  BTy->getKind() == BuiltinType::UShort ||
  BTy->getKind() == BuiltinType::ULong ||
  BTy->getKind() == BuiltinType::ULongLong;
 } else {
-  // AArch32 polynomial vector are signed.
+ 

[PATCH] D79708: [clang][BFloat] add NEON emitter for bfloat

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 264587.
stuij added a comment.

adhere to patch attribution conventions


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79708/new/

https://reviews.llvm.org/D79708

Files:
  clang/include/clang/Basic/arm_bf16.td
  clang/include/clang/Basic/arm_neon_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/Preprocessor/aarch64-target-features.c
  clang/test/Preprocessor/arm-target-features.c
  clang/utils/TableGen/NeonEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -85,6 +85,7 @@
 
 void EmitNeon(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitFP16(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitBF16(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeonSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeonTest(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitNeon2(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -63,6 +63,7 @@
   GenClangOpenCLBuiltins,
   GenArmNeon,
   GenArmFP16,
+  GenArmBF16,
   GenArmNeonSema,
   GenArmNeonTest,
   GenArmMveHeader,
@@ -186,6 +187,7 @@
"Generate OpenCL builtin declaration handlers"),
 clEnumValN(GenArmNeon, "gen-arm-neon", "Generate arm_neon.h for clang"),
 clEnumValN(GenArmFP16, "gen-arm-fp16", "Generate arm_fp16.h for clang"),
+clEnumValN(GenArmBF16, "gen-arm-bf16", "Generate arm_bf16.h for clang"),
 clEnumValN(GenArmNeonSema, "gen-arm-neon-sema",
"Generate ARM NEON sema support for clang"),
 clEnumValN(GenArmNeonTest, "gen-arm-neon-test",
@@ -360,6 +362,9 @@
   case GenArmFP16:
 EmitFP16(Records, OS);
 break;
+  case GenArmBF16:
+EmitBF16(Records, OS);
+break;
   case GenArmNeonSema:
 EmitNeonSema(Records, OS);
 break;
Index: clang/utils/TableGen/NeonEmitter.cpp
===
--- clang/utils/TableGen/NeonEmitter.cpp
+++ clang/utils/TableGen/NeonEmitter.cpp
@@ -99,7 +99,8 @@
   Poly128,
   Float16,
   Float32,
-  Float64
+  Float64,
+  BFloat16
 };
 
 } // end namespace NeonTypeFlags
@@ -147,6 +148,7 @@
 SInt,
 UInt,
 Poly,
+BFloat16,
   };
   TypeKind Kind;
   bool Immediate, Constant, Pointer;
@@ -199,6 +201,7 @@
   bool isInt() const { return isInteger() && ElementBitwidth == 32; }
   bool isLong() const { return isInteger() && ElementBitwidth == 64; }
   bool isVoid() const { return Kind == Void; }
+  bool isBFloat16() const { return Kind == BFloat16; }
   unsigned getNumElements() const { return Bitwidth / ElementBitwidth; }
   unsigned getSizeInBits() const { return Bitwidth; }
   unsigned getElementSizeInBits() const { return ElementBitwidth; }
@@ -585,8 +588,11 @@
   // runFP16 - Emit arm_fp16.h.inc
   void runFP16(raw_ostream &o);
 
-  // runHeader - Emit all the __builtin prototypes used in arm_neon.h
-	// and arm_fp16.h
+  // runBF16 - Emit arm_bf16.h.inc
+  void runBF16(raw_ostream &o);
+
+  // runHeader - Emit all the __builtin prototypes used in arm_neon.h,
+  // arm_fp16.h and arm_bf16.h
   void runHeader(raw_ostream &o);
 
   // runTests - Emit tests for all the Neon intrinsics.
@@ -611,12 +617,15 @@
 S += "poly";
   else if (isFloating())
 S += "float";
+  else if (isBFloat16())
+S += "bfloat";
   else
 S += "int";
 
   S += utostr(ElementBitwidth);
   if (isVector())
 S += "x" + utostr(getNumElements());
+
   if (NumVectors > 1)
 S += "x" + utostr(NumVectors);
   S += "_t";
@@ -650,7 +659,10 @@
 case 128: S += "LLLi"; break;
 default: llvm_unreachable("Unhandled case!");
 }
-  else
+  else if (isBFloat16()) {
+assert(ElementBitwidth == 16 && "BFloat16 can only be 16 bits");
+S += "y";
+  } else
 switch (ElementBitwidth) {
 case 16: S += "h"; break;
 case 32: S += "f"; break;
@@ -704,6 +716,11 @@
 Base = (unsigned)NeonTypeFlags::Float16 + (Addend - 1);
   }
 
+  if (isBFloat16()) {
+assert(Addend == 1 && "BFloat16 is only 16 bit");
+Base = (unsigned)NeonTypeFlags::BFloat16;
+  }
+
   if (Bitwidth == 128)
 Base |= (unsigned)NeonTypeFlags::QuadFlag;
   if (isInteger() && !isSigned())
@@ -727,6 +744,9 @@
   } else if (Name.startswith("poly")) {
 T.Kind = Poly;
 Name = Name.drop_front(4);
+  } else if (Name.startswith("bfloat")) {
+T.Kind = BFloat16;
+Name = Name.drop_front(6);
   } else {
 assert(Name.startswith("int"));
 Name = Na

[PATCH] D79710: [clang][BFloat] add create/set/get/dup intrinsics

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 264588.
stuij added a comment.

adhere to patch attribution conventions: change author to Ties, add all the 
contributors


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79710/new/

https://reviews.llvm.org/D79710

Files:
  clang/include/clang/Basic/arm_neon.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-bf16-getset-intrinsics.c

Index: clang/test/CodeGen/aarch64-bf16-getset-intrinsics.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-bf16-getset-intrinsics.c
@@ -0,0 +1,120 @@
+// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +neon -target-feature +bf16 \
+// RUN:  -O2 -fallow-half-arguments-and-returns -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK64
+// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi hard \
+// RUN:  -O2 -fallow-half-arguments-and-returns -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK32
+
+#include 
+
+bfloat16x4_t test_vcreate_bf16(uint64_t a) {
+  return vcreate_bf16(a);
+}
+// CHECK-LABEL: test_vcreate_bf16
+// CHECK64: %0 = bitcast i64 %a to <4 x bfloat>
+// CHECK32: %0 = bitcast i64 %a to <4 x bfloat>
+
+bfloat16x4_t test_vdup_n_bf16(bfloat16_t v) {
+  return vdup_n_bf16(v);
+}
+// CHECK-LABEL: test_vdup_n_bf16
+// CHECK64: %vecinit.i = insertelement <4 x bfloat> undef, bfloat %v, i32 0
+// CHECK32: %vecinit.i = insertelement <4 x bfloat> undef, bfloat %v, i32 0
+// CHECK: %vecinit{{.*}} = shufflevector <4 x bfloat> %vecinit.i, <4 x bfloat> undef, <4 x i32> zeroinitializer
+
+bfloat16x8_t test_vdupq_n_bf16(bfloat16_t v) {
+  return vdupq_n_bf16(v);
+}
+// CHECK-LABEL: test_vdupq_n_bf16
+// CHECK64: %vecinit.i = insertelement <8 x bfloat> undef, bfloat %v, i32 0
+// CHECK32: %vecinit.i = insertelement <8 x bfloat> undef, bfloat %v, i32 0
+// CHECK:   %vecinit{{.*}} = shufflevector <8 x bfloat> %vecinit.i, <8 x bfloat> undef, <8 x i32> zeroinitializer
+
+bfloat16x4_t test_vdup_lane_bf16(bfloat16x4_t v) {
+  return vdup_lane_bf16(v, 1);
+}
+// CHECK-LABEL: test_vdup_lane_bf16
+// CHECK64: %lane = shufflevector <4 x bfloat> %v, <4 x bfloat> undef, <4 x i32> 
+// CHECK32: %lane = shufflevector <4 x bfloat> %v, <4 x bfloat> undef, <4 x i32> 
+
+bfloat16x8_t test_vdupq_lane_bf16(bfloat16x4_t v) {
+  return vdupq_lane_bf16(v, 1);
+}
+// CHECK-LABEL: test_vdupq_lane_bf16
+// CHECK64: %lane = shufflevector <4 x bfloat> %v, <4 x bfloat> undef, <8 x i32> 
+// CHECK32: %lane = shufflevector <4 x bfloat> %v, <4 x bfloat> undef, <8 x i32> 
+
+bfloat16x4_t test_vdup_laneq_bf16(bfloat16x8_t v) {
+  return vdup_laneq_bf16(v, 7);
+}
+// CHECK-LABEL: test_vdup_laneq_bf16
+// CHECK64: %lane = shufflevector <8 x bfloat> %v, <8 x bfloat> undef, <4 x i32> 
+// CHECK32: %lane = shufflevector <8 x bfloat> %v, <8 x bfloat> undef, <4 x i32> 
+
+bfloat16x8_t test_vdupq_laneq_bf16(bfloat16x8_t v) {
+  return vdupq_laneq_bf16(v, 7);
+}
+// CHECK-LABEL: test_vdupq_laneq_bf16
+// CHECK64: %lane = shufflevector <8 x bfloat> %v, <8 x bfloat> undef, <8 x i32> 
+// CHECK32: %lane = shufflevector <8 x bfloat> %v, <8 x bfloat> undef, <8 x i32> 
+
+bfloat16x8_t test_vcombine_bf16(bfloat16x4_t low, bfloat16x4_t high) {
+  return vcombine_bf16(low, high);
+}
+// CHECK-LABEL: test_vcombine_bf16
+// CHECK64: %shuffle.i = shufflevector <4 x bfloat> %low, <4 x bfloat> %high, <8 x i32> 
+// CHECK32: %shuffle.i = shufflevector <4 x bfloat> %low, <4 x bfloat> %high, <8 x i32> 
+
+bfloat16x4_t test_vget_high_bf16(bfloat16x8_t a) {
+  return vget_high_bf16(a);
+}
+// CHECK-LABEL: test_vget_high_bf16
+// CHECK64: %shuffle.i = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> 
+// CHECK32: %shuffle.i = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> 
+
+bfloat16x4_t test_vget_low_bf16(bfloat16x8_t a) {
+  return vget_low_bf16(a);
+}
+// CHECK-LABEL: test_vget_low_bf16
+// CHECK64: %shuffle.i = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> 
+// CHECK32: %shuffle.i = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> 
+
+bfloat16_t test_vget_lane_bf16(bfloat16x4_t v) {
+  return vget_lane_bf16(v, 1);
+}
+// CHECK-LABEL: test_vget_lane_bf16
+// CHECK64: %vget_lane = extractelement <4 x bfloat> %v, i32 1
+// CHECK32: %vget_lane = extractelement <4 x bfloat> %v, i32 1
+
+bfloat16_t test_vgetq_lane_bf16(bfloat16x8_t v) {
+  return vgetq_lane_bf16(v, 7);
+}
+// CHECK-LABEL: test_vgetq_lane_bf16
+// CHECK64: %vgetq_lane = extractelement <8 x bfloat> %v, i32 7
+// CHECK32: %vget_lane = extractelement <8 x bfloat> %v, i32 7
+
+bfloat16x4_t test_vset_lane_bf16(bfloat16_t a, bfloat16x4_t v) {
+  return vset_lane_bf16(a, v, 1);
+}
+// CHECK-LABEL: test_vset_lane_bf16
+// CHECK64: %vset_lane = insertelement <4 x bfloat> %v, bfloat %a, i32 1
+// CHECK32: %vset_lane = insertelement <4 x bfloat> %v, bfloat %a, i32 1
+
+bfloat16x8_t test_v

[PATCH] D79869: [clang][BFloat] Add reinterpret cast intrinsics

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 264590.
stuij added a comment.

adhere to attribution conventions: change author to Ties, add all the 
contributors


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79869/new/

https://reviews.llvm.org/D79869

Files:
  clang/include/clang/Basic/arm_neon.td
  clang/include/clang/Basic/arm_neon_incl.td
  clang/test/CodeGen/aarch64-bf16-reinterpret-intrinsics.c
  clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
  clang/utils/TableGen/NeonEmitter.cpp

Index: clang/utils/TableGen/NeonEmitter.cpp
===
--- clang/utils/TableGen/NeonEmitter.cpp
+++ clang/utils/TableGen/NeonEmitter.cpp
@@ -313,7 +313,7 @@
   /// The unmangled name.
   std::string Name;
   /// The input and output typespecs. InTS == OutTS except when
-  /// CartesianProductOfTypes is 1 - this is the case for vreinterpret.
+  /// CartesianProductWith is non-empty - this is the case for vreinterpret.
   TypeSpec OutTS, InTS;
   /// The base class kind. Most intrinsics use ClassS, which has full type
   /// info for integers (s32/u32). Some use ClassI, which doesn't care about
@@ -346,7 +346,7 @@
   /// The set of intrinsics that this intrinsic uses/requires.
   std::set Dependencies;
   /// The "base type", which is Type('d', OutTS). InBaseType is only
-  /// different if CartesianProductOfTypes = 1 (for vreinterpret).
+  /// different if CartesianProductWith is non-empty (for vreinterpret).
   Type BaseType, InBaseType;
   /// The return variable.
   Variable RetVar;
@@ -1939,10 +1939,10 @@
   std::string Proto = std::string(R->getValueAsString("Prototype"));
   std::string Types = std::string(R->getValueAsString("Types"));
   Record *OperationRec = R->getValueAsDef("Operation");
-  bool CartesianProductOfTypes = R->getValueAsBit("CartesianProductOfTypes");
   bool BigEndianSafe  = R->getValueAsBit("BigEndianSafe");
   std::string Guard = std::string(R->getValueAsString("ArchGuard"));
   bool IsUnavailable = OperationRec->getValueAsBit("Unavailable");
+  std::string CartesianProductWith = std::string(R->getValueAsString("CartesianProductWith"));
 
   // Set the global current record. This allows assert_with_loc to produce
   // decent location information even when highly nested.
@@ -1957,17 +1957,20 @@
 CK = ClassMap[R->getSuperClasses()[1].first];
 
   std::vector> NewTypeSpecs;
-  for (auto TS : TypeSpecs) {
-if (CartesianProductOfTypes) {
+  if (!CartesianProductWith.empty()) {
+std::vector ProductTypeSpecs = TypeSpec::fromTypeSpecs(CartesianProductWith);
+for (auto TS : TypeSpecs) {
   Type DefaultT(TS, ".");
-  for (auto SrcTS : TypeSpecs) {
+  for (auto SrcTS : ProductTypeSpecs) {
 Type DefaultSrcT(SrcTS, ".");
 if (TS == SrcTS ||
 DefaultSrcT.getSizeInBits() != DefaultT.getSizeInBits())
   continue;
 NewTypeSpecs.push_back(std::make_pair(TS, SrcTS));
   }
-} else {
+}
+  } else {
+for (auto TS : TypeSpecs) {
   NewTypeSpecs.push_back(std::make_pair(TS, TS));
 }
   }
Index: clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
===
--- /dev/null
+++ clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
@@ -0,0 +1,314 @@
+// RUN: %clang_cc1 -triple armv8.2a-arm-none-eabi -target-feature +neon -target-feature +bf16 \
+// RUN: -disable-O0-optnone -S -emit-llvm -o - %s \
+// RUN: | opt -S -instcombine \
+// RUN: | FileCheck %s
+
+// REQUIRES: arm-registered-target
+
+#include 
+
+// CHECK-LABEL: @test_vreinterpret_bf16_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <8 x i8> [[A:%.*]] to <4 x bfloat>
+// CHECK-NEXT:ret <4 x bfloat> [[TMP0]]
+//
+bfloat16x4_t test_vreinterpret_bf16_s8(int8x8_t a)  { return vreinterpret_bf16_s8(a);}
+// CHECK-LABEL: @test_vreinterpret_bf16_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <4 x i16> [[A:%.*]] to <4 x bfloat>
+// CHECK-NEXT:ret <4 x bfloat> [[TMP0]]
+//
+bfloat16x4_t test_vreinterpret_bf16_s16(int16x4_t a){ return vreinterpret_bf16_s16(a);   }
+// CHECK-LABEL: @test_vreinterpret_bf16_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <2 x i32> [[A:%.*]] to <4 x bfloat>
+// CHECK-NEXT:ret <4 x bfloat> [[A:%.*]]
+//
+bfloat16x4_t test_vreinterpret_bf16_s32(int32x2_t a){ return vreinterpret_bf16_s32(a);   }
+// CHECK-LABEL: @test_vreinterpret_bf16_f32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <2 x float> [[A:%.*]] to <4 x bfloat>
+// CHECK-NEXT:ret <4 x bfloat> [[TMP0]]
+//
+bfloat16x4_t test_vreinterpret_bf16_f32(float32x2_t a)  { return vreinterpret_bf16_f32(a);   }
+// CHECK-LABEL: @test_vreinterpret_bf16_u8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <8 x i8> [[A:%.*]] to <4 x bfloat>
+// CHECK-NEXT:ret <4 x bfloat> [[TMP0]]
+//
+bfloat16x4_t test_vreinterp

[PATCH] D76077: [ARM] Add __bf16 as new Bfloat16 C Type

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Comment at: clang/docs/LanguageExtensions.rst:518
+Clang supports three half-precision (16-bit) floating point types: ``__fp16``,
+``_Float16`` and ``__bf16``.  These types are supported in all language modes.
 

SjoerdMeijer wrote:
> stuij wrote:
> > SjoerdMeijer wrote:
> > > Not my field of expertise, and sorry if I've missed this somewhere, but 
> > > was wondering if this (i.e. all language modes) means we need C++ name 
> > > mangling support for bfloat? In the AArch64 backend I saw this:
> > > 
> > >   getBFloat16Mangling() const override { return "u6__bf16"; }
> > > 
> > > But that's something else I guess, and I was guessing a 2 letter mangling 
> > > needs to be added here?
> > > 
> > > https://itanium-cxx-abi.github.io/cxx-abi/abi.html#mangling-builtin
> > Yes, we need name-mangling support, and yes that method you mentioned does 
> > that. There's one for AArch32 as well. And yes we have documented it in the 
> > 'C++ ABI for the latest Arm Architecture' docs:
> > 
> > aarch32: https://developer.arm.com/docs/ihi0041/latest
> > aarch64: https://developer.arm.com/docs/ihi0059/latest
> But does that mean that for other targets this is not (yet) supported?
Currently bfloat is a vendor-extended type, hence the 'u' prefix. So to me it 
would make sense that backends should implement their own naming, as there's no 
guarantee that the naming scheme chosen for Arm is compatible with all backends.


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[PATCH] D131555: [Clang] Propagate const context info when emitting compound literal

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This patch fixes a crash when trying to emit a constant compound literal.

For C++ Clang evaluates either casts or binary operations at translation time,
but doesn't pass on the InConstantContext information that was inferred when
parsing the statement.  Because of this, strict FP evaluation (-ftrapping-math)
which should be in effect yet, then causes checkFloatingpointResult to return
false, which in tryEmitGlobalCompoundLiteral will trigger an assert that the
compound literal wasn't constant.

The discussion here around 'manifestly constant evaluated contexts' was very
helpful to me when trying to understand what LLVM's position is on what
evaluation context should be in effect, together with the explanatory text in
that patch itself:
https://reviews.llvm.org/D87528


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Files:
  clang/lib/CodeGen/CGExprConstant.cpp
  clang/lib/CodeGen/ConstantEmitter.h
  clang/test/CodeGen/const-init.c


Index: clang/test/CodeGen/const-init.c
===
--- clang/test/CodeGen/const-init.c
+++ clang/test/CodeGen/const-init.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu 
-ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -emit-llvm -o - %s 
| FileCheck %s
+// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu 
-ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion 
-ffp-exception-behavior=strict -emit-llvm -o - %s | FileCheck %s
 
 #include 
 
@@ -181,3 +181,7 @@
 #pragma pack()
   // CHECK: @g31.a = internal global %struct.anon.2 { i16 23122, i32 
-12312731, i16 -312 }, align 4
 }
+
+struct { const float *floats; } compoundliteral = {
+  (float[1]) { 0.1, },
+};
Index: clang/lib/CodeGen/ConstantEmitter.h
===
--- clang/lib/CodeGen/ConstantEmitter.h
+++ clang/lib/CodeGen/ConstantEmitter.h
@@ -67,6 +67,9 @@
 return Abstract;
   }
 
+  bool isInConstantContext() const { return InConstantContext; }
+  void setInConstantContext(bool var) { InConstantContext = var; }
+
   /// Try to emit the initiaizer of the given declaration as an abstract
   /// constant.  If this succeeds, the emission must be finalized.
   llvm::Constant *tryEmitForInitializer(const VarDecl &D);
Index: clang/lib/CodeGen/CGExprConstant.cpp
===
--- clang/lib/CodeGen/CGExprConstant.cpp
+++ clang/lib/CodeGen/CGExprConstant.cpp
@@ -913,17 +913,15 @@
 // ConstExprEmitter
 
//===--===//
 
-static ConstantAddress tryEmitGlobalCompoundLiteral(CodeGenModule &CGM,
-CodeGenFunction *CGF,
+static ConstantAddress tryEmitGlobalCompoundLiteral(ConstantEmitter &emitter,
   const CompoundLiteralExpr *E) {
+  CodeGenModule &CGM = emitter.CGM;
   CharUnits Align = CGM.getContext().getTypeAlignInChars(E->getType());
   if (llvm::GlobalVariable *Addr =
   CGM.getAddrOfConstantCompoundLiteralIfEmitted(E))
 return ConstantAddress(Addr, Addr->getValueType(), Align);
 
   LangAS addressSpace = E->getType().getAddressSpace();
-
-  ConstantEmitter emitter(CGM, CGF);
   llvm::Constant *C = emitter.tryEmitForInitializer(E->getInitializer(),
 addressSpace, 
E->getType());
   if (!C) {
@@ -1970,7 +1968,9 @@
 
 ConstantLValue
 ConstantLValueEmitter::VisitCompoundLiteralExpr(const CompoundLiteralExpr *E) {
-  return tryEmitGlobalCompoundLiteral(CGM, Emitter.CGF, E);
+  ConstantEmitter CompoundLiteralEmitter(CGM, Emitter.CGF);
+  CompoundLiteralEmitter.setInConstantContext(Emitter.isInConstantContext());
+  return tryEmitGlobalCompoundLiteral(CompoundLiteralEmitter, E);
 }
 
 ConstantLValue
@@ -2214,7 +2214,8 @@
 ConstantAddress
 CodeGenModule::GetAddrOfConstantCompoundLiteral(const CompoundLiteralExpr *E) {
   assert(E->isFileScope() && "not a file-scope compound literal expr");
-  return tryEmitGlobalCompoundLiteral(*this, nullptr, E);
+  ConstantEmitter emitter(*this, nullptr);
+  return tryEmitGlobalCompoundLiteral(emitter, E);
 }
 
 llvm::Constant *


Index: clang/test/CodeGen/const-init.c
===
--- clang/test/CodeGen/const-init.c
+++ clang/test/CodeGen/const-init.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu -ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu -ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -ffp-exception-behavior=stric

[PATCH] D121206: [AARCH64] ssbs should be enabled by default for cortex-x1c

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addressed review comments


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Files:
  clang/test/Driver/aarch64-ssbs.c
  clang/test/Preprocessor/aarch64-target-features.c
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Target/AArch64/AArch64.td


Index: llvm/lib/Target/AArch64/AArch64.td
===
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -957,7 +957,7 @@
  FeatureRCPC, FeatureSSBS, FeaturePerfMon];
   list A77  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
  FeatureNEON, FeatureFullFP16, FeatureDotProd,
- FeatureRCPC, FeaturePerfMon];
+ FeatureRCPC, FeaturePerfMon, FeatureSSBS];
   list A78  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
  FeatureNEON, FeatureFullFP16, FeatureDotProd,
  FeatureRCPC, FeaturePerfMon, FeatureSPE,
@@ -975,11 +975,12 @@
  FeatureSB];
   list X1   = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
  FeatureNEON, FeatureRCPC, FeaturePerfMon,
- FeatureSPE, FeatureFullFP16, FeatureDotProd];
+ FeatureSPE, FeatureFullFP16, FeatureDotProd,
+ FeatureSSBS];
   list X1C  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
  FeatureNEON, FeatureRCPC, FeaturePerfMon,
  FeatureSPE, FeatureFullFP16, FeatureDotProd,
- FeaturePAuth];
+ FeaturePAuth, FeatureSSBS];
   list X2   = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
  FeatureMatMulInt8, FeatureBF16, FeatureAM,
  FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
Index: llvm/lib/Support/AArch64TargetParser.cpp
===
--- llvm/lib/Support/AArch64TargetParser.cpp
+++ llvm/lib/Support/AArch64TargetParser.cpp
@@ -120,6 +120,8 @@
 Features.push_back("+mops");
   if (Extensions & AArch64::AEK_PERFMON)
 Features.push_back("+perfmon");
+  if (Extensions & AArch64::AEK_SSBS)
+Features.push_back("+ssbs");
 
   return true;
 }
Index: clang/test/Preprocessor/aarch64-target-features.c
===
--- clang/test/Preprocessor/aarch64-target-features.c
+++ clang/test/Preprocessor/aarch64-target-features.c
@@ -285,7 +285,7 @@
 // CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
-// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"  
"-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" 
"+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" 
"+rdm" "-target-feature" "+rcpc" "-target-feature" "+fullfp16"
+// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"  
"-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" 
"+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" 
"+rdm" "-target-feature" "+rcpc" "-target-feature" "+ssbs" "-target-feature" 
"+fullfp16"
 // CHECK-MCPU-M3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-M4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" 
"+dotprod" "-target-feature" "+fullfp16"
 // CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"
Index: clang/test/Driver/aarch64-ssbs.c
===
--- clang/test/Driver/aarch64-ssbs.c
+++ clang/test/Driver/aarch64-ssbs.c
@@ -1,7 +1,11 @@
 // RUN: %clang -### -target aar

[PATCH] D121206: [AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c, cortex-a77

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Comment at: clang/test/Preprocessor/aarch64-target-features.c:288
 // CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
-// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"  
"-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" 
"+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" 
"+rdm" "-target-feature" "+rcpc" "-target-feature" "+fullfp16"
+// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"  
"-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" 
"+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" 
"+rdm" "-target-feature" "+rcpc" "-target-feature" "+ssbs" "-target-feature" 
"+fullfp16"
 // CHECK-MCPU-M3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"

DavidSpickett wrote:
> Why did this change, was it just not correct before or is r82 some equivalent 
> of the x1c?
yes, not correct. ssbs was enabled by default for cortex-r82, but we're now 
making sure we're passing +ssbs to the backend, like we do with other 
extensions.



Comment at: llvm/lib/Target/AArch64/AArch64.td:978
  FeatureNEON, FeatureRCPC, FeaturePerfMon,
  FeatureSPE, FeatureFullFP16, FeatureDotProd];
   list X1C  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,

dmgreen wrote:
> X1 and A77 missing SSBS too. Should they be added at the same time?
Yes they should. Thanks!


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[PATCH] D121206: [AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c, cortex-a77

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Comment at: llvm/lib/Target/AArch64/AArch64.td:978
  FeatureNEON, FeatureRCPC, FeaturePerfMon,
  FeatureSPE, FeatureFullFP16, FeatureDotProd];
   list X1C  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,

amilendra wrote:
> stuij wrote:
> > dmgreen wrote:
> > > X1 and A77 missing SSBS too. Should they be added at the same time?
> > Yes they should. Thanks!
> Maybe add unit tests for X1 and A77 too?
I did. See the top file.

In general it'd be good to have better testing for individual cores. This will 
happen more structurally in future changes.


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[PATCH] D121206: [AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c, cortex-a77

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This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG352453569b2b: [AARCH64] ssbs should be enabled by default 
for cortex-x1, cortex-x1c, cortex… (authored by stuij).

Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/test/Driver/aarch64-ssbs.c
  clang/test/Preprocessor/aarch64-target-features.c
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Target/AArch64/AArch64.td


Index: llvm/lib/Target/AArch64/AArch64.td
===
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -957,7 +957,7 @@
  FeatureRCPC, FeatureSSBS, FeaturePerfMon];
   list A77  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
  FeatureNEON, FeatureFullFP16, FeatureDotProd,
- FeatureRCPC, FeaturePerfMon];
+ FeatureRCPC, FeaturePerfMon, FeatureSSBS];
   list A78  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
  FeatureNEON, FeatureFullFP16, FeatureDotProd,
  FeatureRCPC, FeaturePerfMon, FeatureSPE,
@@ -975,11 +975,12 @@
  FeatureSB];
   list X1   = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
  FeatureNEON, FeatureRCPC, FeaturePerfMon,
- FeatureSPE, FeatureFullFP16, FeatureDotProd];
+ FeatureSPE, FeatureFullFP16, FeatureDotProd,
+ FeatureSSBS];
   list X1C  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
  FeatureNEON, FeatureRCPC, FeaturePerfMon,
  FeatureSPE, FeatureFullFP16, FeatureDotProd,
- FeaturePAuth];
+ FeaturePAuth, FeatureSSBS];
   list X2   = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
  FeatureMatMulInt8, FeatureBF16, FeatureAM,
  FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
Index: llvm/lib/Support/AArch64TargetParser.cpp
===
--- llvm/lib/Support/AArch64TargetParser.cpp
+++ llvm/lib/Support/AArch64TargetParser.cpp
@@ -120,6 +120,8 @@
 Features.push_back("+mops");
   if (Extensions & AArch64::AEK_PERFMON)
 Features.push_back("+perfmon");
+  if (Extensions & AArch64::AEK_SSBS)
+Features.push_back("+ssbs");
 
   return true;
 }
Index: clang/test/Preprocessor/aarch64-target-features.c
===
--- clang/test/Preprocessor/aarch64-target-features.c
+++ clang/test/Preprocessor/aarch64-target-features.c
@@ -285,7 +285,7 @@
 // CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
-// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"  
"-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" 
"+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" 
"+rdm" "-target-feature" "+rcpc" "-target-feature" "+fullfp16"
+// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"  
"-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" 
"+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" 
"+rdm" "-target-feature" "+rcpc" "-target-feature" "+ssbs" "-target-feature" 
"+fullfp16"
 // CHECK-MCPU-M3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-M4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" 
"+dotprod" "-target-feature" "+fullfp16"
 // CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"
Index: clang/test/Driver/aarch64-ssbs.c
==

[PATCH] D119008: Add Cortex-X1C to Clang LLVM 14 release notes

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Files:
  clang/docs/ReleaseNotes.rst


Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -101,6 +101,10 @@
   - RISC-V SiFive S51 (``sifive-s51``).
   - RISC-V SiFive S54 (``sifive-s54``).
   - RISC-V SiFive S76 (``sifive-s76``).
+  - Arm Cortex-X1C (``cortex-x1c``)
+  - Arm Cortex-X2 (``cortex-x2``)
+  - Arm Cortex-A510 (``cortex-a510``)
+  - Arm Cortex-A710 (``cortex-a710``)
 
 - Support has been added for the following architectures (``-march`` 
identifiers in parentheses):
 
@@ -281,11 +285,6 @@
 Arm and AArch64 Support in Clang
 
 
-- Support has been added for the following processors (command-line 
identifiers in parentheses):
-  - Arm Cortex-A510 (``cortex-a510``)
-  - Arm Cortex-X2 (``cortex-x2``)
-  - Arm Cortex-A710 (``cortex-A710``)
-
 - The -mtune flag is no longer ignored for AArch64. It is now possible to
   tune code generation for a particular CPU with -mtune without setting any
   architectural features. For example, compiling with


Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -101,6 +101,10 @@
   - RISC-V SiFive S51 (``sifive-s51``).
   - RISC-V SiFive S54 (``sifive-s54``).
   - RISC-V SiFive S76 (``sifive-s76``).
+  - Arm Cortex-X1C (``cortex-x1c``)
+  - Arm Cortex-X2 (``cortex-x2``)
+  - Arm Cortex-A510 (``cortex-a510``)
+  - Arm Cortex-A710 (``cortex-a710``)
 
 - Support has been added for the following architectures (``-march`` identifiers in parentheses):
 
@@ -281,11 +285,6 @@
 Arm and AArch64 Support in Clang
 
 
-- Support has been added for the following processors (command-line identifiers in parentheses):
-  - Arm Cortex-A510 (``cortex-a510``)
-  - Arm Cortex-X2 (``cortex-x2``)
-  - Arm Cortex-A710 (``cortex-A710``)
-
 - The -mtune flag is no longer ignored for AArch64. It is now possible to
   tune code generation for a particular CPU with -mtune without setting any
   architectural features. For example, compiling with
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[PATCH] D123763: [randstruct] Enforce using a designated init for a randomized struct

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stuij added inline comments.



Comment at: clang/lib/Sema/SemaInit.cpp:2171
 
 if (Field == FieldEnd) {
   // We've run out of fields. We're done.

@void Unfortunately this end of fields check will break the non-designated 
initializer check below.

I GDB'ed through a failure of the below test, and if I'm understanding this 
correctly, the `CheckDesignatedInitializer` invocation above will move `Field` 
to the next available field in the struct. If there is none, we will break out 
of the loop and never reach the code below (On an AArch64 Linux host the field 
was placed last in the struct).

Instead I get a different error:

error: 'error' diagnostics expected but not seen:
  File /Users/zeno/code/llvm/clean/clang/test/Sema/init-randomized-struct.c 
Line 46: a randomized struct can only be initialized with a designated 
initializer
error: 'error' diagnostics seen but not expected:
  File /Users/zeno/code/llvm/clean/clang/test/Sema/init-randomized-struct.c 
Line 46: excess elements in struct initializer
2 errors generated.

You can replicate this on other build setups by varying the value of 
-frandomoze-layout-seed. On x86_64 Linux and on Aarch64 OSX this worked for me 
(in seed value of lit test, change `f` to `d`):
-frandomize-layout-seed=1234567890abcded

Also, I know this was talked about before, and I know a fix is planned, but 
just to add my two cents: yes, it would be great if the `std::shuffle` could be 
changed to `llvm::shuffle`, also because we're expecting to produced the same 
code across different platforms for safety (compliance) reasons.


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[PATCH] D87463: [clang][aarch64] Fix mangling of bfloat16 neon vectors

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stuij accepted this revision.
stuij added a comment.
This revision is now accepted and ready to land.

Thanks, this one crept in during mass-renaming.


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[PATCH] D87463: [clang][aarch64] Fix mangling of bfloat16 neon vectors

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stuij added a comment.

I'm not sure what the procedure is to get patches into LLVM 11, but I think 
there's still time. Could you try to get this in there as well @c-rhodes ?


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[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

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stuij added a comment.

@ostannard: pinging on behalf of @dnsampaio. The changes still apply cleanly.


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[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

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stuij commandeered this revision.
stuij added a reviewer: dnsampaio.
stuij added a comment.

Commandeering as I've made some changes to the patch.


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[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

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stuij marked 6 inline comments as done.
stuij added inline comments.



Comment at: clang/include/clang/Basic/CodeGenOptions.def:396
+/// according to the field declaring type width.
+CODEGENOPT(ForceNoAAPCSBitfieldWidth, 1, 0)
+

ostannard wrote:
> dnsampaio wrote:
> > ostannard wrote:
> > > Why is this a negative option, when the one above is positive?
> > The enforcing of number of accesses would not be accepted if it was not an 
> > opt-in option. This one I expect it should be accepted with a single 
> > opt-out option.
> My problem is with the name of the option (adding an extra negative just 
> makes things more confusing), not with the default value. This could just be 
> called `AAPCSBitfieldWidth`, (unless you think the `Force` is adding 
> something), and default to true father than false.
done



Comment at: clang/include/clang/Driver/Options.td:2328
   HelpText<"Follows the AAPCS standard that all volatile bit-field write 
generates at least one load. (ARM only).">;
+def ForceNoAAPCSBitfieldWidth : Flag<["-"], "fno-AAPCSBitfieldWidth">, 
Group,
+  Flags<[DriverOption,CC1Option]>,

ostannard wrote:
> ostannard wrote:
> > Command-line options are in kebab-case, so this should be something like 
> > `fno-aapcs-bitfield-width`. This also applies to the `fAAPCSBitfieldLoad` 
> > option above, assuming it's not too late to change that.
> > 
> > Please also add a positive version of this option (i.e. 
> > `faapcs-bitfield-width`).
> This still needs a positive version.
done


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[PATCH] D88566: be more specific when testing for no fuse-ld warnings

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stuij created this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.
stuij requested review of this revision.

This test broke for our toolchain as this test triggered unrelated
warnings. Being more specific about not expecting fuse-ld warnings won't
invalidate the test, while playing a bit nicer with possible unrelated features.


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Files:
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Index: clang/test/Driver/fuse-ld.c
===
--- clang/test/Driver/fuse-ld.c
+++ clang/test/Driver/fuse-ld.c
@@ -12,7 +12,7 @@
 // RUN: %clang %s -### -target x86_64-unknown-linux \
 // RUN:   -fuse-ld=/usr/local/bin/or1k-linux-ld 2>&1 | \
 // RUN:   FileCheck %s --check-prefix=CHECK-NO-WARN
-// CHECK-NO-WARN-NOT: warning:
+// CHECK-NO-WARN-NOT: warning: 'fuse-ld'
 
 // RUN: %clang %s -### \
 // RUN: -target x86_64-unknown-freebsd 2>&1 \


Index: clang/test/Driver/fuse-ld.c
===
--- clang/test/Driver/fuse-ld.c
+++ clang/test/Driver/fuse-ld.c
@@ -12,7 +12,7 @@
 // RUN: %clang %s -### -target x86_64-unknown-linux \
 // RUN:   -fuse-ld=/usr/local/bin/or1k-linux-ld 2>&1 | \
 // RUN:   FileCheck %s --check-prefix=CHECK-NO-WARN
-// CHECK-NO-WARN-NOT: warning:
+// CHECK-NO-WARN-NOT: warning: 'fuse-ld'
 
 // RUN: %clang %s -### \
 // RUN: -target x86_64-unknown-freebsd 2>&1 \
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[PATCH] D88566: be more specific when testing for no fuse-ld warnings

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stuij updated this revision to Diff 295262.
stuij added a comment.

slight change in commit message


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Files:
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Index: clang/test/Driver/fuse-ld.c
===
--- clang/test/Driver/fuse-ld.c
+++ clang/test/Driver/fuse-ld.c
@@ -12,7 +12,7 @@
 // RUN: %clang %s -### -target x86_64-unknown-linux \
 // RUN:   -fuse-ld=/usr/local/bin/or1k-linux-ld 2>&1 | \
 // RUN:   FileCheck %s --check-prefix=CHECK-NO-WARN
-// CHECK-NO-WARN-NOT: warning:
+// CHECK-NO-WARN-NOT: warning: 'fuse-ld'
 
 // RUN: %clang %s -### \
 // RUN: -target x86_64-unknown-freebsd 2>&1 \


Index: clang/test/Driver/fuse-ld.c
===
--- clang/test/Driver/fuse-ld.c
+++ clang/test/Driver/fuse-ld.c
@@ -12,7 +12,7 @@
 // RUN: %clang %s -### -target x86_64-unknown-linux \
 // RUN:   -fuse-ld=/usr/local/bin/or1k-linux-ld 2>&1 | \
 // RUN:   FileCheck %s --check-prefix=CHECK-NO-WARN
-// CHECK-NO-WARN-NOT: warning:
+// CHECK-NO-WARN-NOT: warning: 'fuse-ld'
 
 // RUN: %clang %s -### \
 // RUN: -target x86_64-unknown-freebsd 2>&1 \
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[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

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stuij reopened this revision.
stuij added a comment.
This revision is now accepted and ready to land.

Reopening as this commit made clang/test/CodeGen/volatile.c fail on Arm/AArch64 
buildbot hosts.


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[PATCH] D88566: be more specific when testing for no fuse-ld warnings

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stuij added a comment.

Hi @MaskRay. Yes, so we're seeing a warning specific to our Armcompiler 
toolchain, so I'm guessing that isn't relevant to OSS LLVM:
`armclang: warning: '--target=x86_64-unknown-linux' is not supported.`

As David Green pointed out, we have a perfectly fine workaround. But I figured 
that a similar situation might crop up in OSS LLVM, and this way the test is a 
bit more future proof, and we might spare some future head-scratching.

However I feel bad already for wasting our time with such a minor change. Feel 
free to reject it :)


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[PATCH] D88566: be more specific when testing for no fuse-ld warnings

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stuij added inline comments.



Comment at: clang/test/Driver/fuse-ld.c:15
 // RUN:   FileCheck %s --check-prefix=CHECK-NO-WARN
-// CHECK-NO-WARN-NOT: warning:
+// CHECK-NO-WARN-NOT: warning: 'fuse-ld'
 

MaskRay wrote:
> How does this line trigger unrelated warnings? Can you dump it?
see my top-level comment


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[PATCH] D88566: be more specific when testing for no fuse-ld warnings

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stuij added a comment.

ping


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