[PATCH] D98264: [AArch64] Implement __rndr, __rndrrs intrinsics

2021-03-09 Thread Stelios Ioannou via Phabricator via cfe-commits 
stelios-arm created this revision.
stelios-arm added reviewers: dmgreen, SjoerdMeijer, fhahn, simon_tatham, 
ostannard, c-rhodes.
stelios-arm added a project: LLVM.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
stelios-arm requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

This patch implements the  `__rndr` and `__rndrrs` intrinsics to provide access 
to the random number instructions introduced in Armv8.5-A. They are only 
defined for the AArch64 execution state and are available when 
`__ARM_FEATURE_RNG` is defined.

These intrinsics store the random number in their pointer argument and return a 
status code if the generation succeeded. The difference between `__rndr` and 
`__rndrrs`, is that the latter intrinsic reseeds the random number generator.

The instructions write the NZCV flags indicating the success of the operation 
that we can then read with a CSET.

[1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics
[2] https://bugs.llvm.org/show_bug.cgi?id=47838


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98264

Files:
  clang/include/clang/Basic/BuiltinsAArch64.def
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/arm_acle.h
  clang/test/CodeGen/arm_acle.c
  clang/test/CodeGen/builtins-arm64.c
  clang/test/Preprocessor/init-aarch64.c
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/rand.ll
  llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

Index: llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
===
--- llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
+++ llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
@@ -100,11 +100,11 @@
   bb.0:
 liveins: $x0
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 renamable $x8 = MOVZXi 15309, 0
 renamable $x8 = MOVKXi renamable $x8, 26239, 16
 STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 8)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRXui killed renamable  $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 8)
 RET undef $lr
 
@@ -134,9 +134,9 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRXui killed renamable  $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
@@ -166,9 +166,9 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
@@ -275,10 +275,10 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 renamable $w8 = ORRWrs $wzr, killed renamable $w8, 0, implicit-def $x8
 STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
Index: llvm/test/CodeGen/AArch64/rand.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/rand.ll
@@ -0,0 +1,37 @@
+; RUN: llc -mtriple=aarch64 -mcpu=neoverse-v1 -mattr=+rand %s -o - | FileCheck %s
+
+define  i32 @rndr(i64* %__addr) {
+; CHECK-LABEL: rndr:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:mrs x8, RNDR
+; CHECK-NEXT:cset w9, ne
+; CHECK-NEXT:str x8, [x0]
+; CHECK-NEXT:and w0, w9, #0x1
+; CHECK-NEXT:ret
+  %1 = tail call { i64, i1 } @llvm.aarch64.rndr()
+  %2 = extractvalue { i64, i1 } %1, 0
+  %3 = extractvalue { i64, i1 } %1, 1
+  store i64 %2, i64* %__addr, align 8
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}
+
+
+define  i32 @rndrrs(i64*  %__addr) {
+; CHECK-LABEL: rndrrs:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:mrs x8, RNDRRS
+; CHECK-NEXT:cset w9, ne
+; CHECK-NEXT:str x8, [x0]
+; CHECK-NEXT:and w0, w9, #0x1
+; CHECK-NEXT:ret
+  %1 = tail call { i64, i1 } @llvm.aarch64.rndrrs()
+  %2 = extractvalue { i64, i1 } %1, 0
+  %3 = extractvalue { i64, i1 } %1, 1
+  store i64 %2, i64* %__addr, align 8
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}
+
+declare

[PATCH] D98264: [AArch64] Implement __rndr, __rndrrs intrinsics

2021-03-10 Thread Stelios Ioannou via Phabricator via cfe-commits 
stelios-arm added a comment.

@SjoerdMeijer @dmgreen Thanks for your reviews, I will be looking into this.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98264/new/

https://reviews.llvm.org/D98264

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D98264: [AArch64] Implement __rndr, __rndrrs intrinsics

2021-03-10 Thread Stelios Ioannou via Phabricator via cfe-commits 
stelios-arm marked 4 inline comments as done.
stelios-arm added inline comments.



Comment at: clang/lib/Basic/Targets/AArch64.cpp:363
 
+  if (HasRandGen)
+Builder.defineMacro("__ARM_FEATURE_RNG", "1");

SjoerdMeijer wrote:
> Where/when is `HasRandGen` set?
Oh, I forgot to set it, I am going to address this in the new revision. 



Comment at: clang/test/Preprocessor/init-aarch64.c:28
 // AARCH64-NEXT: #define __ARM_FEATURE_NUMERIC_MAXMIN 1
+// AARCH64-NEXT: #define  __ARM_FEATURE_RNG 1
 // AARCH64-NEXT: #define __ARM_FEATURE_UNALIGNED 1

SjoerdMeijer wrote:
> Why are we expecting this here? Are we not only expecting this for v8.5?
> 
> We also need a negative test and CHECK-NOT of this where we don't expect this.
Correct this shouldn't be here. I am going to address this in a new revision. 



Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:1495
   let DecoderNamespace = "Fallback";
+  let Defs = [NZCV];
 }

SjoerdMeijer wrote:
> SjoerdMeijer wrote:
> > dmgreen wrote:
> > > SjoerdMeijer wrote:
> > > > dmgreen wrote:
> > > > > SjoerdMeijer wrote:
> > > > > > Do all MRS instructions do this?
> > > > > No, but some do and it's not obvious which ones do and don't. I think 
> > > > > it should be reasonable to always def NZCV here, even if they are 
> > > > > just dead. It should be very rare that it would be beneficial for 
> > > > > NZCV to be live across a MRS instruction.
> > > > True, but since creating another definition is cheap, what would the 
> > > > cons be of:
> > > > 
> > > >   class MRS_NZCV : MRSI {
> > > > ..
> > > > let Defs = [NZCV];
> > > >   }
> > > > 
> > > > The way I look at it is that the description would be more accurate?
> > > I believe that would have an over-lapping definition with the existing 
> > > MRS instruction?
> > > 
> > > It would need to be a pseudo I think, which would eventually be turned 
> > > into a MSR proper late enough on the pipeline for it to be valid (or the 
> > > other way around, the no-nzcv version gets turned into a the nzcv version 
> > > to keep the verifier happy).
> > > 
> > > It could also be a optional def, but those are only used in the arm 
> > > backend and I would not recommend using them anywhere else.  I would 
> > > probably suggest just setting MRS as a NZCV setting instruction, unless 
> > > we find a reason to need to implement it differently.
> > > I believe that would have an over-lapping definition with the existing 
> > > MRS instruction?
> > 
> > Ah yeah, that might be true.
> > 
> > > It would need to be a pseudo I think
> > 
> > How much work is adding a pseudo for this case? My first reaction would be 
> > just trying to model this correctly, then we potentially don't have to 
> > worry again later about this. 
> I just wanted to add that I don't have too strong opinions on this, but what 
> I suggested seemed more the correct, even though the consequence of setting 
> NCZV for all MRS is minimal. So I will leave this one up to you @dmgreen and 
> @stelios-arm .
I will talk with @dmgreen and if it is decided that it is needed to change, I 
will address it in a future revision. Please note that the next revision of 
patch, will not address this comment (temporarily). 



Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:1274
+def : Pat<(AArch64mrs imm:$id),
+  (MRS imm:$id)>;
+

dmgreen wrote:
> SjoerdMeijer wrote:
> > Nit: can be on the same line.
> I always prefer Pat's to have input and output lines separate, for what it's 
> worth. It makes them more easily readable.
The styling for Pat's is not consistent across the file, some are in one line 
and others have the input and output lines separate. I also prefer the latter 
for readability. 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98264/new/

https://reviews.llvm.org/D98264

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D98264: [AArch64] Implement __rndr, __rndrrs intrinsics

2021-03-10 Thread Stelios Ioannou via Phabricator via cfe-commits 
stelios-arm updated this revision to Diff 329799.
stelios-arm marked 2 inline comments as done.
stelios-arm added a comment.

Addressed the comments made by @SjoerdMeijer and @dmgreen.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98264/new/

https://reviews.llvm.org/D98264

Files:
  clang/include/clang/Basic/BuiltinsAArch64.def
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/arm_acle.h
  clang/test/CodeGen/arm_acle.c
  clang/test/CodeGen/builtins-arm64.c
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/rand.ll
  llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

Index: llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
===
--- llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
+++ llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
@@ -100,11 +100,11 @@
   bb.0:
 liveins: $x0
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 renamable $x8 = MOVZXi 15309, 0
 renamable $x8 = MOVKXi renamable $x8, 26239, 16
 STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 8)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRXui killed renamable  $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 8)
 RET undef $lr
 
@@ -134,9 +134,9 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRXui killed renamable  $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
@@ -166,9 +166,9 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
@@ -275,10 +275,10 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 renamable $w8 = ORRWrs $wzr, killed renamable $w8, 0, implicit-def $x8
 STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
Index: llvm/test/CodeGen/AArch64/rand.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/rand.ll
@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 -mcpu=neoverse-v1 -mattr=+rand %s -o - | FileCheck %s
+
+define  i32 @rndr(i64* %__addr) {
+; CHECK-LABEL: rndr:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:mrs x8, RNDR
+; CHECK-NEXT:cset w9, eq
+; CHECK-NEXT:str x8, [x0]
+; CHECK-NEXT:and w0, w9, #0x1
+; CHECK-NEXT:ret
+  %1 = tail call { i64, i1 } @llvm.aarch64.rndr()
+  %2 = extractvalue { i64, i1 } %1, 0
+  %3 = extractvalue { i64, i1 } %1, 1
+  store i64 %2, i64* %__addr, align 8
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}
+
+
+define  i32 @rndrrs(i64*  %__addr) {
+; CHECK-LABEL: rndrrs:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:mrs x8, RNDRRS
+; CHECK-NEXT:cset w9, eq
+; CHECK-NEXT:str x8, [x0]
+; CHECK-NEXT:and w0, w9, #0x1
+; CHECK-NEXT:ret
+  %1 = tail call { i64, i1 } @llvm.aarch64.rndrrs()
+  %2 = extractvalue { i64, i1 } %1, 0
+  %3 = extractvalue { i64, i1 } %1, 1
+  store i64 %2, i64* %__addr, align 8
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}
+
+declare { i64, i1 } @llvm.aarch64.rndr()
+declare { i64, i1 } @llvm.aarch64.rndrrs()
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -607,7 +607,10 @@
 def AArch64stnp : SDNode<"AArch64ISD::STNP", SDT_AArch64stnp, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 
 def AArch64tbl : SDNode<"AArch64ISD::TBL", SDT_AArch64TBL>;
-
+// MRS from CodeGen.
+def AArch64mrs : SDNode<"AArch64ISD::MRS",
+SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, i32>]>,
+[SDNPHasChain, SDNPOutGlue]>;
 //===--===//
 
 //===

[PATCH] D98264: [AArch64] Implement __rndr, __rndrrs intrinsics

2021-03-11 Thread Stelios Ioannou via Phabricator via cfe-commits 
stelios-arm updated this revision to Diff 329931.
stelios-arm marked an inline comment as done.
stelios-arm added a comment.

1. Addressed the comment made by @SjoerdMeijer and added the comment for the 
MRS instruction.
2. Added the `+rang` feature in `arm_acle.c `




CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98264/new/

https://reviews.llvm.org/D98264

Files:
  clang/include/clang/Basic/BuiltinsAArch64.def
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/arm_acle.h
  clang/test/CodeGen/arm_acle.c
  clang/test/CodeGen/builtins-arm64.c
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/rand.ll
  llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

Index: llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
===
--- llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
+++ llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
@@ -100,11 +100,11 @@
   bb.0:
 liveins: $x0
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 renamable $x8 = MOVZXi 15309, 0
 renamable $x8 = MOVKXi renamable $x8, 26239, 16
 STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 8)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRXui killed renamable  $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 8)
 RET undef $lr
 
@@ -134,9 +134,9 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRXui killed renamable  $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
@@ -166,9 +166,9 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
@@ -275,10 +275,10 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 renamable $w8 = ORRWrs $wzr, killed renamable $w8, 0, implicit-def $x8
 STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
Index: llvm/test/CodeGen/AArch64/rand.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/rand.ll
@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 -mcpu=neoverse-v1 -mattr=+rand %s -o - | FileCheck %s
+
+define  i32 @rndr(i64* %__addr) {
+; CHECK-LABEL: rndr:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:mrs x8, RNDR
+; CHECK-NEXT:cset w9, eq
+; CHECK-NEXT:str x8, [x0]
+; CHECK-NEXT:and w0, w9, #0x1
+; CHECK-NEXT:ret
+  %1 = tail call { i64, i1 } @llvm.aarch64.rndr()
+  %2 = extractvalue { i64, i1 } %1, 0
+  %3 = extractvalue { i64, i1 } %1, 1
+  store i64 %2, i64* %__addr, align 8
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}
+
+
+define  i32 @rndrrs(i64*  %__addr) {
+; CHECK-LABEL: rndrrs:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:mrs x8, RNDRRS
+; CHECK-NEXT:cset w9, eq
+; CHECK-NEXT:str x8, [x0]
+; CHECK-NEXT:and w0, w9, #0x1
+; CHECK-NEXT:ret
+  %1 = tail call { i64, i1 } @llvm.aarch64.rndrrs()
+  %2 = extractvalue { i64, i1 } %1, 0
+  %3 = extractvalue { i64, i1 } %1, 1
+  store i64 %2, i64* %__addr, align 8
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}
+
+declare { i64, i1 } @llvm.aarch64.rndr()
+declare { i64, i1 } @llvm.aarch64.rndrrs()
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -607,7 +607,10 @@
 def AArch64stnp : SDNode<"AArch64ISD::STNP", SDT_AArch64stnp, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 
 def AArch64tbl : SDNode<"AArch64ISD::TBL", SDT_AArch64TBL>;
-
+// MRS from CodeGen.
+def AArch64mrs : SDNode<"AArch64ISD::MRS",
+SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, i32>]>,
+[SDNPHasChain, SDNPOutGlue]>;
 //===

[PATCH] D98264: [AArch64] Implement __rndr, __rndrrs intrinsics

2021-03-11 Thread Stelios Ioannou via Phabricator via cfe-commits 
stelios-arm updated this revision to Diff 329941.
stelios-arm added a comment.

Rephrased a comment.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98264/new/

https://reviews.llvm.org/D98264

Files:
  clang/include/clang/Basic/BuiltinsAArch64.def
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/arm_acle.h
  clang/test/CodeGen/arm_acle.c
  clang/test/CodeGen/builtins-arm64.c
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/rand.ll
  llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

Index: llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
===
--- llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
+++ llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
@@ -100,11 +100,11 @@
   bb.0:
 liveins: $x0
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 renamable $x8 = MOVZXi 15309, 0
 renamable $x8 = MOVKXi renamable $x8, 26239, 16
 STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 8)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRXui killed renamable  $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 8)
 RET undef $lr
 
@@ -134,9 +134,9 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRXui killed renamable  $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
@@ -166,9 +166,9 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
@@ -275,10 +275,10 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 renamable $w8 = ORRWrs $wzr, killed renamable $w8, 0, implicit-def $x8
 STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
Index: llvm/test/CodeGen/AArch64/rand.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/rand.ll
@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 -mcpu=neoverse-v1 -mattr=+rand %s -o - | FileCheck %s
+
+define  i32 @rndr(i64* %__addr) {
+; CHECK-LABEL: rndr:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:mrs x8, RNDR
+; CHECK-NEXT:cset w9, eq
+; CHECK-NEXT:str x8, [x0]
+; CHECK-NEXT:and w0, w9, #0x1
+; CHECK-NEXT:ret
+  %1 = tail call { i64, i1 } @llvm.aarch64.rndr()
+  %2 = extractvalue { i64, i1 } %1, 0
+  %3 = extractvalue { i64, i1 } %1, 1
+  store i64 %2, i64* %__addr, align 8
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}
+
+
+define  i32 @rndrrs(i64*  %__addr) {
+; CHECK-LABEL: rndrrs:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:mrs x8, RNDRRS
+; CHECK-NEXT:cset w9, eq
+; CHECK-NEXT:str x8, [x0]
+; CHECK-NEXT:and w0, w9, #0x1
+; CHECK-NEXT:ret
+  %1 = tail call { i64, i1 } @llvm.aarch64.rndrrs()
+  %2 = extractvalue { i64, i1 } %1, 0
+  %3 = extractvalue { i64, i1 } %1, 1
+  store i64 %2, i64* %__addr, align 8
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}
+
+declare { i64, i1 } @llvm.aarch64.rndr()
+declare { i64, i1 } @llvm.aarch64.rndrrs()
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -607,7 +607,10 @@
 def AArch64stnp : SDNode<"AArch64ISD::STNP", SDT_AArch64stnp, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 
 def AArch64tbl : SDNode<"AArch64ISD::TBL", SDT_AArch64TBL>;
-
+// MRS from CodeGen.
+def AArch64mrs : SDNode<"AArch64ISD::MRS",
+SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, i32>]>,
+[SDNPHasChain, SDNPOutGlue]>;
 //===--===//
 
 //===--===//
@@ -1266,6 +1269,9 @@
 def MSRpstateImm1 : MSRpstate

[PATCH] D98264: [AArch64] Implement __rndr, __rndrrs intrinsics

2021-03-12 Thread Stelios Ioannou via Phabricator via cfe-commits 
stelios-arm updated this revision to Diff 330230.
stelios-arm marked an inline comment as done.
stelios-arm added a comment.

1. Removed a redundant comment
2. Removed the changes made in the `test/CodeGen/arm_acle.c`, since the test is 
disabled.
3. Added a clang preprocessor test to check the presence and absence of the 
`__ARM_FEATURE_RNG` macro.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98264/new/

https://reviews.llvm.org/D98264

Files:
  clang/include/clang/Basic/BuiltinsAArch64.def
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/arm_acle.h
  clang/test/CodeGen/builtins-arm64.c
  clang/test/Preprocessor/aarch64-target-features.c
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/rand.ll
  llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

Index: llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
===
--- llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
+++ llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
@@ -100,11 +100,11 @@
   bb.0:
 liveins: $x0
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 renamable $x8 = MOVZXi 15309, 0
 renamable $x8 = MOVKXi renamable $x8, 26239, 16
 STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 8)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRXui killed renamable  $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 8)
 RET undef $lr
 
@@ -134,9 +134,9 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRXui killed renamable  $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
@@ -166,9 +166,9 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
@@ -275,10 +275,10 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 renamable $w8 = ORRWrs $wzr, killed renamable $w8, 0, implicit-def $x8
 STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
Index: llvm/test/CodeGen/AArch64/rand.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/rand.ll
@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 -mcpu=neoverse-v1 -mattr=+rand %s -o - | FileCheck %s
+
+define  i32 @rndr(i64* %__addr) {
+; CHECK-LABEL: rndr:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:mrs x8, RNDR
+; CHECK-NEXT:cset w9, eq
+; CHECK-NEXT:str x8, [x0]
+; CHECK-NEXT:and w0, w9, #0x1
+; CHECK-NEXT:ret
+  %1 = tail call { i64, i1 } @llvm.aarch64.rndr()
+  %2 = extractvalue { i64, i1 } %1, 0
+  %3 = extractvalue { i64, i1 } %1, 1
+  store i64 %2, i64* %__addr, align 8
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}
+
+
+define  i32 @rndrrs(i64*  %__addr) {
+; CHECK-LABEL: rndrrs:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:mrs x8, RNDRRS
+; CHECK-NEXT:cset w9, eq
+; CHECK-NEXT:str x8, [x0]
+; CHECK-NEXT:and w0, w9, #0x1
+; CHECK-NEXT:ret
+  %1 = tail call { i64, i1 } @llvm.aarch64.rndrrs()
+  %2 = extractvalue { i64, i1 } %1, 0
+  %3 = extractvalue { i64, i1 } %1, 1
+  store i64 %2, i64* %__addr, align 8
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}
+
+declare { i64, i1 } @llvm.aarch64.rndr()
+declare { i64, i1 } @llvm.aarch64.rndrrs()
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -607,7 +607,9 @@
 def AArch64stnp : SDNode<"AArch64ISD::STNP", SDT_AArch64stnp, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 
 def AArch64tbl : SDNode<"AArch64ISD::TBL", SDT_AArch64TBL>;
-
+def AArch64mrs : SDNode<"AArch64ISD::MRS",
+SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, i32>]>,
+

[PATCH] D98264: [AArch64] Implement __rndr, __rndrrs intrinsics

2021-03-12 Thread Stelios Ioannou via Phabricator via cfe-commits 
stelios-arm added inline comments.



Comment at: clang/test/CodeGen/arm_acle.c:908
+#if __ARM_64BIT_STATE && defined(__ARM_FEATURE_RNG)
+// AArch64-v8_3-LABEL: @test_rndr(
+// AArch64-v8_3-NEXT:  entry:

SjoerdMeijer wrote:
> Not sure if I am surprised that this works This is (re)using tag 
> `AArch64-v8_3` and for the other tests that use this and don't have RNG set, 
> I was expecting FileCheck to complain about this, not sure if I am missing 
> something though.
It turns out that this test is disabled 
(https://github.com/llvm/llvm-project/commit/6fcd4e080f09c9765d6e0ea03b1da91669c8509a).
 I am going to remove the changes in this file. 


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98264/new/

https://reviews.llvm.org/D98264

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D98264: [AArch64] Implement __rndr, __rndrrs intrinsics

2021-03-15 Thread Stelios Ioannou via Phabricator via cfe-commits 
stelios-arm added inline comments.



Comment at: clang/test/CodeGen/arm_acle.c:908
+#if __ARM_64BIT_STATE && defined(__ARM_FEATURE_RNG)
+// AArch64-v8_3-LABEL: @test_rndr(
+// AArch64-v8_3-NEXT:  entry:

SjoerdMeijer wrote:
> stelios-arm wrote:
> > SjoerdMeijer wrote:
> > > Not sure if I am surprised that this works This is (re)using tag 
> > > `AArch64-v8_3` and for the other tests that use this and don't have RNG 
> > > set, I was expecting FileCheck to complain about this, not sure if I am 
> > > missing something though.
> > It turns out that this test is disabled 
> > (https://github.com/llvm/llvm-project/commit/6fcd4e080f09c9765d6e0ea03b1da91669c8509a).
> >  I am going to remove the changes in this file. 
> But this seems to be a useful test to have. Are we testing this elsewhere now?
@dmgreen created a patch to re-enable this test 
(https://reviews.llvm.org/D98510). I am going to add the tests again. 


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98264/new/

https://reviews.llvm.org/D98264

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D98264: [AArch64] Implement __rndr, __rndrrs intrinsics

2021-03-15 Thread Stelios Ioannou via Phabricator via cfe-commits 
stelios-arm updated this revision to Diff 330616.
stelios-arm added a comment.

Added tests in `arm_acle.c`.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98264/new/

https://reviews.llvm.org/D98264

Files:
  clang/include/clang/Basic/BuiltinsAArch64.def
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/arm_acle.h
  clang/test/CodeGen/arm_acle.c
  clang/test/CodeGen/builtins-arm64.c
  clang/test/Preprocessor/aarch64-target-features.c
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/rand.ll
  llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

Index: llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
===
--- llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
+++ llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
@@ -100,11 +100,11 @@
   bb.0:
 liveins: $x0
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 renamable $x8 = MOVZXi 15309, 0
 renamable $x8 = MOVKXi renamable $x8, 26239, 16
 STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 8)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRXui killed renamable  $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 8)
 RET undef $lr
 
@@ -134,9 +134,9 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRXui killed renamable  $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
@@ -166,9 +166,9 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
@@ -275,10 +275,10 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 renamable $w8 = ORRWrs $wzr, killed renamable $w8, 0, implicit-def $x8
 STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
Index: llvm/test/CodeGen/AArch64/rand.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/rand.ll
@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 -mcpu=neoverse-v1 -mattr=+rand %s -o - | FileCheck %s
+
+define  i32 @rndr(i64* %__addr) {
+; CHECK-LABEL: rndr:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:mrs x8, RNDR
+; CHECK-NEXT:cset w9, eq
+; CHECK-NEXT:str x8, [x0]
+; CHECK-NEXT:and w0, w9, #0x1
+; CHECK-NEXT:ret
+  %1 = tail call { i64, i1 } @llvm.aarch64.rndr()
+  %2 = extractvalue { i64, i1 } %1, 0
+  %3 = extractvalue { i64, i1 } %1, 1
+  store i64 %2, i64* %__addr, align 8
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}
+
+
+define  i32 @rndrrs(i64*  %__addr) {
+; CHECK-LABEL: rndrrs:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:mrs x8, RNDRRS
+; CHECK-NEXT:cset w9, eq
+; CHECK-NEXT:str x8, [x0]
+; CHECK-NEXT:and w0, w9, #0x1
+; CHECK-NEXT:ret
+  %1 = tail call { i64, i1 } @llvm.aarch64.rndrrs()
+  %2 = extractvalue { i64, i1 } %1, 0
+  %3 = extractvalue { i64, i1 } %1, 1
+  store i64 %2, i64* %__addr, align 8
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}
+
+declare { i64, i1 } @llvm.aarch64.rndr()
+declare { i64, i1 } @llvm.aarch64.rndrrs()
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -607,7 +607,9 @@
 def AArch64stnp : SDNode<"AArch64ISD::STNP", SDT_AArch64stnp, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 
 def AArch64tbl : SDNode<"AArch64ISD::TBL", SDT_AArch64TBL>;
-
+def AArch64mrs : SDNode<"AArch64ISD::MRS",
+SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, i32>]>,
+[SDNPHasChain, SDNPOutGlue]>;
 //===--===//
 
 //===--===//
@@ -1266,6 +126

[PATCH] D98264: [AArch64] Implement __rndr, __rndrrs intrinsics

2021-03-15 Thread Stelios Ioannou via Phabricator via cfe-commits 
stelios-arm updated this revision to Diff 330670.
stelios-arm added a comment.

Change the  `rand.ll` llc arguments to the ones that are only relevant.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98264/new/

https://reviews.llvm.org/D98264

Files:
  clang/include/clang/Basic/BuiltinsAArch64.def
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/arm_acle.h
  clang/test/CodeGen/arm_acle.c
  clang/test/CodeGen/builtins-arm64.c
  clang/test/Preprocessor/aarch64-target-features.c
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/rand.ll
  llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

Index: llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
===
--- llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
+++ llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
@@ -100,11 +100,11 @@
   bb.0:
 liveins: $x0
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 renamable $x8 = MOVZXi 15309, 0
 renamable $x8 = MOVKXi renamable $x8, 26239, 16
 STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 8)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRXui killed renamable  $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 8)
 RET undef $lr
 
@@ -134,9 +134,9 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRXui killed renamable  $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
@@ -166,9 +166,9 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
@@ -275,10 +275,10 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 renamable $w8 = ORRWrs $wzr, killed renamable $w8, 0, implicit-def $x8
 STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
Index: llvm/test/CodeGen/AArch64/rand.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/rand.ll
@@ -0,0 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 -mattr=+v8.5a,+rand %s -o - | FileCheck %s
+
+define  i32 @rndr(i64* %__addr) {
+; CHECK-LABEL: rndr:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:mrs x9, RNDR
+; CHECK-NEXT:cset w8, eq
+; CHECK-NEXT:and w8, w8, #0x1
+; CHECK-NEXT:str x9, [x0]
+; CHECK-NEXT:mov w0, w8
+; CHECK-NEXT:ret
+  %1 = tail call { i64, i1 } @llvm.aarch64.rndr()
+  %2 = extractvalue { i64, i1 } %1, 0
+  %3 = extractvalue { i64, i1 } %1, 1
+  store i64 %2, i64* %__addr, align 8
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}
+
+
+define  i32 @rndrrs(i64*  %__addr) {
+; CHECK-LABEL: rndrrs:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:mrs x9, RNDRRS
+; CHECK-NEXT:cset w8, eq
+; CHECK-NEXT:and w8, w8, #0x1
+; CHECK-NEXT:str x9, [x0]
+; CHECK-NEXT:mov w0, w8
+; CHECK-NEXT:ret
+  %1 = tail call { i64, i1 } @llvm.aarch64.rndrrs()
+  %2 = extractvalue { i64, i1 } %1, 0
+  %3 = extractvalue { i64, i1 } %1, 1
+  store i64 %2, i64* %__addr, align 8
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}
+
+declare { i64, i1 } @llvm.aarch64.rndr()
+declare { i64, i1 } @llvm.aarch64.rndrrs()
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -607,7 +607,9 @@
 def AArch64stnp : SDNode<"AArch64ISD::STNP", SDT_AArch64stnp, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 
 def AArch64tbl : SDNode<"AArch64ISD::TBL", SDT_AArch64TBL>;
-
+def AArch64mrs : SDNode<"AArch64ISD::MRS",
+SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, i32>]>,
+[SDNPHasChain, SDNPOutGlue]>;
 //===--===//
 
 //===-

[PATCH] D98264: [AArch64] Implement __rndr, __rndrrs intrinsics

2021-03-15 Thread Stelios Ioannou via Phabricator via cfe-commits 
stelios-arm updated this revision to Diff 330694.
stelios-arm added a comment.

Typo fix for `__ARM_FEATURE_RNG` macro check in `aarch64-target-features.c`.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98264/new/

https://reviews.llvm.org/D98264

Files:
  clang/include/clang/Basic/BuiltinsAArch64.def
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/arm_acle.h
  clang/test/CodeGen/arm_acle.c
  clang/test/CodeGen/builtins-arm64.c
  clang/test/Preprocessor/aarch64-target-features.c
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/rand.ll
  llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

Index: llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
===
--- llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
+++ llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
@@ -100,11 +100,11 @@
   bb.0:
 liveins: $x0
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 renamable $x8 = MOVZXi 15309, 0
 renamable $x8 = MOVKXi renamable $x8, 26239, 16
 STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 8)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRXui killed renamable  $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 8)
 RET undef $lr
 
@@ -134,9 +134,9 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRXui killed renamable  $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
@@ -166,9 +166,9 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
@@ -275,10 +275,10 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 renamable $w8 = ORRWrs $wzr, killed renamable $w8, 0, implicit-def $x8
 STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
Index: llvm/test/CodeGen/AArch64/rand.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/rand.ll
@@ -0,0 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 -mattr=+v8.5a,+rand %s -o - | FileCheck %s
+
+define  i32 @rndr(i64* %__addr) {
+; CHECK-LABEL: rndr:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:mrs x9, RNDR
+; CHECK-NEXT:cset w8, eq
+; CHECK-NEXT:and w8, w8, #0x1
+; CHECK-NEXT:str x9, [x0]
+; CHECK-NEXT:mov w0, w8
+; CHECK-NEXT:ret
+  %1 = tail call { i64, i1 } @llvm.aarch64.rndr()
+  %2 = extractvalue { i64, i1 } %1, 0
+  %3 = extractvalue { i64, i1 } %1, 1
+  store i64 %2, i64* %__addr, align 8
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}
+
+
+define  i32 @rndrrs(i64*  %__addr) {
+; CHECK-LABEL: rndrrs:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:mrs x9, RNDRRS
+; CHECK-NEXT:cset w8, eq
+; CHECK-NEXT:and w8, w8, #0x1
+; CHECK-NEXT:str x9, [x0]
+; CHECK-NEXT:mov w0, w8
+; CHECK-NEXT:ret
+  %1 = tail call { i64, i1 } @llvm.aarch64.rndrrs()
+  %2 = extractvalue { i64, i1 } %1, 0
+  %3 = extractvalue { i64, i1 } %1, 1
+  store i64 %2, i64* %__addr, align 8
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}
+
+declare { i64, i1 } @llvm.aarch64.rndr()
+declare { i64, i1 } @llvm.aarch64.rndrrs()
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -607,7 +607,9 @@
 def AArch64stnp : SDNode<"AArch64ISD::STNP", SDT_AArch64stnp, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 
 def AArch64tbl : SDNode<"AArch64ISD::TBL", SDT_AArch64TBL>;
-
+def AArch64mrs : SDNode<"AArch64ISD::MRS",
+SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, i32>]>,
+[SDNPHasChain, SDNPOutGlue]>;
 //===--===//
 
 /

[PATCH] D98264: [AArch64] Implement __rndr, __rndrrs intrinsics

2021-03-15 Thread Stelios Ioannou via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGab86edbc88fa: [AArch64] Implement __rndr, __rndrrs 
intrinsics (authored by stelios-arm).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98264/new/

https://reviews.llvm.org/D98264

Files:
  clang/include/clang/Basic/BuiltinsAArch64.def
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/arm_acle.h
  clang/test/CodeGen/arm_acle.c
  clang/test/CodeGen/builtins-arm64.c
  clang/test/Preprocessor/aarch64-target-features.c
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/rand.ll
  llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

Index: llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
===
--- llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
+++ llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
@@ -100,11 +100,11 @@
   bb.0:
 liveins: $x0
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 renamable $x8 = MOVZXi 15309, 0
 renamable $x8 = MOVKXi renamable $x8, 26239, 16
 STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 8)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRXui killed renamable  $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 8)
 RET undef $lr
 
@@ -134,9 +134,9 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRXui killed renamable  $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
@@ -166,9 +166,9 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
@@ -275,10 +275,10 @@
   bb.0:
 liveins: $x0, $x1
 
-renamable $x8 = MRS 58880
+renamable $x8 = MRS 58880, implicit-def $nzcv
 renamable $w8 = ORRWrs $wzr, killed renamable $w8, 0, implicit-def $x8
 STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-renamable $x8 = MRS 55840
+renamable $x8 = MRS 55840, implicit-def $nzcv
 STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
 RET undef $lr
 
Index: llvm/test/CodeGen/AArch64/rand.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/rand.ll
@@ -0,0 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 -mattr=+v8.5a,+rand %s -o - | FileCheck %s
+
+define  i32 @rndr(i64* %__addr) {
+; CHECK-LABEL: rndr:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:mrs x9, RNDR
+; CHECK-NEXT:cset w8, eq
+; CHECK-NEXT:and w8, w8, #0x1
+; CHECK-NEXT:str x9, [x0]
+; CHECK-NEXT:mov w0, w8
+; CHECK-NEXT:ret
+  %1 = tail call { i64, i1 } @llvm.aarch64.rndr()
+  %2 = extractvalue { i64, i1 } %1, 0
+  %3 = extractvalue { i64, i1 } %1, 1
+  store i64 %2, i64* %__addr, align 8
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}
+
+
+define  i32 @rndrrs(i64*  %__addr) {
+; CHECK-LABEL: rndrrs:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:mrs x9, RNDRRS
+; CHECK-NEXT:cset w8, eq
+; CHECK-NEXT:and w8, w8, #0x1
+; CHECK-NEXT:str x9, [x0]
+; CHECK-NEXT:mov w0, w8
+; CHECK-NEXT:ret
+  %1 = tail call { i64, i1 } @llvm.aarch64.rndrrs()
+  %2 = extractvalue { i64, i1 } %1, 0
+  %3 = extractvalue { i64, i1 } %1, 1
+  store i64 %2, i64* %__addr, align 8
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}
+
+declare { i64, i1 } @llvm.aarch64.rndr()
+declare { i64, i1 } @llvm.aarch64.rndrrs()
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -607,7 +607,9 @@
 def AArch64stnp : SDNode<"AArch64ISD::STNP", SDT_AArch64stnp, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 
 def AArch64tbl : SDNode<"AArch64ISD::TBL", SDT_AArch64TBL>;
-
+def AArch64mrs : SDNode<"AArch64ISD::MRS",
+SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, i32>]>,
+