[PATCH] D50557: [clang][mips] Set __mips_fpr correctly for -mfpxx
smaksimovic created this revision.
smaksimovic added a reviewer: atanasyan.
Herald added subscribers: arichardson, sdardis.
Set __mips_fpr to 0 if o32 ABI is used with either -mfpxx or none of -mfp32,
-mfpxx, -mfp64 being specified.
Introduce additional checks:
- -mfpxx is only to be used in conjunction with the o32 ABI.
- report an error when incompatible options are provided.
Formerly no errors were raised when combining n32/n64 ABIs with -mfp32 and
-mfpxx.
There are other cases when __mips_fpr should be set to 0 that are not covered,
ex. using o32 on a mips64 cpu which is valid but not supported in the backend
as of yet.
https://reviews.llvm.org/D50557
Files:
include/clang/Basic/DiagnosticCommonKinds.td
lib/Basic/Targets/Mips.cpp
lib/Basic/Targets/Mips.h
Index: lib/Basic/Targets/Mips.h
===
--- lib/Basic/Targets/Mips.h
+++ lib/Basic/Targets/Mips.h
@@ -58,15 +58,16 @@
protected:
bool HasFP64;
+ bool HasFPXX;
std::string ABI;
public:
MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
: TargetInfo(Triple), IsMips16(false), IsMicromips(false),
IsNan2008(false), IsAbs2008(false), IsSingleFloat(false),
IsNoABICalls(false), CanUseBSDABICalls(false), FloatABI(HardFloat),
DspRev(NoDSP), HasMSA(false), DisableMadd4(false),
-UseIndirectJumpHazard(false), HasFP64(false) {
+UseIndirectJumpHazard(false), HasFP64(false), HasFPXX(false) {
TheCXXABI.set(TargetCXXABI::GenericMIPS);
setABI(getTriple().isMIPS32() ? "o32" : "n64");
@@ -181,6 +182,8 @@
return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
}
+ unsigned getISARev(const std::string& CPU) const;
+
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override;
@@ -328,6 +331,8 @@
HasFP64 = true;
else if (Feature == "-fp64")
HasFP64 = false;
+ else if (Feature == "+fpxx")
+HasFPXX = true;
else if (Feature == "+nan2008")
IsNan2008 = true;
else if (Feature == "-nan2008")
Index: lib/Basic/Targets/Mips.cpp
===
--- lib/Basic/Targets/Mips.cpp
+++ lib/Basic/Targets/Mips.cpp
@@ -59,6 +59,16 @@
Values.append(std::begin(ValidCPUNames), std::end(ValidCPUNames));
}
+unsigned MipsTargetInfo::getISARev(const std::string& CPU) const {
+ return llvm::StringSwitch(getCPU())
+ .Cases("mips32", "mips64", 1)
+ .Cases("mips32r2", "mips64r2", 2)
+ .Cases("mips32r3", "mips64r3", 3)
+ .Cases("mips32r5", "mips64r5", 5)
+ .Cases("mips32r6", "mips64r6", 6)
+ .Default(0);
+}
+
void MipsTargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
if (BigEndian) {
@@ -84,13 +94,8 @@
Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
}
- const std::string ISARev = llvm::StringSwitch(getCPU())
- .Cases("mips32", "mips64", "1")
- .Cases("mips32r2", "mips64r2", "2")
- .Cases("mips32r3", "mips64r3", "3")
- .Cases("mips32r5", "mips64r5", "5")
- .Cases("mips32r6", "mips64r6", "6")
- .Default("");
+ const std::string ISARev = std::to_string(getISARev(getCPU()));
+
if (!ISARev.empty())
Builder.defineMacro("__mips_isa_rev", ISARev);
@@ -129,7 +134,8 @@
if (IsSingleFloat)
Builder.defineMacro("__mips_single_float", Twine(1));
- Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
+ Builder.defineMacro("__mips_fpr",
+ Twine(HasFPXX ? 0 : (HasFP64 ? 64 : 32)));
Builder.defineMacro("_MIPS_FPSET",
Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
@@ -235,5 +241,29 @@
return false;
}
+ // -fpxx is valid only for the o32 ABI
+ if (HasFPXX && (ABI == "n32" || ABI == "n64")) {
+Diags.Report(diag::err_unsupported_abi_for_opt) << "-mfpxx" << "o32";
+return false;
+ }
+
+ // -mfp32 and n32/n64 ABIs are incompatible
+ if (!HasFP64 && !HasFPXX && !IsSingleFloat &&
+ (ABI == "n32" || ABI == "n64")) {
+Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfpxx" << CPU;
+return false;
+ }
+ // Mips revision 6 and -mfp32 are incompatible
+ if (!HasFP64 && !HasFPXX && (CPU == "mips32r6" || CPU == "mips64r6")) {
+Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfp32" << CPU;
+return false;
+ }
+ // Option -mfp64 permitted on Mips32 iff revision 2 or higher is present
+ if (HasFP64 && (CPU == "mips1" || CPU == "mips2" ||
+ getISARev(CPU) < 2) && ABI == "o32") {
+Diags.Report(diag::err_mips_fp64_req) << "-mfp64";
+return false;
+ }
+
return true;
}
Index
[PATCH] D50557: [clang][mips] Set __mips_fpr correctly for -mfpxx
smaksimovic updated this revision to Diff 161233.
smaksimovic added a comment.
Added test cases.
https://reviews.llvm.org/D50557
Files:
include/clang/Basic/DiagnosticCommonKinds.td
lib/Basic/Targets/Mips.cpp
lib/Basic/Targets/Mips.h
test/Preprocessor/init.c
Index: test/Preprocessor/init.c
===
--- test/Preprocessor/init.c
+++ test/Preprocessor/init.c
@@ -3442,7 +3442,7 @@
// MIPS32BE:#define __mips 32
// MIPS32BE:#define __mips__ 1
// MIPS32BE:#define __mips_abicalls 1
-// MIPS32BE:#define __mips_fpr 32
+// MIPS32BE:#define __mips_fpr 0
// MIPS32BE:#define __mips_hard_float 1
// MIPS32BE:#define __mips_o32 1
// MIPS32BE:#define _mips 1
@@ -3649,7 +3649,7 @@
// MIPS32EL:#define __mips 32
// MIPS32EL:#define __mips__ 1
// MIPS32EL:#define __mips_abicalls 1
-// MIPS32EL:#define __mips_fpr 32
+// MIPS32EL:#define __mips_fpr 0
// MIPS32EL:#define __mips_hard_float 1
// MIPS32EL:#define __mips_o32 1
// MIPS32EL:#define _mips 1
@@ -4900,6 +4900,41 @@
// RUN: | FileCheck -match-full-lines -check-prefix NOMIPS-ABS2008 %s
// NOMIPS-ABS2008-NOT:#define __mips_abs2008 1
//
+// RUN: %clang_cc1 \
+// RUN: -E -dM -triple=mips-none-none < /dev/null \
+// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-NOFP %s
+// MIPS32-NOFP:#define __mips_fpr 0
+//
+// RUN: %clang_cc1 -target-feature +fpxx \
+// RUN: -E -dM -triple=mips-none-none < /dev/null \
+// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-MFPXX %s
+// MIPS32-MFPXX:#define __mips_fpr 0
+//
+// RUN: %clang_cc1 -target-cpu mips32r6 -target-feature +fpxx \
+// RUN: -E -dM -triple=mips-none-none < /dev/null \
+// RUN: | FileCheck -match-full-lines -check-prefix MIPS32R6-MFPXX %s
+// MIPS32R6-MFPXX:#define __mips_fpr 0
+//
+// RUN: %clang_cc1 \
+// RUN: -E -dM -triple=mips64-none-none < /dev/null \
+// RUN: | FileCheck -match-full-lines -check-prefix MIPS64-NOFP %s
+// MIPS64-NOFP:#define __mips_fpr 64
+//
+// RUN: not %clang_cc1 -target-feature -fp64 \
+// RUN: -E -dM -triple=mips64-none-none < /dev/null 2>&1 \
+// RUN: | FileCheck -match-full-lines -check-prefix MIPS64-MFP32 %s
+// MIPS64-MFP32:error: option '-mfpxx' cannot be specified with 'mips64r2'
+//
+// RUN: not %clang_cc1 -target-feature +fpxx \
+// RUN: -E -dM -triple=mips64-none-none < /dev/null 2>&1 \
+// RUN: | FileCheck -match-full-lines -check-prefix MIPS64-MFPXX %s
+// MIPS64-MFPXX:error: '-mfpxx' can only be used with the 'o32' ABI
+//
+// RUN: not %clang_cc1 -target-cpu mips64r6 -target-feature +fpxx \
+// RUN: -E -dM -triple=mips64-none-none < /dev/null 2>&1 \
+// RUN: | FileCheck -match-full-lines -check-prefix MIPS64R6-MFPXX %s
+// MIPS64R6-MFPXX:error: '-mfpxx' can only be used with the 'o32' ABI
+//
// RUN: %clang_cc1 -target-feature -fp64 \
// RUN: -E -dM -triple=mips-none-none < /dev/null \
// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-MFP32 %s
@@ -4916,7 +4951,7 @@
// RUN: -E -dM -triple=mips-none-none < /dev/null \
// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-MFP32SF %s
// MIPS32-MFP32SF:#define _MIPS_FPSET 32
-// MIPS32-MFP32SF:#define __mips_fpr 32
+// MIPS32-MFP32SF:#define __mips_fpr 0
//
// RUN: %clang_cc1 -target-feature +fp64 \
// RUN: -E -dM -triple=mips64-none-none < /dev/null \
Index: lib/Basic/Targets/Mips.h
===
--- lib/Basic/Targets/Mips.h
+++ lib/Basic/Targets/Mips.h
@@ -57,16 +57,16 @@
bool UseIndirectJumpHazard;
protected:
- bool HasFP64;
+ enum FPModeEnum { FPXX, FP32, FP64 } FPMode;
std::string ABI;
public:
MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
: TargetInfo(Triple), IsMips16(false), IsMicromips(false),
IsNan2008(false), IsAbs2008(false), IsSingleFloat(false),
IsNoABICalls(false), CanUseBSDABICalls(false), FloatABI(HardFloat),
DspRev(NoDSP), HasMSA(false), DisableMadd4(false),
-UseIndirectJumpHazard(false), HasFP64(false) {
+UseIndirectJumpHazard(false), FPMode(FPXX) {
TheCXXABI.set(TargetCXXABI::GenericMIPS);
setABI(getTriple().isMIPS32() ? "o32" : "n64");
@@ -181,6 +181,8 @@
return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
}
+ unsigned getISARev() const;
+
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override;
@@ -305,7 +307,7 @@
IsSingleFloat = false;
FloatABI = HardFloat;
DspRev = NoDSP;
-HasFP64 = isFP64Default();
+FPMode = isFP64Default() ? FP64 : FPXX;
for (const auto &Feature : Features) {
if (Feature == "+single-float")
@@ -325,9 +327,11 @@
else if (Feature == "+nomadd4")
DisableMadd4 = true;
else if (Feature == "+fp64")
-HasFP64 = true;
+FPMode = FP64;
else if (Feature == "-fp64")
-HasFP64 = false;
+FPMode = FP32;
+ else if (
[PATCH] D50557: [clang][mips] Set __mips_fpr correctly for -mfpxx
smaksimovic added inline comments.
Comment at: lib/Basic/Targets/Mips.cpp:62
+unsigned MipsTargetInfo::getISARev(const std::string& CPU) const {
+ return llvm::StringSwitch(getCPU())
atanasyan wrote:
> The CPU argument looks unused. We can either remove it or make this routine a
> non-member static function. Probably we can change the CPU’s type to
> StringRef.
I opted to remove the argument.
Comment at: lib/Basic/Targets/Mips.cpp:97
- const std::string ISARev = llvm::StringSwitch(getCPU())
- .Cases("mips32", "mips64", "1")
- .Cases("mips32r2", "mips64r2", "2")
- .Cases("mips32r3", "mips64r3", "3")
- .Cases("mips32r5", "mips64r5", "5")
- .Cases("mips32r6", "mips64r6", "6")
- .Default("");
+ const std::string ISARev = std::to_string(getISARev(getCPU()));
+
atanasyan wrote:
> Is this change required for the fix? It looks like a refactoring and maybe
> done by a separate commit.
Since I took the code that originally was here in order to reuse it down below,
I changed this line because the new function returns an int instead, as it was
easier to do comparisons at line 264.
https://reviews.llvm.org/D50557
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[PATCH] D50557: [clang][mips] Set __mips_fpr correctly for -mfpxx
smaksimovic updated this revision to Diff 161690.
smaksimovic added a comment.
Expanded a piece of code using switch cases as suggested.
https://reviews.llvm.org/D50557
Files:
include/clang/Basic/DiagnosticCommonKinds.td
lib/Basic/Targets/Mips.cpp
lib/Basic/Targets/Mips.h
test/Preprocessor/init.c
Index: test/Preprocessor/init.c
===
--- test/Preprocessor/init.c
+++ test/Preprocessor/init.c
@@ -3442,7 +3442,7 @@
// MIPS32BE:#define __mips 32
// MIPS32BE:#define __mips__ 1
// MIPS32BE:#define __mips_abicalls 1
-// MIPS32BE:#define __mips_fpr 32
+// MIPS32BE:#define __mips_fpr 0
// MIPS32BE:#define __mips_hard_float 1
// MIPS32BE:#define __mips_o32 1
// MIPS32BE:#define _mips 1
@@ -3649,7 +3649,7 @@
// MIPS32EL:#define __mips 32
// MIPS32EL:#define __mips__ 1
// MIPS32EL:#define __mips_abicalls 1
-// MIPS32EL:#define __mips_fpr 32
+// MIPS32EL:#define __mips_fpr 0
// MIPS32EL:#define __mips_hard_float 1
// MIPS32EL:#define __mips_o32 1
// MIPS32EL:#define _mips 1
@@ -4900,6 +4900,41 @@
// RUN: | FileCheck -match-full-lines -check-prefix NOMIPS-ABS2008 %s
// NOMIPS-ABS2008-NOT:#define __mips_abs2008 1
//
+// RUN: %clang_cc1 \
+// RUN: -E -dM -triple=mips-none-none < /dev/null \
+// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-NOFP %s
+// MIPS32-NOFP:#define __mips_fpr 0
+//
+// RUN: %clang_cc1 -target-feature +fpxx \
+// RUN: -E -dM -triple=mips-none-none < /dev/null \
+// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-MFPXX %s
+// MIPS32-MFPXX:#define __mips_fpr 0
+//
+// RUN: %clang_cc1 -target-cpu mips32r6 -target-feature +fpxx \
+// RUN: -E -dM -triple=mips-none-none < /dev/null \
+// RUN: | FileCheck -match-full-lines -check-prefix MIPS32R6-MFPXX %s
+// MIPS32R6-MFPXX:#define __mips_fpr 0
+//
+// RUN: %clang_cc1 \
+// RUN: -E -dM -triple=mips64-none-none < /dev/null \
+// RUN: | FileCheck -match-full-lines -check-prefix MIPS64-NOFP %s
+// MIPS64-NOFP:#define __mips_fpr 64
+//
+// RUN: not %clang_cc1 -target-feature -fp64 \
+// RUN: -E -dM -triple=mips64-none-none < /dev/null 2>&1 \
+// RUN: | FileCheck -match-full-lines -check-prefix MIPS64-MFP32 %s
+// MIPS64-MFP32:error: option '-mfpxx' cannot be specified with 'mips64r2'
+//
+// RUN: not %clang_cc1 -target-feature +fpxx \
+// RUN: -E -dM -triple=mips64-none-none < /dev/null 2>&1 \
+// RUN: | FileCheck -match-full-lines -check-prefix MIPS64-MFPXX %s
+// MIPS64-MFPXX:error: '-mfpxx' can only be used with the 'o32' ABI
+//
+// RUN: not %clang_cc1 -target-cpu mips64r6 -target-feature +fpxx \
+// RUN: -E -dM -triple=mips64-none-none < /dev/null 2>&1 \
+// RUN: | FileCheck -match-full-lines -check-prefix MIPS64R6-MFPXX %s
+// MIPS64R6-MFPXX:error: '-mfpxx' can only be used with the 'o32' ABI
+//
// RUN: %clang_cc1 -target-feature -fp64 \
// RUN: -E -dM -triple=mips-none-none < /dev/null \
// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-MFP32 %s
@@ -4916,7 +4951,7 @@
// RUN: -E -dM -triple=mips-none-none < /dev/null \
// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-MFP32SF %s
// MIPS32-MFP32SF:#define _MIPS_FPSET 32
-// MIPS32-MFP32SF:#define __mips_fpr 32
+// MIPS32-MFP32SF:#define __mips_fpr 0
//
// RUN: %clang_cc1 -target-feature +fp64 \
// RUN: -E -dM -triple=mips64-none-none < /dev/null \
Index: lib/Basic/Targets/Mips.h
===
--- lib/Basic/Targets/Mips.h
+++ lib/Basic/Targets/Mips.h
@@ -57,16 +57,16 @@
bool UseIndirectJumpHazard;
protected:
- bool HasFP64;
+ enum FPModeEnum { FPXX, FP32, FP64 } FPMode;
std::string ABI;
public:
MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
: TargetInfo(Triple), IsMips16(false), IsMicromips(false),
IsNan2008(false), IsAbs2008(false), IsSingleFloat(false),
IsNoABICalls(false), CanUseBSDABICalls(false), FloatABI(HardFloat),
DspRev(NoDSP), HasMSA(false), DisableMadd4(false),
-UseIndirectJumpHazard(false), HasFP64(false) {
+UseIndirectJumpHazard(false), FPMode(FPXX) {
TheCXXABI.set(TargetCXXABI::GenericMIPS);
setABI(getTriple().isMIPS32() ? "o32" : "n64");
@@ -181,6 +181,8 @@
return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
}
+ unsigned getISARev() const;
+
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override;
@@ -305,7 +307,7 @@
IsSingleFloat = false;
FloatABI = HardFloat;
DspRev = NoDSP;
-HasFP64 = isFP64Default();
+FPMode = isFP64Default() ? FP64 : FPXX;
for (const auto &Feature : Features) {
if (Feature == "+single-float")
@@ -325,9 +327,11 @@
else if (Feature == "+nomadd4")
DisableMadd4 = true;
else if (Feature == "+fp64")
-HasFP64 = true;
+FPMode = FP64;
else if (Feature == "-fp64")
-HasFP64 = false;
[PATCH] D50557: [clang][mips] Set __mips_fpr correctly for -mfpxx
This revision was automatically updated to reflect the committed changes.
Closed by commit rL340391: [clang][mips] Set __mips_fpr correctly for -mfpxx
(authored by smaksimovic, committed by ).
Herald added subscribers: llvm-commits, jrtc27.
Changed prior to commit:
https://reviews.llvm.org/D50557?vs=161690&id=161907#toc
Repository:
rL LLVM
https://reviews.llvm.org/D50557
Files:
cfe/trunk/include/clang/Basic/DiagnosticCommonKinds.td
cfe/trunk/lib/Basic/Targets/Mips.cpp
cfe/trunk/lib/Basic/Targets/Mips.h
cfe/trunk/test/Preprocessor/init.c
Index: cfe/trunk/lib/Basic/Targets/Mips.cpp
===
--- cfe/trunk/lib/Basic/Targets/Mips.cpp
+++ cfe/trunk/lib/Basic/Targets/Mips.cpp
@@ -59,6 +59,16 @@
Values.append(std::begin(ValidCPUNames), std::end(ValidCPUNames));
}
+unsigned MipsTargetInfo::getISARev() const {
+ return llvm::StringSwitch(getCPU())
+ .Cases("mips32", "mips64", 1)
+ .Cases("mips32r2", "mips64r2", 2)
+ .Cases("mips32r3", "mips64r3", 3)
+ .Cases("mips32r5", "mips64r5", 5)
+ .Cases("mips32r6", "mips64r6", 6)
+ .Default(0);
+}
+
void MipsTargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
if (BigEndian) {
@@ -84,13 +94,8 @@
Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
}
- const std::string ISARev = llvm::StringSwitch(getCPU())
- .Cases("mips32", "mips64", "1")
- .Cases("mips32r2", "mips64r2", "2")
- .Cases("mips32r3", "mips64r3", "3")
- .Cases("mips32r5", "mips64r5", "5")
- .Cases("mips32r6", "mips64r6", "6")
- .Default("");
+ const std::string ISARev = std::to_string(getISARev());
+
if (!ISARev.empty())
Builder.defineMacro("__mips_isa_rev", ISARev);
@@ -129,9 +134,22 @@
if (IsSingleFloat)
Builder.defineMacro("__mips_single_float", Twine(1));
- Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
- Builder.defineMacro("_MIPS_FPSET",
- Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
+ switch (FPMode) {
+ case FPXX:
+Builder.defineMacro("__mips_fpr", Twine(0));
+break;
+ case FP32:
+Builder.defineMacro("__mips_fpr", Twine(32));
+break;
+ case FP64:
+Builder.defineMacro("__mips_fpr", Twine(64));
+break;
+}
+
+ if (FPMode == FP64 || IsSingleFloat)
+Builder.defineMacro("_MIPS_FPSET", Twine(32));
+ else
+Builder.defineMacro("_MIPS_FPSET", Twine(16));
if (IsMips16)
Builder.defineMacro("__mips16", Twine(1));
@@ -189,7 +207,7 @@
bool MipsTargetInfo::hasFeature(StringRef Feature) const {
return llvm::StringSwitch(Feature)
.Case("mips", true)
- .Case("fp64", HasFP64)
+ .Case("fp64", FPMode == FP64)
.Default(false);
}
@@ -235,5 +253,30 @@
return false;
}
+ // -fpxx is valid only for the o32 ABI
+ if (FPMode == FPXX && (ABI == "n32" || ABI == "n64")) {
+Diags.Report(diag::err_unsupported_abi_for_opt) << "-mfpxx" << "o32";
+return false;
+ }
+
+ // -mfp32 and n32/n64 ABIs are incompatible
+ if (FPMode != FP64 && FPMode != FPXX && !IsSingleFloat &&
+ (ABI == "n32" || ABI == "n64")) {
+Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfpxx" << CPU;
+return false;
+ }
+ // Mips revision 6 and -mfp32 are incompatible
+ if (FPMode != FP64 && FPMode != FPXX && (CPU == "mips32r6" ||
+ CPU == "mips64r6")) {
+Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfp32" << CPU;
+return false;
+ }
+ // Option -mfp64 permitted on Mips32 iff revision 2 or higher is present
+ if (FPMode == FP64 && (CPU == "mips1" || CPU == "mips2" ||
+ getISARev() < 2) && ABI == "o32") {
+Diags.Report(diag::err_mips_fp64_req) << "-mfp64";
+return false;
+ }
+
return true;
}
Index: cfe/trunk/lib/Basic/Targets/Mips.h
===
--- cfe/trunk/lib/Basic/Targets/Mips.h
+++ cfe/trunk/lib/Basic/Targets/Mips.h
@@ -57,16 +57,16 @@
bool UseIndirectJumpHazard;
protected:
- bool HasFP64;
+ enum FPModeEnum { FPXX, FP32, FP64 } FPMode;
std::string ABI;
public:
MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
: TargetInfo(Triple), IsMips16(false), IsMicromips(false),
IsNan2008(false), IsAbs2008(false), IsSingleFloat(false),
IsNoABICalls(false), CanUseBSDABICalls(false), FloatABI(HardFloat),
DspRev(NoDSP), HasMSA(false), DisableMadd4(false),
-UseIndirectJumpHazard(false), HasFP64(false) {
+UseIndirectJumpHazard(false), FPMode(FPXX) {
TheCXXABI.set(TargetCXXABI::GenericMIPS);
setABI(getTriple().isMIPS32() ? "o32" : "n64");
@@ -181,6 +181,8 @@
return TargetInfo::initF
[PATCH] D49289: [mips64][clang] Provide the signext attribute for i32 return values
This revision was automatically updated to reflect the committed changes.
Closed by commit rC338239: [mips64][clang] Provide the signext attribute for
i32 return values (authored by smaksimovic, committed by ).
Repository:
rC Clang
https://reviews.llvm.org/D49289
Files:
lib/CodeGen/TargetInfo.cpp
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -6985,8 +6985,14 @@
if (const EnumType *EnumTy = RetTy->getAs())
RetTy = EnumTy->getDecl()->getIntegerType();
- return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
- : ABIArgInfo::getDirect());
+ if (RetTy->isPromotableIntegerType())
+return ABIArgInfo::getExtend(RetTy);
+
+ if ((RetTy->isUnsignedIntegerOrEnumerationType() ||
+ RetTy->isSignedIntegerOrEnumerationType()) && Size == 32 && !IsO32)
+return ABIArgInfo::getSignExtend(RetTy);
+
+ return ABIArgInfo::getDirect();
}
void MipsABIInfo::computeInfo(CGFunctionInfo &FI) const {
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -6985,8 +6985,14 @@
if (const EnumType *EnumTy = RetTy->getAs())
RetTy = EnumTy->getDecl()->getIntegerType();
- return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
- : ABIArgInfo::getDirect());
+ if (RetTy->isPromotableIntegerType())
+return ABIArgInfo::getExtend(RetTy);
+
+ if ((RetTy->isUnsignedIntegerOrEnumerationType() ||
+ RetTy->isSignedIntegerOrEnumerationType()) && Size == 32 && !IsO32)
+return ABIArgInfo::getSignExtend(RetTy);
+
+ return ABIArgInfo::getDirect();
}
void MipsABIInfo::computeInfo(CGFunctionInfo &FI) const {
___
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[PATCH] D33401: [mips] Add runtime options to enable/disable generation of madd.fmt, msub.fmt
smaksimovic updated this revision to Diff 101010.
smaksimovic added a comment.
Changed feature name from madd4 to nomadd4 to reflect the change from the
dependency.
Added macro definition when +nomadd4 is present.
https://reviews.llvm.org/D33401
Files:
include/clang/Driver/Options.td
lib/Basic/Targets.cpp
lib/Driver/ToolChains/Arch/Mips.cpp
test/CodeGen/mips-madd4.c
Index: test/CodeGen/mips-madd4.c
===
--- test/CodeGen/mips-madd4.c
+++ test/CodeGen/mips-madd4.c
@@ -0,0 +1,86 @@
+// RUN: %clang --target=mips64-unknown-linux -S -mmadd4%s -o -| FileCheck %s -check-prefix=MADD4
+// RUN: %clang --target=mips64-unknown-linux -S -mno-madd4 %s -o -| FileCheck %s -check-prefix=NOMADD4
+// RUN: %clang --target=mips64-unknown-linux -S -mmadd4-fno-honor-nans %s -o -| FileCheck %s -check-prefix=MADD4-NONAN
+// RUN: %clang --target=mips64-unknown-linux -S -mno-madd4 -fno-honor-nans %s -o -| FileCheck %s -check-prefix=NOMADD4-NONAN
+
+float madd_s (float f, float g, float h)
+{
+ return (f * g) + h;
+}
+// MADD4: madd.s
+// NOMADD4: mul.s
+// NOMADD4: add.s
+
+float msub_s (float f, float g, float h)
+{
+ return (f * g) - h;
+}
+// MADD4: msub.s
+// NOMADD4: mul.s
+// NOMADD4: sub.s
+
+double madd_d (double f, double g, double h)
+{
+ return (f * g) + h;
+}
+// MADD4: madd.d
+// NOMADD4: mul.d
+// NOMADD4: add.d
+
+double msub_d (double f, double g, double h)
+{
+ return (f * g) - h;
+}
+// MADD4: msub.d
+// NOMADD4: mul.d
+// NOMADD4: sub.d
+
+
+float nmadd_s (float f, float g, float h)
+{
+ // FIXME: Zero has been explicitly placed to force generation of a positive
+ // zero in IR until pattern used to match this instruction is changed to
+ // comply with negative zero as well.
+ return 0-((f * g) + h);
+}
+// MADD4-NONAN: nmadd.s
+// NOMADD4-NONAN: mul.s
+// NOMADD4-NONAN: add.s
+// NOMADD4-NONAN: sub.s
+
+float nmsub_s (float f, float g, float h)
+{
+ // FIXME: Zero has been explicitly placed to force generation of a positive
+ // zero in IR until pattern used to match this instruction is changed to
+ // comply with negative zero as well.
+ return 0-((f * g) - h);
+}
+// MADD4-NONAN: nmsub.s
+// NOMADD4-NONAN: mul.s
+// NOMADD4-NONAN: sub.s
+// NOMADD4-NONAN: sub.s
+
+double nmadd_d (double f, double g, double h)
+{
+ // FIXME: Zero has been explicitly placed to force generation of a positive
+ // zero in IR until pattern used to match this instruction is changed to
+ // comply with negative zero as well.
+ return 0-((f * g) + h);
+}
+// MADD4-NONAN: nmadd.d
+// NOMADD4-NONAN: mul.d
+// NOMADD4-NONAN: add.d
+// NOMADD4-NONAN: sub.d
+
+double nmsub_d (double f, double g, double h)
+{
+ // FIXME: Zero has been explicitly placed to force generation of a positive
+ // zero in IR until pattern used to match this instruction is changed to
+ // comply with negative zero as well.
+ return 0-((f * g) - h);
+}
+// MADD4-NONAN: nmsub.d
+// NOMADD4-NONAN: mul.d
+// NOMADD4-NONAN: sub.d
+// NOMADD4-NONAN: sub.d
+
Index: lib/Driver/ToolChains/Arch/Mips.cpp
===
--- lib/Driver/ToolChains/Arch/Mips.cpp
+++ lib/Driver/ToolChains/Arch/Mips.cpp
@@ -298,6 +298,13 @@
AddTargetFeature(Args, Features, options::OPT_mno_odd_spreg,
options::OPT_modd_spreg, "nooddspreg");
+
+ if(Arg *A = Args.getLastArg(options::OPT_mmadd4, options::OPT_mno_madd4)) {
+if(A->getOption().matches(options::OPT_mmadd4))
+ Features.push_back("-nomadd4");
+else
+ Features.push_back("+nomadd4");
+ }
}
mips::NanEncoding mips::getSupportedNanEncoding(StringRef &CPU) {
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -7700,6 +7700,7 @@
NoDSP, DSP1, DSP2
} DspRev;
bool HasMSA;
+ bool DisableMadd4;
protected:
bool HasFP64;
@@ -7710,7 +7711,7 @@
: TargetInfo(Triple), IsMips16(false), IsMicromips(false),
IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false),
CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP),
-HasMSA(false), HasFP64(false) {
+HasMSA(false), DisableMadd4(false), HasFP64(false) {
TheCXXABI.set(TargetCXXABI::GenericMIPS);
setABI((getTriple().getArch() == llvm::Triple::mips ||
@@ -7956,6 +7957,9 @@
if (HasMSA)
Builder.defineMacro("__mips_msa", Twine(1));
+if (DisableMadd4)
+ Builder.defineMacro("__mips_no_madd4", Twine(1));
+
Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
@@ -8118,6 +8122,8 @@
DspRev = std::max(DspRev, DSP2);
else if (Feature == "+msa")
HasMSA = true;
+ else if (Feature == "+nomadd4")
+DisableMadd4 = true;
else if (
[PATCH] D33401: [mips] Add runtime options to enable/disable generation of madd.fmt, msub.fmt
smaksimovic updated this revision to Diff 101562.
smaksimovic added a comment.
Provided define checks, one when the target feature is present, other when the
feature isn't provided at all (default).
https://reviews.llvm.org/D33401
Files:
include/clang/Driver/Options.td
lib/Basic/Targets.cpp
lib/Driver/ToolChains/Arch/Mips.cpp
test/CodeGen/mips-madd4.c
test/Preprocessor/init.c
Index: test/Preprocessor/init.c
===
--- test/Preprocessor/init.c
+++ test/Preprocessor/init.c
@@ -4664,6 +4664,16 @@
// RUN: | FileCheck -match-full-lines -check-prefix MIPS-MSA %s
// MIPS-MSA:#define __mips_msa 1
//
+// RUN: %clang_cc1 -target-feature +nomadd4 \
+// RUN: -E -dM -triple=mips-none-none < /dev/null \
+// RUN: | FileCheck -match-full-lines -check-prefix MIPS-NOMADD4 %s
+// MIPS-NOMADD4:#define __mips_no_madd4 1
+//
+// RUN: %clang_cc1 \
+// RUN: -E -dM -triple=mips-none-none < /dev/null \
+// RUN: | FileCheck -match-full-lines -check-prefix MIPS-MADD4 %s
+// MIPS-MADD4-NOT:#define __mips_no_madd4 1
+//
// RUN: %clang_cc1 -target-cpu mips32r3 -target-feature +nan2008 \
// RUN: -E -dM -triple=mips-none-none < /dev/null \
// RUN: | FileCheck -match-full-lines -check-prefix MIPS-NAN2008 %s
Index: test/CodeGen/mips-madd4.c
===
--- test/CodeGen/mips-madd4.c
+++ test/CodeGen/mips-madd4.c
@@ -0,0 +1,86 @@
+// RUN: %clang --target=mips64-unknown-linux -S -mmadd4%s -o -| FileCheck %s -check-prefix=MADD4
+// RUN: %clang --target=mips64-unknown-linux -S -mno-madd4 %s -o -| FileCheck %s -check-prefix=NOMADD4
+// RUN: %clang --target=mips64-unknown-linux -S -mmadd4-fno-honor-nans %s -o -| FileCheck %s -check-prefix=MADD4-NONAN
+// RUN: %clang --target=mips64-unknown-linux -S -mno-madd4 -fno-honor-nans %s -o -| FileCheck %s -check-prefix=NOMADD4-NONAN
+
+float madd_s (float f, float g, float h)
+{
+ return (f * g) + h;
+}
+// MADD4: madd.s
+// NOMADD4: mul.s
+// NOMADD4: add.s
+
+float msub_s (float f, float g, float h)
+{
+ return (f * g) - h;
+}
+// MADD4: msub.s
+// NOMADD4: mul.s
+// NOMADD4: sub.s
+
+double madd_d (double f, double g, double h)
+{
+ return (f * g) + h;
+}
+// MADD4: madd.d
+// NOMADD4: mul.d
+// NOMADD4: add.d
+
+double msub_d (double f, double g, double h)
+{
+ return (f * g) - h;
+}
+// MADD4: msub.d
+// NOMADD4: mul.d
+// NOMADD4: sub.d
+
+
+float nmadd_s (float f, float g, float h)
+{
+ // FIXME: Zero has been explicitly placed to force generation of a positive
+ // zero in IR until pattern used to match this instruction is changed to
+ // comply with negative zero as well.
+ return 0-((f * g) + h);
+}
+// MADD4-NONAN: nmadd.s
+// NOMADD4-NONAN: mul.s
+// NOMADD4-NONAN: add.s
+// NOMADD4-NONAN: sub.s
+
+float nmsub_s (float f, float g, float h)
+{
+ // FIXME: Zero has been explicitly placed to force generation of a positive
+ // zero in IR until pattern used to match this instruction is changed to
+ // comply with negative zero as well.
+ return 0-((f * g) - h);
+}
+// MADD4-NONAN: nmsub.s
+// NOMADD4-NONAN: mul.s
+// NOMADD4-NONAN: sub.s
+// NOMADD4-NONAN: sub.s
+
+double nmadd_d (double f, double g, double h)
+{
+ // FIXME: Zero has been explicitly placed to force generation of a positive
+ // zero in IR until pattern used to match this instruction is changed to
+ // comply with negative zero as well.
+ return 0-((f * g) + h);
+}
+// MADD4-NONAN: nmadd.d
+// NOMADD4-NONAN: mul.d
+// NOMADD4-NONAN: add.d
+// NOMADD4-NONAN: sub.d
+
+double nmsub_d (double f, double g, double h)
+{
+ // FIXME: Zero has been explicitly placed to force generation of a positive
+ // zero in IR until pattern used to match this instruction is changed to
+ // comply with negative zero as well.
+ return 0-((f * g) - h);
+}
+// MADD4-NONAN: nmsub.d
+// NOMADD4-NONAN: mul.d
+// NOMADD4-NONAN: sub.d
+// NOMADD4-NONAN: sub.d
+
Index: lib/Driver/ToolChains/Arch/Mips.cpp
===
--- lib/Driver/ToolChains/Arch/Mips.cpp
+++ lib/Driver/ToolChains/Arch/Mips.cpp
@@ -298,6 +298,13 @@
AddTargetFeature(Args, Features, options::OPT_mno_odd_spreg,
options::OPT_modd_spreg, "nooddspreg");
+
+ if(Arg *A = Args.getLastArg(options::OPT_mmadd4, options::OPT_mno_madd4)) {
+if(A->getOption().matches(options::OPT_mmadd4))
+ Features.push_back("-nomadd4");
+else
+ Features.push_back("+nomadd4");
+ }
}
mips::NanEncoding mips::getSupportedNanEncoding(StringRef &CPU) {
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -7716,6 +7716,7 @@
NoDSP, DSP1, DSP2
} DspRev;
bool HasMSA;
+ bool DisableMadd4;
protected:
bool HasFP64;
@@ -7726,7 +7727,7 @@
: TargetInfo(Triple), IsMips16(false), IsMicromips(false),
IsNan2008(false
[PATCH] D49289: [mips64][clang] Provide the signext attribute for i32 return values
smaksimovic created this revision.
smaksimovic added a reviewer: atanasyan.
Herald added subscribers: arichardson, sdardis.
Patch for the backend part of the problem here: https://reviews.llvm.org/D48374
https://reviews.llvm.org/D49289
Files:
lib/CodeGen/TargetInfo.cpp
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -6985,8 +6985,14 @@
if (const EnumType *EnumTy = RetTy->getAs())
RetTy = EnumTy->getDecl()->getIntegerType();
- return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
- : ABIArgInfo::getDirect());
+ if (RetTy->isPromotableIntegerType())
+return ABIArgInfo::getExtend(RetTy);
+
+ if ((RetTy->isUnsignedIntegerOrEnumerationType() ||
+ RetTy->isSignedIntegerOrEnumerationType()) && Size == 32 && !IsO32)
+return ABIArgInfo::getSignExtend(RetTy);
+
+ return ABIArgInfo::getDirect();
}
void MipsABIInfo::computeInfo(CGFunctionInfo &FI) const {
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -6985,8 +6985,14 @@
if (const EnumType *EnumTy = RetTy->getAs())
RetTy = EnumTy->getDecl()->getIntegerType();
- return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
- : ABIArgInfo::getDirect());
+ if (RetTy->isPromotableIntegerType())
+return ABIArgInfo::getExtend(RetTy);
+
+ if ((RetTy->isUnsignedIntegerOrEnumerationType() ||
+ RetTy->isSignedIntegerOrEnumerationType()) && Size == 32 && !IsO32)
+return ABIArgInfo::getSignExtend(RetTy);
+
+ return ABIArgInfo::getDirect();
}
void MipsABIInfo::computeInfo(CGFunctionInfo &FI) const {
___
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[PATCH] D31082: [mips][msa] Range adjustment for ldi_b builtin function operand
smaksimovic created this revision.
Reasoning behind this change was allowing the function to accept all values
from range [-128, 255] since all of them can be encoded in an 8bit wide value.
This differs from the prior state where only range [-128, 127] was accepted,
where values were assumed to be signed, whereas now the actual interpretation
of the immediate is deferred to the consumer as required.
https://reviews.llvm.org/D31082
Files:
lib/Sema/SemaChecking.cpp
test/CodeGen/builtins-mips-msa-error.c
Index: test/CodeGen/builtins-mips-msa-error.c
===
--- test/CodeGen/builtins-mips-msa-error.c
+++ test/CodeGen/builtins-mips-msa-error.c
@@ -119,7 +119,7 @@
v4i32_r = __msa_ld_w(&v4i32_a, 512); // expected-error
{{argument should be a value from -512 to 511}}
v2i64_r = __msa_ld_d(&v2i64_a, 512); // expected-error
{{argument should be a value from -512 to 511}}
- v16i8_r = __msa_ldi_b(512);// expected-error
{{argument should be a value from -512 to 511}}
+ v16i8_r = __msa_ldi_b(256);// expected-error
{{argument should be a value from -128 to 255}}
v8i16_r = __msa_ldi_h(512);// expected-error
{{argument should be a value from -512 to 511}}
v4i32_r = __msa_ldi_w(512);// expected-error
{{argument should be a value from -512 to 511}}
v2i64_r = __msa_ldi_d(512);// expected-error
{{argument should be a value from -512 to 511}}
@@ -310,7 +310,7 @@
v4i32_r = __msa_ld_w(&v4i32_a, -513); // expected-error
{{argument should be a value from -512 to 511}}
v2i64_r = __msa_ld_d(&v2i64_a, -513); // expected-error
{{argument should be a value from -512 to 511}}
- v16i8_r = __msa_ldi_b(-513); // expected-error
{{argument should be a value from -512 to 511}}
+ v16i8_r = __msa_ldi_b(-129); // expected-error
{{argument should be a value from -128 to 255}}
v8i16_r = __msa_ldi_h(-513); // expected-error
{{argument should be a value from -512 to 511}}
v4i32_r = __msa_ldi_w(-513); // expected-error
{{argument should be a value from -512 to 511}}
v2i64_r = __msa_ldi_d(-513); // expected-error
{{argument should be a value from -512 to 511}}
Index: lib/Sema/SemaChecking.cpp
===
--- lib/Sema/SemaChecking.cpp
+++ lib/Sema/SemaChecking.cpp
@@ -1640,7 +1640,7 @@
case Mips::BI__builtin_msa_sldi_d: i = 2; l = 0; u = 1; break;
// Memory offsets and immediate loads.
// These intrinsics take a signed 10 bit immediate.
- case Mips::BI__builtin_msa_ldi_b: i = 0; l = -128; u = 127; break;
+ case Mips::BI__builtin_msa_ldi_b: i = 0; l = -128; u = 255; break;
case Mips::BI__builtin_msa_ldi_h:
case Mips::BI__builtin_msa_ldi_w:
case Mips::BI__builtin_msa_ldi_d: i = 0; l = -512; u = 511; break;
Index: test/CodeGen/builtins-mips-msa-error.c
===
--- test/CodeGen/builtins-mips-msa-error.c
+++ test/CodeGen/builtins-mips-msa-error.c
@@ -119,7 +119,7 @@
v4i32_r = __msa_ld_w(&v4i32_a, 512); // expected-error {{argument should be a value from -512 to 511}}
v2i64_r = __msa_ld_d(&v2i64_a, 512); // expected-error {{argument should be a value from -512 to 511}}
- v16i8_r = __msa_ldi_b(512);// expected-error {{argument should be a value from -512 to 511}}
+ v16i8_r = __msa_ldi_b(256);// expected-error {{argument should be a value from -128 to 255}}
v8i16_r = __msa_ldi_h(512);// expected-error {{argument should be a value from -512 to 511}}
v4i32_r = __msa_ldi_w(512);// expected-error {{argument should be a value from -512 to 511}}
v2i64_r = __msa_ldi_d(512);// expected-error {{argument should be a value from -512 to 511}}
@@ -310,7 +310,7 @@
v4i32_r = __msa_ld_w(&v4i32_a, -513); // expected-error {{argument should be a value from -512 to 511}}
v2i64_r = __msa_ld_d(&v2i64_a, -513); // expected-error {{argument should be a value from -512 to 511}}
- v16i8_r = __msa_ldi_b(-513); // expected-error {{argument should be a value from -512 to 511}}
+ v16i8_r = __msa_ldi_b(-129); // expected-error {{argument should be a value from -128 to 255}}
v8i16_r = __msa_ldi_h(-513); // expected-error {{argument should be a value from -512 to 511}}
v4i32_r = __msa_ldi_w(-513); // expected-error {{argument should be a value from -512 to 511}}
v2i64_r = __msa_ldi_d(-513); // expected-error {{argument should be a value from
[PATCH] D31082: [mips][msa] Range adjustment for ldi_b builtin function operand
smaksimovic updated this revision to Diff 92439.
smaksimovic added a comment.
Added a new test to test/CodeGen/builtins-mips-msa.c, covering the new extended
range for ldi.b.
https://reviews.llvm.org/D31082
Files:
lib/Sema/SemaChecking.cpp
test/CodeGen/builtins-mips-msa-error.c
test/CodeGen/builtins-mips-msa.c
Index: test/CodeGen/builtins-mips-msa.c
===
--- test/CodeGen/builtins-mips-msa.c
+++ test/CodeGen/builtins-mips-msa.c
@@ -526,6 +526,8 @@
v2i64_r = __msa_ld_d(&v2i64_a, 96); // CHECK: call <2 x i64>
@llvm.mips.ld.d(
v16i8_r = __msa_ldi_b(3); // CHECK: call <16 x i8> @llvm.mips.ldi.b(
+ v16i8_r = __msa_ldi_b(-128); // CHECK: call <16 x i8> @llvm.mips.ldi.b(
+ v16i8_r = __msa_ldi_b(255); // CHECK: call <16 x i8> @llvm.mips.ldi.b(
v8i16_r = __msa_ldi_h(3); // CHECK: call <8 x i16> @llvm.mips.ldi.h(
v4i32_r = __msa_ldi_w(3); // CHECK: call <4 x i32> @llvm.mips.ldi.w(
v2i64_r = __msa_ldi_d(3); // CHECK: call <2 x i64> @llvm.mips.ldi.d(
Index: test/CodeGen/builtins-mips-msa-error.c
===
--- test/CodeGen/builtins-mips-msa-error.c
+++ test/CodeGen/builtins-mips-msa-error.c
@@ -119,7 +119,7 @@
v4i32_r = __msa_ld_w(&v4i32_a, 512); // expected-error
{{argument should be a value from -512 to 511}}
v2i64_r = __msa_ld_d(&v2i64_a, 512); // expected-error
{{argument should be a value from -512 to 511}}
- v16i8_r = __msa_ldi_b(512);// expected-error
{{argument should be a value from -512 to 511}}
+ v16i8_r = __msa_ldi_b(256);// expected-error
{{argument should be a value from -128 to 255}}
v8i16_r = __msa_ldi_h(512);// expected-error
{{argument should be a value from -512 to 511}}
v4i32_r = __msa_ldi_w(512);// expected-error
{{argument should be a value from -512 to 511}}
v2i64_r = __msa_ldi_d(512);// expected-error
{{argument should be a value from -512 to 511}}
@@ -310,7 +310,7 @@
v4i32_r = __msa_ld_w(&v4i32_a, -513); // expected-error
{{argument should be a value from -512 to 511}}
v2i64_r = __msa_ld_d(&v2i64_a, -513); // expected-error
{{argument should be a value from -512 to 511}}
- v16i8_r = __msa_ldi_b(-513); // expected-error
{{argument should be a value from -512 to 511}}
+ v16i8_r = __msa_ldi_b(-129); // expected-error
{{argument should be a value from -128 to 255}}
v8i16_r = __msa_ldi_h(-513); // expected-error
{{argument should be a value from -512 to 511}}
v4i32_r = __msa_ldi_w(-513); // expected-error
{{argument should be a value from -512 to 511}}
v2i64_r = __msa_ldi_d(-513); // expected-error
{{argument should be a value from -512 to 511}}
Index: lib/Sema/SemaChecking.cpp
===
--- lib/Sema/SemaChecking.cpp
+++ lib/Sema/SemaChecking.cpp
@@ -1640,7 +1640,7 @@
case Mips::BI__builtin_msa_sldi_d: i = 2; l = 0; u = 1; break;
// Memory offsets and immediate loads.
// These intrinsics take a signed 10 bit immediate.
- case Mips::BI__builtin_msa_ldi_b: i = 0; l = -128; u = 127; break;
+ case Mips::BI__builtin_msa_ldi_b: i = 0; l = -128; u = 255; break;
case Mips::BI__builtin_msa_ldi_h:
case Mips::BI__builtin_msa_ldi_w:
case Mips::BI__builtin_msa_ldi_d: i = 0; l = -512; u = 511; break;
Index: test/CodeGen/builtins-mips-msa.c
===
--- test/CodeGen/builtins-mips-msa.c
+++ test/CodeGen/builtins-mips-msa.c
@@ -526,6 +526,8 @@
v2i64_r = __msa_ld_d(&v2i64_a, 96); // CHECK: call <2 x i64> @llvm.mips.ld.d(
v16i8_r = __msa_ldi_b(3); // CHECK: call <16 x i8> @llvm.mips.ldi.b(
+ v16i8_r = __msa_ldi_b(-128); // CHECK: call <16 x i8> @llvm.mips.ldi.b(
+ v16i8_r = __msa_ldi_b(255); // CHECK: call <16 x i8> @llvm.mips.ldi.b(
v8i16_r = __msa_ldi_h(3); // CHECK: call <8 x i16> @llvm.mips.ldi.h(
v4i32_r = __msa_ldi_w(3); // CHECK: call <4 x i32> @llvm.mips.ldi.w(
v2i64_r = __msa_ldi_d(3); // CHECK: call <2 x i64> @llvm.mips.ldi.d(
Index: test/CodeGen/builtins-mips-msa-error.c
===
--- test/CodeGen/builtins-mips-msa-error.c
+++ test/CodeGen/builtins-mips-msa-error.c
@@ -119,7 +119,7 @@
v4i32_r = __msa_ld_w(&v4i32_a, 512); // expected-error {{argument should be a value from -512 to 511}}
v2i64_r = __msa_ld_d(&v2i64_a, 512); // expected-error {{argument should be a value from -512 to 511}}
- v16i8_r = __msa_ldi_b(512);// expected-error {{argument should be a value from -512 to 511}}
+ v16i8_r = __msa_ldi_b(256);// expect
[PATCH] D30693: [mips][msa] Remove range checks for non-immediate sld.[bhwd] instructions
smaksimovic created this revision.
Removes immediate range checks for these instructions, since they have GPR rt
as their input operand.
https://reviews.llvm.org/D30693
Files:
lib/Sema/SemaChecking.cpp
test/CodeGen/builtins-mips-msa-error.c
test/CodeGen/builtins-mips-msa.c
Index: test/CodeGen/builtins-mips-msa.c
===
--- test/CodeGen/builtins-mips-msa.c
+++ test/CodeGen/builtins-mips-msa.c
@@ -698,6 +698,11 @@
v8i16_r = __msa_sld_h(v8i16_r, v8i16_a, 5); // CHECK: call <8 x i16>
@llvm.mips.sld.h(
v4i32_r = __msa_sld_w(v4i32_r, v4i32_a, 3); // CHECK: call <4 x i32>
@llvm.mips.sld.w(
v2i64_r = __msa_sld_d(v2i64_r, v2i64_a, 1); // CHECK: call <2 x i64>
@llvm.mips.sld.d(
+
+ v16i8_r = __msa_sld_b(v16i8_r, v16i8_a, 16); // CHECK: call <16 x i8>
@llvm.mips.sld.b(
+ v8i16_r = __msa_sld_h(v8i16_r, v8i16_a, 8); // CHECK: call <8 x i16>
@llvm.mips.sld.h(
+ v4i32_r = __msa_sld_w(v4i32_r, v4i32_a, 4); // CHECK: call <4 x i32>
@llvm.mips.sld.w(
+ v2i64_r = __msa_sld_d(v2i64_r, v2i64_a, 2); // CHECK: call <2 x i64>
@llvm.mips.sld.d(
v16i8_r = __msa_sldi_b(v16i8_r, v16i8_a, 7); // CHECK: call <16 x i8>
@llvm.mips.sldi.b(
v8i16_r = __msa_sldi_h(v8i16_r, v8i16_a, 3); // CHECK: call <8 x i16>
@llvm.mips.sldi.h(
Index: test/CodeGen/builtins-mips-msa-error.c
===
--- test/CodeGen/builtins-mips-msa-error.c
+++ test/CodeGen/builtins-mips-msa-error.c
@@ -162,11 +162,6 @@
v8i16_r = __msa_shf_h(v8i16_a, 256); // CHECK: warning:
argument should be a value from 0 to 255}}
v4i32_r = __msa_shf_w(v4i32_a, 256); // CHECK: warning:
argument should be a value from 0 to 255}}
- v16i8_r = __msa_sld_b(v16i8_r, v16i8_a, 16); // expected-error
{{argument should be a value from 0 to 15}}
- v8i16_r = __msa_sld_h(v8i16_r, v8i16_a, 8); // expected-error
{{argument should be a value from 0 to 7}}
- v4i32_r = __msa_sld_w(v4i32_r, v4i32_a, 4); // expected-error
{{argument should be a value from 0 to 3}}
- v2i64_r = __msa_sld_d(v2i64_r, v2i64_a, 2); // expected-error
{{argument should be a value from 0 to 1}}
-
v16i8_r = __msa_sldi_b(v16i8_r, v16i8_a, 16); // expected-error
{{argument should be a value from 0 to 15}}
v8i16_r = __msa_sldi_h(v8i16_r, v8i16_a, 8); // expected-error
{{argument should be a value from 0 to 7}}
v4i32_r = __msa_sldi_w(v4i32_r, v4i32_a, 4); // expected-error
{{argument should be a value from 0 to 3}}
@@ -358,11 +353,6 @@
v8i16_r = __msa_shf_h(v8i16_a, -1);// CHECK: warning:
argument should be a value from 0 to 255}}
v4i32_r = __msa_shf_w(v4i32_a, -1);// CHECK: warning:
argument should be a value from 0 to 255}}
- v16i8_r = __msa_sld_b(v16i8_r, v16i8_a, -17); // expected-error
{{argument should be a value from 0 to 15}}
- v8i16_r = __msa_sld_h(v8i16_r, v8i16_a, -8); // expected-error
{{argument should be a value from 0 to 7}}
- v4i32_r = __msa_sld_w(v4i32_r, v4i32_a, -4); // expected-error
{{argument should be a value from 0 to 3}}
- v2i64_r = __msa_sld_d(v2i64_r, v2i64_a, -2); // expected-error
{{argument should be a value from 0 to 1}}
-
v16i8_r = __msa_sldi_b(v16i8_r, v16i8_a, -17); // expected-error
{{argument should be a value from 0 to 15}}
v8i16_r = __msa_sldi_h(v8i16_r, v8i16_a, -8); // expected-error
{{argument should be a value from 0 to 7}}
v4i32_r = __msa_sldi_w(v4i32_r, v4i32_a, -4); // expected-error
{{argument should be a value from 0 to 3}}
Index: lib/Sema/SemaChecking.cpp
===
--- lib/Sema/SemaChecking.cpp
+++ lib/Sema/SemaChecking.cpp
@@ -1619,28 +1619,24 @@
case Mips::BI__builtin_msa_copy_u_b:
case Mips::BI__builtin_msa_insve_b:
case Mips::BI__builtin_msa_splati_b: i = 1; l = 0; u = 15; break;
- case Mips::BI__builtin_msa_sld_b:
case Mips::BI__builtin_msa_sldi_b: i = 2; l = 0; u = 15; break;
// These intrinsics take an unsigned 3 bit immediate.
case Mips::BI__builtin_msa_copy_s_h:
case Mips::BI__builtin_msa_copy_u_h:
case Mips::BI__builtin_msa_insve_h:
case Mips::BI__builtin_msa_splati_h: i = 1; l = 0; u = 7; break;
- case Mips::BI__builtin_msa_sld_h:
case Mips::BI__builtin_msa_sldi_h: i = 2; l = 0; u = 7; break;
// These intrinsics take an unsigned 2 bit immediate.
case Mips::BI__builtin_msa_copy_s_w:
case Mips::BI__builtin_msa_copy_u_w:
case Mips::BI__builtin_msa_insve_w:
case Mips::BI__builtin_msa_splati_w: i = 1; l = 0; u = 3; break;
- case Mips::BI__builtin_msa_sld_w:
case Mips::BI__builtin_msa_sldi_w: i = 2; l = 0; u = 3; break;
// These intrinsics take an unsigned 1 bit immediate.
case Mips::BI__builtin_msa_copy_s_d:
case Mips::BI__builtin_msa_copy_u_d:
case Mips::BI__builtin_msa_insve_d:
case Mips::BI__bui
[PATCH] D30693: [mips][msa] Remove range checks for non-immediate sld.[bhwd] instructions
smaksimovic updated this revision to Diff 91158.
smaksimovic added a comment.
Removed whitespace.
https://reviews.llvm.org/D30693
Files:
lib/Sema/SemaChecking.cpp
test/CodeGen/builtins-mips-msa-error.c
test/CodeGen/builtins-mips-msa.c
Index: test/CodeGen/builtins-mips-msa.c
===
--- test/CodeGen/builtins-mips-msa.c
+++ test/CodeGen/builtins-mips-msa.c
@@ -699,6 +699,11 @@
v4i32_r = __msa_sld_w(v4i32_r, v4i32_a, 3); // CHECK: call <4 x i32>
@llvm.mips.sld.w(
v2i64_r = __msa_sld_d(v2i64_r, v2i64_a, 1); // CHECK: call <2 x i64>
@llvm.mips.sld.d(
+ v16i8_r = __msa_sld_b(v16i8_r, v16i8_a, 16); // CHECK: call <16 x i8>
@llvm.mips.sld.b(
+ v8i16_r = __msa_sld_h(v8i16_r, v8i16_a, 8); // CHECK: call <8 x i16>
@llvm.mips.sld.h(
+ v4i32_r = __msa_sld_w(v4i32_r, v4i32_a, 4); // CHECK: call <4 x i32>
@llvm.mips.sld.w(
+ v2i64_r = __msa_sld_d(v2i64_r, v2i64_a, 2); // CHECK: call <2 x i64>
@llvm.mips.sld.d(
+
v16i8_r = __msa_sldi_b(v16i8_r, v16i8_a, 7); // CHECK: call <16 x i8>
@llvm.mips.sldi.b(
v8i16_r = __msa_sldi_h(v8i16_r, v8i16_a, 3); // CHECK: call <8 x i16>
@llvm.mips.sldi.h(
v4i32_r = __msa_sldi_w(v4i32_r, v4i32_a, 2); // CHECK: call <4 x i32>
@llvm.mips.sldi.w(
Index: test/CodeGen/builtins-mips-msa-error.c
===
--- test/CodeGen/builtins-mips-msa-error.c
+++ test/CodeGen/builtins-mips-msa-error.c
@@ -162,11 +162,6 @@
v8i16_r = __msa_shf_h(v8i16_a, 256); // CHECK: warning:
argument should be a value from 0 to 255}}
v4i32_r = __msa_shf_w(v4i32_a, 256); // CHECK: warning:
argument should be a value from 0 to 255}}
- v16i8_r = __msa_sld_b(v16i8_r, v16i8_a, 16); // expected-error
{{argument should be a value from 0 to 15}}
- v8i16_r = __msa_sld_h(v8i16_r, v8i16_a, 8); // expected-error
{{argument should be a value from 0 to 7}}
- v4i32_r = __msa_sld_w(v4i32_r, v4i32_a, 4); // expected-error
{{argument should be a value from 0 to 3}}
- v2i64_r = __msa_sld_d(v2i64_r, v2i64_a, 2); // expected-error
{{argument should be a value from 0 to 1}}
-
v16i8_r = __msa_sldi_b(v16i8_r, v16i8_a, 16); // expected-error
{{argument should be a value from 0 to 15}}
v8i16_r = __msa_sldi_h(v8i16_r, v8i16_a, 8); // expected-error
{{argument should be a value from 0 to 7}}
v4i32_r = __msa_sldi_w(v4i32_r, v4i32_a, 4); // expected-error
{{argument should be a value from 0 to 3}}
@@ -358,11 +353,6 @@
v8i16_r = __msa_shf_h(v8i16_a, -1);// CHECK: warning:
argument should be a value from 0 to 255}}
v4i32_r = __msa_shf_w(v4i32_a, -1);// CHECK: warning:
argument should be a value from 0 to 255}}
- v16i8_r = __msa_sld_b(v16i8_r, v16i8_a, -17); // expected-error
{{argument should be a value from 0 to 15}}
- v8i16_r = __msa_sld_h(v8i16_r, v8i16_a, -8); // expected-error
{{argument should be a value from 0 to 7}}
- v4i32_r = __msa_sld_w(v4i32_r, v4i32_a, -4); // expected-error
{{argument should be a value from 0 to 3}}
- v2i64_r = __msa_sld_d(v2i64_r, v2i64_a, -2); // expected-error
{{argument should be a value from 0 to 1}}
-
v16i8_r = __msa_sldi_b(v16i8_r, v16i8_a, -17); // expected-error
{{argument should be a value from 0 to 15}}
v8i16_r = __msa_sldi_h(v8i16_r, v8i16_a, -8); // expected-error
{{argument should be a value from 0 to 7}}
v4i32_r = __msa_sldi_w(v4i32_r, v4i32_a, -4); // expected-error
{{argument should be a value from 0 to 3}}
Index: lib/Sema/SemaChecking.cpp
===
--- lib/Sema/SemaChecking.cpp
+++ lib/Sema/SemaChecking.cpp
@@ -1619,28 +1619,24 @@
case Mips::BI__builtin_msa_copy_u_b:
case Mips::BI__builtin_msa_insve_b:
case Mips::BI__builtin_msa_splati_b: i = 1; l = 0; u = 15; break;
- case Mips::BI__builtin_msa_sld_b:
case Mips::BI__builtin_msa_sldi_b: i = 2; l = 0; u = 15; break;
// These intrinsics take an unsigned 3 bit immediate.
case Mips::BI__builtin_msa_copy_s_h:
case Mips::BI__builtin_msa_copy_u_h:
case Mips::BI__builtin_msa_insve_h:
case Mips::BI__builtin_msa_splati_h: i = 1; l = 0; u = 7; break;
- case Mips::BI__builtin_msa_sld_h:
case Mips::BI__builtin_msa_sldi_h: i = 2; l = 0; u = 7; break;
// These intrinsics take an unsigned 2 bit immediate.
case Mips::BI__builtin_msa_copy_s_w:
case Mips::BI__builtin_msa_copy_u_w:
case Mips::BI__builtin_msa_insve_w:
case Mips::BI__builtin_msa_splati_w: i = 1; l = 0; u = 3; break;
- case Mips::BI__builtin_msa_sld_w:
case Mips::BI__builtin_msa_sldi_w: i = 2; l = 0; u = 3; break;
// These intrinsics take an unsigned 1 bit immediate.
case Mips::BI__builtin_msa_copy_s_d:
case Mips::BI__builtin_msa_copy_u_d:
case Mips::BI__builtin_msa_insve_d:
case Mips::BI__builtin_msa_splati_d: i = 1; l = 0; u = 1;
[PATCH] D32900: [mips] Impose a threshold for coercion of aggregates
smaksimovic created this revision.
Herald added a subscriber: arichardson.
Modified MipsABIInfo::classifyArgumentType so that it now coerces aggregate
structures
only if the size of said aggregate is less than 16/64 bytes, depending on the
ABI.
https://reviews.llvm.org/D32900
Files:
lib/CodeGen/TargetInfo.cpp
test/CodeGen/mips-aggregate-arg.c
Index: test/CodeGen/mips-aggregate-arg.c
===
--- test/CodeGen/mips-aggregate-arg.c
+++ test/CodeGen/mips-aggregate-arg.c
@@ -0,0 +1,38 @@
+// RUN: %clang_cc1 -triple mipsel-unknown-linux-gnu -S -emit-llvm -o - %s |
FileCheck -check-prefix=O32 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s
-target-abi n32 | FileCheck -check-prefix=N32-N64 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s
-target-abi n64| FileCheck -check-prefix=N32-N64 %s
+
+struct t1 {
+ char t1[10];
+};
+
+struct t2 {
+ char t2[20];
+};
+
+struct t3 {
+ char t3[65];
+};
+
+extern struct t1 g1;
+extern struct t2 g2;
+extern struct t3 g3;
+extern void f1(struct t1);
+extern void f2(struct t2);
+extern void f3(struct t3);
+
+void f() {
+
+// O32: call void @f1(i32 inreg %3, i32 inreg %5, i16 inreg %7)
+// O32: call void @f2(%struct.t2* byval align 4 %tmp)
+// O32: call void @f3(%struct.t3* byval align 4 %tmp1)
+
+// N32-N64: call void @f1(i64 inreg %3, i16 inreg %5)
+// N32-N64: call void @f2(i64 inreg %9, i64 inreg %11, i32 inreg %13)
+// N32-N64: call void @f3(%struct.t3* byval align 8 %tmp)
+
+ f1(g1);
+ f2(g2);
+ f3(g3);
+}
+
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -6696,6 +6696,14 @@
return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
}
+// Use indirect if the aggregate cannot fit into registers for
+// passing arguments according to the ABI
+unsigned Threshold = IsO32 ? 16 : 64;
+
+if(getContext().getTypeSizeInChars(Ty) >
CharUnits::fromQuantity(Threshold))
+ return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align), true,
+ getContext().getTypeAlign(Ty) / 8 >
Align);
+
// If we have reached here, aggregates are passed directly by coercing to
// another structure type. Padding is inserted if the offset of the
// aggregate is unaligned.
Index: test/CodeGen/mips-aggregate-arg.c
===
--- test/CodeGen/mips-aggregate-arg.c
+++ test/CodeGen/mips-aggregate-arg.c
@@ -0,0 +1,38 @@
+// RUN: %clang_cc1 -triple mipsel-unknown-linux-gnu -S -emit-llvm -o - %s | FileCheck -check-prefix=O32 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s -target-abi n32 | FileCheck -check-prefix=N32-N64 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s -target-abi n64| FileCheck -check-prefix=N32-N64 %s
+
+struct t1 {
+ char t1[10];
+};
+
+struct t2 {
+ char t2[20];
+};
+
+struct t3 {
+ char t3[65];
+};
+
+extern struct t1 g1;
+extern struct t2 g2;
+extern struct t3 g3;
+extern void f1(struct t1);
+extern void f2(struct t2);
+extern void f3(struct t3);
+
+void f() {
+
+// O32: call void @f1(i32 inreg %3, i32 inreg %5, i16 inreg %7)
+// O32: call void @f2(%struct.t2* byval align 4 %tmp)
+// O32: call void @f3(%struct.t3* byval align 4 %tmp1)
+
+// N32-N64: call void @f1(i64 inreg %3, i16 inreg %5)
+// N32-N64: call void @f2(i64 inreg %9, i64 inreg %11, i32 inreg %13)
+// N32-N64: call void @f3(%struct.t3* byval align 8 %tmp)
+
+ f1(g1);
+ f2(g2);
+ f3(g3);
+}
+
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -6696,6 +6696,14 @@
return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
}
+// Use indirect if the aggregate cannot fit into registers for
+// passing arguments according to the ABI
+unsigned Threshold = IsO32 ? 16 : 64;
+
+if(getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(Threshold))
+ return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align), true,
+ getContext().getTypeAlign(Ty) / 8 > Align);
+
// If we have reached here, aggregates are passed directly by coercing to
// another structure type. Padding is inserted if the offset of the
// aggregate is unaligned.
___
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cfe-commits@lists.llvm.org
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[PATCH] D32900: [mips] Impose a threshold for coercion of aggregates
smaksimovic updated this revision to Diff 98269.
smaksimovic added a comment.
Herald added a subscriber: krytarowski.
Thanks, fixed.
https://reviews.llvm.org/D32900
Files:
lib/CodeGen/TargetInfo.cpp
test/CodeGen/mips-aggregate-arg.c
Index: test/CodeGen/mips-aggregate-arg.c
===
--- test/CodeGen/mips-aggregate-arg.c
+++ test/CodeGen/mips-aggregate-arg.c
@@ -0,0 +1,38 @@
+// RUN: %clang_cc1 -triple mipsel-unknown-linux-gnu -S -emit-llvm -o - %s |
FileCheck -check-prefix=O32 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s
-target-abi n32 | FileCheck -check-prefix=N32-N64 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s
-target-abi n64 | FileCheck -check-prefix=N32-N64 %s
+
+struct t1 {
+ char t1[10];
+};
+
+struct t2 {
+ char t2[20];
+};
+
+struct t3 {
+ char t3[65];
+};
+
+extern struct t1 g1;
+extern struct t2 g2;
+extern struct t3 g3;
+extern void f1(struct t1);
+extern void f2(struct t2);
+extern void f3(struct t3);
+
+void f() {
+
+// O32: call void @f1(i32 inreg %3, i32 inreg %5, i16 inreg %7)
+// O32: call void @f2(%struct.t2* byval align 4 %tmp)
+// O32: call void @f3(%struct.t3* byval align 4 %tmp1)
+
+// N32-N64: call void @f1(i64 inreg %3, i16 inreg %5)
+// N32-N64: call void @f2(i64 inreg %9, i64 inreg %11, i32 inreg %13)
+// N32-N64: call void @f3(%struct.t3* byval align 8 %tmp)
+
+ f1(g1);
+ f2(g2);
+ f3(g3);
+}
+
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -6696,6 +6696,14 @@
return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
}
+// Use indirect if the aggregate cannot fit into registers for
+// passing arguments according to the ABI
+unsigned Threshold = IsO32 ? 16 : 64;
+
+if(getContext().getTypeSizeInChars(Ty) >
CharUnits::fromQuantity(Threshold))
+ return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align), true,
+ getContext().getTypeAlign(Ty) / 8 >
Align);
+
// If we have reached here, aggregates are passed directly by coercing to
// another structure type. Padding is inserted if the offset of the
// aggregate is unaligned.
Index: test/CodeGen/mips-aggregate-arg.c
===
--- test/CodeGen/mips-aggregate-arg.c
+++ test/CodeGen/mips-aggregate-arg.c
@@ -0,0 +1,38 @@
+// RUN: %clang_cc1 -triple mipsel-unknown-linux-gnu -S -emit-llvm -o - %s | FileCheck -check-prefix=O32 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s -target-abi n32 | FileCheck -check-prefix=N32-N64 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s -target-abi n64 | FileCheck -check-prefix=N32-N64 %s
+
+struct t1 {
+ char t1[10];
+};
+
+struct t2 {
+ char t2[20];
+};
+
+struct t3 {
+ char t3[65];
+};
+
+extern struct t1 g1;
+extern struct t2 g2;
+extern struct t3 g3;
+extern void f1(struct t1);
+extern void f2(struct t2);
+extern void f3(struct t3);
+
+void f() {
+
+// O32: call void @f1(i32 inreg %3, i32 inreg %5, i16 inreg %7)
+// O32: call void @f2(%struct.t2* byval align 4 %tmp)
+// O32: call void @f3(%struct.t3* byval align 4 %tmp1)
+
+// N32-N64: call void @f1(i64 inreg %3, i16 inreg %5)
+// N32-N64: call void @f2(i64 inreg %9, i64 inreg %11, i32 inreg %13)
+// N32-N64: call void @f3(%struct.t3* byval align 8 %tmp)
+
+ f1(g1);
+ f2(g2);
+ f3(g3);
+}
+
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -6696,6 +6696,14 @@
return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
}
+// Use indirect if the aggregate cannot fit into registers for
+// passing arguments according to the ABI
+unsigned Threshold = IsO32 ? 16 : 64;
+
+if(getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(Threshold))
+ return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align), true,
+ getContext().getTypeAlign(Ty) / 8 > Align);
+
// If we have reached here, aggregates are passed directly by coercing to
// another structure type. Padding is inserted if the offset of the
// aggregate is unaligned.
___
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[PATCH] D33401: [mips] Add runtime options to enable/disable generation of madd.fmt, msub.fmt
smaksimovic created this revision.
Herald added a subscriber: arichardson.
Added options to clang are -mmadd4 and -mno-madd4, used to enable or disable
generation
of madd.fmt and similar instructions respectively, as per GCC.
https://reviews.llvm.org/D33401
Files:
include/clang/Driver/Options.td
lib/Driver/ToolChains/Arch/Mips.cpp
test/CodeGen/mips-madd4.c
Index: test/CodeGen/mips-madd4.c
===
--- test/CodeGen/mips-madd4.c
+++ test/CodeGen/mips-madd4.c
@@ -0,0 +1,86 @@
+// RUN: %clang --target=mips64-unknown-linux -S -mmadd4%s -o -| FileCheck %s -check-prefix=MADD4
+// RUN: %clang --target=mips64-unknown-linux -S -mno-madd4 %s -o -| FileCheck %s -check-prefix=NOMADD4
+// RUN: %clang --target=mips64-unknown-linux -S -mmadd4-fno-honor-nans %s -o -| FileCheck %s -check-prefix=MADD4-NONAN
+// RUN: %clang --target=mips64-unknown-linux -S -mno-madd4 -fno-honor-nans %s -o -| FileCheck %s -check-prefix=NOMADD4-NONAN
+
+float madd_s (float f, float g, float h)
+{
+ return (f * g) + h;
+}
+// MADD4: madd.s
+// NOMADD4: mul.s
+// NOMADD4: add.s
+
+float msub_s (float f, float g, float h)
+{
+ return (f * g) - h;
+}
+// MADD4: msub.s
+// NOMADD4: mul.s
+// NOMADD4: sub.s
+
+double madd_d (double f, double g, double h)
+{
+ return (f * g) + h;
+}
+// MADD4: madd.d
+// NOMADD4: mul.d
+// NOMADD4: add.d
+
+double msub_d (double f, double g, double h)
+{
+ return (f * g) - h;
+}
+// MADD4: msub.d
+// NOMADD4: mul.d
+// NOMADD4: sub.d
+
+
+float nmadd_s (float f, float g, float h)
+{
+ // FIXME: Zero has been explicitly placed to force generation of a positive
+ // zero in IR until pattern used to match this instruction is changed to
+ // comply with negative zero as well.
+ return 0-((f * g) + h);
+}
+// MADD4-NONAN: nmadd.s
+// NOMADD4-NONAN: mul.s
+// NOMADD4-NONAN: add.s
+// NOMADD4-NONAN: sub.s
+
+float nmsub_s (float f, float g, float h)
+{
+ // FIXME: Zero has been explicitly placed to force generation of a positive
+ // zero in IR until pattern used to match this instruction is changed to
+ // comply with negative zero as well.
+ return 0-((f * g) - h);
+}
+// MADD4-NONAN: nmsub.s
+// NOMADD4-NONAN: mul.s
+// NOMADD4-NONAN: sub.s
+// NOMADD4-NONAN: sub.s
+
+double nmadd_d (double f, double g, double h)
+{
+ // FIXME: Zero has been explicitly placed to force generation of a positive
+ // zero in IR until pattern used to match this instruction is changed to
+ // comply with negative zero as well.
+ return 0-((f * g) + h);
+}
+// MADD4-NONAN: nmadd.d
+// NOMADD4-NONAN: mul.d
+// NOMADD4-NONAN: add.d
+// NOMADD4-NONAN: sub.d
+
+double nmsub_d (double f, double g, double h)
+{
+ // FIXME: Zero has been explicitly placed to force generation of a positive
+ // zero in IR until pattern used to match this instruction is changed to
+ // comply with negative zero as well.
+ return 0-((f * g) - h);
+}
+// MADD4-NONAN: nmsub.d
+// NOMADD4-NONAN: mul.d
+// NOMADD4-NONAN: sub.d
+// NOMADD4-NONAN: sub.d
+
Index: lib/Driver/ToolChains/Arch/Mips.cpp
===
--- lib/Driver/ToolChains/Arch/Mips.cpp
+++ lib/Driver/ToolChains/Arch/Mips.cpp
@@ -298,6 +298,13 @@
AddTargetFeature(Args, Features, options::OPT_mno_odd_spreg,
options::OPT_modd_spreg, "nooddspreg");
+
+ if(Arg *A = Args.getLastArg(options::OPT_mmadd4, options::OPT_mno_madd4)) {
+if(A->getOption().matches(options::OPT_mmadd4))
+ Features.push_back("+madd4");
+else
+ Features.push_back("-madd4");
+ }
}
mips::NanEncoding mips::getSupportedNanEncoding(StringRef &CPU) {
Index: include/clang/Driver/Options.td
===
--- include/clang/Driver/Options.td
+++ include/clang/Driver/Options.td
@@ -1998,6 +1998,10 @@
def mno_dspr2 : Flag<["-"], "mno-dspr2">, Group;
def msingle_float : Flag<["-"], "msingle-float">, Group;
def mdouble_float : Flag<["-"], "mdouble-float">, Group;
+def mmadd4 : Flag<["-"], "mmadd4">, Group,
+ HelpText<"Enable the generation of 4-operand madd.s, madd.d and related instructions.">;
+def mno_madd4 : Flag<["-"], "mno-madd4">, Group,
+ HelpText<"Disable the generation of 4-operand madd.s, madd.d and related instructions.">;
def mmsa : Flag<["-"], "mmsa">, Group,
HelpText<"Enable MSA ASE (MIPS only)">;
def mno_msa : Flag<["-"], "mno-msa">, Group,
___
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