r367399 - [RISCV] Add support for floating point registers in inlineasm
Author: simoncook
Date: Wed Jul 31 02:12:00 2019
New Revision: 367399
URL: http://llvm.org/viewvc/llvm-project?rev=367399&view=rev
Log:
[RISCV] Add support for floating point registers in inlineasm
This adds support for parsing/emitting in IR the floating-point RISC-V
registers in inline assembly clobber lists.
Differential Revision: https://reviews.llvm.org/D64737
Added:
cfe/trunk/test/Sema/riscv-asm.c
Modified:
cfe/trunk/lib/Basic/Targets/RISCV.cpp
Modified: cfe/trunk/lib/Basic/Targets/RISCV.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/RISCV.cpp?rev=367399&r1=367398&r2=367399&view=diff
==
--- cfe/trunk/lib/Basic/Targets/RISCV.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/RISCV.cpp Wed Jul 31 02:12:00 2019
@@ -19,23 +19,38 @@ using namespace clang::targets;
ArrayRef RISCVTargetInfo::getGCCRegNames() const {
static const char *const GCCRegNames[] = {
+ // Integer registers
"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
"x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
- "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31"};
+ "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
+
+ // Floating point registers
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
return llvm::makeArrayRef(GCCRegNames);
}
ArrayRef RISCVTargetInfo::getGCCRegAliases() const {
static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
- {{"zero"}, "x0"}, {{"ra"}, "x1"}, {{"sp"}, "x2"}, {{"gp"}, "x3"},
- {{"tp"}, "x4"}, {{"t0"}, "x5"}, {{"t1"}, "x6"}, {{"t2"}, "x7"},
- {{"s0"}, "x8"}, {{"s1"}, "x9"}, {{"a0"}, "x10"}, {{"a1"}, "x11"},
- {{"a2"}, "x12"}, {{"a3"}, "x13"}, {{"a4"}, "x14"}, {{"a5"}, "x15"},
- {{"a6"}, "x16"}, {{"a7"}, "x17"}, {{"s2"}, "x18"}, {{"s3"}, "x19"},
- {{"s4"}, "x20"}, {{"s5"}, "x21"}, {{"s6"}, "x22"}, {{"s7"}, "x23"},
- {{"s8"}, "x24"}, {{"s9"}, "x25"}, {{"s10"}, "x26"}, {{"s11"}, "x27"},
- {{"t3"}, "x28"}, {{"t4"}, "x29"}, {{"t5"}, "x30"}, {{"t6"}, "x31"}};
+ {{"zero"}, "x0"}, {{"ra"}, "x1"}, {{"sp"}, "x2"},{{"gp"}, "x3"},
+ {{"tp"}, "x4"}, {{"t0"}, "x5"}, {{"t1"}, "x6"},{{"t2"}, "x7"},
+ {{"s0"}, "x8"}, {{"s1"}, "x9"}, {{"a0"}, "x10"}, {{"a1"}, "x11"},
+ {{"a2"}, "x12"}, {{"a3"}, "x13"}, {{"a4"}, "x14"}, {{"a5"}, "x15"},
+ {{"a6"}, "x16"}, {{"a7"}, "x17"}, {{"s2"}, "x18"}, {{"s3"}, "x19"},
+ {{"s4"}, "x20"}, {{"s5"}, "x21"}, {{"s6"}, "x22"}, {{"s7"}, "x23"},
+ {{"s8"}, "x24"}, {{"s9"}, "x25"}, {{"s10"}, "x26"}, {{"s11"}, "x27"},
+ {{"t3"}, "x28"}, {{"t4"}, "x29"}, {{"t5"}, "x30"}, {{"t6"}, "x31"},
+ {{"ft0"}, "f0"}, {{"ft1"}, "f1"}, {{"ft2"}, "f2"}, {{"ft3"}, "f3"},
+ {{"ft4"}, "f4"}, {{"ft5"}, "f5"}, {{"ft6"}, "f6"}, {{"ft7"}, "f7"},
+ {{"fs0"}, "f8"}, {{"fs1"}, "f9"}, {{"fa0"}, "f10"}, {{"fa1"}, "f11"},
+ {{"fa2"}, "f12"}, {{"fa3"}, "f13"}, {{"fa4"}, "f14"}, {{"fa5"}, "f15"},
+ {{"fa6"}, "f16"}, {{"fa7"}, "f17"}, {{"fs2"}, "f18"}, {{"fs3"}, "f19"},
+ {{"fs4"}, "f20"}, {{"fs5"}, "f21"}, {{"fs6"}, "f22"}, {{"fs7"}, "f23"},
+ {{"fs8"}, "f24"}, {{"fs9"}, "f25"}, {{"fs10"}, "f26"}, {{"fs11"}, "f27"},
+ {{"ft8"}, "f28"}, {{"ft9"}, "f29"}, {{"ft10"}, "f30"}, {{"ft11"},
"f31"}};
return llvm::makeArrayRef(GCCRegAliases);
}
Added: cfe/trunk/test/Sema/riscv-asm.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Sema/riscv-asm.c?rev=367399&view=auto
==
--- cfe/trunk/test/Sema/riscv-asm.c (added)
+++ cfe/trunk/test/Sema/riscv-asm.c Wed Jul 31 02:12:00 2019
@@ -0,0 +1,28 @@
+// RUN: %clang_cc1 %s -triple riscv32 -verify -fsyntax-only
+// RUN: %clang_cc1 %s -triple riscv64 -verify -fsyntax-only
+
+// expected-no-diagnostics
+
+void i (void) {
+ asm volatile ("" ::: "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7");
+ asm volatile ("" ::: "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15");
+ asm volatile ("" ::: "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23");
+ asm volatile ("" ::: "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31");
+
+ asm volatile ("" ::: "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2");
+ asm volatile ("" ::: "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5");
+ asm volatile ("" ::: "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7");
+ asm volatile ("" ::: "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6");
+}
+
+void f (void) {
+ asm volatile ("" ::: "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7");
+ asm volatile ("" ::: "f8", "f9",
[clang] aed9d6d - [RISCV] Add support for -ffixed-xX flags
Author: Simon Cook
Date: 2019-10-22T21:25:01+01:00
New Revision: aed9d6d64a38d155cd09232da5640b5ade069bd9
URL:
https://github.com/llvm/llvm-project/commit/aed9d6d64a38d155cd09232da5640b5ade069bd9
DIFF:
https://github.com/llvm/llvm-project/commit/aed9d6d64a38d155cd09232da5640b5ade069bd9.diff
LOG: [RISCV] Add support for -ffixed-xX flags
This adds support for reserving GPRs such that the compiler will not
choose a register for register allocation. The implementation follows
the same design as for AArch64; each reserved register becomes a target
feature and used for getting the reserved registers for a given
MachineFunction. The backend checks that it does not need to write to
any reserved register; if it does a relevant error is generated.
Differential Revision: https://reviews.llvm.org/D67185
Added:
clang/test/Driver/riscv-fixed-x-register.c
llvm/test/CodeGen/RISCV/reserved-reg-errors.ll
llvm/test/CodeGen/RISCV/reserved-regs.ll
Modified:
clang/include/clang/Driver/Options.td
clang/lib/Driver/ToolChains/Arch/RISCV.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
llvm/lib/Target/RISCV/RISCVRegisterInfo.h
llvm/lib/Target/RISCV/RISCVSubtarget.cpp
llvm/lib/Target/RISCV/RISCVSubtarget.h
Removed:
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 4db7cd844d15..20d7c241a937 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -2263,9 +2263,9 @@ def mfix_cortex_a53_835769 : Flag<["-"],
"mfix-cortex-a53-835769">,
def mno_fix_cortex_a53_835769 : Flag<["-"], "mno-fix-cortex-a53-835769">,
Group,
HelpText<"Don't workaround Cortex-A53 erratum 835769 (AArch64 only)">;
-foreach i = {1-7,9-15,18,20-28} in
- def ffixed_x#i : Flag<["-"], "ffixed-x"#i>, Group,
-HelpText<"Reserve the "#i#" register (AArch64 only)">;
+foreach i = {1-31} in
+ def ffixed_x#i : Flag<["-"], "ffixed-x"#i>, Group,
+HelpText<"Reserve the "#i#" register (AArch64/RISC-V only)">;
foreach i = {8-15,18} in
def fcall_saved_x#i : Flag<["-"], "fcall-saved-x"#i>,
Group,
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 624788a5874e..a26f723a5073 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -367,6 +367,70 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
if (MArch.hasValue() && !getArchFeatures(D, *MArch, Features, Args))
return;
+ // Handle features corresponding to "-ffixed-X" options
+ if (Args.hasArg(options::OPT_ffixed_x1))
+Features.push_back("+reserve-x1");
+ if (Args.hasArg(options::OPT_ffixed_x2))
+Features.push_back("+reserve-x2");
+ if (Args.hasArg(options::OPT_ffixed_x3))
+Features.push_back("+reserve-x3");
+ if (Args.hasArg(options::OPT_ffixed_x4))
+Features.push_back("+reserve-x4");
+ if (Args.hasArg(options::OPT_ffixed_x5))
+Features.push_back("+reserve-x5");
+ if (Args.hasArg(options::OPT_ffixed_x6))
+Features.push_back("+reserve-x6");
+ if (Args.hasArg(options::OPT_ffixed_x7))
+Features.push_back("+reserve-x7");
+ if (Args.hasArg(options::OPT_ffixed_x8))
+Features.push_back("+reserve-x8");
+ if (Args.hasArg(options::OPT_ffixed_x9))
+Features.push_back("+reserve-x9");
+ if (Args.hasArg(options::OPT_ffixed_x10))
+Features.push_back("+reserve-x10");
+ if (Args.hasArg(options::OPT_ffixed_x11))
+Features.push_back("+reserve-x11");
+ if (Args.hasArg(options::OPT_ffixed_x12))
+Features.push_back("+reserve-x12");
+ if (Args.hasArg(options::OPT_ffixed_x13))
+Features.push_back("+reserve-x13");
+ if (Args.hasArg(options::OPT_ffixed_x14))
+Features.push_back("+reserve-x14");
+ if (Args.hasArg(options::OPT_ffixed_x15))
+Features.push_back("+reserve-x15");
+ if (Args.hasArg(options::OPT_ffixed_x16))
+Features.push_back("+reserve-x16");
+ if (Args.hasArg(options::OPT_ffixed_x17))
+Features.push_back("+reserve-x17");
+ if (Args.hasArg(options::OPT_ffixed_x18))
+Features.push_back("+reserve-x18");
+ if (Args.hasArg(options::OPT_ffixed_x19))
+Features.push_back("+reserve-x19");
+ if (Args.hasArg(options::OPT_ffixed_x20))
+Features.push_back("+reserve-x20");
+ if (Args.hasArg(options::OPT_ffixed_x21))
+Features.push_back("+reserve-x21");
+ if (Args.hasArg(options::OPT_ffixed_x22))
+Features.push_back("+reserve-x22");
+ if (Args.hasArg(options::OPT_ffixed_x23))
+Features.push_back("+reserve-x23");
+ if (Args.hasArg(options::OPT_ffixed_x24))
+Features.push_back("+reserve-x24");
+ if (Args.hasArg(options::OPT_ffixed_x25))
+Features.push_back("+reserve-x25"
[clang] dd1ee6d - [RISCV] Support experimental/unratified extensions
Author: Simon Cook
Date: 2020-04-09T18:04:22+01:00
New Revision: dd1ee6dc076fe1da6cf6eeb9cf614d9c1796759a
URL:
https://github.com/llvm/llvm-project/commit/dd1ee6dc076fe1da6cf6eeb9cf614d9c1796759a
DIFF:
https://github.com/llvm/llvm-project/commit/dd1ee6dc076fe1da6cf6eeb9cf614d9c1796759a.diff
LOG: [RISCV] Support experimental/unratified extensions
This adds support for enabling experimental/unratified RISC-V ISA
extensions in the -march string in the case where an explicit version
number has been declared, and the -menable-experimental-extensions flag
has been provided.
This follows the design as discussed on the mailing lists in the
following RFC: http://lists.llvm.org/pipermail/llvm-dev/2020-January/138364.html
Since the RISC-V toolchain definition currently rejects any extension
with an explicit version number, the parsing logic has been tweaked to
support this, and to allow standard extensions to have their versions
checked in future patches.
The bitmanip 'b' extension has been added as a first use of this support,
it should easily extend to other as yet unratified extensions (such as
the vector 'v' extension).
Differential Revision: https://reviews.llvm.org/D73891
Added:
Modified:
clang/include/clang/Driver/Options.td
clang/lib/Driver/ToolChains/Arch/RISCV.cpp
clang/test/Driver/riscv-arch.c
Removed:
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index a395b680eb88..5becd52dae80 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -2332,6 +2332,8 @@ def mcmodel_EQ_medlow : Flag<["-"], "mcmodel=medlow">,
Group,
Group,
Flags<[CC1Option]>, Alias, AliasArgs<["medium"]>,
HelpText<"Equivalent to -mcmodel=medium, compatible with RISC-V gcc.">;
+def menable_experimental_extensions : Flag<["-"],
"menable-experimental-extensions">, Group,
+ HelpText<"Enable use of experimental RISC-V extensions.">;
def munaligned_access : Flag<["-"], "munaligned-access">,
Group,
HelpText<"Allow memory accesses to be unaligned (AArch32/AArch64 only)">;
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index f5764ca5dc06..f16827e00f1f 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -22,6 +22,14 @@ using namespace clang::driver::tools;
using namespace clang;
using namespace llvm::opt;
+namespace {
+// Represents the major and version number components of a RISC-V extension
+struct RISCVExtensionVersion {
+ StringRef Major;
+ StringRef Minor;
+};
+} // end anonymous namespace
+
static StringRef getExtensionTypeDesc(StringRef Ext) {
if (Ext.startswith("sx"))
return "non-standard supervisor-level extension";
@@ -29,6 +37,8 @@ static StringRef getExtensionTypeDesc(StringRef Ext) {
return "standard supervisor-level extension";
if (Ext.startswith("x"))
return "non-standard user-level extension";
+ if (Ext.startswith("z"))
+return "standard user-level extension";
return StringRef();
}
@@ -39,10 +49,27 @@ static StringRef getExtensionType(StringRef Ext) {
return "s";
if (Ext.startswith("x"))
return "x";
+ if (Ext.startswith("z"))
+return "z";
return StringRef();
}
+// If the extension is supported as experimental, return the version of that
+// extension that the compiler currently supports.
+static Optional
+isExperimentalExtension(StringRef Ext) {
+ if (Ext == "b" || Ext == "zbb" || Ext == "zbc" || Ext == "zbe" ||
+ Ext == "zbf" || Ext == "zbm" || Ext == "zbp" || Ext == "zbr" ||
+ Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
+return RISCVExtensionVersion{"0", "92"};
+ return None;
+}
+
static bool isSupportedExtension(StringRef Ext) {
+ // LLVM supports "z" extensions which are marked as experimental.
+ if (isExperimentalExtension(Ext))
+return true;
+
// LLVM does not support "sx", "s" nor "x" extensions.
return false;
}
@@ -52,15 +79,13 @@ static bool isSupportedExtension(StringRef Ext) {
// Version number is divided into major and minor version numbers,
// separated by a 'p'. If the minor version is 0 then 'p0' can be
// omitted from the version string. E.g., rv32i2p0, rv32i2, rv32i2p1.
-static bool getExtensionVersion(const Driver &D, StringRef MArch,
-StringRef Ext, StringRef In,
+static bool getExtensionVersion(const Driver &D, const ArgList &Args,
+StringRef MArch, StringRef Ext, StringRef In,
std::string &Major, std::string &Minor) {
Major = std::string(In.take_while(isDigit));
In = In.substr(Major.size());
- if (Major.empty())
-return true;
- if (In.consume_front("p")) {
+ if (Major.size() && In.consume_front("p")) {
Minor = std::string(In.take_while(isDigit));
In = In.su
[clang] 61ff296 - [RISCV] Add Clang frontend support for Bitmanip extension
Author: Scott Egerton
Date: 2020-04-09T18:04:22+01:00
New Revision: 61ff29637501afcd7476e52064f7a266a95c6e28
URL:
https://github.com/llvm/llvm-project/commit/61ff29637501afcd7476e52064f7a266a95c6e28
DIFF:
https://github.com/llvm/llvm-project/commit/61ff29637501afcd7476e52064f7a266a95c6e28.diff
LOG: [RISCV] Add Clang frontend support for Bitmanip extension
This adds the __riscv_bitmanip macro and the 'b' target feature to enable it.
Differential Revision: https://reviews.llvm.org/D71553
Added:
Modified:
clang/lib/Basic/Targets/RISCV.cpp
clang/lib/Basic/Targets/RISCV.h
clang/test/Preprocessor/riscv-target-features.c
Removed:
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index ab8272c034fd..522776437cd2 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -125,6 +125,9 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions
&Opts,
if (HasC)
Builder.defineMacro("__riscv_compressed");
+
+ if (HasB)
+Builder.defineMacro("__riscv_bitmanip");
}
/// Return true if has this feature, need to sync with handleTargetFeatures.
@@ -139,6 +142,7 @@ bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
.Case("f", HasF)
.Case("d", HasD)
.Case("c", HasC)
+ .Case("experimental-b", HasB)
.Default(false);
}
@@ -156,6 +160,8 @@ bool
RISCVTargetInfo::handleTargetFeatures(std::vector &Features,
HasD = true;
else if (Feature == "+c")
HasC = true;
+else if (Feature == "+experimental-b")
+ HasB = true;
}
return true;
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index 9118494a87ab..05da13230bf8 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -30,11 +30,12 @@ class RISCVTargetInfo : public TargetInfo {
bool HasF;
bool HasD;
bool HasC;
+ bool HasB;
public:
RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
: TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
-HasD(false), HasC(false) {
+HasD(false), HasC(false), HasB(false) {
LongDoubleWidth = 128;
LongDoubleAlign = 128;
LongDoubleFormat = &llvm::APFloat::IEEEquad();
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index a93d7e6a9a43..d8c18f76e53b 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
// CHECK-NOT: __riscv_mul
// CHECK-NOT: __riscv_muldiv
// CHECK-NOT: __riscv_compressed
+// CHECK-NOT: __riscv_bitmanip
// CHECK-NOT: __riscv_flen
// CHECK-NOT: __riscv_fdiv
// CHECK-NOT: __riscv_fsqrt
@@ -48,6 +49,12 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
// CHECK-C-EXT: __riscv_compressed 1
+// RUN: %clang -target riscv32-unknown-linux-gnu
-menable-experimental-extensions -march=rv32ib0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu
-menable-experimental-extensions -march=rv64ib0p92 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_bitmanip 1
+
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -mabi=ilp32 -x
c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SOFT %s
// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -mabi=lp64 -x
c -E -dM %s \
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 562bc30 - [Driver] Improve help message for -ffixed-xX flags
Author: Simon Cook
Date: 2020-04-10T11:30:24+01:00
New Revision: 562bc307c03de86dc083a019f358cd36c48488b0
URL:
https://github.com/llvm/llvm-project/commit/562bc307c03de86dc083a019f358cd36c48488b0
DIFF:
https://github.com/llvm/llvm-project/commit/562bc307c03de86dc083a019f358cd36c48488b0.diff
LOG: [Driver] Improve help message for -ffixed-xX flags
This improves the message by adding the missing 'x' prefix in register
names, such that the messages say for example 'Reserve the x10 register',
instead of 'Reserve the 10 register'.
Added:
Modified:
clang/include/clang/Driver/Options.td
Removed:
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 5becd52dae80..02875f68ebfe 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -2374,7 +2374,7 @@ def mno_fix_cortex_a53_835769 : Flag<["-"],
"mno-fix-cortex-a53-835769">,
HelpText<"Don't workaround Cortex-A53 erratum 835769 (AArch64 only)">;
foreach i = {1-31} in
def ffixed_x#i : Flag<["-"], "ffixed-x"#i>, Group,
-HelpText<"Reserve the "#i#" register (AArch64/RISC-V only)">;
+HelpText<"Reserve the x"#i#" register (AArch64/RISC-V only)">;
foreach i = {8-15,18} in
def fcall_saved_x#i : Flag<["-"], "fcall-saved-x"#i>,
Group,
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] de7bf72 - [RISCV] Add error checking for extensions missing separating underscores
Author: Simon Cook
Date: 2020-07-15T09:23:35+01:00
New Revision: de7bf722c23a1ab006bd306165c094669071577f
URL:
https://github.com/llvm/llvm-project/commit/de7bf722c23a1ab006bd306165c094669071577f
DIFF:
https://github.com/llvm/llvm-project/commit/de7bf722c23a1ab006bd306165c094669071577f.diff
LOG: [RISCV] Add error checking for extensions missing separating underscores
Currently if two multi-letter extensions are provided in a -march=
string, the verification code checks the version of the first and
consumes the second, resulting in that part of the architecture
string being ignored. This adds a test that when a version number has
been parsed for an extension, there are no subsequent characters.
Differential Revision: https://reviews.llvm.org/D83819
Added:
Modified:
clang/lib/Driver/ToolChains/Arch/RISCV.cpp
clang/test/Driver/riscv-arch.c
Removed:
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 8659ebf17a72..80d12e5aa8da 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -89,7 +89,7 @@ static bool getExtensionVersion(const Driver &D, const
ArgList &Args,
if (Major.size() && In.consume_front("p")) {
Minor = std::string(In.take_while(isDigit));
-In = In.substr(Major.size());
+In = In.substr(Major.size() + 1);
// Expected 'p' to be followed by minor version number.
if (Minor.empty()) {
@@ -101,6 +101,16 @@ static bool getExtensionVersion(const Driver &D, const
ArgList &Args,
}
}
+ // Expected multi-character extension with version number to have no
+ // subsequent characters (i.e. must either end string or be followed by
+ // an underscore).
+ if (Ext.size() > 1 && In.size()) {
+std::string Error =
+"multi-character extensions must be separated by underscores";
+D.Diag(diag::err_drv_invalid_riscv_ext_arch_name) << MArch << Error << In;
+return false;
+ }
+
// If experimental extension, require use of current version number number
if (auto ExperimentalExtension = isExperimentalExtension(Ext)) {
if (!Args.hasArg(options::OPT_menable_experimental_extensions)) {
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index e3062feb7dee..13d0748a967a 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -361,6 +361,10 @@
// RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbb"
// RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbp"
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p92zbp0p92
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck
-check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
+// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name
'rv32izbb0p92zbp0p92', multi-character extensions must be separated by
underscores
+
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOFLAG %s
// RV32-EXPERIMENTAL-V-NOFLAG: error: invalid arch name 'rv32iv'
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] afd483e - [RISCV] Add support for Zvamo/Zvlsseg to driver
Author: Simon Cook
Date: 2021-01-24T22:07:56Z
New Revision: afd483e57d166418e94a65bd9716e7dc4c114eed
URL:
https://github.com/llvm/llvm-project/commit/afd483e57d166418e94a65bd9716e7dc4c114eed
DIFF:
https://github.com/llvm/llvm-project/commit/afd483e57d166418e94a65bd9716e7dc4c114eed.diff
LOG: [RISCV] Add support for Zvamo/Zvlsseg to driver
Differential Revision: https://reviews.llvm.org/D94930
Added:
Modified:
clang/lib/Driver/ToolChains/Arch/RISCV.cpp
clang/test/Driver/riscv-arch.c
Removed:
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index ae7cc21ec235..2a303dd22062 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -62,7 +62,7 @@ isExperimentalExtension(StringRef Ext) {
Ext == "zbe" || Ext == "zbf" || Ext == "zbm" || Ext == "zbp" ||
Ext == "zbr" || Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
return RISCVExtensionVersion{"0", "93"};
- if (Ext == "v")
+ if (Ext == "v" || Ext == "zvamo" || Ext == "zvlsseg")
return RISCVExtensionVersion{"0", "9"};
if (Ext == "zfh")
return RISCVExtensionVersion{"0", "1"};
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index ebd9b8e79b8d..04dce2ab8215 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -396,3 +396,41 @@
// RUN: %clang -target riscv32-unknown-elf -march=rv32izfh0p1
-menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZFH %s
// RV32-EXPERIMENTAL-ZFH: "-target-feature" "+experimental-zfh"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo -### %s -c 2>&1 |
\
+// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-NOFLAG %s
+// RV32-EXPERIMENTAL-ZVAMO-NOFLAG: error: invalid arch name 'rv32izvamo'
+// RV32-EXPERIMENTAL-ZVAMO-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-NOVERS %s
+// RV32-EXPERIMENTAL-ZVAMO-NOVERS: error: invalid arch name 'rv32izvamo'
+// RV32-EXPERIMENTAL-ZVAMO-NOVERS: experimental extension requires explicit
version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo0p1
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-BADVERS %s
+// RV32-EXPERIMENTAL-ZVAMO-BADVERS: error: invalid arch name 'rv32izvamo0p1'
+// RV32-EXPERIMENTAL-ZVAMO-BADVERS: unsupported version number 0.1 for
experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo0p9
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-GOODVERS %s
+// RV32-EXPERIMENTAL-ZVAMO-GOODVERS: "-target-feature" "+experimental-zvamo"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg -### %s -c 2>&1
| \
+// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG %s
+// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: error: invalid arch name 'rv32izvlsseg'
+// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: requires
'-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOVERS %s
+// RV32-EXPERIMENTAL-ZVLSSEG-NOVERS: error: invalid arch name 'rv32izvlsseg'
+// RV32-EXPERIMENTAL-ZVLSSEG-NOVERS: experimental extension requires explicit
version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p1
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-BADVERS %s
+// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: error: invalid arch name
'rv32izvlsseg0p1'
+// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: unsupported version number 0.1 for
experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p9
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS %s
+// RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS: "-target-feature"
"+experimental-zvlsseg"
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 666815d - [RISCV] Implement new architecture extension macros
Author: Simon Cook
Date: 2021-01-25T08:58:46Z
New Revision: 666815d61bc2475aa7b3ecf8e3a91022d6ccce4b
URL:
https://github.com/llvm/llvm-project/commit/666815d61bc2475aa7b3ecf8e3a91022d6ccce4b
DIFF:
https://github.com/llvm/llvm-project/commit/666815d61bc2475aa7b3ecf8e3a91022d6ccce4b.diff
LOG: [RISCV] Implement new architecture extension macros
This adds support for the new architecture extension test macros as
defined in the C-API Document:
https://github.com/riscv/riscv-c-api-doc/blob/master/riscv-c-api.md
Extension versions have been taken from what are used in
RISCVTargetStreamer for ratified extensions, and the -march parser
for experimental extensions.
Differential Revision: https://reviews.llvm.org/D94403
Added:
Modified:
clang/lib/Basic/Targets/RISCV.cpp
clang/lib/Basic/Targets/RISCV.h
clang/lib/Driver/ToolChains/Arch/RISCV.cpp
clang/test/Preprocessor/riscv-target-features.c
Removed:
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 4436db904d59..7e6118af38e0 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -109,13 +109,18 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions
&Opts,
if (ABIName == "ilp32e")
Builder.defineMacro("__riscv_abi_rve");
+ Builder.defineMacro("__riscv_arch_test");
+ Builder.defineMacro("__riscv_i", "200");
+
if (HasM) {
+Builder.defineMacro("__riscv_m", "200");
Builder.defineMacro("__riscv_mul");
Builder.defineMacro("__riscv_div");
Builder.defineMacro("__riscv_muldiv");
}
if (HasA) {
+Builder.defineMacro("__riscv_a", "200");
Builder.defineMacro("__riscv_atomic");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
@@ -125,22 +130,71 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions
&Opts,
}
if (HasF || HasD) {
+Builder.defineMacro("__riscv_f", "200");
Builder.defineMacro("__riscv_flen", HasD ? "64" : "32");
Builder.defineMacro("__riscv_fdiv");
Builder.defineMacro("__riscv_fsqrt");
}
- if (HasC)
+ if (HasD)
+Builder.defineMacro("__riscv_d", "200");
+
+ if (HasC) {
+Builder.defineMacro("__riscv_c", "200");
Builder.defineMacro("__riscv_compressed");
+ }
- if (HasB)
+ if (HasB) {
+Builder.defineMacro("__riscv_b", "93000");
Builder.defineMacro("__riscv_bitmanip");
+ }
- if (HasV)
+ if (HasV) {
+Builder.defineMacro("__riscv_v", "9000");
Builder.defineMacro("__riscv_vector");
+ }
+
+ if (HasZba)
+Builder.defineMacro("__riscv_zba", "93000");
+
+ if (HasZbb)
+Builder.defineMacro("__riscv_zbb", "93000");
+
+ if (HasZbc)
+Builder.defineMacro("__riscv_zbc", "93000");
+
+ if (HasZbe)
+Builder.defineMacro("__riscv_zbe", "93000");
+
+ if (HasZbf)
+Builder.defineMacro("__riscv_zbf", "93000");
+
+ if (HasZbm)
+Builder.defineMacro("__riscv_zbm", "93000");
+
+ if (HasZbp)
+Builder.defineMacro("__riscv_zbp", "93000");
+
+ if (HasZbproposedc)
+Builder.defineMacro("__riscv_zbproposedc", "93000");
+
+ if (HasZbr)
+Builder.defineMacro("__riscv_zbr", "93000");
+
+ if (HasZbs)
+Builder.defineMacro("__riscv_zbs", "93000");
+
+ if (HasZbt)
+Builder.defineMacro("__riscv_zbt", "93000");
if (HasZfh)
-Builder.defineMacro("__riscv_zfh");
+Builder.defineMacro("__riscv_zfh", "1000");
+
+ if (HasZvamo)
+Builder.defineMacro("__riscv_zvamo", "9000");
+
+ if (HasZvlsseg)
+Builder.defineMacro("__riscv_zvlsseg", "9000");
}
/// Return true if has this feature, need to sync with handleTargetFeatures.
@@ -157,7 +211,20 @@ bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
.Case("c", HasC)
.Case("experimental-b", HasB)
.Case("experimental-v", HasV)
+ .Case("experimental-zba", HasZba)
+ .Case("experimental-zbb", HasZbb)
+ .Case("experimental-zbc", HasZbc)
+ .Case("experimental-zbe", HasZbe)
+ .Case("experimental-zbf", HasZbf)
+ .Case("experimental-zbm", HasZbm)
+ .Case("experimental-zbp", HasZbp)
+ .Case("experimental-zbproposedc", HasZbproposedc)
+ .Case("experimental-zbr", HasZbr)
+ .Case("experimental-zbs", HasZbs)
+ .Case("experimental-zbt", HasZbt)
.Case("experimental-zfh", HasZfh)
+ .Case("experimental-zvamo", HasZvamo)
+ .Case("experimental-zvlsseg", HasZvlsseg)
.Default(false);
}
@@ -179,8 +246,34 @@ bool
RISCVTargetInfo::handleTargetFeatures(std::vector &Features,
HasB = true;
else if (Feature == "+experimental-v")
HasV = true;
+else if (Feature == "+experimental-zba")
+ HasZba = true;
+else if (Feature == "+experimental-zbb")
+ HasZbb = true;
+else if (Feature == "+experimental-zbc")
+ HasZbc = true;
+else if (Feature == "+exper
[clang] c00e5cf - [RISCV] Set triple based on -march flag
Author: Simon Cook
Date: 2019-11-18T10:44:24Z
New Revision: c00e5cf29d49e51701b00382a3f41a4dfe1c0c0f
URL:
https://github.com/llvm/llvm-project/commit/c00e5cf29d49e51701b00382a3f41a4dfe1c0c0f
DIFF:
https://github.com/llvm/llvm-project/commit/c00e5cf29d49e51701b00382a3f41a4dfe1c0c0f.diff
LOG: [RISCV] Set triple based on -march flag
For RISC-V the value provided to -march should determine whether to
compile for 32- or 64-bit RISC-V irrespective of the target provided to
the Clang driver. This adds a test for this flag for RISC-V and sets the
Target architecture correctly in these cases.
Differential Revision: https://reviews.llvm.org/D54214
Added:
Modified:
clang/docs/ReleaseNotes.rst
clang/lib/Driver/Driver.cpp
clang/test/Driver/riscv-arch.c
Removed:
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index aa0d88db1c9f..5c8f3bd13d5a 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -112,7 +112,8 @@ future versions of Clang.
Modified Compiler Flags
---
-- ...
+- RISC-V now sets the architecture (riscv32/riscv64) based on the value
provided
+ to the ``-march`` flag, overriding the target provided by ``-triple``.
New Pragmas in Clang
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 3fb38a79051c..cdf4a579f431 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -541,6 +541,17 @@ static llvm::Triple computeTargetTriple(const Driver &D,
}
}
+ // If target is RISC-V adjust the target triple according to
+ // provided architecture name
+ A = Args.getLastArg(options::OPT_march_EQ);
+ if (A && Target.isRISCV()) {
+StringRef ArchName = A->getValue();
+if (ArchName.startswith_lower("rv32"))
+ Target.setArch(llvm::Triple::riscv32);
+else if (ArchName.startswith_lower("rv64"))
+ Target.setArch(llvm::Triple::riscv64);
+ }
+
return Target;
}
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 5329fe87aac7..3e1be9a011bf 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -315,3 +315,15 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-S-SX-INVAL %s
// RV32-X-S-SX-INVAL: error: invalid arch name 'rv32ixabc_sdef_sxghi',
// RV32-X-S-SX-INVAL: unsupported non-standard user-level extension 'xabc'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv32i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
+// RV32-TARGET: "-triple" "riscv32-unknown-unknown-elf"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv64i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
+// RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Allow YAML file to control multilib selection (PR #98856)
simonpcook wrote: I think the fake flag hack may have a limitation in that since the `--XXX-fake-flag-...` appears in `--print-multi-lib` it may get imported into some build system and used as a flag for building particular libraries. For example with the above, newlib will not build since `error: unknown argument: '--XXX-fake-flag-yaml-has-m'`. Of course, I can build newlib with a different multilib.yaml file that I later distribute the tools with - more an FYI for anyone who hits that one in the future. https://github.com/llvm/llvm-project/pull/98856 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
