[PATCH] D128604: [WIP][RISCV] Support Zbpbo extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 440267.
sunshaoce added a comment.

Add more tests


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128604/new/

https://reviews.llvm.org/D128604

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv32-zbpbo.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv64-zbpbo.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/rv32zbpbo.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv32zbpbo-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-valid.s

Index: llvm/test/MC/RISCV/rv64zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-valid.s
@@ -0,0 +1,29 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
+fsrw t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s  -triple=riscv64 -mattr=+experimental-zbpbo \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 63
+# CHECK-S-OBJ: rev t0, t1
+rev x5, x6
Index: llvm/test/MC/RISCV/rv32zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-valid.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
+clz t0, t1
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
+fsr t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: fsri t0, t1, t2, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x3c]
+fsri t0, t1, t2, 0
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s

[PATCH] D128604: [RISCV] Support Zbpbo extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:352
 MinorStr = In.take_while(isDigit);
-In = In.substr(MajorStr.size() + 1);
+In = In.substr(MajorStr.size() + MinorStr.size() - 1);
 

Modifications here have been submitted separately in D128644.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D128604: [WIP][RISCV] Support Zbpbo extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 440324.
sunshaoce added a comment.
Herald added a subscriber: jdoerfert.

Fully supported Zbpbo v0.9.11


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128604/new/

https://reviews.llvm.org/D128604

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv32-zbpbo.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv64-zbpbo.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv32zbpbo-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-valid.s

Index: llvm/test/MC/RISCV/rv64zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-valid.s
@@ -0,0 +1,29 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
+fsrw t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s  -triple=riscv64 -mattr=+experimental-zbpbo \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 63
+# CHECK-S-OBJ: rev t0, t1
+rev x5, x6
Index: llvm/test/MC/RISCV/rv32zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-valid.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
+clz t0, t1
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
+fsr t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: fsri t0, t1, t2, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x3c]
+fsri t0, t1, t2, 0
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-ali

[PATCH] D128604: [RISCV] Support Zbpbo extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 440613.
sunshaoce added a comment.

Rebased on D128644 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128604/new/

https://reviews.llvm.org/D128604

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv32-zbpbo.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv64-zbpbo.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv32zbpbo-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-valid.s

Index: llvm/test/MC/RISCV/rv64zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-valid.s
@@ -0,0 +1,29 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
+fsrw t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s  -triple=riscv64 -mattr=+experimental-zbpbo \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 63
+# CHECK-S-OBJ: rev t0, t1
+rev x5, x6
Index: llvm/test/MC/RISCV/rv32zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-valid.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
+clz t0, t1
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
+fsr t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: fsri t0, t1, t2, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x3c]
+fsri t0, t1, t2, 0
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
@

[PATCH] D128604: [RISCV] Support Zbpbo extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 440714.
sunshaoce marked an inline comment as done.
sunshaoce added a comment.

Address @craig.topper's comment. Thanks!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128604/new/

https://reviews.llvm.org/D128604

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv32-zbpbo.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv64-zbpbo.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv32zbpbo-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-valid.s

Index: llvm/test/MC/RISCV/rv64zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-valid.s
@@ -0,0 +1,29 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
+fsrw t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s  -triple=riscv64 -mattr=+experimental-zbpbo \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 63
+# CHECK-S-OBJ: rev t0, t1
+rev x5, x6
Index: llvm/test/MC/RISCV/rv32zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-valid.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
+clz t0, t1
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
+fsr t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: fsri t0, t1, t2, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x3c]
+fsri t0, t1, t2, 0
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
===

[PATCH] D128604: [RISCV] Support Zbpbo extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 441052.
sunshaoce added a comment.

Add alias instructions


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128604/new/

https://reviews.llvm.org/D128604

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv32-zbpbo.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv64-zbpbo.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv32zbpbo-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-valid.s

Index: llvm/test/MC/RISCV/rv64zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-valid.s
@@ -0,0 +1,29 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
+fsrw t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s  -triple=riscv64 -mattr=+experimental-zbpbo \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 63
+# CHECK-S-OBJ: rev t0, t1
+rev x5, x6
Index: llvm/test/MC/RISCV/rv32zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-valid.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
+clz t0, t1
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
+fsr t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: fsri t0, t1, t2, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x3c]
+fsri t0, t1, t2, 0
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce added a comment.

Hello @Jim! We are developing the P extension, are you still maintaining this 
patch? Or would you mind co-development together?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

___
cfe-commits mailing list
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[PATCH] D128604: [RISCV] Support Zbpbo extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 441872.
sunshaoce added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128604/new/

https://reviews.llvm.org/D128604

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv32-zbpbo.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv64-zbpbo.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv32zbpbo-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-valid.s

Index: llvm/test/MC/RISCV/rv64zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-valid.s
@@ -0,0 +1,29 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
+fsrw t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s  -triple=riscv64 -mattr=+experimental-zbpbo \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 63
+# CHECK-S-OBJ: rev t0, t1
+rev x5, x6
Index: llvm/test/MC/RISCV/rv32zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-valid.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
+clz t0, t1
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
+fsr t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: fsri t0, t1, t2, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x3c]
+fsri t0, t1, t2, 0
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
@@ -0,0 +1,26 

[PATCH] D108189: [RISCV] Support experimental 'P' extension 0.9.11

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 441925.
sunshaoce added a comment.

Support for P extension version 0.9.11


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108189/new/

https://reviews.llvm.org/D108189

Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -187,3 +187,15 @@
 
 .attribute arch, "rv32if_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
+
+.attribute arch, "rv32ip0p911"
+# CHECK: attribute  5, "rv32i2p0_p0p911_zbpbo0p911_zpn0p911_zpsfoperand0p911"
+
+.attribute arch, "rv32izbpbo0p911"
+# CHECK: attribute  5, "rv32i2p0_zbpbo0p911"
+
+.attribute arch, "rv32izpn0p911"
+# CHECK: attribute  5, "rv32i2p0_zpn0p911"
+
+.attribute arch, "rv32izpsfoperand0p911"
+# CHECK: attribute  5, "rv32i2p0_zpsfoperand0p911"
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -109,6 +109,11 @@
 {"zbr", RISCVExtensionVersion{0, 93}},
 {"zbt", RISCVExtensionVersion{0, 93}},
 {"zvfh", RISCVExtensionVersion{0, 1}},
+
+{"p", RISCVExtensionVersion{0, 911}},
+{"zbpbo", RISCVExtensionVersion{0, 911}},
+{"zpn", RISCVExtensionVersion{0, 911}},
+{"zpsfoperand", RISCVExtensionVersion{0, 911}},
 };
 
 static bool stripExperimentalPrefix(StringRef &Ext) {
@@ -598,8 +603,8 @@
 
 // The order is OK, then push it into features.
 // TODO: Use version number when setting target features
-// Currently LLVM supports only "mafdcbv".
-StringRef SupportedStandardExtension = "mafdcbv";
+// Currently LLVM supports only "mafdcbpv".
+StringRef SupportedStandardExtension = "mafdcbpv";
 if (!SupportedStandardExtension.contains(C))
   return createStringError(errc::invalid_argument,
"unsupported standard user-level extension '%c'",
@@ -773,6 +778,7 @@
 static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"};
 static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
 static const char *ImpliedExtsZvfh[] = {"zve32f"};
+static const char *ImpliedExtsP[] = {"zbpbo", "zpn", "zpsfoperand"};
 
 struct ImpliedExtsEntry {
   StringLiteral Name;
@@ -787,6 +793,7 @@
 
 // Note: The table needs to be sorted by name.
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
+{{"p"}, {ImpliedExtsP}},
 {{"v"}, {ImpliedExtsV}},
 {{"zdinx"}, {ImpliedExtsZdinx}},
 {{"zfh"}, {ImpliedExtsZfh}},
Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -42,6 +42,10 @@
 // CHECK-NOT: __riscv_zkr
 // CHECK-NOT: __riscv_zkt
 // CHECK-NOT: __riscv_zk
+// CHECK-NOT: __riscv_p
+// CHECK-NOT: __riscv_zbpbo
+// CHECK-NOT: __riscv_zpn
+// CHECK-NOT: __riscv_zpsfoperand
 // CHECK-NOT: __riscv_zicbom
 // CHECK-NOT: __riscv_zicboz
 
@@ -224,6 +228,44 @@
 // CHECK-ZBT-NOT: __riscv_b
 // CHECK-ZBT-EXT: __riscv_zbt 93000{{$}}
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32ip0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64ip0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// CHECK-P-EXT: __riscv_p 911000{{$}}
+// CHECK-P-EXT: __riscv_zbpbo 911000{{$}}
+// CHECK-P-EXT: __riscv_zpn 911000{{$}}
+// CHECK-P-EXT: __riscv_zpsfoperand 911000{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izbpbo0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBPBO-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izbpbo0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBPBO-EXT %s
+// CHECK-ZBPBO-NOT: __riscv_p
+// CHECK-ZBPBO-EXT: __riscv_zbpbo 911000{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpn0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpn0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// CHECK-ZPN-NOT: __riscv_p
+// CHECK-ZPN-EXT: __riscv_zpn 911000{{$}}
+
+// RUN: %clang -targ

[PATCH] D128604: [RISCV] Support Zbpbo extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 441931.
sunshaoce added a comment.

Rebase on D99158 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128604/new/

https://reviews.llvm.org/D128604

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv32-zbpbo.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv64-zbpbo.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo.ll
  llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv32zbpbo-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-valid.s

Index: llvm/test/MC/RISCV/rv64zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-valid.s
@@ -0,0 +1,29 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
+fsrw t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s  -triple=riscv64 -mattr=+experimental-zbpbo \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 63
+# CHECK-S-OBJ: rev t0, t1
+rev x5, x6
Index: llvm/test/MC/RISCV/rv32zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-valid.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
+clz t0, t1
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
+fsr t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: fsri t0, t1, t2, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x3c]
+fsri t0, t1, t2, 0
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
@@ -0,0 +1,26 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-al

[PATCH] D121670: [RISCV] Add zihintntl instructions

[Shao-Ce SUN via Phabricator via cfe-commits]

s updated this revision to Diff 415703.
s added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Add preprocessor test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121670/new/

https://reviews.llvm.org/D121670

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/rv32zihintntl-valid.s

Index: llvm/test/MC/RISCV/rv32zihintntl-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zihintntl-valid.s
@@ -0,0 +1,26 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: add zero, zero, sp
+# CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
+ntl.p1
+
+# CHECK-ASM-AND-OBJ: add zero, zero, gp
+# CHECK-ASM: encoding: [0x33,0x00,0x30,0x00]
+ntl.pall
+
+# CHECK-ASM-AND-OBJ: add zero, zero, tp
+# CHECK-ASM: encoding: [0x33,0x00,0x40,0x00]
+ntl.s1
+
+# CHECK-ASM-AND-OBJ: add zero, zero, t0
+# CHECK-ASM: encoding: [0x33,0x00,0x50,0x00]
+ntl.all
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -6,6 +6,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefix=RV32D %s
 ; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefix=RV32C %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zihintpause %s -o - | FileCheck --check-prefix=RV32ZIHINTPAUSE %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zihintntl %s -o - | FileCheck --check-prefix=RV32ZIHINTNTL %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin %s -o - | FileCheck --check-prefix=RV32ZFHMIN %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh %s -o - | FileCheck --check-prefix=RV32ZFH %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zba %s -o - | FileCheck --check-prefix=RV32ZBA %s
@@ -42,6 +43,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s
 ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zihintpause %s -o - | FileCheck --check-prefix=RV64ZIHINTPAUSE %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zihintntl %s -o - | FileCheck --check-prefix=RV64ZIHINTNTL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin %s -o - | FileCheck --check-prefix=RV64ZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh %s -o - | FileCheck --check-prefix=RV64ZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zba %s -o - | FileCheck --check-prefix=RV64ZBA %s
@@ -79,6 +81,7 @@
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
 ; RV32ZIHINTPAUSE: .attribute 5, "rv32i2p0_zihintpause2p0"
+; RV32ZIHINTNTL: .attribute 5, "rv32i2p0_zihintntl0p2"
 ; RV32ZFHMIN: .attribute 5, "rv32i2p0_f2p0_zfhmin1p0"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh1p0"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0"
@@ -116,6 +119,7 @@
 ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
 ; RV64C: .attribute 5, "rv64i2p0_c2p0"
 ; RV64ZIHINTPAUSE: .attribute 5, "rv64i2p0_zihintpause2p0"
+; RV64ZIHINTNTL: .attribute 5, "rv64i2p0_zihintntl0p2"
 ; RV64ZFHMIN: .attribute 5, "rv64i2p0_f2p0_zfhmin1p0"
 ; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh1p0"
 ; RV64ZBA: .attribute 5, "rv64i2p0_zba1p0"
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -66,6 +66,7 @@
   bool HasStdExtD = false;
   bool HasStdExtC = false;
   bool HasStdExtZihintpause = false;
+  bool HasStdExtZihintntl = false;
   bool HasStdExtZba = false;
   bool HasStdExtZbb = false;
   bool HasStdExtZbc = false;
@@ -163,6 +164,7 @@
   bool hasStdExtC() const { return HasStdExtC; }
   bool hasStdExtV() const { return HasStdExtV; }
   bool hasStdExtZihintpause() const { return HasStdExtZihintpause; }
+  bool hasStdExtZihintntl() const { return HasStdExtZihintntl; }
   bool hasStdExtZba() const { return HasStdExtZba; }
   bool hasStdExtZb

[PATCH] D112774: [RISCV] Support k-ext clang intrinsics

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 405605.
achieveartificialintelligence added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112774/new/

https://reviews.llvm.org/D112774

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -31,6 +31,16 @@
 // CHECK-NOT: __riscv_zfh
 // CHECK-NOT: __riscv_v
 // CHECK-NOT: __riscv_vector
+// CHECK-NOT: __riscv_zbkc
+// CHECK-NOT: __riscv_zbkx
+// CHECK-NOT: __riscv_zbkb
+// CHECK-NOT: __riscv_zkne
+// CHECK-NOT: __riscv_zknd
+// CHECK-NOT: __riscv_zknh
+// CHECK-NOT: __riscv_zksh
+// CHECK-NOT: __riscv_zksed
+// CHECK-NOT: __riscv_zkr
+// CHECK-NOT: __riscv_zk
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -343,3 +353,53 @@
 // CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32X-EXT: __riscv_vector 1
 // CHECK-ZVE32X-EXT: __riscv_zve32x 100{{$}}
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkc1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKC-EXT %s
+// CHECK-ZBKC-EXT: __riscv_zbkc
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkx1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKX-EXT %s
+// CHECK-ZBKX-EXT: __riscv_zbkx
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkb1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKB-EXT %s
+// CHECK-ZBKB-EXT: __riscv_zbkb
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknd1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKND-EXT %s
+// CHECK-ZKND-EXT: __riscv_zknd
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkne1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNE-EXT %s
+// CHECK-ZKNE-EXT: __riscv_zkne
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNH-EXT %s
+// CHECK-ZKNH-EXT: __riscv_zknh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSH-EXT %s
+// CHECK-ZKSH-EXT: __riscv_zksh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksed1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSED-EXT %s
+// CHECK-ZKSED-EXT: __riscv_zksed
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkr1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKR-EXT %s
+// CHECK-ZKR-EXT: __riscv_zkr
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izk1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZK-EXT %s
+// CHECK-ZK-EXT: __riscv_zk
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -414,3 +414,15 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b1p0 -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-ZVL-GOODVERS %s
 // RV32-ZVL-GOODVERS: "-target-feature" "+zvl32b"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkc1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBKC %s
+// RV32-ZBKC: "-target-feature" "+zbkc"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkx1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBKX %s
+// RV32-ZBKX: "-t

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

In D93298#3296515 , @luismarques wrote:

> Assuming this will be merged soon, do you want to submit a backport request 
> for the 14.0 branch?

Yes.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D112774: [RISCV] Support k-ext clang intrinsics

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 405989.
achieveartificialintelligence marked 3 inline comments as done.
achieveartificialintelligence added a comment.

Address comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112774/new/

https://reviews.llvm.org/D112774

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -31,6 +31,16 @@
 // CHECK-NOT: __riscv_zfh
 // CHECK-NOT: __riscv_v
 // CHECK-NOT: __riscv_vector
+// CHECK-NOT: __riscv_zbkc
+// CHECK-NOT: __riscv_zbkx
+// CHECK-NOT: __riscv_zbkb
+// CHECK-NOT: __riscv_zkne
+// CHECK-NOT: __riscv_zknd
+// CHECK-NOT: __riscv_zknh
+// CHECK-NOT: __riscv_zksh
+// CHECK-NOT: __riscv_zksed
+// CHECK-NOT: __riscv_zkr
+// CHECK-NOT: __riscv_zk
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -343,3 +353,53 @@
 // CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32X-EXT: __riscv_vector 1
 // CHECK-ZVE32X-EXT: __riscv_zve32x 100{{$}}
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkc1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKC-EXT %s
+// CHECK-ZBKC-EXT: __riscv_zbkc
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkx1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKX-EXT %s
+// CHECK-ZBKX-EXT: __riscv_zbkx
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkb1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKB-EXT %s
+// CHECK-ZBKB-EXT: __riscv_zbkb
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknd1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKND-EXT %s
+// CHECK-ZKND-EXT: __riscv_zknd
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkne1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNE-EXT %s
+// CHECK-ZKNE-EXT: __riscv_zkne
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNH-EXT %s
+// CHECK-ZKNH-EXT: __riscv_zknh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSH-EXT %s
+// CHECK-ZKSH-EXT: __riscv_zksh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksed1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSED-EXT %s
+// CHECK-ZKSED-EXT: __riscv_zksed
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkr1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKR-EXT %s
+// CHECK-ZKR-EXT: __riscv_zkr
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izk1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZK-EXT %s
+// CHECK-ZK-EXT: __riscv_zk
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -414,3 +414,15 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b1p0 -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-ZVL-GOODVERS %s
 // RV32-ZVL-GOODVERS: "-target-feature" "+zvl32b"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkc1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBKC %s
+// RV32-ZBKC: "-target-feature" "+zbkc"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkx1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check

[PATCH] D112774: [RISCV] Support k-ext clang intrinsics

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 405997.
achieveartificialintelligence added a comment.

Amend tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112774/new/

https://reviews.llvm.org/D112774

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -31,6 +31,17 @@
 // CHECK-NOT: __riscv_zfh
 // CHECK-NOT: __riscv_v
 // CHECK-NOT: __riscv_vector
+// CHECK-NOT: __riscv_zbkc
+// CHECK-NOT: __riscv_zbkx
+// CHECK-NOT: __riscv_zbkb
+// CHECK-NOT: __riscv_zkne
+// CHECK-NOT: __riscv_zknd
+// CHECK-NOT: __riscv_zknh
+// CHECK-NOT: __riscv_zksh
+// CHECK-NOT: __riscv_zksed
+// CHECK-NOT: __riscv_zkr
+// CHECK-NOT: __riscv_zkt
+// CHECK-NOT: __riscv_zk
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -343,3 +354,58 @@
 // CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32X-EXT: __riscv_vector 1
 // CHECK-ZVE32X-EXT: __riscv_zve32x 100{{$}}
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkc1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKC-EXT %s
+// CHECK-ZBKC-EXT: __riscv_zbkc
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkx1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKX-EXT %s
+// CHECK-ZBKX-EXT: __riscv_zbkx
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkb1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKB-EXT %s
+// CHECK-ZBKB-EXT: __riscv_zbkb
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknd1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKND-EXT %s
+// CHECK-ZKND-EXT: __riscv_zknd
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkne1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNE-EXT %s
+// CHECK-ZKNE-EXT: __riscv_zkne
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNH-EXT %s
+// CHECK-ZKNH-EXT: __riscv_zknh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSH-EXT %s
+// CHECK-ZKSH-EXT: __riscv_zksh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksed1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSED-EXT %s
+// CHECK-ZKSED-EXT: __riscv_zksed
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkr1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKR-EXT %s
+// CHECK-ZKR-EXT: __riscv_zkr
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKT-EXT %s
+// CHECK-ZKT-EXT: __riscv_zkt
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izk1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZK-EXT %s
+// CHECK-ZK-EXT: __riscv_zk
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -414,3 +414,47 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b1p0 -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-ZVL-GOODVERS %s
 // RV32-ZVL-GOODVERS: "-target-feature" "+zvl32b"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkc1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBKC %s
+// RV32-ZBKC: "-

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 407482.
achieveartificialintelligence marked 2 inline comments as done.
achieveartificialintelligence added a comment.

Address comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4
+fcvt.h.w t6, a4
+# CHECK-INST: fcvt.h.wu s0, a5, dyn
+# CHECK-ALIAS: fcvt.h.wu s0, a5
+fcvt.h.wu s0, a5
Index: llvm/test/MC/RIS

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:555
+def GPRF64  : RegisterClass<"RISCV", [f64], 64, (add GPR)>;
+def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add
+X10_PD, X12_PD, X14_PD, X16_PD,

craig.topper wrote:
> Jim wrote:
> > Is XLenRI correct for GPRPF64? RV32 has size 32.
> I'm not sure the RegInfos are correct for the other classes either. The 
> RegInfos override the register size, the spill size, and spill alignment. I 
> think those should all be based on the FP type.
> 
> So I don't think any of these should have a RegInfos.
Without `RegInfo`, it would cause `spill size` to be changed for a large number 
of other tests.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence marked an inline comment as done.
achieveartificialintelligence added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:557
+
+let RegInfos = RegInfoByHwMode<[RV64], [RegInfo<64, 64, 64>]> in
+def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add

Jim wrote:
> Is register pair only on RV32 for used as f64?
Yes.


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[PATCH] D112774: [RISCV] Support k-ext clang intrinsics

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 408310.
achieveartificialintelligence added a comment.

Ping & Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112774/new/

https://reviews.llvm.org/D112774

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -31,6 +31,17 @@
 // CHECK-NOT: __riscv_zfh
 // CHECK-NOT: __riscv_v
 // CHECK-NOT: __riscv_vector
+// CHECK-NOT: __riscv_zbkc
+// CHECK-NOT: __riscv_zbkx
+// CHECK-NOT: __riscv_zbkb
+// CHECK-NOT: __riscv_zkne
+// CHECK-NOT: __riscv_zknd
+// CHECK-NOT: __riscv_zknh
+// CHECK-NOT: __riscv_zksh
+// CHECK-NOT: __riscv_zksed
+// CHECK-NOT: __riscv_zkr
+// CHECK-NOT: __riscv_zkt
+// CHECK-NOT: __riscv_zk
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -343,3 +354,58 @@
 // CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32X-EXT: __riscv_vector 1
 // CHECK-ZVE32X-EXT: __riscv_zve32x 100{{$}}
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkc1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKC-EXT %s
+// CHECK-ZBKC-EXT: __riscv_zbkc
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkx1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKX-EXT %s
+// CHECK-ZBKX-EXT: __riscv_zbkx
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkb1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKB-EXT %s
+// CHECK-ZBKB-EXT: __riscv_zbkb
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknd1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKND-EXT %s
+// CHECK-ZKND-EXT: __riscv_zknd
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkne1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNE-EXT %s
+// CHECK-ZKNE-EXT: __riscv_zkne
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNH-EXT %s
+// CHECK-ZKNH-EXT: __riscv_zknh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSH-EXT %s
+// CHECK-ZKSH-EXT: __riscv_zksh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksed1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSED-EXT %s
+// CHECK-ZKSED-EXT: __riscv_zksed
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkr1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKR-EXT %s
+// CHECK-ZKR-EXT: __riscv_zkr
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKT-EXT %s
+// CHECK-ZKT-EXT: __riscv_zkt
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izk1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZK-EXT %s
+// CHECK-ZK-EXT: __riscv_zk
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -414,3 +414,47 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b1p0 -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-ZVL-GOODVERS %s
 // RV32-ZVL-GOODVERS: "-target-feature" "+zvl32b"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkc1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBKC %s
+// RV32-ZBKC: 

[PATCH] D112774: [RISCV] Support k-ext clang intrinsics

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 408319.
achieveartificialintelligence marked 4 inline comments as done.
achieveartificialintelligence added a comment.

Address @craig.topper's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112774/new/

https://reviews.llvm.org/D112774

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -31,6 +31,17 @@
 // CHECK-NOT: __riscv_zfh
 // CHECK-NOT: __riscv_v
 // CHECK-NOT: __riscv_vector
+// CHECK-NOT: __riscv_zbkc
+// CHECK-NOT: __riscv_zbkx
+// CHECK-NOT: __riscv_zbkb
+// CHECK-NOT: __riscv_zkne
+// CHECK-NOT: __riscv_zknd
+// CHECK-NOT: __riscv_zknh
+// CHECK-NOT: __riscv_zksh
+// CHECK-NOT: __riscv_zksed
+// CHECK-NOT: __riscv_zkr
+// CHECK-NOT: __riscv_zkt
+// CHECK-NOT: __riscv_zk
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -343,3 +354,58 @@
 // CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32X-EXT: __riscv_vector 1
 // CHECK-ZVE32X-EXT: __riscv_zve32x 100{{$}}
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkc1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKC-EXT %s
+// CHECK-ZBKC-EXT: __riscv_zbkc
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkx1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKX-EXT %s
+// CHECK-ZBKX-EXT: __riscv_zbkx
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkb1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKB-EXT %s
+// CHECK-ZBKB-EXT: __riscv_zbkb
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknd1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKND-EXT %s
+// CHECK-ZKND-EXT: __riscv_zknd
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkne1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNE-EXT %s
+// CHECK-ZKNE-EXT: __riscv_zkne
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNH-EXT %s
+// CHECK-ZKNH-EXT: __riscv_zknh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSH-EXT %s
+// CHECK-ZKSH-EXT: __riscv_zksh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksed1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSED-EXT %s
+// CHECK-ZKSED-EXT: __riscv_zksed
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkr1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKR-EXT %s
+// CHECK-ZKR-EXT: __riscv_zkr
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKT-EXT %s
+// CHECK-ZKT-EXT: __riscv_zkt
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izk1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZK-EXT %s
+// CHECK-ZK-EXT: __riscv_zk
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -414,3 +414,47 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b1p0 -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-ZVL-GOODVERS %s
 // RV32-ZVL-GOODVERS: "-target-feature" "+zvl32b"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkc1p0 -### %s \

[PATCH] D119846: [NFC][MC] remove unused argument `MCRegisterInfo` in `MCCodeEmitter`

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence created this revision.
achieveartificialintelligence added reviewers: grosbach, Eugene.Zelenko, asb, 
jrtc27, craig.topper.
Herald added subscribers: ayermolo, sdasgup3, wenzhicui, wrengr, Chia-hungDuan, 
dcaballe, cota, teijeong, frasercrmck, rdzhabarov, tatianashp, msifontes, 
jurahul, Kayjukh, grosul1, Joonsoo, liufengdb, aartbik, mgester, arpith-jacob, 
csigg, antiagainst, shauheen, rriddle, mehdi_amini, luismarques, apazos, 
sameer.abuasal, pengfei, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, 
MartinMosbeck, rogfer01, edward-jones, zzheng, gbedwell, niosHD, sabuasal, 
simoncook, johnrusso, rbar, hiraditya.
Herald added a reviewer: andreadb.
Herald added a reviewer: bondhugula.
Herald added a reviewer: rafauler.
Herald added a reviewer: Amir.
Herald added a reviewer: maksfb.
achieveartificialintelligence requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, yota9, 
stephenneuendorffer, nicolasvasilache, MaskRay.
Herald added a reviewer: herhut.
Herald added projects: clang, MLIR, LLVM.

For ten years, it seems that `MCRegisterInfo` is not used by any target.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119846

Files:
  bolt/include/bolt/Core/BinaryContext.h
  bolt/lib/Core/BinaryContext.cpp
  clang/tools/driver/cc1as_main.cpp
  llvm/include/llvm/MC/TargetRegistry.h
  llvm/lib/CodeGen/LLVMTargetMachine.cpp
  llvm/lib/DWARFLinker/DWARFStreamer.cpp
  llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
  llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
  llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
  llvm/lib/Target/X86/X86AsmPrinter.cpp
  llvm/tools/llvm-dwp/llvm-dwp.cpp
  llvm/tools/llvm-exegesis/lib/LlvmState.cpp
  llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp
  llvm/tools/llvm-mc/llvm-mc.cpp
  llvm/tools/llvm-mca/llvm-mca.cpp
  llvm/tools/llvm-ml/llvm-ml.cpp
  llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
  llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
  llvm/unittests/MC/DwarfLineTableHeaders.cpp
  mlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp

Index: mlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp
===
--- mlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp
+++ mlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp
@@ -376,7 +376,7 @@
   std::unique_ptr mcStreamer;
   std::unique_ptr mcii(target->createMCInstrInfo());
 
-  llvm::MCCodeEmitter *ce = target->createMCCodeEmitter(*mcii, *mri, ctx);
+  llvm::MCCodeEmitter *ce = target->createMCCodeEmitter(*mcii, ctx);
   llvm::MCAsmBackend *mab = target->createMCAsmBackend(*sti, *mri, mcOptions);
   mcStreamer.reset(target->createMCObjectStreamer(
   triple, ctx, std::unique_ptr(mab),
Index: llvm/unittests/MC/DwarfLineTableHeaders.cpp
===
--- llvm/unittests/MC/DwarfLineTableHeaders.cpp
+++ llvm/unittests/MC/DwarfLineTableHeaders.cpp
@@ -77,8 +77,7 @@
 Res.Ctx->setObjectFileInfo(Res.MOFI.get());
 
 Res.MII.reset(TheTarget->createMCInstrInfo());
-MCCodeEmitter *MCE =
-TheTarget->createMCCodeEmitter(*Res.MII, *MRI, *Res.Ctx);
+MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*Res.MII, *Res.Ctx);
 MCAsmBackend *MAB =
 TheTarget->createMCAsmBackend(*STI, *MRI, MCTargetOptions());
 std::unique_ptr OW = MAB->createObjectWriter(OS);
Index: llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
===
--- llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
+++ llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
@@ -464,7 +464,7 @@
   TLOF->Initialize(*MC, *TM);
   MC->setObjectFileInfo(TLOF);
 
-  MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *MC);
+  MCE = TheTarget->createMCCodeEmitter(*MII, *MC);
   if (!MCE)
 return make_error("no code emitter for target " + TripleName,
inconvertibleErrorCode());
Index: llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
===
--- llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
+++ llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
@@ -106,7 +106,7 @@
   Res.Ctx->setObjectFileInfo(Res.MOFI.get());
 
   Res.MII.reset(TheTarget->createMCInstrInfo());
-  MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*Res.MII, *MRI, *Res.Ctx);
+  MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*Res.MII, *Res.Ctx);
   MCAsmBackend *MAB =
   TheTarget->createMCAsmBackend(*STI, *MRI, MCTargetOptions());
   std::unique_ptr OW = MAB->createObjectWriter(OS);
Index: llvm/tools/llvm-ml/llvm-ml.cpp
===
--- llvm/tools/llvm-ml/llvm-

[PATCH] D119846: [NFC][MC] remove unused argument `MCRegisterInfo` in `MCCodeEmitter`

[Shao-Ce SUN via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGfe25c06cc5bd: [NFC][MC] remove unused argument 
`MCRegisterInfo` in `MCCodeEmitter` (authored by achieveartificialintelligence).

Repository:
  rG LLVM Github Monorepo

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Files:
  bolt/include/bolt/Core/BinaryContext.h
  bolt/lib/Core/BinaryContext.cpp
  clang/tools/driver/cc1as_main.cpp
  llvm/include/llvm/MC/TargetRegistry.h
  llvm/lib/CodeGen/LLVMTargetMachine.cpp
  llvm/lib/DWARFLinker/DWARFStreamer.cpp
  llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
  llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
  llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
  llvm/lib/Target/X86/X86AsmPrinter.cpp
  llvm/tools/llvm-dwp/llvm-dwp.cpp
  llvm/tools/llvm-exegesis/lib/LlvmState.cpp
  llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp
  llvm/tools/llvm-mc/llvm-mc.cpp
  llvm/tools/llvm-mca/llvm-mca.cpp
  llvm/tools/llvm-ml/llvm-ml.cpp
  llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
  llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
  llvm/unittests/MC/DwarfLineTableHeaders.cpp
  mlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp

Index: mlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp
===
--- mlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp
+++ mlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp
@@ -377,7 +377,7 @@
   std::unique_ptr mcStreamer;
   std::unique_ptr mcii(target->createMCInstrInfo());
 
-  llvm::MCCodeEmitter *ce = target->createMCCodeEmitter(*mcii, *mri, ctx);
+  llvm::MCCodeEmitter *ce = target->createMCCodeEmitter(*mcii, ctx);
   llvm::MCAsmBackend *mab = target->createMCAsmBackend(*sti, *mri, mcOptions);
   mcStreamer.reset(target->createMCObjectStreamer(
   triple, ctx, std::unique_ptr(mab),
Index: llvm/unittests/MC/DwarfLineTableHeaders.cpp
===
--- llvm/unittests/MC/DwarfLineTableHeaders.cpp
+++ llvm/unittests/MC/DwarfLineTableHeaders.cpp
@@ -77,8 +77,7 @@
 Res.Ctx->setObjectFileInfo(Res.MOFI.get());
 
 Res.MII.reset(TheTarget->createMCInstrInfo());
-MCCodeEmitter *MCE =
-TheTarget->createMCCodeEmitter(*Res.MII, *MRI, *Res.Ctx);
+MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*Res.MII, *Res.Ctx);
 MCAsmBackend *MAB =
 TheTarget->createMCAsmBackend(*STI, *MRI, MCTargetOptions());
 std::unique_ptr OW = MAB->createObjectWriter(OS);
Index: llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
===
--- llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
+++ llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
@@ -464,7 +464,7 @@
   TLOF->Initialize(*MC, *TM);
   MC->setObjectFileInfo(TLOF);
 
-  MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *MC);
+  MCE = TheTarget->createMCCodeEmitter(*MII, *MC);
   if (!MCE)
 return make_error("no code emitter for target " + TripleName,
inconvertibleErrorCode());
Index: llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
===
--- llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
+++ llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
@@ -106,7 +106,7 @@
   Res.Ctx->setObjectFileInfo(Res.MOFI.get());
 
   Res.MII.reset(TheTarget->createMCInstrInfo());
-  MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*Res.MII, *MRI, *Res.Ctx);
+  MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*Res.MII, *Res.Ctx);
   MCAsmBackend *MAB =
   TheTarget->createMCAsmBackend(*STI, *MRI, MCTargetOptions());
   std::unique_ptr OW = MAB->createObjectWriter(OS);
Index: llvm/tools/llvm-ml/llvm-ml.cpp
===
--- llvm/tools/llvm-ml/llvm-ml.cpp
+++ llvm/tools/llvm-ml/llvm-ml.cpp
@@ -377,7 +377,7 @@
 // Set up the AsmStreamer.
 std::unique_ptr CE;
 if (InputArgs.hasArg(OPT_show_encoding))
-  CE.reset(TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx));
+  CE.reset(TheTarget->createMCCodeEmitter(*MCII, Ctx));
 
 std::unique_ptr MAB(
 TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions));
@@ -395,7 +395,7 @@
   OS = BOS.get();
 }
 
-MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
+MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, Ctx);
 MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions);
 Str.reset(TheTarget->createMCObjectStreamer(
 TheTriple, Ctx, std::unique_ptr(MAB),
Index: llvm/tools/llvm-mca/llvm-mca.cpp
==

[PATCH] D119846: [NFC][MC] remove unused argument `MCRegisterInfo` in `MCCodeEmitter`

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

In D119846#3325334 , @skan wrote:

> @achieveartificialintelligence  Please explain why a patch is reverted in the 
> commit message next time.

OK, thanks for your guidance!


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
achieveartificialintelligence marked an inline comment as done.
Closed by commit rG7798ecca9c3d: [RISCV] add the MC layer support of Zfinx 
extension (authored by achieveartificialintelligence).

Changed prior to commit:
  https://reviews.llvm.org/D93298?vs=407482&id=409617#toc

Repository:
  rG LLVM Github Monorepo

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Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcv

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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achieveartificialintelligence added a comment.

Thanks all!


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[PATCH] D108189: [RISCV] Support experimental 'P' extension 0.9.11

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sunshaoce updated this revision to Diff 443552.
sunshaoce added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -187,3 +187,15 @@
 
 .attribute arch, "rv32if_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
+
+.attribute arch, "rv32ip0p911"
+# CHECK: attribute  5, "rv32i2p0_p0p911_zbpbo0p911_zpn0p911_zpsfoperand0p911"
+
+.attribute arch, "rv32izbpbo0p911"
+# CHECK: attribute  5, "rv32i2p0_zbpbo0p911"
+
+.attribute arch, "rv32izpn0p911"
+# CHECK: attribute  5, "rv32i2p0_zpn0p911"
+
+.attribute arch, "rv32izpsfoperand0p911"
+# CHECK: attribute  5, "rv32i2p0_zpsfoperand0p911"
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -109,6 +109,11 @@
 {"zbr", RISCVExtensionVersion{0, 93}},
 {"zbt", RISCVExtensionVersion{0, 93}},
 {"zvfh", RISCVExtensionVersion{0, 1}},
+
+{"p", RISCVExtensionVersion{0, 911}},
+{"zbpbo", RISCVExtensionVersion{0, 911}},
+{"zpn", RISCVExtensionVersion{0, 911}},
+{"zpsfoperand", RISCVExtensionVersion{0, 911}},
 };
 
 static bool stripExperimentalPrefix(StringRef &Ext) {
@@ -598,8 +603,8 @@
 
 // The order is OK, then push it into features.
 // TODO: Use version number when setting target features
-// Currently LLVM supports only "mafdcbv".
-StringRef SupportedStandardExtension = "mafdcbv";
+// Currently LLVM supports only "mafdcbpv".
+StringRef SupportedStandardExtension = "mafdcbpv";
 if (!SupportedStandardExtension.contains(C))
   return createStringError(errc::invalid_argument,
"unsupported standard user-level extension '%c'",
@@ -773,6 +778,7 @@
 static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"};
 static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
 static const char *ImpliedExtsZvfh[] = {"zve32f"};
+static const char *ImpliedExtsP[] = {"zbpbo", "zpn", "zpsfoperand"};
 
 struct ImpliedExtsEntry {
   StringLiteral Name;
@@ -787,6 +793,7 @@
 
 // Note: The table needs to be sorted by name.
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
+{{"p"}, {ImpliedExtsP}},
 {{"v"}, {ImpliedExtsV}},
 {{"zdinx"}, {ImpliedExtsZdinx}},
 {{"zfh"}, {ImpliedExtsZfh}},
Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -42,6 +42,10 @@
 // CHECK-NOT: __riscv_zkr
 // CHECK-NOT: __riscv_zkt
 // CHECK-NOT: __riscv_zk
+// CHECK-NOT: __riscv_p
+// CHECK-NOT: __riscv_zbpbo
+// CHECK-NOT: __riscv_zpn
+// CHECK-NOT: __riscv_zpsfoperand
 // CHECK-NOT: __riscv_zicbom
 // CHECK-NOT: __riscv_zicboz
 
@@ -224,6 +228,44 @@
 // CHECK-ZBT-NOT: __riscv_b
 // CHECK-ZBT-EXT: __riscv_zbt 93000{{$}}
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32ip0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64ip0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// CHECK-P-EXT: __riscv_p 911000{{$}}
+// CHECK-P-EXT: __riscv_zbpbo 911000{{$}}
+// CHECK-P-EXT: __riscv_zpn 911000{{$}}
+// CHECK-P-EXT: __riscv_zpsfoperand 911000{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izbpbo0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBPBO-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izbpbo0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBPBO-EXT %s
+// CHECK-ZBPBO-NOT: __riscv_p
+// CHECK-ZBPBO-EXT: __riscv_zbpbo 911000{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpn0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpn0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// CHECK-ZPN-NOT: __riscv_p
+// CHECK-ZPN-EXT: __riscv_zpn 911000{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -me

[PATCH] D128604: [RISCV] Support Zbpbo extension v0.9.11

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 443555.
sunshaoce added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128604/new/

https://reviews.llvm.org/D128604

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv32-zbpbo.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv64-zbpbo.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo.ll
  llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv32zbpbo-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-valid.s

Index: llvm/test/MC/RISCV/rv64zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-valid.s
@@ -0,0 +1,29 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
+fsrw t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s  -triple=riscv64 -mattr=+experimental-zbpbo \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 63
+# CHECK-S-OBJ: rev t0, t1
+rev x5, x6
Index: llvm/test/MC/RISCV/rv32zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-valid.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
+clz t0, t1
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
+fsr t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: fsri t0, t1, t2, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x3c]
+fsri t0, t1, t2, 0
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
@@ -0,0 +1,26 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases \
+# RUN: | FileCheck -check-prefi

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce added a comment.

In D95588#3641900 , @Jim wrote:

> In D95588#3622052 , @sunshaoce wrote:
>
>> Hello @Jim! We are developing the P extension, are you still maintaining 
>> this patch? Or would you mind co-development together?
>
> Yes, I am still on developing the P extension. But it seems spec has the 
> issue https://github.com/riscv/riscv-p-spec/issues/137 need to clarify.
> And some instruction (CLZ, FSR and FSRI) in Zbpbo only be aliased to B 
> extension on RV32. It is complicated if P extension are enabled on RV64.

Yes, this problem does exist. Thanks for your reply, looking forward to more 
cooperation!


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[PATCH] D125157: [RISCV][NFC] Add more tests for clang driver.

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sunshaoce added inline comments.



Comment at: clang/test/Driver/riscv-arch.c:583
+// RV32-ZHINX-BADVERS: unsupported version number 0.1 for extension 'zhinx'
\ No newline at end of file


Add a newline here.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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achieveartificialintelligence added a comment.
Herald added a subscriber: vkmr.

Ping


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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achieveartificialintelligence updated this revision to Diff 372863.
achieveartificialintelligence added a comment.

support zfinx-1.0-rc


Repository:
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Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZdinx.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZhinx.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzfdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfhinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zfinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zfinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zfinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zfinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zfinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zfinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zfinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zfinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.s s1, s2, s2
+# CHECK-ALIAS: fabs.s s1, s2
+fabs.s s1, s2
+# CHECK-INST: fsgnjn.s s2, s3, s3
+# CHECK-ALIAS: fneg.s s2, s3
+fneg.s s2, s3
+
+# CHECK-INST: flt.s tp, s6, s5
+# CHECK-ALIAS: flt.s tp, s6, s5
+fgt.s x4, s5, s6
+# CHECK-INST: fle.s t2, s1, s0
+# CHECK-ALIAS: fle.s t2, s1, s0
+fge.s x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.s a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.s a0, a1, a2, a3{{[[:space:]]}}
+fmadd.s x10, x11, x12, x13
+# CHECK-INST: fmsub.s a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.s a4, a5, a6, a7{{[[:space:]]}}
+fmsub.s x14, x15, x16, x17
+# CHECK-INST: fnmsub.s s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.s s2, s3, s4, s5{{[[:space:]]}}
+fnmsub.s x18, x19, x20, x21
+# CHECK-INST: fnmadd.s s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.s s6, s7, s8, s9{{[[:space:]]}}
+fnmadd.s x22, x23, x24, x25
+# CHECK-INST: fadd.s s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.s s10, s11, t3{{[[:space:]]}}
+fadd.s x26, x27, x28
+# CHECK-INST: fsub.s t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.s t4, t5, t6{{[[:space:]]}}
+fsub.s x29, x30, x31
+# CHECK-INST: fmul.s s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.s s0, s1, s2{{[[:space:]]}}
+fmul.s s0, s1, s2
+# CHECK-INST: fdiv.s s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.s s3, s4, s5{{[[:space:]]}}
+fdiv.s s3, s4, s5
+# CHECK-INST: sqrt.s s6, s7, dyn
+# CHECK-ALIAS: sqrt.s s6, s7{{[[:space:]]}}
+fsqrt.s s6, s7
+# CHECK-INST: fcvt.w.s a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.s a0, s5{{[[:space:]]}}
+fcvt.w.s a0, s5
+# CHECK-INST: fcvt.wu.s a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.s a1, s6{{[[:space:]]}}
+fcvt.wu.s a

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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achieveartificialintelligence updated this revision to Diff 372866.
achieveartificialintelligence added a comment.

Updating D93298 : [RISCV] add the MC layer 
support of Zfinx extension


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Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZdinx.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZhinx.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,83 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3{{[[:space:]]}}
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7{{[[:space:]]}}
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5{{[[:space:]]}}
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9{{[[:space:]]}}
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3{{[[:space:]]}}
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6{{[[:space:]]}}
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2{{[[:space:]]}}
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5{{[[:space:]]}}
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7{{[[:space:]]}}
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5{{[[:space:]]}}
+fcvt.w.h a0, s5
+# CHECK-INS

[PATCH] D109799: [RISCV] add Half-precision test for load/store

[Shao-Ce Sun via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 373129.
achieveartificialintelligence added a comment.

add Half-precision test for segment load/store


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Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsse.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c

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[PATCH] D109799: [RISCV] add Half-precision test for load/store

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achieveartificialintelligence updated this revision to Diff 373161.
achieveartificialintelligence added a comment.

add more Half-precision tests


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Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vamoadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vamoand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vamomax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vamomin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vamoor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vamoswap.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vamoxor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vasub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfabs.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfirst.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredosum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmclr.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmmv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmnand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmnor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmnot.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmseq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmset.c
  clang/test/Code

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce Sun via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 373170.
achieveartificialintelligence added a comment.

fix CI error


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZdinx.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZhinx.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,83 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3{{[[:space:]]}}
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7{{[[:space:]]}}
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5{{[[:space:]]}}
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9{{[[:space:]]}}
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3{{[[:space:]]}}
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6{{[[:space:]]}}
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2{{[[:space:]]}}
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5{{[[:space:]]}}
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7{{[[:space:]]}}
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5{{[[:space:]]}}
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6{{[[:space:]]}}
+fcvt.wu.h a1, s6

[PATCH] D109799: [RISCV] add Half-precision test for clang

[Shao-Ce Sun via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 374095.
achieveartificialintelligence added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109799/new/

https://reviews.llvm.org/D109799

Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfabs.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredosum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vreinterpret.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vrgather.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsse.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vundefined.c

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[PATCH] D109799: [RISCV] add Half-precision test for clang

[Shao-Ce Sun via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

In D109799#3008067 , @craig.topper 
wrote:

> This patch is really large and touches tests for integer operations. Can you 
> just pre-commit the removal of lines with just comment characters. No need to 
> review for that. That should reduce the noise in this patch.

Addressed, and thanks!


Repository:
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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce Sun via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

ping.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D109799: [RISCV] add Half-precision test for clang

[Shao-Ce Sun via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe247fed23b92: [RISCV] add Half-precision test for clang 
(authored by achieveartificialintelligence).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109799/new/

https://reviews.llvm.org/D109799

Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfabs.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredosum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vreinterpret.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vrgather.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsse.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vundefined.c

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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce Sun via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 374131.
achieveartificialintelligence added a comment.

Address @jrtc27 's comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZdinx.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZhinx.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,83 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zhinx < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3{{[[:space:]]}}
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7{{[[:space:]]}}
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5{{[[:space:]]}}
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9{{[[:space:]]}}
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3{{[[:space:]]}}
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6{{[[:space:]]}}
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2{{[[:space:]]}}
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5{{[[:space:]]}}
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7{{[[:space:]]}}
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5{{[[:space:]]}}
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6{{[[:space:]]}}
+fc

[PATCH] D97138: [Driver] replace argc_ with argc

[Shao-Ce Sun via Phabricator via cfe-commits]

achieveartificialintelligence created this revision.
achieveartificialintelligence added reviewers: MaskRay, jhenderson, aganea, 
richard.barton.arm, sameeranjoshi.
Herald added a reviewer: awarzynski.
achieveartificialintelligence requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Using `int main(int argc, const char **argv)` instead of `int main(int argc_, 
const char **argv_)` to keep pace with other `main()`s.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D97138

Files:
  clang/tools/driver/driver.cpp
  flang/tools/flang-driver/driver.cpp

Index: flang/tools/flang-driver/driver.cpp
===
--- flang/tools/flang-driver/driver.cpp
+++ flang/tools/flang-driver/driver.cpp
@@ -66,27 +66,27 @@
   return 1;
 }
 
-int main(int argc_, const char **argv_) {
+int main(int argc, const char **argv) {
 
   // Initialize variables to call the driver
-  llvm::InitLLVM x(argc_, argv_);
-  llvm::SmallVector argv(argv_, argv_ + argc_);
+  llvm::InitLLVM x(argc, argv);
+  llvm::SmallVector Argv(argv, argv + argc);
 
   clang::driver::ParsedClangName targetandMode("flang", "--driver-mode=flang");
-  std::string driverPath = GetExecutablePath(argv[0]);
+  std::string driverPath = GetExecutablePath(Argv[0]);
 
   // Check if flang-new is in the frontend mode
   auto firstArg = std::find_if(
-  argv.begin() + 1, argv.end(), [](const char *a) { return a != nullptr; });
-  if (firstArg != argv.end()) {
-if (llvm::StringRef(argv[1]).startswith("-cc1")) {
-  llvm::errs() << "error: unknown integrated tool '" << argv[1] << "'. "
+  Argv.begin() + 1, Argv.end(), [](const char *a) { return a != nullptr; });
+  if (firstArg != Argv.end()) {
+if (llvm::StringRef(Argv[1]).startswith("-cc1")) {
+  llvm::errs() << "error: unknown integrated tool '" << Argv[1] << "'. "
<< "Valid tools include '-fc1'.\n";
   return 1;
 }
 // Call flang-new frontend
-if (llvm::StringRef(argv[1]).startswith("-fc1")) {
-  return ExecuteFC1Tool(argv);
+if (llvm::StringRef(Argv[1]).startswith("-fc1")) {
+  return ExecuteFC1Tool(Argv);
 }
   }
 
@@ -94,14 +94,14 @@
 
   // Create DiagnosticsEngine for the compiler driver
   llvm::IntrusiveRefCntPtr diagOpts =
-  CreateAndPopulateDiagOpts(argv);
+  CreateAndPopulateDiagOpts(Argv);
   llvm::IntrusiveRefCntPtr diagID(
   new clang::DiagnosticIDs());
   Fortran::frontend::TextDiagnosticPrinter *diagClient =
   new Fortran::frontend::TextDiagnosticPrinter(llvm::errs(), &*diagOpts);
 
   diagClient->set_prefix(
-  std::string(llvm::sys::path::stem(GetExecutablePath(argv[0];
+  std::string(llvm::sys::path::stem(GetExecutablePath(Argv[0];
 
   clang::DiagnosticsEngine diags(diagID, &*diagOpts, diagClient);
 
@@ -110,7 +110,7 @@
   llvm::sys::getDefaultTargetTriple(), diags, "flang LLVM compiler");
   theDriver.setTargetAndMode(targetandMode);
   std::unique_ptr c(
-  theDriver.BuildCompilation(argv));
+  theDriver.BuildCompilation(Argv));
   llvm::SmallVector, 4>
   failingCommands;
 
Index: clang/tools/driver/driver.cpp
===
--- clang/tools/driver/driver.cpp
+++ clang/tools/driver/driver.cpp
@@ -340,25 +340,25 @@
   return 1;
 }
 
-int main(int argc_, const char **argv_) {
+int main(int argc, const char **argv) {
   noteBottomOfStack();
-  llvm::InitLLVM X(argc_, argv_);
+  llvm::InitLLVM X(argc, argv);
   llvm::setBugReportMsg("PLEASE submit a bug report to " BUG_REPORT_URL
 " and include the crash backtrace, preprocessed "
 "source, and associated run script.\n");
-  SmallVector argv(argv_, argv_ + argc_);
+  SmallVector Argv(argv, argv + argc);
 
   if (llvm::sys::Process::FixupStandardFileDescriptors())
 return 1;
 
   llvm::InitializeAllTargets();
-  auto TargetAndMode = ToolChain::getTargetAndModeFromProgramName(argv[0]);
+  auto TargetAndMode = ToolChain::getTargetAndModeFromProgramName(Argv[0]);
 
   llvm::BumpPtrAllocator A;
   llvm::StringSaver Saver(A);
 
   // Parse response files using the GNU syntax, unless we're in CL mode. There
-  // are two ways to put clang in CL compatibility mode: argv[0] is either
+  // are two ways to put clang in CL compatibility mode: Argv[0] is either
   // clang-cl or cl, or --driver-mode=cl is on the command line. The normal
   // command line parsing can't happen until after response file parsing, so we
   // have to manually search for a --driver-mode=cl argument the hard way.
@@ -366,20 +366,20 @@
   // response files written by clang will tokenize the same way in either mode.
   bool ClangCLMode = false;
   if (StringRef(TargetAndMode.DriverMode).equals("--driver-mode=cl") ||
-  llvm::find_if(argv, [](const char *F) {
+  llvm::find_if(Argv, [](const char *F) {
 return F && strcmp(F, "--d

[PATCH] D97138: [clang][flang] Improve the consistency of the code-base

[Shao-Ce Sun via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 325609.
achieveartificialintelligence retitled this revision from "[Driver] replace 
argc_ with argc" to "[clang][flang] Improve the consistency of the code-base".
achieveartificialintelligence edited the summary of this revision.
achieveartificialintelligence removed a reviewer: jhenderson.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/tools/driver/driver.cpp
  flang/tools/flang-driver/driver.cpp

Index: flang/tools/flang-driver/driver.cpp
===
--- flang/tools/flang-driver/driver.cpp
+++ flang/tools/flang-driver/driver.cpp
@@ -66,27 +66,27 @@
   return 1;
 }
 
-int main(int argc_, const char **argv_) {
+int main(int argC, const char **argV) {
 
   // Initialize variables to call the driver
-  llvm::InitLLVM x(argc_, argv_);
-  llvm::SmallVector argv(argv_, argv_ + argc_);
+  llvm::InitLLVM x(argC, argV);
+  llvm::SmallVector argValues(argV, argV + argC);
 
   clang::driver::ParsedClangName targetandMode("flang", "--driver-mode=flang");
-  std::string driverPath = GetExecutablePath(argv[0]);
+  std::string driverPath = GetExecutablePath(argValues[0]);
 
   // Check if flang-new is in the frontend mode
-  auto firstArg = std::find_if(
-  argv.begin() + 1, argv.end(), [](const char *a) { return a != nullptr; });
-  if (firstArg != argv.end()) {
-if (llvm::StringRef(argv[1]).startswith("-cc1")) {
-  llvm::errs() << "error: unknown integrated tool '" << argv[1] << "'. "
-   << "Valid tools include '-fc1'.\n";
+  auto firstArg = std::find_if(argValues.begin() + 1, argValues.end(),
+  [](const char *a) { return a != nullptr; });
+  if (firstArg != argValues.end()) {
+if (llvm::StringRef(argValues[1]).startswith("-cc1")) {
+  llvm::errs() << "error: unknown integrated tool '" << argValues[1]
+   << "'. " << "Valid tools include '-fc1'.\n";
   return 1;
 }
 // Call flang-new frontend
-if (llvm::StringRef(argv[1]).startswith("-fc1")) {
-  return ExecuteFC1Tool(argv);
+if (llvm::StringRef(argValues[1]).startswith("-fc1")) {
+  return ExecuteFC1Tool(argValues);
 }
   }
 
@@ -94,14 +94,14 @@
 
   // Create DiagnosticsEngine for the compiler driver
   llvm::IntrusiveRefCntPtr diagOpts =
-  CreateAndPopulateDiagOpts(argv);
+  CreateAndPopulateDiagOpts(argValues);
   llvm::IntrusiveRefCntPtr diagID(
   new clang::DiagnosticIDs());
   Fortran::frontend::TextDiagnosticPrinter *diagClient =
   new Fortran::frontend::TextDiagnosticPrinter(llvm::errs(), &*diagOpts);
 
   diagClient->set_prefix(
-  std::string(llvm::sys::path::stem(GetExecutablePath(argv[0];
+  std::string(llvm::sys::path::stem(GetExecutablePath(argValues[0];
 
   clang::DiagnosticsEngine diags(diagID, &*diagOpts, diagClient);
 
@@ -110,7 +110,7 @@
   llvm::sys::getDefaultTargetTriple(), diags, "flang LLVM compiler");
   theDriver.setTargetAndMode(targetandMode);
   std::unique_ptr c(
-  theDriver.BuildCompilation(argv));
+  theDriver.BuildCompilation(argValues));
   llvm::SmallVector, 4>
   failingCommands;
 
Index: clang/tools/driver/driver.cpp
===
--- clang/tools/driver/driver.cpp
+++ clang/tools/driver/driver.cpp
@@ -340,25 +340,25 @@
   return 1;
 }
 
-int main(int argc_, const char **argv_) {
+int main(int Argc, const char **Argv) {
   noteBottomOfStack();
-  llvm::InitLLVM X(argc_, argv_);
+  llvm::InitLLVM X(Argc, Argv);
   llvm::setBugReportMsg("PLEASE submit a bug report to " BUG_REPORT_URL
 " and include the crash backtrace, preprocessed "
 "source, and associated run script.\n");
-  SmallVector argv(argv_, argv_ + argc_);
+  SmallVector ArgValues(Argv, Argv + Argc);
 
   if (llvm::sys::Process::FixupStandardFileDescriptors())
 return 1;
 
   llvm::InitializeAllTargets();
-  auto TargetAndMode = ToolChain::getTargetAndModeFromProgramName(argv[0]);
+  auto TargetAndMode = ToolChain::getTargetAndModeFromProgramName(ArgValues[0]);
 
   llvm::BumpPtrAllocator A;
   llvm::StringSaver Saver(A);
 
   // Parse response files using the GNU syntax, unless we're in CL mode. There
-  // are two ways to put clang in CL compatibility mode: argv[0] is either
+  // are two ways to put clang in CL compatibility mode: ArgValues[0] is either
   // clang-cl or cl, or --driver-mode=cl is on the command line. The normal
   // command line parsing can't happen until after response file parsing, so we
   // have to manually search for a --driver-mode=cl argument the hard way.
@@ -366,22 +366,22 @@
   // response files written by clang will tokenize the same way in either mode.
   bool ClangCLMode = false;
   if (StringRef(TargetAndMode.DriverMode).equals("--driver-mode=cl") ||
-  llvm::find_if(a

[PATCH] D97138: [clang][flang] Improve the consistency of the code-base

[Shao-Ce Sun via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

In D97138#2578563 , @awarzynski wrote:

> Thank you for submitting this @achieveartificialintelligence !
>
> The aim of these changes is to improve the consistency of the code-base with 
> respect to the coding standards documented separately for Clang 
>  and Flang 
> . 
> I think that this is a very positive suggestion, but would like to request a 
> few refinements before this is ready:
>
> - Please note that in LLVM/Clang, variables names start with upper case (so 
> it should be int `main(int Argc, const char **Argv)` instead of `main(int 
> argc, const char **argv)` ). link 
> 
> - In Flang the rules are slightly different, and the variable names start 
> with a lower case (so it should be int `main(int Argc, const char **Argv)` 
> instead of `main(int argc, const char **argv)` ). link 
> 
> - Your commit message refers to _a driver_, but in fact you are updating 2 
> specific drivers: Clang compiler driver and Flang compiler driver - could you 
> clarify?
> - Your commit message refers to `argc_` specifically, but you are updating 
> `argc_`, `argv_` and `Argv/argv` too.
>
> Personally I'd prefer `ArgC/argC` and `ArgV/argV` for input parameters and 
> `ArgValues/argValues` for the local variable. This way it would be more 
> self-explanatory. But that's a matter of style. As long as this is consistent 
> with the coding standards, I think that this should be accepted.

Thank you very much for your comment.


Repository:
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[PATCH] D97138: [clang][flang] Improve the consistency of the code-base

[Shao-Ce Sun via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 326313.
achieveartificialintelligence edited the summary of this revision.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97138/new/

https://reviews.llvm.org/D97138

Files:
  clang/tools/driver/driver.cpp
  flang/tools/flang-driver/driver.cpp

Index: flang/tools/flang-driver/driver.cpp
===
--- flang/tools/flang-driver/driver.cpp
+++ flang/tools/flang-driver/driver.cpp
@@ -66,27 +66,27 @@
   return 1;
 }
 
-int main(int argc_, const char **argv_) {
+int main(int argc, const char **argv) {
 
   // Initialize variables to call the driver
-  llvm::InitLLVM x(argc_, argv_);
-  llvm::SmallVector argv(argv_, argv_ + argc_);
+  llvm::InitLLVM x(argc, argv);
+  llvm::SmallVector args(argv, argv + argc);
 
   clang::driver::ParsedClangName targetandMode("flang", "--driver-mode=flang");
-  std::string driverPath = GetExecutablePath(argv[0]);
+  std::string driverPath = GetExecutablePath(args[0]);
 
   // Check if flang-new is in the frontend mode
   auto firstArg = std::find_if(
-  argv.begin() + 1, argv.end(), [](const char *a) { return a != nullptr; });
-  if (firstArg != argv.end()) {
-if (llvm::StringRef(argv[1]).startswith("-cc1")) {
-  llvm::errs() << "error: unknown integrated tool '" << argv[1] << "'. "
+  args.begin() + 1, args.end(), [](const char *a) { return a != nullptr; });
+  if (firstArg != args.end()) {
+if (llvm::StringRef(args[1]).startswith("-cc1")) {
+  llvm::errs() << "error: unknown integrated tool '" << args[1] << "'. "
<< "Valid tools include '-fc1'.\n";
   return 1;
 }
 // Call flang-new frontend
-if (llvm::StringRef(argv[1]).startswith("-fc1")) {
-  return ExecuteFC1Tool(argv);
+if (llvm::StringRef(args[1]).startswith("-fc1")) {
+  return ExecuteFC1Tool(args);
 }
   }
 
@@ -94,14 +94,14 @@
 
   // Create DiagnosticsEngine for the compiler driver
   llvm::IntrusiveRefCntPtr diagOpts =
-  CreateAndPopulateDiagOpts(argv);
+  CreateAndPopulateDiagOpts(args);
   llvm::IntrusiveRefCntPtr diagID(
   new clang::DiagnosticIDs());
   Fortran::frontend::TextDiagnosticPrinter *diagClient =
   new Fortran::frontend::TextDiagnosticPrinter(llvm::errs(), &*diagOpts);
 
   diagClient->set_prefix(
-  std::string(llvm::sys::path::stem(GetExecutablePath(argv[0];
+  std::string(llvm::sys::path::stem(GetExecutablePath(args[0];
 
   clang::DiagnosticsEngine diags(diagID, &*diagOpts, diagClient);
 
@@ -110,7 +110,7 @@
   llvm::sys::getDefaultTargetTriple(), diags, "flang LLVM compiler");
   theDriver.setTargetAndMode(targetandMode);
   std::unique_ptr c(
-  theDriver.BuildCompilation(argv));
+  theDriver.BuildCompilation(args));
   llvm::SmallVector, 4>
   failingCommands;
 
Index: clang/tools/driver/driver.cpp
===
--- clang/tools/driver/driver.cpp
+++ clang/tools/driver/driver.cpp
@@ -340,25 +340,25 @@
   return 1;
 }
 
-int main(int argc_, const char **argv_) {
+int main(int Argc, const char **Argv) {
   noteBottomOfStack();
-  llvm::InitLLVM X(argc_, argv_);
+  llvm::InitLLVM X(Argc, Argv);
   llvm::setBugReportMsg("PLEASE submit a bug report to " BUG_REPORT_URL
 " and include the crash backtrace, preprocessed "
 "source, and associated run script.\n");
-  SmallVector argv(argv_, argv_ + argc_);
+  SmallVector Args(Argv, Argv + Argc);
 
   if (llvm::sys::Process::FixupStandardFileDescriptors())
 return 1;
 
   llvm::InitializeAllTargets();
-  auto TargetAndMode = ToolChain::getTargetAndModeFromProgramName(argv[0]);
+  auto TargetAndMode = ToolChain::getTargetAndModeFromProgramName(Args[0]);
 
   llvm::BumpPtrAllocator A;
   llvm::StringSaver Saver(A);
 
   // Parse response files using the GNU syntax, unless we're in CL mode. There
-  // are two ways to put clang in CL compatibility mode: argv[0] is either
+  // are two ways to put clang in CL compatibility mode: Args[0] is either
   // clang-cl or cl, or --driver-mode=cl is on the command line. The normal
   // command line parsing can't happen until after response file parsing, so we
   // have to manually search for a --driver-mode=cl argument the hard way.
@@ -366,20 +366,20 @@
   // response files written by clang will tokenize the same way in either mode.
   bool ClangCLMode = false;
   if (StringRef(TargetAndMode.DriverMode).equals("--driver-mode=cl") ||
-  llvm::find_if(argv, [](const char *F) {
+  llvm::find_if(Args, [](const char *F) {
 return F && strcmp(F, "--driver-mode=cl") == 0;
-  }) != argv.end()) {
+  }) != Args.end()) {
 ClangCLMode = true;
   }
   enum { Default, POSIX, Windows } RSPQuoting = Default;
-  for (const char *F : argv) {
+  for (const char *F : Args) {
 if (strcmp(F, "--rsp-quoting=posix") == 0)
   RSPQuoting = POSIX;
 else 

[PATCH] D97138: [clang][flang] Improve the consistency of the code-base

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achieveartificialintelligence marked an inline comment as done.
achieveartificialintelligence added a comment.

Thanks @aganea. And I have a question that, should I use `argc` & `argv` or 
`argC` & `argV` in the flang part now ?


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[PATCH] D97138: [clang][flang] Improve the consistency of the code-base

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This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGad14ccc8c22e: [clang][flang] Improve the consistency of the 
code-base (authored by achieveartificialintelligence).

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Files:
  clang/tools/driver/driver.cpp
  flang/tools/flang-driver/driver.cpp

Index: flang/tools/flang-driver/driver.cpp
===
--- flang/tools/flang-driver/driver.cpp
+++ flang/tools/flang-driver/driver.cpp
@@ -66,27 +66,27 @@
   return 1;
 }
 
-int main(int argc_, const char **argv_) {
+int main(int argc, const char **argv) {
 
   // Initialize variables to call the driver
-  llvm::InitLLVM x(argc_, argv_);
-  llvm::SmallVector argv(argv_, argv_ + argc_);
+  llvm::InitLLVM x(argc, argv);
+  llvm::SmallVector args(argv, argv + argc);
 
   clang::driver::ParsedClangName targetandMode("flang", "--driver-mode=flang");
-  std::string driverPath = GetExecutablePath(argv[0]);
+  std::string driverPath = GetExecutablePath(args[0]);
 
   // Check if flang-new is in the frontend mode
   auto firstArg = std::find_if(
-  argv.begin() + 1, argv.end(), [](const char *a) { return a != nullptr; });
-  if (firstArg != argv.end()) {
-if (llvm::StringRef(argv[1]).startswith("-cc1")) {
-  llvm::errs() << "error: unknown integrated tool '" << argv[1] << "'. "
+  args.begin() + 1, args.end(), [](const char *a) { return a != nullptr; });
+  if (firstArg != args.end()) {
+if (llvm::StringRef(args[1]).startswith("-cc1")) {
+  llvm::errs() << "error: unknown integrated tool '" << args[1] << "'. "
<< "Valid tools include '-fc1'.\n";
   return 1;
 }
 // Call flang-new frontend
-if (llvm::StringRef(argv[1]).startswith("-fc1")) {
-  return ExecuteFC1Tool(argv);
+if (llvm::StringRef(args[1]).startswith("-fc1")) {
+  return ExecuteFC1Tool(args);
 }
   }
 
@@ -94,14 +94,14 @@
 
   // Create DiagnosticsEngine for the compiler driver
   llvm::IntrusiveRefCntPtr diagOpts =
-  CreateAndPopulateDiagOpts(argv);
+  CreateAndPopulateDiagOpts(args);
   llvm::IntrusiveRefCntPtr diagID(
   new clang::DiagnosticIDs());
   Fortran::frontend::TextDiagnosticPrinter *diagClient =
   new Fortran::frontend::TextDiagnosticPrinter(llvm::errs(), &*diagOpts);
 
   diagClient->set_prefix(
-  std::string(llvm::sys::path::stem(GetExecutablePath(argv[0];
+  std::string(llvm::sys::path::stem(GetExecutablePath(args[0];
 
   clang::DiagnosticsEngine diags(diagID, &*diagOpts, diagClient);
 
@@ -110,7 +110,7 @@
   llvm::sys::getDefaultTargetTriple(), diags, "flang LLVM compiler");
   theDriver.setTargetAndMode(targetandMode);
   std::unique_ptr c(
-  theDriver.BuildCompilation(argv));
+  theDriver.BuildCompilation(args));
   llvm::SmallVector, 4>
   failingCommands;
 
Index: clang/tools/driver/driver.cpp
===
--- clang/tools/driver/driver.cpp
+++ clang/tools/driver/driver.cpp
@@ -340,25 +340,25 @@
   return 1;
 }
 
-int main(int argc_, const char **argv_) {
+int main(int Argc, const char **Argv) {
   noteBottomOfStack();
-  llvm::InitLLVM X(argc_, argv_);
+  llvm::InitLLVM X(Argc, Argv);
   llvm::setBugReportMsg("PLEASE submit a bug report to " BUG_REPORT_URL
 " and include the crash backtrace, preprocessed "
 "source, and associated run script.\n");
-  SmallVector argv(argv_, argv_ + argc_);
+  SmallVector Args(Argv, Argv + Argc);
 
   if (llvm::sys::Process::FixupStandardFileDescriptors())
 return 1;
 
   llvm::InitializeAllTargets();
-  auto TargetAndMode = ToolChain::getTargetAndModeFromProgramName(argv[0]);
+  auto TargetAndMode = ToolChain::getTargetAndModeFromProgramName(Args[0]);
 
   llvm::BumpPtrAllocator A;
   llvm::StringSaver Saver(A);
 
   // Parse response files using the GNU syntax, unless we're in CL mode. There
-  // are two ways to put clang in CL compatibility mode: argv[0] is either
+  // are two ways to put clang in CL compatibility mode: Args[0] is either
   // clang-cl or cl, or --driver-mode=cl is on the command line. The normal
   // command line parsing can't happen until after response file parsing, so we
   // have to manually search for a --driver-mode=cl argument the hard way.
@@ -366,20 +366,20 @@
   // response files written by clang will tokenize the same way in either mode.
   bool ClangCLMode = false;
   if (StringRef(TargetAndMode.DriverMode).equals("--driver-mode=cl") ||
-  llvm::find_if(argv, [](const char *F) {
+  llvm::find_if(Args, [](const char *F) {
 return F && strcmp(F, "--driver-mode=cl") == 0;
-  }) != argv.end()) {
+  }) != Args.end()) {
 ClangCLMode = true;
   }
   enum { Default, POSIX, Windows } RS

[PATCH] D111866: [RISCV] Support Zfhmin extension

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achieveartificialintelligence updated this revision to Diff 382195.
achieveartificialintelligence added a comment.

Rebase


Repository:
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Files:
  clang/test/Driver/riscv-arch.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zfhmin-invalid.s
  llvm/test/MC/RISCV/rv32zfhmin-valid.s

Index: llvm/test/MC/RISCV/rv32zfhmin-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zfhmin-valid.s
@@ -0,0 +1,62 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfhmin,+d -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfhmin,+d -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfhmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfhmin,+d -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfhmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfhmin,+d -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: flh ft0, 12(a0)
+# CHECK-ASM: encoding: [0x07,0x10,0xc5,0x00]
+flh f0, 12(a0)
+# CHECK-ASM-AND-OBJ: flh ft1, 4(ra)
+# CHECK-ASM: encoding: [0x87,0x90,0x40,0x00]
+flh f1, +4(ra)
+# CHECK-ASM-AND-OBJ: flh ft2, -2048(a3)
+# CHECK-ASM: encoding: [0x07,0x91,0x06,0x80]
+flh f2, -2048(x13)
+# CHECK-ASM-AND-OBJ: flh ft3, -2048(s1)
+# CHECK-ASM: encoding: [0x87,0x91,0x04,0x80]
+flh f3, %lo(2048)(s1)
+# CHECK-ASM-AND-OBJ: flh ft4, 2047(s2)
+# CHECK-ASM: encoding: [0x07,0x12,0xf9,0x7f]
+flh f4, 2047(s2)
+# CHECK-ASM-AND-OBJ: flh ft5, 0(s3)
+# CHECK-ASM: encoding: [0x87,0x92,0x09,0x00]
+flh f5, 0(s3)
+
+# CHECK-ASM-AND-OBJ: fsh ft6, 2047(s4)
+# CHECK-ASM: encoding: [0xa7,0x1f,0x6a,0x7e]
+fsh f6, 2047(s4)
+# CHECK-ASM-AND-OBJ: fsh ft7, -2048(s5)
+# CHECK-ASM: encoding: [0x27,0x90,0x7a,0x80]
+fsh f7, -2048(s5)
+# CHECK-ASM-AND-OBJ: fsh fs0, -2048(s6)
+# CHECK-ASM: encoding: [0x27,0x10,0x8b,0x80]
+fsh f8, %lo(2048)(s6)
+# CHECK-ASM-AND-OBJ: fsh fs1, 999(s7)
+# CHECK-ASM: encoding: [0xa7,0x93,0x9b,0x3e]
+fsh f9, 999(s7)
+
+# CHECK-ASM-AND-OBJ: fmv.x.h a2, fs7
+# CHECK-ASM: encoding: [0x53,0x86,0x0b,0xe4]
+fmv.x.h a2, fs7
+# CHECK-ASM-AND-OBJ: fmv.h.x ft1, a6
+# CHECK-ASM: encoding: [0xd3,0x00,0x08,0xf4]
+fmv.h.x ft1, a6
+
+# CHECK-ASM-AND-OBJ: fcvt.s.h fa0, ft0
+# CHECK-ASM: encoding: [0x53,0x05,0x20,0x40]
+fcvt.s.h fa0, ft0
+# CHECK-ASM-AND-OBJ: fcvt.h.s ft2, fa2
+# CHECK-ASM: encoding: [0x53,0x71,0x06,0x44]
+fcvt.h.s ft2, fa2
+# CHECK-ASM-AND-OBJ: fcvt.d.h fa0, ft0
+# CHECK-ASM: encoding: [0x53,0x05,0x20,0x42]
+fcvt.d.h fa0, ft0
+# CHECK-ASM-AND-OBJ: fcvt.h.d ft2, fa2
+# CHECK-ASM: encoding: [0x53,0x71,0x16,0x44]
+fcvt.h.d ft2, fa2
Index: llvm/test/MC/RISCV/rv32zfhmin-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zfhmin-invalid.s
@@ -0,0 +1,23 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfhmin < %s 2>&1 | \
+# RUN:   FileCheck %s
+
+# Out of range immediates
+## simm12
+flh ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+fsh ft2, 2048(a1) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+# Memory operand not formatted correctly
+flh ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+
+# Invalid register names
+flh ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+flh ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
+
+# Integer registers where FP regs are expected
+fmv.x.h fs7, a2 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+
+# FP registers where integer regs are expected
+fmv.h.x a8, ft2 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+
+# Zfh instructions
+fmadd.h f10, f11, f12, f13, dyn # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point)
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -66,8 +66,11 @@
 .attribute arch, "rv32izbt"
 # CHECK: attribute  5, "rv32i2p0_zbt0p93"
 
+.attribute arch, "rv32ifzfhmi

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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achieveartificialintelligence marked 6 inline comments as done.
achieveartificialintelligence added inline comments.



Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:164
 
+static DecodeStatus DecodeGPRF16RegisterClass(MCInst &Inst, uint64_t RegNo,
+  uint64_t Address,

MaskRay wrote:
> Use `functionName`.
> 
> There is inconsistency in the code base but `functionName` is used much more 
> than `FunctionName`.
I fix this in D112520



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:539
 
+let RegAltNameIndices = [ABIRegAltName] in {
+  foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22,

jrtc27 wrote:
> This needs to be coordinated with D95588; you both define GPR pairs for RV32 
> but in different ways. There needs to be only one.
After D95588 is accepted, we will reuse this.


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[PATCH] D111866: [RISCV] Support Zfhmin extension

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achieveartificialintelligence updated this revision to Diff 383040.
achieveartificialintelligence added a comment.

Address @asb 's comment


Repository:
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Files:
  clang/test/Driver/riscv-arch.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zfhmin-invalid.s
  llvm/test/MC/RISCV/rv32zfhmin-valid.s

Index: llvm/test/MC/RISCV/rv32zfhmin-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zfhmin-valid.s
@@ -0,0 +1,62 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfhmin,+d -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfhmin,+d -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfhmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfhmin,+d -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfhmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfhmin,+d -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: flh ft0, 12(a0)
+# CHECK-ASM: encoding: [0x07,0x10,0xc5,0x00]
+flh f0, 12(a0)
+# CHECK-ASM-AND-OBJ: flh ft1, 4(ra)
+# CHECK-ASM: encoding: [0x87,0x90,0x40,0x00]
+flh f1, +4(ra)
+# CHECK-ASM-AND-OBJ: flh ft2, -2048(a3)
+# CHECK-ASM: encoding: [0x07,0x91,0x06,0x80]
+flh f2, -2048(x13)
+# CHECK-ASM-AND-OBJ: flh ft3, -2048(s1)
+# CHECK-ASM: encoding: [0x87,0x91,0x04,0x80]
+flh f3, %lo(2048)(s1)
+# CHECK-ASM-AND-OBJ: flh ft4, 2047(s2)
+# CHECK-ASM: encoding: [0x07,0x12,0xf9,0x7f]
+flh f4, 2047(s2)
+# CHECK-ASM-AND-OBJ: flh ft5, 0(s3)
+# CHECK-ASM: encoding: [0x87,0x92,0x09,0x00]
+flh f5, 0(s3)
+
+# CHECK-ASM-AND-OBJ: fsh ft6, 2047(s4)
+# CHECK-ASM: encoding: [0xa7,0x1f,0x6a,0x7e]
+fsh f6, 2047(s4)
+# CHECK-ASM-AND-OBJ: fsh ft7, -2048(s5)
+# CHECK-ASM: encoding: [0x27,0x90,0x7a,0x80]
+fsh f7, -2048(s5)
+# CHECK-ASM-AND-OBJ: fsh fs0, -2048(s6)
+# CHECK-ASM: encoding: [0x27,0x10,0x8b,0x80]
+fsh f8, %lo(2048)(s6)
+# CHECK-ASM-AND-OBJ: fsh fs1, 999(s7)
+# CHECK-ASM: encoding: [0xa7,0x93,0x9b,0x3e]
+fsh f9, 999(s7)
+
+# CHECK-ASM-AND-OBJ: fmv.x.h a2, fs7
+# CHECK-ASM: encoding: [0x53,0x86,0x0b,0xe4]
+fmv.x.h a2, fs7
+# CHECK-ASM-AND-OBJ: fmv.h.x ft1, a6
+# CHECK-ASM: encoding: [0xd3,0x00,0x08,0xf4]
+fmv.h.x ft1, a6
+
+# CHECK-ASM-AND-OBJ: fcvt.s.h fa0, ft0
+# CHECK-ASM: encoding: [0x53,0x05,0x20,0x40]
+fcvt.s.h fa0, ft0
+# CHECK-ASM-AND-OBJ: fcvt.h.s ft2, fa2
+# CHECK-ASM: encoding: [0x53,0x71,0x06,0x44]
+fcvt.h.s ft2, fa2
+# CHECK-ASM-AND-OBJ: fcvt.d.h fa0, ft0
+# CHECK-ASM: encoding: [0x53,0x05,0x20,0x42]
+fcvt.d.h fa0, ft0
+# CHECK-ASM-AND-OBJ: fcvt.h.d ft2, fa2
+# CHECK-ASM: encoding: [0x53,0x71,0x16,0x44]
+fcvt.h.d ft2, fa2
Index: llvm/test/MC/RISCV/rv32zfhmin-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zfhmin-invalid.s
@@ -0,0 +1,23 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfhmin < %s 2>&1 | \
+# RUN:   FileCheck %s
+
+# Out of range immediates
+## simm12
+flh ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+fsh ft2, 2048(a1) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+# Memory operand not formatted correctly
+flh ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+
+# Invalid register names
+flh ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+flh ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
+
+# Integer registers where FP regs are expected
+fmv.x.h fs7, a2 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+
+# FP registers where integer regs are expected
+fmv.h.x a8, ft2 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+
+# Zfh instructions
+fmadd.h f10, f11, f12, f13, dyn # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point)
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -66,8 +66,11 @@
 .attribute arch, "rv32izbt"
 # CHECK: attribute  5, "rv32i2p0_zbt0p93"
 
+.attribute a

[PATCH] D112774: Support k-ext clang intrinsics

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence created this revision.
achieveartificialintelligence added reviewers: HsiangKai, kito-cheng, 
craig.topper, jrtc27, luismarques, asb.
Herald added subscribers: frasercrmck, apazos, sameer.abuasal, s.egerton, Jim, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, niosHD, sabuasal, simoncook, johnrusso, rbar.
achieveartificialintelligence requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D112774

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -28,6 +28,19 @@
 // CHECK-NOT: __riscv_zbr
 // CHECK-NOT: __riscv_zbs
 // CHECK-NOT: __riscv_zbt
+// CHECK-NOT: __riscv_zbkb
+// CHECK-NOT: __riscv_zbkc
+// CHECK-NOT: __riscv_zbkx
+// CHECK-NOT: __riscv_zknd
+// CHECK-NOT: __riscv_zkne
+// CHECK-NOT: __riscv_zknh
+// CHECK-NOT: __riscv_zksed
+// CHECK-NOT: __riscv_zksh
+// CHECK-NOT: __riscv_zkr
+// CHECK-NOT: __riscv_zkn
+// CHECK-NOT: __riscv_zks
+// CHECK-NOT: __riscv_zkt
+// CHECK-NOT: __riscv_zk
 // CHECK-NOT: __riscv_zfh
 // CHECK-NOT: __riscv_v
 // CHECK-NOT: __riscv_vector
@@ -189,6 +202,123 @@
 // CHECK-ZBT-NOT: __riscv_b
 // CHECK-ZBT-EXT: __riscv_zbt 93000
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izbkb1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBKB-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izbkb1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBKB-EXT %s
+// CHECK-ZBKB-NOT: __riscv_k
+// CHECK-ZBKB-EXT: __riscv_zbkb 10
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izbkc1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBKC-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izbkc1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBKC-EXT %s
+// CHECK-ZBKC-NOT: __riscv_k
+// CHECK-ZBKC-EXT: __riscv_zbkc 10
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izbkx1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBKX-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izbkx1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBKX-EXT %s
+// CHECK-ZBKX-NOT: __riscv_k
+// CHECK-ZBKX-EXT: __riscv_zbkx 10
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izknd1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKND-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izknd1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKND-EXT %s
+// CHECK-ZKND-NOT: __riscv_k
+// CHECK-ZKND-EXT: __riscv_zknd 10
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izkne1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKNE-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izkne1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZKNE-EXT %s
+// CHECK-ZKNE-NOT: __riscv_k
+// CHECK-ZKNE-EXT: __riscv_zkne 10
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izknh1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefi

[PATCH] D111866: [RISCV] Support Zfhmin extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 384337.
achieveartificialintelligence added a comment.

Address @asb 's comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111866/new/

https://reviews.llvm.org/D111866

Files:
  clang/test/Driver/riscv-arch.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zfhmin-invalid.s
  llvm/test/MC/RISCV/rv32zfhmin-valid.s

Index: llvm/test/MC/RISCV/rv32zfhmin-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zfhmin-valid.s
@@ -0,0 +1,62 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfhmin,+d -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfhmin,+d -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfhmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfhmin,+d -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfhmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfhmin,+d -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: flh ft0, 12(a0)
+# CHECK-ASM: encoding: [0x07,0x10,0xc5,0x00]
+flh f0, 12(a0)
+# CHECK-ASM-AND-OBJ: flh ft1, 4(ra)
+# CHECK-ASM: encoding: [0x87,0x90,0x40,0x00]
+flh f1, +4(ra)
+# CHECK-ASM-AND-OBJ: flh ft2, -2048(a3)
+# CHECK-ASM: encoding: [0x07,0x91,0x06,0x80]
+flh f2, -2048(x13)
+# CHECK-ASM-AND-OBJ: flh ft3, -2048(s1)
+# CHECK-ASM: encoding: [0x87,0x91,0x04,0x80]
+flh f3, %lo(2048)(s1)
+# CHECK-ASM-AND-OBJ: flh ft4, 2047(s2)
+# CHECK-ASM: encoding: [0x07,0x12,0xf9,0x7f]
+flh f4, 2047(s2)
+# CHECK-ASM-AND-OBJ: flh ft5, 0(s3)
+# CHECK-ASM: encoding: [0x87,0x92,0x09,0x00]
+flh f5, 0(s3)
+
+# CHECK-ASM-AND-OBJ: fsh ft6, 2047(s4)
+# CHECK-ASM: encoding: [0xa7,0x1f,0x6a,0x7e]
+fsh f6, 2047(s4)
+# CHECK-ASM-AND-OBJ: fsh ft7, -2048(s5)
+# CHECK-ASM: encoding: [0x27,0x90,0x7a,0x80]
+fsh f7, -2048(s5)
+# CHECK-ASM-AND-OBJ: fsh fs0, -2048(s6)
+# CHECK-ASM: encoding: [0x27,0x10,0x8b,0x80]
+fsh f8, %lo(2048)(s6)
+# CHECK-ASM-AND-OBJ: fsh fs1, 999(s7)
+# CHECK-ASM: encoding: [0xa7,0x93,0x9b,0x3e]
+fsh f9, 999(s7)
+
+# CHECK-ASM-AND-OBJ: fmv.x.h a2, fs7
+# CHECK-ASM: encoding: [0x53,0x86,0x0b,0xe4]
+fmv.x.h a2, fs7
+# CHECK-ASM-AND-OBJ: fmv.h.x ft1, a6
+# CHECK-ASM: encoding: [0xd3,0x00,0x08,0xf4]
+fmv.h.x ft1, a6
+
+# CHECK-ASM-AND-OBJ: fcvt.s.h fa0, ft0
+# CHECK-ASM: encoding: [0x53,0x05,0x20,0x40]
+fcvt.s.h fa0, ft0
+# CHECK-ASM-AND-OBJ: fcvt.h.s ft2, fa2
+# CHECK-ASM: encoding: [0x53,0x71,0x06,0x44]
+fcvt.h.s ft2, fa2
+# CHECK-ASM-AND-OBJ: fcvt.d.h fa0, ft0
+# CHECK-ASM: encoding: [0x53,0x05,0x20,0x42]
+fcvt.d.h fa0, ft0
+# CHECK-ASM-AND-OBJ: fcvt.h.d ft2, fa2
+# CHECK-ASM: encoding: [0x53,0x71,0x16,0x44]
+fcvt.h.d ft2, fa2
Index: llvm/test/MC/RISCV/rv32zfhmin-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zfhmin-invalid.s
@@ -0,0 +1,23 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfhmin < %s 2>&1 | \
+# RUN:   FileCheck %s
+
+# Out of range immediates
+## simm12
+flh ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+fsh ft2, 2048(a1) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+# Memory operand not formatted correctly
+flh ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+
+# Invalid register names
+flh ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+flh ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
+
+# Integer registers where FP regs are expected
+fmv.x.h fs7, a2 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+
+# FP registers where integer regs are expected
+fmv.h.x a8, ft2 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+
+# Zfh instructions
+fmadd.h f10, f11, f12, f13, dyn # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point)
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -66,8 +66,11 @@
 .attribute arch, "rv32izbt"
 # CHECK: attribute  5, "rv32i2p0_zbt0p93"
 
+.attribute 

[PATCH] D111866: [RISCV] Support Zfhmin extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence marked 4 inline comments as done.
achieveartificialintelligence added a comment.

Thanks!


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D111866/new/

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[PATCH] D111866: [RISCV] Support Zfhmin extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 384729.
achieveartificialintelligence added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111866/new/

https://reviews.llvm.org/D111866

Files:
  clang/test/Driver/riscv-arch.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zfhmin-invalid.s
  llvm/test/MC/RISCV/rv32zfhmin-valid.s

Index: llvm/test/MC/RISCV/rv32zfhmin-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zfhmin-valid.s
@@ -0,0 +1,62 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfhmin,+d -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfhmin,+d -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfhmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfhmin,+d -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfhmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfhmin,+d -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: flh ft0, 12(a0)
+# CHECK-ASM: encoding: [0x07,0x10,0xc5,0x00]
+flh f0, 12(a0)
+# CHECK-ASM-AND-OBJ: flh ft1, 4(ra)
+# CHECK-ASM: encoding: [0x87,0x90,0x40,0x00]
+flh f1, +4(ra)
+# CHECK-ASM-AND-OBJ: flh ft2, -2048(a3)
+# CHECK-ASM: encoding: [0x07,0x91,0x06,0x80]
+flh f2, -2048(x13)
+# CHECK-ASM-AND-OBJ: flh ft3, -2048(s1)
+# CHECK-ASM: encoding: [0x87,0x91,0x04,0x80]
+flh f3, %lo(2048)(s1)
+# CHECK-ASM-AND-OBJ: flh ft4, 2047(s2)
+# CHECK-ASM: encoding: [0x07,0x12,0xf9,0x7f]
+flh f4, 2047(s2)
+# CHECK-ASM-AND-OBJ: flh ft5, 0(s3)
+# CHECK-ASM: encoding: [0x87,0x92,0x09,0x00]
+flh f5, 0(s3)
+
+# CHECK-ASM-AND-OBJ: fsh ft6, 2047(s4)
+# CHECK-ASM: encoding: [0xa7,0x1f,0x6a,0x7e]
+fsh f6, 2047(s4)
+# CHECK-ASM-AND-OBJ: fsh ft7, -2048(s5)
+# CHECK-ASM: encoding: [0x27,0x90,0x7a,0x80]
+fsh f7, -2048(s5)
+# CHECK-ASM-AND-OBJ: fsh fs0, -2048(s6)
+# CHECK-ASM: encoding: [0x27,0x10,0x8b,0x80]
+fsh f8, %lo(2048)(s6)
+# CHECK-ASM-AND-OBJ: fsh fs1, 999(s7)
+# CHECK-ASM: encoding: [0xa7,0x93,0x9b,0x3e]
+fsh f9, 999(s7)
+
+# CHECK-ASM-AND-OBJ: fmv.x.h a2, fs7
+# CHECK-ASM: encoding: [0x53,0x86,0x0b,0xe4]
+fmv.x.h a2, fs7
+# CHECK-ASM-AND-OBJ: fmv.h.x ft1, a6
+# CHECK-ASM: encoding: [0xd3,0x00,0x08,0xf4]
+fmv.h.x ft1, a6
+
+# CHECK-ASM-AND-OBJ: fcvt.s.h fa0, ft0
+# CHECK-ASM: encoding: [0x53,0x05,0x20,0x40]
+fcvt.s.h fa0, ft0
+# CHECK-ASM-AND-OBJ: fcvt.h.s ft2, fa2
+# CHECK-ASM: encoding: [0x53,0x71,0x06,0x44]
+fcvt.h.s ft2, fa2
+# CHECK-ASM-AND-OBJ: fcvt.d.h fa0, ft0
+# CHECK-ASM: encoding: [0x53,0x05,0x20,0x42]
+fcvt.d.h fa0, ft0
+# CHECK-ASM-AND-OBJ: fcvt.h.d ft2, fa2
+# CHECK-ASM: encoding: [0x53,0x71,0x16,0x44]
+fcvt.h.d ft2, fa2
Index: llvm/test/MC/RISCV/rv32zfhmin-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zfhmin-invalid.s
@@ -0,0 +1,23 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfhmin < %s 2>&1 | \
+# RUN:   FileCheck %s
+
+# Out of range immediates
+## simm12
+flh ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+fsh ft2, 2048(a1) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+# Memory operand not formatted correctly
+flh ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+
+# Invalid register names
+flh ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+flh ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
+
+# Integer registers where FP regs are expected
+fmv.x.h fs7, a2 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+
+# FP registers where integer regs are expected
+fmv.h.x a8, ft2 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+
+# Zfh instructions
+fmadd.h f10, f11, f12, f13, dyn # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point)
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -66,8 +66,11 @@
 .attribute arch, "rv32izbt"
 # CHECK: attribute  5, "rv32i2p0_zbt0p93"
 
+.attribute arch, "rv32ifzfhmi

[PATCH] D111866: [RISCV] Support Zfhmin extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 385121.
achieveartificialintelligence added a comment.

Fix


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111866/new/

https://reviews.llvm.org/D111866

Files:
  clang/test/Driver/riscv-arch.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zfhmin-invalid.s
  llvm/test/MC/RISCV/rv32zfhmin-valid.s

Index: llvm/test/MC/RISCV/rv32zfhmin-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zfhmin-valid.s
@@ -0,0 +1,62 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfhmin,+d -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfhmin,+d -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfhmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfhmin,+d -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfhmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfhmin,+d -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: flh ft0, 12(a0)
+# CHECK-ASM: encoding: [0x07,0x10,0xc5,0x00]
+flh f0, 12(a0)
+# CHECK-ASM-AND-OBJ: flh ft1, 4(ra)
+# CHECK-ASM: encoding: [0x87,0x90,0x40,0x00]
+flh f1, +4(ra)
+# CHECK-ASM-AND-OBJ: flh ft2, -2048(a3)
+# CHECK-ASM: encoding: [0x07,0x91,0x06,0x80]
+flh f2, -2048(x13)
+# CHECK-ASM-AND-OBJ: flh ft3, -2048(s1)
+# CHECK-ASM: encoding: [0x87,0x91,0x04,0x80]
+flh f3, %lo(2048)(s1)
+# CHECK-ASM-AND-OBJ: flh ft4, 2047(s2)
+# CHECK-ASM: encoding: [0x07,0x12,0xf9,0x7f]
+flh f4, 2047(s2)
+# CHECK-ASM-AND-OBJ: flh ft5, 0(s3)
+# CHECK-ASM: encoding: [0x87,0x92,0x09,0x00]
+flh f5, 0(s3)
+
+# CHECK-ASM-AND-OBJ: fsh ft6, 2047(s4)
+# CHECK-ASM: encoding: [0xa7,0x1f,0x6a,0x7e]
+fsh f6, 2047(s4)
+# CHECK-ASM-AND-OBJ: fsh ft7, -2048(s5)
+# CHECK-ASM: encoding: [0x27,0x90,0x7a,0x80]
+fsh f7, -2048(s5)
+# CHECK-ASM-AND-OBJ: fsh fs0, -2048(s6)
+# CHECK-ASM: encoding: [0x27,0x10,0x8b,0x80]
+fsh f8, %lo(2048)(s6)
+# CHECK-ASM-AND-OBJ: fsh fs1, 999(s7)
+# CHECK-ASM: encoding: [0xa7,0x93,0x9b,0x3e]
+fsh f9, 999(s7)
+
+# CHECK-ASM-AND-OBJ: fmv.x.h a2, fs7
+# CHECK-ASM: encoding: [0x53,0x86,0x0b,0xe4]
+fmv.x.h a2, fs7
+# CHECK-ASM-AND-OBJ: fmv.h.x ft1, a6
+# CHECK-ASM: encoding: [0xd3,0x00,0x08,0xf4]
+fmv.h.x ft1, a6
+
+# CHECK-ASM-AND-OBJ: fcvt.s.h fa0, ft0
+# CHECK-ASM: encoding: [0x53,0x05,0x20,0x40]
+fcvt.s.h fa0, ft0
+# CHECK-ASM-AND-OBJ: fcvt.h.s ft2, fa2
+# CHECK-ASM: encoding: [0x53,0x71,0x06,0x44]
+fcvt.h.s ft2, fa2
+# CHECK-ASM-AND-OBJ: fcvt.d.h fa0, ft0
+# CHECK-ASM: encoding: [0x53,0x05,0x20,0x42]
+fcvt.d.h fa0, ft0
+# CHECK-ASM-AND-OBJ: fcvt.h.d ft2, fa2
+# CHECK-ASM: encoding: [0x53,0x71,0x16,0x44]
+fcvt.h.d ft2, fa2
Index: llvm/test/MC/RISCV/rv32zfhmin-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zfhmin-invalid.s
@@ -0,0 +1,23 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfhmin < %s 2>&1 | \
+# RUN:   FileCheck %s
+
+# Out of range immediates
+## simm12
+flh ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+fsh ft2, 2048(a1) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+# Memory operand not formatted correctly
+flh ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+
+# Invalid register names
+flh ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+flh ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
+
+# Integer registers where FP regs are expected
+fmv.x.h fs7, a2 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+
+# FP registers where integer regs are expected
+fmv.h.x a8, ft2 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+
+# Zfh instructions
+fmadd.h f10, f11, f12, f13, dyn # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point)
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -66,8 +66,11 @@
 .attribute arch, "rv32izbt"
 # CHECK: attribute  5, "rv32i2p0_zbt0p93"
 
+.attribute arch, "rv32ifzfhmin"

[PATCH] D111866: [RISCV] Support Zfhmin extension

[Shao-Ce SUN via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG5c3d7184b435: [RISCV] Support Zfhmin extension (authored by 
achieveartificialintelligence).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111866/new/

https://reviews.llvm.org/D111866

Files:
  clang/test/Driver/riscv-arch.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zfhmin-invalid.s
  llvm/test/MC/RISCV/rv32zfhmin-valid.s

Index: llvm/test/MC/RISCV/rv32zfhmin-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zfhmin-valid.s
@@ -0,0 +1,62 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfhmin,+d -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfhmin,+d -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfhmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfhmin,+d -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfhmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfhmin,+d -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: flh ft0, 12(a0)
+# CHECK-ASM: encoding: [0x07,0x10,0xc5,0x00]
+flh f0, 12(a0)
+# CHECK-ASM-AND-OBJ: flh ft1, 4(ra)
+# CHECK-ASM: encoding: [0x87,0x90,0x40,0x00]
+flh f1, +4(ra)
+# CHECK-ASM-AND-OBJ: flh ft2, -2048(a3)
+# CHECK-ASM: encoding: [0x07,0x91,0x06,0x80]
+flh f2, -2048(x13)
+# CHECK-ASM-AND-OBJ: flh ft3, -2048(s1)
+# CHECK-ASM: encoding: [0x87,0x91,0x04,0x80]
+flh f3, %lo(2048)(s1)
+# CHECK-ASM-AND-OBJ: flh ft4, 2047(s2)
+# CHECK-ASM: encoding: [0x07,0x12,0xf9,0x7f]
+flh f4, 2047(s2)
+# CHECK-ASM-AND-OBJ: flh ft5, 0(s3)
+# CHECK-ASM: encoding: [0x87,0x92,0x09,0x00]
+flh f5, 0(s3)
+
+# CHECK-ASM-AND-OBJ: fsh ft6, 2047(s4)
+# CHECK-ASM: encoding: [0xa7,0x1f,0x6a,0x7e]
+fsh f6, 2047(s4)
+# CHECK-ASM-AND-OBJ: fsh ft7, -2048(s5)
+# CHECK-ASM: encoding: [0x27,0x90,0x7a,0x80]
+fsh f7, -2048(s5)
+# CHECK-ASM-AND-OBJ: fsh fs0, -2048(s6)
+# CHECK-ASM: encoding: [0x27,0x10,0x8b,0x80]
+fsh f8, %lo(2048)(s6)
+# CHECK-ASM-AND-OBJ: fsh fs1, 999(s7)
+# CHECK-ASM: encoding: [0xa7,0x93,0x9b,0x3e]
+fsh f9, 999(s7)
+
+# CHECK-ASM-AND-OBJ: fmv.x.h a2, fs7
+# CHECK-ASM: encoding: [0x53,0x86,0x0b,0xe4]
+fmv.x.h a2, fs7
+# CHECK-ASM-AND-OBJ: fmv.h.x ft1, a6
+# CHECK-ASM: encoding: [0xd3,0x00,0x08,0xf4]
+fmv.h.x ft1, a6
+
+# CHECK-ASM-AND-OBJ: fcvt.s.h fa0, ft0
+# CHECK-ASM: encoding: [0x53,0x05,0x20,0x40]
+fcvt.s.h fa0, ft0
+# CHECK-ASM-AND-OBJ: fcvt.h.s ft2, fa2
+# CHECK-ASM: encoding: [0x53,0x71,0x06,0x44]
+fcvt.h.s ft2, fa2
+# CHECK-ASM-AND-OBJ: fcvt.d.h fa0, ft0
+# CHECK-ASM: encoding: [0x53,0x05,0x20,0x42]
+fcvt.d.h fa0, ft0
+# CHECK-ASM-AND-OBJ: fcvt.h.d ft2, fa2
+# CHECK-ASM: encoding: [0x53,0x71,0x16,0x44]
+fcvt.h.d ft2, fa2
Index: llvm/test/MC/RISCV/rv32zfhmin-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zfhmin-invalid.s
@@ -0,0 +1,23 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfhmin < %s 2>&1 | \
+# RUN:   FileCheck %s
+
+# Out of range immediates
+## simm12
+flh ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+fsh ft2, 2048(a1) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+# Memory operand not formatted correctly
+flh ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+
+# Invalid register names
+flh ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+flh ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
+
+# Integer registers where FP regs are expected
+fmv.x.h fs7, a2 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+
+# FP registers where integer regs are expected
+fmv.h.x a8, ft2 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+
+# Zfh instructions
+fmadd.h f10, f11, f12, f13, dyn # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point)
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -66,8 

[PATCH] D111866: [RISCV] Support Zfhmin extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

In D111866#3111243 , @asb wrote:

> LGTM, modulo one tiny nit on a comment. Thanks!

Thank you for your detailed suggestions!


Repository:
  rG LLVM Github Monorepo

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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

Ping


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D93298

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[PATCH] D114408: Fold a lot of ffixed_x if judgments

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence created this revision.
achieveartificialintelligence added reviewers: simoncook, asb, lenary, 
luismarques.
Herald added subscribers: frasercrmck, apazos, sameer.abuasal, s.egerton, Jim, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, niosHD, sabuasal, johnrusso, rbar.
achieveartificialintelligence requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D114408

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp


Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -73,68 +73,12 @@
 getRISCFeaturesFromMcpu(D, Triple, Args, A, A->getValue(), Features);
 
   // Handle features corresponding to "-ffixed-X" options
-  if (Args.hasArg(options::OPT_ffixed_x1))
-Features.push_back("+reserve-x1");
-  if (Args.hasArg(options::OPT_ffixed_x2))
-Features.push_back("+reserve-x2");
-  if (Args.hasArg(options::OPT_ffixed_x3))
-Features.push_back("+reserve-x3");
-  if (Args.hasArg(options::OPT_ffixed_x4))
-Features.push_back("+reserve-x4");
-  if (Args.hasArg(options::OPT_ffixed_x5))
-Features.push_back("+reserve-x5");
-  if (Args.hasArg(options::OPT_ffixed_x6))
-Features.push_back("+reserve-x6");
-  if (Args.hasArg(options::OPT_ffixed_x7))
-Features.push_back("+reserve-x7");
-  if (Args.hasArg(options::OPT_ffixed_x8))
-Features.push_back("+reserve-x8");
-  if (Args.hasArg(options::OPT_ffixed_x9))
-Features.push_back("+reserve-x9");
-  if (Args.hasArg(options::OPT_ffixed_x10))
-Features.push_back("+reserve-x10");
-  if (Args.hasArg(options::OPT_ffixed_x11))
-Features.push_back("+reserve-x11");
-  if (Args.hasArg(options::OPT_ffixed_x12))
-Features.push_back("+reserve-x12");
-  if (Args.hasArg(options::OPT_ffixed_x13))
-Features.push_back("+reserve-x13");
-  if (Args.hasArg(options::OPT_ffixed_x14))
-Features.push_back("+reserve-x14");
-  if (Args.hasArg(options::OPT_ffixed_x15))
-Features.push_back("+reserve-x15");
-  if (Args.hasArg(options::OPT_ffixed_x16))
-Features.push_back("+reserve-x16");
-  if (Args.hasArg(options::OPT_ffixed_x17))
-Features.push_back("+reserve-x17");
-  if (Args.hasArg(options::OPT_ffixed_x18))
-Features.push_back("+reserve-x18");
-  if (Args.hasArg(options::OPT_ffixed_x19))
-Features.push_back("+reserve-x19");
-  if (Args.hasArg(options::OPT_ffixed_x20))
-Features.push_back("+reserve-x20");
-  if (Args.hasArg(options::OPT_ffixed_x21))
-Features.push_back("+reserve-x21");
-  if (Args.hasArg(options::OPT_ffixed_x22))
-Features.push_back("+reserve-x22");
-  if (Args.hasArg(options::OPT_ffixed_x23))
-Features.push_back("+reserve-x23");
-  if (Args.hasArg(options::OPT_ffixed_x24))
-Features.push_back("+reserve-x24");
-  if (Args.hasArg(options::OPT_ffixed_x25))
-Features.push_back("+reserve-x25");
-  if (Args.hasArg(options::OPT_ffixed_x26))
-Features.push_back("+reserve-x26");
-  if (Args.hasArg(options::OPT_ffixed_x27))
-Features.push_back("+reserve-x27");
-  if (Args.hasArg(options::OPT_ffixed_x28))
-Features.push_back("+reserve-x28");
-  if (Args.hasArg(options::OPT_ffixed_x29))
-Features.push_back("+reserve-x29");
-  if (Args.hasArg(options::OPT_ffixed_x30))
-Features.push_back("+reserve-x30");
-  if (Args.hasArg(options::OPT_ffixed_x31))
-Features.push_back("+reserve-x31");
+#define HAS_FFIXED_X(I)
\
+  (if (Args.hasArg(options::OPT_ffixed_x(I)))  
\
+   Features.push_back("+reserve-x(I)"))
+
+  for (int i = 1; i <= 31; ++i)
+HAS_FFIXED_X(i);
 
   // -mrelax is default, unless -mno-relax is specified.
   if (Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax, true))


Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -73,68 +73,12 @@
 getRISCFeaturesFromMcpu(D, Triple, Args, A, A->getValue(), Features);
 
   // Handle features corresponding to "-ffixed-X" options
-  if (Args.hasArg(options::OPT_ffixed_x1))
-Features.push_back("+reserve-x1");
-  if (Args.hasArg(options::OPT_ffixed_x2))
-Features.push_back("+reserve-x2");
-  if (Args.hasArg(options::OPT_ffixed_x3))
-Features.push_back("+reserve-x3");
-  if (Args.hasArg(options::OPT_ffixed_x4))
-Features.push_back("+reserve-x4");
-  if (Args.hasArg(options::OPT_ffixed_x5))
-Features.push_back("+reserve-x5");
-  if (Args.hasArg(options::OPT_ffixed_x6))
-Features.push_back("+reserve-x6");
-  if (Args.hasArg(options::OPT_ffixed_x7))
-Features.push_back("+reserve-x7");
-  if (Arg

[PATCH] D114408: Fold a lot of ffixed_x if judgments

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 389091.
achieveartificialintelligence added a comment.

Fix


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114408/new/

https://reviews.llvm.org/D114408

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp


Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -73,68 +73,12 @@
 getRISCFeaturesFromMcpu(D, Triple, Args, A, A->getValue(), Features);
 
   // Handle features corresponding to "-ffixed-X" options
-  if (Args.hasArg(options::OPT_ffixed_x1))
-Features.push_back("+reserve-x1");
-  if (Args.hasArg(options::OPT_ffixed_x2))
-Features.push_back("+reserve-x2");
-  if (Args.hasArg(options::OPT_ffixed_x3))
-Features.push_back("+reserve-x3");
-  if (Args.hasArg(options::OPT_ffixed_x4))
-Features.push_back("+reserve-x4");
-  if (Args.hasArg(options::OPT_ffixed_x5))
-Features.push_back("+reserve-x5");
-  if (Args.hasArg(options::OPT_ffixed_x6))
-Features.push_back("+reserve-x6");
-  if (Args.hasArg(options::OPT_ffixed_x7))
-Features.push_back("+reserve-x7");
-  if (Args.hasArg(options::OPT_ffixed_x8))
-Features.push_back("+reserve-x8");
-  if (Args.hasArg(options::OPT_ffixed_x9))
-Features.push_back("+reserve-x9");
-  if (Args.hasArg(options::OPT_ffixed_x10))
-Features.push_back("+reserve-x10");
-  if (Args.hasArg(options::OPT_ffixed_x11))
-Features.push_back("+reserve-x11");
-  if (Args.hasArg(options::OPT_ffixed_x12))
-Features.push_back("+reserve-x12");
-  if (Args.hasArg(options::OPT_ffixed_x13))
-Features.push_back("+reserve-x13");
-  if (Args.hasArg(options::OPT_ffixed_x14))
-Features.push_back("+reserve-x14");
-  if (Args.hasArg(options::OPT_ffixed_x15))
-Features.push_back("+reserve-x15");
-  if (Args.hasArg(options::OPT_ffixed_x16))
-Features.push_back("+reserve-x16");
-  if (Args.hasArg(options::OPT_ffixed_x17))
-Features.push_back("+reserve-x17");
-  if (Args.hasArg(options::OPT_ffixed_x18))
-Features.push_back("+reserve-x18");
-  if (Args.hasArg(options::OPT_ffixed_x19))
-Features.push_back("+reserve-x19");
-  if (Args.hasArg(options::OPT_ffixed_x20))
-Features.push_back("+reserve-x20");
-  if (Args.hasArg(options::OPT_ffixed_x21))
-Features.push_back("+reserve-x21");
-  if (Args.hasArg(options::OPT_ffixed_x22))
-Features.push_back("+reserve-x22");
-  if (Args.hasArg(options::OPT_ffixed_x23))
-Features.push_back("+reserve-x23");
-  if (Args.hasArg(options::OPT_ffixed_x24))
-Features.push_back("+reserve-x24");
-  if (Args.hasArg(options::OPT_ffixed_x25))
-Features.push_back("+reserve-x25");
-  if (Args.hasArg(options::OPT_ffixed_x26))
-Features.push_back("+reserve-x26");
-  if (Args.hasArg(options::OPT_ffixed_x27))
-Features.push_back("+reserve-x27");
-  if (Args.hasArg(options::OPT_ffixed_x28))
-Features.push_back("+reserve-x28");
-  if (Args.hasArg(options::OPT_ffixed_x29))
-Features.push_back("+reserve-x29");
-  if (Args.hasArg(options::OPT_ffixed_x30))
-Features.push_back("+reserve-x30");
-  if (Args.hasArg(options::OPT_ffixed_x31))
-Features.push_back("+reserve-x31");
+#define HAS_FFIXED_X(I)
\
+  (if (Args.hasArg(options::OPT_ffixed_x(I)))  
\
+   Features.push_back("+reserve-x(I)"))
+
+  for (int I = 1; I <= 31; ++I)
+HAS_FFIXED_X(I);
 
   // -mrelax is default, unless -mno-relax is specified.
   if (Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax, true))


Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -73,68 +73,12 @@
 getRISCFeaturesFromMcpu(D, Triple, Args, A, A->getValue(), Features);
 
   // Handle features corresponding to "-ffixed-X" options
-  if (Args.hasArg(options::OPT_ffixed_x1))
-Features.push_back("+reserve-x1");
-  if (Args.hasArg(options::OPT_ffixed_x2))
-Features.push_back("+reserve-x2");
-  if (Args.hasArg(options::OPT_ffixed_x3))
-Features.push_back("+reserve-x3");
-  if (Args.hasArg(options::OPT_ffixed_x4))
-Features.push_back("+reserve-x4");
-  if (Args.hasArg(options::OPT_ffixed_x5))
-Features.push_back("+reserve-x5");
-  if (Args.hasArg(options::OPT_ffixed_x6))
-Features.push_back("+reserve-x6");
-  if (Args.hasArg(options::OPT_ffixed_x7))
-Features.push_back("+reserve-x7");
-  if (Args.hasArg(options::OPT_ffixed_x8))
-Features.push_back("+reserve-x8");
-  if (Args.hasArg(options::OPT_ffixed_x9))
-Features.push_back("+reserve-x9");
-  if (Args.hasArg(options::OPT_ffixed_x10))
-Features.push_back("+reserve-x10");
-  if (Args.hasArg(options::OPT_ffixed_x11))
-Featu

[PATCH] D114408: Fold a lot of ffixed_x if judgments

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achieveartificialintelligence abandoned this revision.
achieveartificialintelligence added a comment.

In D114408#3148311 , @jrtc27 wrote:

> This has clearly not been tested whatsoever, it’s totally broken, the 
> preprocessor does not work like that

Thanks!


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[PATCH] D113237: [RISCV] Support Zifencei extension

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achieveartificialintelligence updated this revision to Diff 391951.
achieveartificialintelligence added a comment.
Herald added subscribers: cfe-commits, jdoerfert, rupprecht, emaste, qcolombet.
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Herald added a reviewer: MaskRay.
Herald added a project: clang.

Update I-ext to Version 2.1


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Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Driver/riscv-cpus.c
  lld/test/ELF/riscv-attributes.s
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
  llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
  llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
  llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
  llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
  llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
  llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
  llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/localvar.ll
  llvm/test/CodeGen/RISCV/rvv/memory-args.ll
  llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector.ll
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
  llvm/test/CodeGen/RISCV/rvv/stepvector.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
  llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir
  llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/attribute-with-insts.s
  llvm/test/MC/RISCV/attribute-with-option.s
  llvm/test/MC/RISCV/attribute.s
  llvm/test/MC/RISCV/csr-aliases.s
  llvm/test/MC/RISCV/deprecated-csr-names.s
  llvm/test/MC/RISCV/invalid-attribute.s
  llvm/test/MC/RISCV/machine-csr-names.s
  llvm/test/MC/RISCV/rv32-machine-csr-names.s
  llvm/test/MC/RISCV/rv32-user-csr-names.s
  llvm/test/MC/RISCV/rv32e-valid.s
  llvm/test/MC/RISCV/rv32i-aliases-valid.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32i-valid.s
  llvm/test/MC/RISCV/rv32zicsr-invalid.s
  llvm/test/MC/RISCV/rv32zicsr-valid.s
  llvm/test/MC/RISCV/rv32zifencei-valid.s
  llvm/test/MC/RISCV/rv64-machine-csr-names.s
  llvm/test/MC/RISCV/rv64-user-csr-names.s
  llvm/test/MC/RISCV/rvf-aliases-valid.s
  llvm/test/MC/RISCV/rvf-user-csr-names.s
  llvm/test/MC/RISCV/rvi-aliases-valid.s
  llvm/test/MC/RISCV/rvv-user-csr-names.s
  llvm/test/MC/RISCV/rvzicsr-aliases-valid.s
  llvm/test/MC/RISCV/supervisor-csr-names.s
  llvm/test/MC/RISCV/user-csr-names.s
  llvm/test/tools/llvm-objdump/ELF/RISCV/unknown-arch-attr.test
  llvm/test/tools/llvm-readobj/ELF/RISCV/attribute.s

Index: llvm/test/tools/llvm-readobj/ELF/RISCV/attribute.s
===
--- llvm/test/tools/llvm-readobj/ELF/RISCV/attribute.s
+++ llvm/test/tools/llvm-readobj/ELF/RISCV/attribute.s
@@ -17,10 +17,10 @@
 # CHECK-OBJ-NEXT: TagName: stack_align
 # CHECK-OBJ-NEXT: Description: Stack alignment is 16-bytes
 
-.attribute  Tag_arch, "rv32i2p0_m2p0_a2p0_c2p0"
+.attribute  Tag_arch, "rv32i

[PATCH] D113237: [RISCV] Support I extension version 2.1

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

In D113237#3124232 , @luismarques 
wrote:

> In D113237#3124188 , @luismarques 
> wrote:
>
>> Should we also support `fence.i` with RVI 2.0, without zifencei?
>
> Here's a proposed path forwards:
>
> - Patch 1: Add support for RVI 2.1 and related changes. Keep RVI 2.0 as the 
> default.
> - Patch 2: Add warnings for uses of the removed `fence.i`, CSRs and counters 
> when using RVI 2.0 (at least when doing so by default; arguably this should 
> error out instead when explicitly specifying version 2.0.)
> - Patch 3: Start defaulting to RVI 2.1. IMO this should only be committed 
> after patch 2 being in effect for a while.

I tried to make I-ext imply `zifencei`, `zicsr`, and `zihintpause` 
automatically. BTW `zihintpause` is implemented in D93019 
.


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[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

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sunshaoce added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoP.td:599
+   Sched<[]>;
+def UKSTSA32 : RVPBinary<0b1110001, 0b011, "ukstsa32">,
+   Sched<[]>;

`0b011` should be `0b010`. 
https://github.com/riscv/riscv-p-spec/blob/master/P-ext-proposal.adoc#847-ukstsa32-simd-32-bit-unsigned-saturating-straight-subtraction--addition


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[PATCH] D121670: [RISCV] Add zihintntl instructions

[Shao-Ce SUN via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7167a4207ee2: [RISCV] Add zihintntl instructions (authored 
by sunshaoce).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D121670

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/rv32zihintntl-valid.s

Index: llvm/test/MC/RISCV/rv32zihintntl-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zihintntl-valid.s
@@ -0,0 +1,26 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: add zero, zero, sp
+# CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
+ntl.p1
+
+# CHECK-ASM-AND-OBJ: add zero, zero, gp
+# CHECK-ASM: encoding: [0x33,0x00,0x30,0x00]
+ntl.pall
+
+# CHECK-ASM-AND-OBJ: add zero, zero, tp
+# CHECK-ASM: encoding: [0x33,0x00,0x40,0x00]
+ntl.s1
+
+# CHECK-ASM-AND-OBJ: add zero, zero, t0
+# CHECK-ASM: encoding: [0x33,0x00,0x50,0x00]
+ntl.all
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -8,6 +8,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefix=RV32D %s
 ; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefix=RV32C %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zihintpause %s -o - | FileCheck --check-prefix=RV32ZIHINTPAUSE %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zihintntl %s -o - | FileCheck --check-prefix=RV32ZIHINTNTL %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin %s -o - | FileCheck --check-prefix=RV32ZFHMIN %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh %s -o - | FileCheck --check-prefix=RV32ZFH %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zba %s -o - | FileCheck --check-prefix=RV32ZBA %s
@@ -49,6 +50,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s
 ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zihintpause %s -o - | FileCheck --check-prefix=RV64ZIHINTPAUSE %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zihintntl %s -o - | FileCheck --check-prefix=RV64ZIHINTNTL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin %s -o - | FileCheck --check-prefix=RV64ZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh %s -o - | FileCheck --check-prefix=RV64ZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zba %s -o - | FileCheck --check-prefix=RV64ZBA %s
@@ -91,6 +93,7 @@
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
 ; RV32ZIHINTPAUSE: .attribute 5, "rv32i2p0_zihintpause2p0"
+; RV32ZIHINTNTL: .attribute 5, "rv32i2p0_zihintntl0p2"
 ; RV32ZFHMIN: .attribute 5, "rv32i2p0_f2p0_zfhmin1p0"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh1p0"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0"
@@ -133,6 +136,7 @@
 ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
 ; RV64C: .attribute 5, "rv64i2p0_c2p0"
 ; RV64ZIHINTPAUSE: .attribute 5, "rv64i2p0_zihintpause2p0"
+; RV64ZIHINTNTL: .attribute 5, "rv64i2p0_zihintntl0p2"
 ; RV64ZFHMIN: .attribute 5, "rv64i2p0_f2p0_zfhmin1p0"
 ; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh1p0"
 ; RV64ZBA: .attribute 5, "rv64i2p0_zba1p0"
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -50,6 +50,7 @@
   bool HasStdExtD = false;
   bool HasStdExtC = false;
   bool HasStdExtZihintpause = false;
+  bool HasStdExtZihintntl = false;
   bool HasStdExtZba = false;
   bool HasStdExtZbb = false;
   bool HasStdExtZbc = false;
@@ -158,6 +159,7 @@
   bool hasStdExtC() const { return HasStdExtC; }
   bool hasStdExtV() const { return HasStdExtV; }
   bool hasStdExtZihintpause() const { return HasStdExtZihintpause; }
+  bool hasStdExtZihintntl() const { return HasStdExtZihintntl; }
   

[PATCH] D127589: [RISCV] Compatible with more RISCV related ld in the test

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce created this revision.
Herald added subscribers: VincentWu, luke957, vkmr, frasercrmck, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
sunshaoce requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD.
Herald added a project: clang.

When `riscv64-unknown-linux-gnu-ld` is in the PATH, `clang -### -fuse-ld=ld 
--target=riscv64-unknown-linux-gnu` will use unknown-linux-gnu-ld first, which 
causes the error in the lit test.


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Files:
  clang/test/Driver/riscv64-toolchain.c


Index: clang/test/Driver/riscv64-toolchain.c
===
--- clang/test/Driver/riscv64-toolchain.c
+++ clang/test/Driver/riscv64-toolchain.c
@@ -21,7 +21,7 @@
 // RUN:   --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf 2>&1 
-no-pie \
 // RUN:   | FileCheck -check-prefix=C-RV64-BAREMETAL-LP64 %s
 
-// C-RV64-BAREMETAL-LP64: 
"{{.*}}Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1/../../..{{/|}}..{{/|}}bin{{/|}}riscv64-unknown-elf-ld"
+// C-RV64-BAREMETAL-LP64: "{{.*}}/riscv64-unknown-elf{{.*}}ld"
 // C-RV64-BAREMETAL-LP64: 
"--sysroot={{.*}}/Inputs/basic_riscv64_tree/riscv64-unknown-elf"
 // C-RV64-BAREMETAL-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/riscv64-unknown-elf/lib{{/|}}crt0.o"
 // C-RV64-BAREMETAL-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtbegin.o"
@@ -36,7 +36,7 @@
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree 2>&1 \
 // RUN:   | FileCheck -check-prefix=C-RV64-BAREMETAL-NOSYSROOT-LP64 %s
 
-// C-RV64-BAREMETAL-NOSYSROOT-LP64: 
"{{.*}}Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1/../../..{{/|}}..{{/|}}bin{{/|}}riscv64-unknown-elf-ld"
+// C-RV64-BAREMETAL-NOSYSROOT-LP64: "{{.*}}/riscv64-unknown-elf{{.*}}ld"
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1/../../..{{/|}}..{{/|}}riscv64-unknown-elf/lib{{/|}}crt0.o"
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtbegin.o"
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: 
"-L{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1"
@@ -51,7 +51,7 @@
 // RUN:   | FileCheck -check-prefix=CXX-RV64-BAREMETAL-LP64 %s
 
 // CXX-RV64-BAREMETAL-LP64: "-internal-isystem" 
"{{.*}}Inputs/basic_riscv64_tree/riscv64-unknown-elf/include/c++{{/|}}8.0.1"
-// CXX-RV64-BAREMETAL-LP64: 
"{{.*}}Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1/../../..{{/|}}..{{/|}}bin{{/|}}riscv64-unknown-elf-ld"
+// CXX-RV64-BAREMETAL-LP64: "{{.*}}/riscv64-unknown-elf{{.*}}ld"
 // CXX-RV64-BAREMETAL-LP64: 
"--sysroot={{.*}}/Inputs/basic_riscv64_tree/riscv64-unknown-elf"
 // CXX-RV64-BAREMETAL-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/riscv64-unknown-elf/lib{{/|}}crt0.o"
 // CXX-RV64-BAREMETAL-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtbegin.o"
@@ -67,7 +67,7 @@
 // RUN:   | FileCheck -check-prefix=CXX-RV64-BAREMETAL-NOSYSROOT-LP64 %s
 
 // CXX-RV64-BAREMETAL-NOSYSROOT-LP64: "-internal-isystem" 
"{{.*}}Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1/../../..{{/|}}..{{/|}}riscv64-unknown-elf/include/c++{{/|}}8.0.1"
-// CXX-RV64-BAREMETAL-NOSYSROOT-LP64: 
"{{.*}}Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1/../../..{{/|}}..{{/|}}bin{{/|}}riscv64-unknown-elf-ld"
+// CXX-RV64-BAREMETAL-NOSYSROOT-LP64: "{{.*}}/riscv64-unknown-elf{{.*}}ld"
 // CXX-RV64-BAREMETAL-NOSYSROOT-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1/../../..{{/|}}..{{/|}}riscv64-unknown-elf/lib{{/|}}crt0.o"
 // CXX-RV64-BAREMETAL-NOSYSROOT-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtbegin.o"
 // CXX-RV64-BAREMETAL-NOSYSROOT-LP64: 
"-L{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1"
@@ -81,7 +81,7 @@
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \
 // RUN:   | FileCheck -check-prefix=C-RV64-LINUX-MULTI-LP64 %s
 
-// C-RV64-LINUX-MULTI-LP64: 
"{{.*}}/Inputs/multilib_riscv_linux_sdk/lib/gcc/riscv64-unknown-linux-gnu/7.2.0/../../..{{/|}}..{{/|}}riscv64-unknown-linux-gnu/bin{{/|}}ld"
+// C-RV64-LINUX-MULTI-LP64: "{{.*}}/riscv64-unknown-linux-gnu{{.*}}ld"
 // C-RV64-LINUX-MULTI-LP64: 
"--sysroot={{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot"
 // C-RV64-LINUX-MULTI-LP64: "-m" "elf64lriscv"
 // C-RV64-LINUX-MULTI-LP64: "-dynamic-linker" "/lib/ld-linux-riscv64-lp64.so.1"
@@ -96,7 +96,7 @@
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&

[PATCH] D127589: [RISCV] Compatible with more RISCV related ld in the test

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 436469.
sunshaoce added a comment.

Address @StephenFan's comment.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D127589/new/

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Files:
  clang/test/Driver/riscv64-toolchain.c


Index: clang/test/Driver/riscv64-toolchain.c
===
--- clang/test/Driver/riscv64-toolchain.c
+++ clang/test/Driver/riscv64-toolchain.c
@@ -15,7 +15,7 @@
 // In the below tests, --rtlib=platform is used so that the driver ignores
 // the configure-time CLANG_DEFAULT_RTLIB option when choosing the runtime lib
 
-// RUN: %clang -### %s -fuse-ld= \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
 // RUN:   --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf 2>&1 
-no-pie \
@@ -30,7 +30,7 @@
 // C-RV64-BAREMETAL-LP64: "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
 // C-RV64-BAREMETAL-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clang -### %s -fuse-ld= \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform \
 // RUN:   --sysroot= \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree 2>&1 \
@@ -44,7 +44,7 @@
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: "--start-group" "-lc" "-lgloss" 
"--end-group" "-lgcc"
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clangxx -### %s -fuse-ld= \
+// RUN: env "PATH=" %clangxx -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf -stdlib=libstdc++ --rtlib=platform \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
 // RUN:   --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf 2>&1 \
@@ -60,7 +60,7 @@
 // CXX-RV64-BAREMETAL-LP64: "-lstdc++" "--start-group" "-lc" "-lgloss" 
"--end-group" "-lgcc"
 // CXX-RV64-BAREMETAL-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clangxx -### %s -fuse-ld= \
+// RUN: env "PATH=" %clangxx -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf -stdlib=libstdc++ --rtlib=platform \
 // RUN:   --sysroot= \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree 2>&1 \
@@ -75,7 +75,7 @@
 // CXX-RV64-BAREMETAL-NOSYSROOT-LP64: "-lstdc++" "--start-group" "-lc" 
"-lgloss" "--end-group" "-lgcc"
 // CXX-RV64-BAREMETAL-NOSYSROOT-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clang -### %s -fuse-ld= -no-pie \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= -no-pie \
 // RUN:   --target=riscv64-unknown-linux-gnu --rtlib=platform -mabi=lp64 \
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk \
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \
@@ -90,7 +90,7 @@
 // C-RV64-LINUX-MULTI-LP64: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/lib64/lp64"
 // C-RV64-LINUX-MULTI-LP64: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib64/lp64"
 
-// RUN: %clang -### %s -fuse-ld=ld -no-pie \
+// RUN: env "PATH=" %clang -### %s -fuse-ld=ld -no-pie \
 // RUN:   --target=riscv64-unknown-linux-gnu --rtlib=platform -march=rv64imafd 
\
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk \
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \


Index: clang/test/Driver/riscv64-toolchain.c
===
--- clang/test/Driver/riscv64-toolchain.c
+++ clang/test/Driver/riscv64-toolchain.c
@@ -15,7 +15,7 @@
 // In the below tests, --rtlib=platform is used so that the driver ignores
 // the configure-time CLANG_DEFAULT_RTLIB option when choosing the runtime lib
 
-// RUN: %clang -### %s -fuse-ld= \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
 // RUN:   --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf 2>&1 -no-pie \
@@ -30,7 +30,7 @@
 // C-RV64-BAREMETAL-LP64: "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
 // C-RV64-BAREMETAL-LP64: "{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clang -### %s -fuse-ld= \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform \
 // RUN:   --sysroot= \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree 2>&1 \
@@ -44,7 +44,7 @@
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: "{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clangxx -### %s -fuse-ld= \
+// RUN: env "PATH=" %clangxx -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf -stdlib=libs

[PATCH] D127684: [NFC] Use `https` instead of `http` in the urls

[Shao-Ce SUN via Phabricator via cfe-commits]

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Files:
  .github/PULL_REQUEST_TEMPLATE.md
  .github/workflows/repo-lockdown.yml
  .gitignore
  README.md
  bolt/docs/CMakeLists.txt
  bolt/docs/OptimizingClang.md
  bolt/docs/doxygen.cfg.in
  clang-tools-extra/.gitignore
  clang-tools-extra/README.txt
  clang-tools-extra/clang-doc/Representation.cpp
  clang-tools-extra/clang-doc/assets/clang-doc-default-stylesheet.css
  
clang-tools-extra/clang-include-fixer/find-all-symbols/tool/run-find-all-symbols.py
  clang-tools-extra/clang-include-fixer/tool/clang-include-fixer.el
  clang-tools-extra/clang-include-fixer/tool/clang-include-fixer.py
  clang-tools-extra/clang-tidy/ClangTidy.cpp
  clang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.cpp
  clang-tools-extra/clang-tidy/abseil/CleanupCtadCheck.h
  clang-tools-extra/clang-tidy/abseil/DurationAdditionCheck.h
  clang-tools-extra/clang-tidy/abseil/DurationComparisonCheck.h
  clang-tools-extra/clang-tidy/abseil/DurationConversionCastCheck.h
  clang-tools-extra/clang-tidy/abseil/DurationDivisionCheck.h
  clang-tools-extra/clang-tidy/abseil/DurationFactoryFloatCheck.h
  clang-tools-extra/clang-tidy/abseil/DurationFactoryScaleCheck.h
  clang-tools-extra/clang-tidy/abseil/DurationSubtractionCheck.h
  clang-tools-extra/clang-tidy/abseil/DurationUnnecessaryConversionCheck.h
  clang-tools-extra/clang-tidy/abseil/FasterStrsplitDelimiterCheck.h
  clang-tools-extra/clang-tidy/abseil/NoInternalDependenciesCheck.h
  clang-tools-extra/clang-tidy/abseil/NoNamespaceCheck.h
  clang-tools-extra/clang-tidy/abseil/RedundantStrcatCallsCheck.h
  clang-tools-extra/clang-tidy/abseil/StrCatAppendCheck.h
  clang-tools-extra/clang-tidy/abseil/StringFindStrContainsCheck.h
  clang-tools-extra/clang-tidy/abseil/TimeComparisonCheck.h
  clang-tools-extra/clang-tidy/abseil/TimeSubtractionCheck.h
  clang-tools-extra/clang-tidy/abseil/UpgradeDurationConversionsCheck.h
  clang-tools-extra/clang-tidy/add_new_check.py
  clang-tools-extra/clang-tidy/altera/IdDependentBackwardBranchCheck.h
  clang-tools-extra/clang-tidy/altera/KernelNameRestrictionCheck.h
  clang-tools-extra/clang-tidy/altera/SingleWorkItemBarrierCheck.h
  clang-tools-extra/clang-tidy/altera/StructPackAlignCheck.h
  clang-tools-extra/clang-tidy/altera/UnrollLoopsCheck.h
  clang-tools-extra/clang-tidy/android/CloexecAccept4Check.h
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  clang-tools-extra/clang-tidy/android/CloexecCreatCheck.h
  clang-tools-extra/clang-tidy/a

[PATCH] D127684: [NFC] Use `https` instead of `http` in the `LLVM.org` URLs

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce abandoned this revision.
sunshaoce added a comment.

Thanks for comments!


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[PATCH] D127589: [Driver][test] Make RISCV tests robust with PATH=

[Shao-Ce SUN via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe180cc5ff1a1: [Driver][test] Make RISCV tests robust with 
PATH= (authored by sunshaoce).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/test/Driver/riscv64-toolchain.c


Index: clang/test/Driver/riscv64-toolchain.c
===
--- clang/test/Driver/riscv64-toolchain.c
+++ clang/test/Driver/riscv64-toolchain.c
@@ -15,7 +15,7 @@
 // In the below tests, --rtlib=platform is used so that the driver ignores
 // the configure-time CLANG_DEFAULT_RTLIB option when choosing the runtime lib
 
-// RUN: %clang -### %s -fuse-ld= \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
 // RUN:   --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf 2>&1 
-no-pie \
@@ -30,7 +30,7 @@
 // C-RV64-BAREMETAL-LP64: "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
 // C-RV64-BAREMETAL-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clang -### %s -fuse-ld= \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform \
 // RUN:   --sysroot= \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree 2>&1 \
@@ -44,7 +44,7 @@
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: "--start-group" "-lc" "-lgloss" 
"--end-group" "-lgcc"
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clangxx -### %s -fuse-ld= \
+// RUN: env "PATH=" %clangxx -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf -stdlib=libstdc++ --rtlib=platform \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
 // RUN:   --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf 2>&1 \
@@ -60,7 +60,7 @@
 // CXX-RV64-BAREMETAL-LP64: "-lstdc++" "--start-group" "-lc" "-lgloss" 
"--end-group" "-lgcc"
 // CXX-RV64-BAREMETAL-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clangxx -### %s -fuse-ld= \
+// RUN: env "PATH=" %clangxx -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf -stdlib=libstdc++ --rtlib=platform \
 // RUN:   --sysroot= \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree 2>&1 \
@@ -75,7 +75,7 @@
 // CXX-RV64-BAREMETAL-NOSYSROOT-LP64: "-lstdc++" "--start-group" "-lc" 
"-lgloss" "--end-group" "-lgcc"
 // CXX-RV64-BAREMETAL-NOSYSROOT-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clang -### %s -fuse-ld= -no-pie \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= -no-pie \
 // RUN:   --target=riscv64-unknown-linux-gnu --rtlib=platform -mabi=lp64 \
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk \
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \
@@ -90,7 +90,7 @@
 // C-RV64-LINUX-MULTI-LP64: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/lib64/lp64"
 // C-RV64-LINUX-MULTI-LP64: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib64/lp64"
 
-// RUN: %clang -### %s -fuse-ld=ld -no-pie \
+// RUN: env "PATH=" %clang -### %s -fuse-ld=ld -no-pie \
 // RUN:   --target=riscv64-unknown-linux-gnu --rtlib=platform -march=rv64imafd 
\
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk \
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \


Index: clang/test/Driver/riscv64-toolchain.c
===
--- clang/test/Driver/riscv64-toolchain.c
+++ clang/test/Driver/riscv64-toolchain.c
@@ -15,7 +15,7 @@
 // In the below tests, --rtlib=platform is used so that the driver ignores
 // the configure-time CLANG_DEFAULT_RTLIB option when choosing the runtime lib
 
-// RUN: %clang -### %s -fuse-ld= \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
 // RUN:   --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf 2>&1 -no-pie \
@@ -30,7 +30,7 @@
 // C-RV64-BAREMETAL-LP64: "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
 // C-RV64-BAREMETAL-LP64: "{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clang -### %s -fuse-ld= \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform \
 // RUN:   --sysroot= \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree 2>&1 \
@@ -44,7 +44,7 @@
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: "{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: 

[PATCH] D121670: [RISCV] Add zihintntl instructions

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 438563.
sunshaoce added a comment.
Herald added a subscriber: shiva0217.

Rebase


Repository:
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Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/rv32zihintntl-valid.s

Index: llvm/test/MC/RISCV/rv32zihintntl-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zihintntl-valid.s
@@ -0,0 +1,26 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: add zero, zero, sp
+# CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
+ntl.p1
+
+# CHECK-ASM-AND-OBJ: add zero, zero, gp
+# CHECK-ASM: encoding: [0x33,0x00,0x30,0x00]
+ntl.pall
+
+# CHECK-ASM-AND-OBJ: add zero, zero, tp
+# CHECK-ASM: encoding: [0x33,0x00,0x40,0x00]
+ntl.s1
+
+# CHECK-ASM-AND-OBJ: add zero, zero, t0
+# CHECK-ASM: encoding: [0x33,0x00,0x50,0x00]
+ntl.all
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -6,6 +6,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefix=RV32D %s
 ; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefix=RV32C %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zihintpause %s -o - | FileCheck --check-prefix=RV32ZIHINTPAUSE %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zihintntl %s -o - | FileCheck --check-prefix=RV32ZIHINTNTL %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin %s -o - | FileCheck --check-prefix=RV32ZFHMIN %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh %s -o - | FileCheck --check-prefix=RV32ZFH %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zba %s -o - | FileCheck --check-prefix=RV32ZBA %s
@@ -42,6 +43,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s
 ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zihintpause %s -o - | FileCheck --check-prefix=RV64ZIHINTPAUSE %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zihintntl %s -o - | FileCheck --check-prefix=RV64ZIHINTNTL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin %s -o - | FileCheck --check-prefix=RV64ZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh %s -o - | FileCheck --check-prefix=RV64ZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zba %s -o - | FileCheck --check-prefix=RV64ZBA %s
@@ -79,6 +81,7 @@
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
 ; RV32ZIHINTPAUSE: .attribute 5, "rv32i2p0_zihintpause2p0"
+; RV32ZIHINTNTL: .attribute 5, "rv32i2p0_zihintntl0p2"
 ; RV32ZFHMIN: .attribute 5, "rv32i2p0_f2p0_zfhmin1p0"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh1p0"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0"
@@ -116,6 +119,7 @@
 ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
 ; RV64C: .attribute 5, "rv64i2p0_c2p0"
 ; RV64ZIHINTPAUSE: .attribute 5, "rv64i2p0_zihintpause2p0"
+; RV64ZIHINTNTL: .attribute 5, "rv64i2p0_zihintntl0p2"
 ; RV64ZFHMIN: .attribute 5, "rv64i2p0_f2p0_zfhmin1p0"
 ; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh1p0"
 ; RV64ZBA: .attribute 5, "rv64i2p0_zba1p0"
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -50,6 +50,7 @@
   bool HasStdExtD = false;
   bool HasStdExtC = false;
   bool HasStdExtZihintpause = false;
+  bool HasStdExtZihintntl = false;
   bool HasStdExtZba = false;
   bool HasStdExtZbb = false;
   bool HasStdExtZbc = false;
@@ -150,6 +151,7 @@
   bool hasStdExtC() const { return HasStdExtC; }
   bool hasStdExtV() const { return HasStdExtV; }
   bool hasStdExtZihintpause() const { return HasStdExtZihintpause; }
+  bool hasStdExtZihintntl() const { return HasStdExtZihintntl; }
   bool hasStdExtZba() const { return HasStdExtZba; }
   bool hasStdExtZbb() const { return HasStdExtZbb;

[PATCH] D128604: [WIP][RISCV] Support Zbpbo extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce created this revision.
sunshaoce added reviewers: asb, craig.topper, jrtc27, Jim, luismarques, 
kito-cheng, frasercrmck.
Herald added subscribers: VincentWu, luke957, StephenFan, vkmr, evandro, 
apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, niosHD, 
sabuasal, simoncook, johnrusso, rbar, hiraditya, arichardson.
Herald added a project: All.
sunshaoce requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD, 
MaskRay.
Herald added projects: clang, LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D128604

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv32-zbpbo.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv64-zbpbo.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/rv32zbpbo.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo.ll
  llvm/test/MC/RISCV/rv32zbpbo-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-valid.s

Index: llvm/test/MC/RISCV/rv64zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-valid.s
@@ -0,0 +1,35 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
+fsrw t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
+
+# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x6b]
+rev t0, t1
Index: llvm/test/MC/RISCV/rv32zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-valid.s
@@ -0,0 +1,43 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
+clz t0, t1
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
+fsr t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: fsri t0, t1, t2, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x3c]
+fsri t0, t1, t2, 0
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
+
+# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x69]
+rev t0, t1
Index: llvm/test/CodeGen/RISCV/rv64zbpbo.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbpbo.ll
@@ -0,0 +1,103 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbpbo -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64ZBPBO
+
+define i64 @pack_i64(i64 %a, i64 %b) nounwind {
+; RV64I-LABEL: pack_i64:
+; RV64I:   # %bb.0:
+; RV64I-NEXT:slli a0, a0, 32
+; RV64I-NEXT:srli a0, a0, 32
+; RV64I-NEXT:slli a1, a1, 32
+; RV64I-NEXT:or a0, a1, a0
+; RV64I-NEXT:ret
+;
+; RV64ZBPBO-LABEL: pack_i64:
+; RV64ZBPBO:   # %bb.0:
+; RV64ZBPBO-NEXT:pack a0, a0, a1
+; RV64ZBPBO-NEXT:ret
+  %shl = and i64 %a, 4294967295
+  %shl1 = shl i64 %b, 32
+  %or = or i64 %shl1,

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce added a comment.

Any other opinions? If not, I will land it later.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145883/new/

https://reviews.llvm.org/D145883

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[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 505363.
sunshaoce added a comment.

Address @MaskRay's comment


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145883/new/

https://reviews.llvm.org/D145883

Files:
  clang/lib/Driver/ToolChains/Flang.cpp
  flang/test/Driver/code-gen-rv64.f90
  flang/test/Driver/target-cpu-features-invalid.f90
  flang/test/Driver/target-cpu-features.f90


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -1,5 +1,3 @@
-! REQUIRES: aarch64-registered-target, x86-registered-target
-
 ! Test that -mcpu/march are used and that the -target-cpu and -target-features
 ! are also added to the fc1 command.
 
@@ -22,14 +20,8 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
-
-! Test that invalid cpu and features are ignored.
-
-! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-cpu supercpu \
-! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-CPU
-
-! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-feature +superspeed \
-! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s 
-check-prefix=CHECK-INVALID-FEATURE
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
 
 
 ! CHECK-A57: "-fc1" "-triple" "aarch64-unknown-linux-gnu"
@@ -52,5 +44,5 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" 
"-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" 
"-target-feature" "-fsgsbase"
 
-! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target 
(ignoring processor)
-! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this 
target (ignoring feature)
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" 
"-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 
"-target-feature" "+c"
Index: flang/test/Driver/target-cpu-features-invalid.f90
===
--- /dev/null
+++ flang/test/Driver/target-cpu-features-invalid.f90
@@ -0,0 +1,13 @@
+! REQUIRES: aarch64-registered-target
+
+! Test that invalid cpu and features are ignored.
+
+! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-cpu supercpu \
+! RUN:   -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-CPU
+
+! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-feature +superspeed \
+! RUN:   -o /dev/null -S %s 2>&1 | FileCheck %s 
-check-prefix=CHECK-INVALID-FEATURE
+
+
+! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target 
(ignoring processor)
+! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this 
target (ignoring feature)
Index: flang/test/Driver/code-gen-rv64.f90
===
--- /dev/null
+++ flang/test/Driver/code-gen-rv64.f90
@@ -0,0 +1,17 @@
+! Test -emit-obj (RISC-V 64)
+
+! REQUIRES: riscv-registered-target
+
+! RUN: rm -f %t.o
+! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \
+! RUN:   -target-feature +d -target-feature +c -emit-obj %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! RUN: rm -f %t.o
+! RUN: %flang --target=riscv64-unknown-linux-gnu -c %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! If Flang failed to emit target-feature info, then Flags will be 0x0.
+! 0x5 means set EF_RISCV_RVC (0x1) and EF_RISCV_FLOAT_ABI_DOUBLE (0x4)
+! CHECK: Flags: 0x5, RVC, double-float ABI
+end program
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -105,7 +105,7 @@
   default:
 break;
   case llvm::Triple::aarch64:
-[[fallthrough]];
+  case llvm::Triple::riscv64:
   case llvm::Triple::x86_64:
 getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
 break;


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -1,5 +1,3 @@
-! REQUIRES: aarch64-registered-target, x86-registered-target
-
 ! Test that -mcpu/march are used and that the -target-cpu and -target-features
 ! are also added to the fc1 command.
 
@@ -22,14 +20,8 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
-
-! Test that invalid cpu and features are ignored.
-
-! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-cpu supercpu \
-! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-CPU
-
-! RUN: %flang_fc1 -t

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Shao-Ce SUN via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
sunshaoce marked an inline comment as done.
Closed by commit rG36278b735fa1: [Flang][RISCV] Emit target features for RISC-V 
(authored by sunshaoce).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145883/new/

https://reviews.llvm.org/D145883

Files:
  clang/lib/Driver/ToolChains/Flang.cpp
  flang/test/Driver/code-gen-rv64.f90
  flang/test/Driver/target-cpu-features-invalid.f90
  flang/test/Driver/target-cpu-features.f90


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -1,5 +1,3 @@
-! REQUIRES: aarch64-registered-target, x86-registered-target
-
 ! Test that -mcpu/march are used and that the -target-cpu and -target-features
 ! are also added to the fc1 command.
 
@@ -22,14 +20,8 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
-
-! Test that invalid cpu and features are ignored.
-
-! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-cpu supercpu \
-! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-CPU
-
-! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-feature +superspeed \
-! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s 
-check-prefix=CHECK-INVALID-FEATURE
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
 
 
 ! CHECK-A57: "-fc1" "-triple" "aarch64-unknown-linux-gnu"
@@ -52,5 +44,5 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" 
"-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" 
"-target-feature" "-fsgsbase"
 
-! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target 
(ignoring processor)
-! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this 
target (ignoring feature)
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" 
"-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 
"-target-feature" "+c"
Index: flang/test/Driver/target-cpu-features-invalid.f90
===
--- /dev/null
+++ flang/test/Driver/target-cpu-features-invalid.f90
@@ -0,0 +1,13 @@
+! REQUIRES: aarch64-registered-target
+
+! Test that invalid cpu and features are ignored.
+
+! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-cpu supercpu \
+! RUN:   -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-CPU
+
+! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-feature +superspeed \
+! RUN:   -o /dev/null -S %s 2>&1 | FileCheck %s 
-check-prefix=CHECK-INVALID-FEATURE
+
+
+! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target 
(ignoring processor)
+! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this 
target (ignoring feature)
Index: flang/test/Driver/code-gen-rv64.f90
===
--- /dev/null
+++ flang/test/Driver/code-gen-rv64.f90
@@ -0,0 +1,17 @@
+! Test -emit-obj (RISC-V 64)
+
+! REQUIRES: riscv-registered-target
+
+! RUN: rm -f %t.o
+! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \
+! RUN:   -target-feature +d -target-feature +c -emit-obj %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! RUN: rm -f %t.o
+! RUN: %flang --target=riscv64-unknown-linux-gnu -c %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! If Flang failed to emit target-feature info, then Flags will be 0x0.
+! 0x5 means set EF_RISCV_RVC (0x1) and EF_RISCV_FLOAT_ABI_DOUBLE (0x4)
+! CHECK: Flags: 0x5, RVC, double-float ABI
+end program
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -105,7 +105,7 @@
   default:
 break;
   case llvm::Triple::aarch64:
-[[fallthrough]];
+  case llvm::Triple::riscv64:
   case llvm::Triple::x86_64:
 getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
 break;


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -1,5 +1,3 @@
-! REQUIRES: aarch64-registered-target, x86-registered-target
-
 ! Test that -mcpu/march are used and that the -target-cpu and -target-features
 ! are also added to the fc1 command.
 
@@ -22,14 +20,8 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
-
-! Test that invalid cpu and features are ignored.
-
-! RUN: %flang_fc1 -triple aarch64-linux-gnu -targ

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

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sunshaoce added inline comments.



Comment at: flang/test/Driver/code-gen-rv64.f90:1
+! Test -emit-obj (RISC-V 64)
+

awarzynski wrote:
> mamrami wrote:
> > Hi :)
> > It seems like the test fails: 
> > https://buildkite.com/llvm-project/premerge-checks/builds/141302#0186e55e-199e-401d-ab9f-9f3d47ec87af
> > I see it in my non related patch https://reviews.llvm.org/D146132
> Sorry about that :(
> 
> ```
>  line 3: llvm-readelf: command not found
> ```
> 
> There are 3 options:
> * revert
> * add `llvm-readelf` here 
> https://github.com/llvm/llvm-project/blob/main/flang/test/CMakeLists.txt#L61
> * updated the test to use `llvm-objdump` instead
> 
> HTH.
Thanks! I've submitted in https://reviews.llvm.org/D146204.


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[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

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sunshaoce added a subscriber: DavidSpickett.
sunshaoce added inline comments.



Comment at: flang/test/Driver/code-gen-rv64.f90:1
+! Test -emit-obj (RISC-V 64)
+

mamrami wrote:
> sunshaoce wrote:
> > awarzynski wrote:
> > > mamrami wrote:
> > > > Hi :)
> > > > It seems like the test fails: 
> > > > https://buildkite.com/llvm-project/premerge-checks/builds/141302#0186e55e-199e-401d-ab9f-9f3d47ec87af
> > > > I see it in my non related patch https://reviews.llvm.org/D146132
> > > Sorry about that :(
> > > 
> > > ```
> > >  line 3: llvm-readelf: command not found
> > > ```
> > > 
> > > There are 3 options:
> > > * revert
> > > * add `llvm-readelf` here 
> > > https://github.com/llvm/llvm-project/blob/main/flang/test/CMakeLists.txt#L61
> > > * updated the test to use `llvm-objdump` instead
> > > 
> > > HTH.
> > Thanks! I've submitted in https://reviews.llvm.org/D146204.
> Hi again!
> The test passed after the fix but it fails again:
> https://buildkite.com/llvm-project/premerge-checks/builds/141905#0186fa14-2339-4c0c-9966-dea23592a86b
> 
I noticed this error before, but @DavidSpickett haven't fixed yet. I'll fix it 
now.
https://reviews.llvm.org/rG9f93b71f20ea


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[PATCH] D145845: [Flang] Allow compile *.f03, *.f08 file

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce created this revision.
sunshaoce added reviewers: awarzynski, klausler, clementval, sscalpone.
Herald added a project: All.
sunshaoce requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Fix issue #61260


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Files:
  clang/lib/Driver/Types.cpp


Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)


Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)
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[PATCH] D145845: [Flang] Allow compile *.f03, *.f08 file

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sunshaoce updated this revision to Diff 504359.
sunshaoce added a comment.

Add tests


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Files:
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  flang/test/Driver/f03-suffix.f03
  flang/test/Driver/f08-suffix.f08


Index: flang/test/Driver/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/f08-suffix.f08
@@ -0,0 +1,6 @@
+! RUN: %flang -### -flang-experimental-exec %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/f03-suffix.f03
@@ -0,0 +1,6 @@
+! RUN: %flang -### -flang-experimental-exec %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)


Index: flang/test/Driver/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/f08-suffix.f08
@@ -0,0 +1,6 @@
+! RUN: %flang -### -flang-experimental-exec %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/f03-suffix.f03
@@ -0,0 +1,6 @@
+! RUN: %flang -### -flang-experimental-exec %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)
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[PATCH] D145845: [Flang] Allow compile *.f03, *.f08 file

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sunshaoce added a comment.

Before

  $ /home/sunshaoce/dev/llvm-project/build/bin/flang-new 
/home/sunshaoce/dev/llvm-project/build/temp.f03 -flang-experimental-exec -o 
temp.out -###
  flang-new version 17.0.0 (https://github.com/llvm/llvm-project.git 
890e6c871d31dca9e461c01118cf25fb303b9cad)
  Target: x86_64-unknown-linux-gnu
  Thread model: posix
  InstalledDir: /home/sunshaoce/dev/llvm-project/build/bin
   "/usr/bin/ld" "-pie" "-z" "relro" "--hash-style=gnu" "--eh-frame-hdr" "-m" 
"elf_x86_64" "-dynamic-linker" "/lib64/ld-linux-x86-64.so.2" "-o" "temp.out" 
"/lib/x86_64-linux-gnu/Scrt1.o" "/lib/x86_64-linux-gnu/crti.o" 
"/usr/lib/gcc/x86_64-linux-gnu/9/crtbeginS.o" 
"-L/usr/lib/gcc/x86_64-linux-gnu/9" 
"-L/usr/lib/gcc/x86_64-linux-gnu/9/../../../../lib64" "-L/lib/x86_64-linux-gnu" 
"-L/lib/../lib64" "-L/usr/lib/x86_64-linux-gnu" "-L/usr/lib/../lib64" "-L/lib" 
"-L/usr/lib" "/home/sunshaoce/dev/llvm-project/build/temp.f03" 
"-L/home/sunshaoce/dev/llvm-project/build/lib" "-lFortran_main" 
"-lFortranRuntime" "-lFortranDecimal" "-lm" "-lgcc" "--as-needed" "-lgcc_s" 
"--no-as-needed" "-lc" "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" 
"/usr/lib/gcc/x86_64-linux-gnu/9/crtendS.o" "/lib/x86_64-linux-gnu/crtn.o"

after

  $ /home/sunshaoce/dev/llvm-project/build/bin/flang-new 
/home/sunshaoce/dev/llvm-project/build/temp.f03 -flang-experimental-exec -o 
temp.out -###
  flang-new version 17.0.0 (https://github.com/llvm/llvm-project.git 
890e6c871d31dca9e461c01118cf25fb303b9cad)
  Target: x86_64-unknown-linux-gnu
  Thread model: posix
  InstalledDir: /home/sunshaoce/dev/llvm-project/build/bin
   "/home/sunshaoce/dev/llvm-project/build/bin/flang-new" "-fc1" "-triple" 
"x86_64-unknown-linux-gnu" "-emit-obj" "-fcolor-diagnostics" 
"-mrelocation-model" "pic" "-pic-level" "2" "-pic-is-pie" "-target-cpu" 
"x86-64" "-o" "/tmp/temp-72c5c0.o" "-x" "f95-cpp-input" 
"/home/sunshaoce/dev/llvm-project/build/temp.f03"
   "/usr/bin/ld" "-pie" "-z" "relro" "--hash-style=gnu" "--eh-frame-hdr" "-m" 
"elf_x86_64" "-dynamic-linker" "/lib64/ld-linux-x86-64.so.2" "-o" "temp.out" 
"/lib/x86_64-linux-gnu/Scrt1.o" "/lib/x86_64-linux-gnu/crti.o" 
"/usr/lib/gcc/x86_64-linux-gnu/9/crtbeginS.o" 
"-L/usr/lib/gcc/x86_64-linux-gnu/9" 
"-L/usr/lib/gcc/x86_64-linux-gnu/9/../../../../lib64" "-L/lib/x86_64-linux-gnu" 
"-L/lib/../lib64" "-L/usr/lib/x86_64-linux-gnu" "-L/usr/lib/../lib64" "-L/lib" 
"-L/usr/lib" "/tmp/temp-72c5c0.o" 
"-L/home/sunshaoce/dev/llvm-project/build/lib" "-lFortran_main" 
"-lFortranRuntime" "-lFortranDecimal" "-lm" "-lgcc" "--as-needed" "-lgcc_s" 
"--no-as-needed" "-lc" "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" 
"/usr/lib/gcc/x86_64-linux-gnu/9/crtendS.o" "/lib/x86_64-linux-gnu/crtn.o"

So, I tested it by checking whether `flang` was called.


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[PATCH] D145845: [Flang] Allow compile *.f03, *.f08 file

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sunshaoce updated this revision to Diff 504360.
sunshaoce added a comment.

Remove -flang-experimental-exec


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Files:
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  flang/test/Driver/f03-suffix.f03
  flang/test/Driver/f08-suffix.f08


Index: flang/test/Driver/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/f08-suffix.f08
@@ -0,0 +1,6 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/f03-suffix.f03
@@ -0,0 +1,6 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)


Index: flang/test/Driver/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/f08-suffix.f08
@@ -0,0 +1,6 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/f03-suffix.f03
@@ -0,0 +1,6 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)
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[PATCH] D145845: [Flang] Allow compile *.f03, *.f08 file

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sunshaoce updated this revision to Diff 504362.
sunshaoce added a comment.

Address @awarzynski's comment


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Files:
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  flang/test/Driver/supported-suffices/f03-suffix.f03
  flang/test/Driver/supported-suffices/f08-suffix.f08


Index: flang/test/Driver/supported-suffices/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,6 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/supported-suffices/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,6 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)


Index: flang/test/Driver/supported-suffices/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,6 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/supported-suffices/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,6 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)
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[PATCH] D145845: [Flang] Allow compile *.f03, *.f08 file

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sunshaoce updated this revision to Diff 504363.
sunshaoce marked 2 inline comments as done.
sunshaoce added a comment.

Sorry, I just missed a comment.


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  flang/test/Driver/supported-suffices/f08-suffix.f08


Index: flang/test/Driver/supported-suffices/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/supported-suffices/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)


Index: flang/test/Driver/supported-suffices/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/supported-suffices/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)
___
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[PATCH] D145845: [Flang] Allow compile *.f03, *.f08 file

[Shao-Ce SUN via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
sunshaoce marked an inline comment as done.
Closed by commit rG171794de533b: [Flang] Allow compile *.f03, *.f08 file 
(authored by sunshaoce).

Repository:
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Files:
  clang/lib/Driver/Types.cpp
  flang/test/Driver/supported-suffices/f03-suffix.f03
  flang/test/Driver/supported-suffices/f08-suffix.f08


Index: flang/test/Driver/supported-suffices/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/supported-suffices/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)


Index: flang/test/Driver/supported-suffices/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/supported-suffices/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)
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[PATCH] D145845: [Flang] Allow compile *.f03, *.f08 file

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce reopened this revision.
sunshaoce added a comment.
This revision is now accepted and ready to land.

Sorry! My previous tests were not comprehensive enough, which resulted in 
failures in the MSVC environment.


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[PATCH] D145845: [Flang] Allow compile *.f03, *.f08 file

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 504372.
sunshaoce added a comment.

Fix the issue of failing in the MSVC environment.


Repository:
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Files:
  clang/lib/Driver/Types.cpp
  flang/test/Driver/supported-suffices/f03-suffix.f03
  flang/test/Driver/supported-suffices/f08-suffix.f08


Index: flang/test/Driver/supported-suffices/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "-o" "{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/supported-suffices/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "-o" "{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)


Index: flang/test/Driver/supported-suffices/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "-o" "{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/supported-suffices/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "-o" "{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)
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[PATCH] D145845: [Flang] Allow compile *.f03, *.f08 file

[Shao-Ce SUN via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGb1fdcd5fbc09: [Flang] Allow compile *.f03, *.f08 file 
(authored by sunshaoce).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145845/new/

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Files:
  clang/lib/Driver/Types.cpp
  flang/test/Driver/supported-suffices/f03-suffix.f03
  flang/test/Driver/supported-suffices/f08-suffix.f08


Index: flang/test/Driver/supported-suffices/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "-o" "{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/supported-suffices/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "-o" "{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)


Index: flang/test/Driver/supported-suffices/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "-o" "{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/supported-suffices/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "-o" "{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)
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[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce created this revision.
sunshaoce added reviewers: awarzynski, klausler, clementval, sscalpone, 
craig.topper, jrtc27, kito-cheng.
Herald added subscribers: VincentWu, vkmr, evandro, luismarques, 
sameer.abuasal, s.egerton, Jim, benna, psnobl, PkmX, rogfer01, shiva0217, 
simoncook, arichardson.
Herald added projects: Flang, All.
sunshaoce requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, jdoerfert, MaskRay.
Herald added a project: clang.

Fix the issue of .o file generated by `Flang` 
with `Flags` info is 0x0 under RISC-V.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D145883

Files:
  clang/lib/Driver/ToolChains/Flang.cpp
  flang/test/Driver/target-features.f90


Index: flang/test/Driver/target-features.f90
===
--- /dev/null
+++ flang/test/Driver/target-features.f90
@@ -0,0 +1,4 @@
+! RUN: %flang --target=riscv64-linux-gnu --target=riscv64 -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
+
+! CHECK-RV64: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" 
"+c" "-target-feature" "-e" "-target-feature" "-f" "-target-feature" "-d" 
"-target-feature" "-h" "-target-feature" "-zihintpause" "-target-feature" 
"-zfhmin" "-target-feature" "-zfh" "-target-feature" "-zfinx" "-target-feature" 
"-zdinx" "-target-feature" "-zhinxmin" "-target-feature" "-zhinx" 
"-target-feature" "-zba" "-target-feature" "-zbb" "-target-feature" "-zbc" 
"-target-feature" "-zbs" "-target-feature" "-zbkb" "-target-feature" "-zbkc" 
"-target-feature" "-zbkx" "-target-feature" "-zknd" "-target-feature" "-zkne" 
"-target-feature" "-zknh" "-target-feature" "-zksed" "-target-feature" "-zksh" 
"-target-feature" "-zkr" "-target-feature" "-zkn" "-target-feature" "-zks" 
"-target-feature" "-zkt" "-target-feature" "-zk" "-target-feature" "-zmmul" 
"-target-feature" "-v" "-target-feature" "-zvl32b" "-target-feature" "-zvl64b" 
"-target-feature" "-zvl128b" "-target-feature" "-zvl256b" "-target-feature" 
"-zvl512b" "-target-feature" "-zvl1024b" "-target-feature" "-zvl2048b" 
"-target-feature" "-zvl4096b" "-target-feature" "-zvl8192b" "-target-feature" 
"-zvl16384b" "-target-feature" "-zvl32768b" "-target-feature" "-zvl65536b" 
"-target-feature" "-zve32x" "-target-feature" "-zve32f" "-target-feature" 
"-zve64x" "-target-feature" "-zve64f" "-target-feature" "-zve64d" 
"-target-feature" "-zicbom" "-target-feature" "-zicboz" "-target-feature" 
"-zicbop" "-target-feature" "-zicsr" "-target-feature" "-zifencei" 
"-target-feature" "-zawrs" "-target-feature" "-svnapot" "-target-feature" 
"-svpbmt" "-target-feature" "-svinval" "-target-feature" "-xtheadba" 
"-target-feature" "-xtheadbb" "-target-feature" "-xtheadbs" "-target-feature" 
"-xtheadcmo" "-target-feature" "-xtheadcondmov" "-target-feature" 
"-xtheadfmemidx" "-target-feature" "-xtheadmac" "-target-feature" 
"-xtheadmemidx" "-target-feature" "-xtheadmempair" "-target-feature" 
"-xtheadsync" "-target-feature" "-xtheadvdot" "-target-feature" 
"-xventanacondops" "-target-feature" "-experimental-zihintntl" 
"-target-feature" "-experimental-zca" "-target-feature" "-experimental-zcb" 
"-target-feature" "-experimental-zcd" "-target-feature" "-experimental-zcf" 
"-target-feature" "-experimental-zfa" "-target-feature" "-experimental-zvfh" 
"-target-feature" "-experimental-ztso" "-target-feature" "+relax" 
"-target-feature" "-save-restore"
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -109,6 +109,9 @@
   case llvm::Triple::x86_64:
 getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
 break;
+  case llvm::Triple::riscv64:
+getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
+break;
   }
 
   // TODO: Add target specific flags, ABI, mtune option etc.


Index: flang/test/Driver/target-features.f90
===
--- /dev/null
+++ flang/test/Driver/target-features.f90
@@ -0,0 +1,4 @@
+! RUN: %flang --target=riscv64-linux-gnu --target=riscv64 -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
+
+! CHECK-RV64: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+c" "-target-feature" "-e" "-target-feature" "-f" "-target-feature" "-d" "-target-feature" "-h" "-target-feature" "-zihintpause" "-target-feature" "-zfhmin" "-target-feature" "-zfh" "-target-feature" "-zfinx" "-target-feature" "-zdinx" "-target-feature" "-zhinxmin" "-target-feature" "-zhinx" "-target-feature" "-zba" "-target-feature" "-zbb" "-target-feature" "-zbc" "-target-feature" "-zbs" "-target-feature" "-zbkb" "-target-feature" "-zbkc" "-target-feature" "-zbkx" "-target-feature" "-zknd" "-target-feature" "-zkne" "-target-feature" "-zknh" "-target-feature" "-zksed" "-target-feature" "-zksh" "-target-feature" "-zkr" "-target-fe

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 504548.
sunshaoce added a comment.

Based on everyone's comments, I merged the test into `target-cpu-features.f90` 
and only kept the generic `-target-feature`. At the same time, I removed the 
`switch (TC.getArch())` and passed the test on x86 and RISC-V 64.


Repository:
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Files:
  clang/lib/Driver/ToolChains/Flang.cpp
  flang/test/Driver/target-cpu-features.f90


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -22,6 +22,12 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
+! RUN: %flang --target=riscv32-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV32
+
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
+
 
 ! Test that invalid cpu and features are ignored.
 
@@ -52,5 +58,12 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" 
"-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" 
"-target-feature" "-fsgsbase"
 
+! CHECK-RV32: "-fc1" "-triple" "riscv32-unknown-linux-gnu"
+! CHECK-RV32-SAME: "-target-cpu" "generic-rv32" "-target-feature" "+m" 
"-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 
"-target-feature" "+c" "-target-feature" "-e"
+
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" 
"-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 
"-target-feature" "+c" "-target-feature" "-e"
+
+
 ! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target 
(ignoring processor)
 ! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this 
target (ignoring feature)
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -101,15 +101,7 @@
   }
 
   // Add the target features.
-  switch (TC.getArch()) {
-  default:
-break;
-  case llvm::Triple::aarch64:
-[[fallthrough]];
-  case llvm::Triple::x86_64:
-getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
-break;
-  }
+  getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
 
   // TODO: Add target specific flags, ABI, mtune option etc.
 }


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -22,6 +22,12 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
+! RUN: %flang --target=riscv32-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV32
+
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
+
 
 ! Test that invalid cpu and features are ignored.
 
@@ -52,5 +58,12 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" "-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" "-target-feature" "-fsgsbase"
 
+! CHECK-RV32: "-fc1" "-triple" "riscv32-unknown-linux-gnu"
+! CHECK-RV32-SAME: "-target-cpu" "generic-rv32" "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c" "-target-feature" "-e"
+
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c" "-target-feature" "-e"
+
+
 ! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target (ignoring processor)
 ! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this target (ignoring feature)
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -101,15 +101,7 @@
   }
 
   // Add the target features.
-  switch (TC.getArch()) {
-  default:
-break;
-  case llvm::Triple::aarch64:
-[[fallthrough]];
-  case llvm::Triple::x86_64:
-getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
-break;
-  }
+  getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
 
   // TODO: Add target specific flags, ABI, mtune option etc.
 }
___
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[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 504616.
sunshaoce added a comment.

Add test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145883/new/

https://reviews.llvm.org/D145883

Files:
  clang/lib/Driver/ToolChains/Flang.cpp
  flang/test/Driver/code-gen-rv64.f90
  flang/test/Driver/target-cpu-features.f90


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -22,6 +22,9 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
+
 
 ! Test that invalid cpu and features are ignored.
 
@@ -52,5 +55,9 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" 
"-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" 
"-target-feature" "-fsgsbase"
 
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" 
"-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 
"-target-feature" "+c"
+
+
 ! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target 
(ignoring processor)
 ! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this 
target (ignoring feature)
Index: flang/test/Driver/code-gen-rv64.f90
===
--- /dev/null
+++ flang/test/Driver/code-gen-rv64.f90
@@ -0,0 +1,13 @@
+! Test -emit-obj (RISC-V 64)
+
+! RUN: rm -f %t.o
+! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \
+! RUN:   -target-feature +d -target-feature +c -emit-obj %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! RUN: rm -f %t.o
+! RUN: %flang --target=riscv64-unknown-linux-gnu -c %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! CHECK: Flags: 0x5, RVC, double-float ABI
+end program
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -106,6 +106,8 @@
 break;
   case llvm::Triple::aarch64:
 [[fallthrough]];
+  case llvm::Triple::riscv64:
+[[fallthrough]];
   case llvm::Triple::x86_64:
 getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
 break;


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -22,6 +22,9 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
+
 
 ! Test that invalid cpu and features are ignored.
 
@@ -52,5 +55,9 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" "-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" "-target-feature" "-fsgsbase"
 
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c"
+
+
 ! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target (ignoring processor)
 ! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this target (ignoring feature)
Index: flang/test/Driver/code-gen-rv64.f90
===
--- /dev/null
+++ flang/test/Driver/code-gen-rv64.f90
@@ -0,0 +1,13 @@
+! Test -emit-obj (RISC-V 64)
+
+! RUN: rm -f %t.o
+! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \
+! RUN:   -target-feature +d -target-feature +c -emit-obj %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! RUN: rm -f %t.o
+! RUN: %flang --target=riscv64-unknown-linux-gnu -c %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! CHECK: Flags: 0x5, RVC, double-float ABI
+end program
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -106,6 +106,8 @@
 break;
   case llvm::Triple::aarch64:
 [[fallthrough]];
+  case llvm::Triple::riscv64:
+[[fallthrough]];
   case llvm::Triple::x86_64:
 getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
 break;
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[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 504672.
sunshaoce marked an inline comment as done.
sunshaoce added a comment.

Address @awarzynski's comment. Thanks!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/lib/Driver/ToolChains/Flang.cpp
  flang/test/Driver/code-gen-rv64.f90
  flang/test/Driver/target-cpu-features.f90


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -22,6 +22,9 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
+
 
 ! Test that invalid cpu and features are ignored.
 
@@ -52,5 +55,9 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" 
"-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" 
"-target-feature" "-fsgsbase"
 
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" 
"-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 
"-target-feature" "+c"
+
+
 ! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target 
(ignoring processor)
 ! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this 
target (ignoring feature)
Index: flang/test/Driver/code-gen-rv64.f90
===
--- /dev/null
+++ flang/test/Driver/code-gen-rv64.f90
@@ -0,0 +1,14 @@
+! Test -emit-obj (RISC-V 64)
+
+! RUN: rm -f %t.o
+! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \
+! RUN:   -target-feature +d -target-feature +c -emit-obj %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! RUN: rm -f %t.o
+! RUN: %flang --target=riscv64-unknown-linux-gnu -c %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! If Flang failed to emit target-feature info, then Flags will be 0x0.
+! CHECK: Flags: 0x5, RVC, double-float ABI
+end program
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -106,6 +106,8 @@
 break;
   case llvm::Triple::aarch64:
 [[fallthrough]];
+  case llvm::Triple::riscv64:
+[[fallthrough]];
   case llvm::Triple::x86_64:
 getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
 break;


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -22,6 +22,9 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
+
 
 ! Test that invalid cpu and features are ignored.
 
@@ -52,5 +55,9 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" "-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" "-target-feature" "-fsgsbase"
 
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c"
+
+
 ! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target (ignoring processor)
 ! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this target (ignoring feature)
Index: flang/test/Driver/code-gen-rv64.f90
===
--- /dev/null
+++ flang/test/Driver/code-gen-rv64.f90
@@ -0,0 +1,14 @@
+! Test -emit-obj (RISC-V 64)
+
+! RUN: rm -f %t.o
+! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \
+! RUN:   -target-feature +d -target-feature +c -emit-obj %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! RUN: rm -f %t.o
+! RUN: %flang --target=riscv64-unknown-linux-gnu -c %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! If Flang failed to emit target-feature info, then Flags will be 0x0.
+! CHECK: Flags: 0x5, RVC, double-float ABI
+end program
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -106,6 +106,8 @@
 break;
   case llvm::Triple::aarch64:
 [[fallthrough]];
+  case llvm::Triple::riscv64:
+[[fallthrough]];
   case llvm::Triple::x86_64:
 getTargetFeatures(D, Tr

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 504695.
sunshaoce added a comment.

Add `REQUIRES` in tests


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145883/new/

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Files:
  clang/lib/Driver/ToolChains/Flang.cpp
  flang/test/Driver/code-gen-rv64.f90
  flang/test/Driver/target-cpu-features.f90


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -1,4 +1,4 @@
-! REQUIRES: aarch64-registered-target, x86-registered-target
+! REQUIRES: aarch64-registered-target, x86-registered-target, 
riscv-registered-target
 
 ! Test that -mcpu/march are used and that the -target-cpu and -target-features
 ! are also added to the fc1 command.
@@ -22,6 +22,9 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
+
 
 ! Test that invalid cpu and features are ignored.
 
@@ -52,5 +55,9 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" 
"-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" 
"-target-feature" "-fsgsbase"
 
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" 
"-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 
"-target-feature" "+c"
+
+
 ! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target 
(ignoring processor)
 ! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this 
target (ignoring feature)
Index: flang/test/Driver/code-gen-rv64.f90
===
--- /dev/null
+++ flang/test/Driver/code-gen-rv64.f90
@@ -0,0 +1,16 @@
+! Test -emit-obj (RISC-V 64)
+
+! REQUIRES: riscv-registered-target
+
+! RUN: rm -f %t.o
+! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \
+! RUN:   -target-feature +d -target-feature +c -emit-obj %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! RUN: rm -f %t.o
+! RUN: %flang --target=riscv64-unknown-linux-gnu -c %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! If Flang failed to emit target-feature info, then Flags will be 0x0.
+! CHECK: Flags: 0x5, RVC, double-float ABI
+end program
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -106,6 +106,8 @@
 break;
   case llvm::Triple::aarch64:
 [[fallthrough]];
+  case llvm::Triple::riscv64:
+[[fallthrough]];
   case llvm::Triple::x86_64:
 getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
 break;


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -1,4 +1,4 @@
-! REQUIRES: aarch64-registered-target, x86-registered-target
+! REQUIRES: aarch64-registered-target, x86-registered-target, riscv-registered-target
 
 ! Test that -mcpu/march are used and that the -target-cpu and -target-features
 ! are also added to the fc1 command.
@@ -22,6 +22,9 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
+
 
 ! Test that invalid cpu and features are ignored.
 
@@ -52,5 +55,9 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" "-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" "-target-feature" "-fsgsbase"
 
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c"
+
+
 ! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target (ignoring processor)
 ! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this target (ignoring feature)
Index: flang/test/Driver/code-gen-rv64.f90
===
--- /dev/null
+++ flang/test/Driver/code-gen-rv64.f90
@@ -0,0 +1,16 @@
+! Test -emit-obj (RISC-V 64)
+
+! REQUIRES: riscv-registered-target
+
+! RUN: rm -f %t.o
+! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \
+! RUN:   -target-feature +d -target-feature +c -emit-obj %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! RUN: rm -f %t.o
+! RUN: %flang --target=riscv64-unknown-li

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce added inline comments.



Comment at: flang/test/Driver/code-gen-rv64.f90:12
+
+! CHECK: Flags: 0x5, RVC, double-float ABI
+end program

awarzynski wrote:
> awarzynski wrote:
> > For those of us less familiar with RISC-V - could you explain what's 
> > significant about this line? For example, [[ 
> > https://github.com/llvm/llvm-project/blob/0aac9a2875bad4f065367e4a6553fad78605f895/flang/test/Driver/code-gen-aarch64.f90#L18
> >  | here ]] it is made clear that with the right triple used, one should see 
> > a `ret` instruction within the main function (`_QQmain`). In here, I just 
> > see a "magic" number :)
> Follow-up questions - what's "Flags" and why "0x5"? Is there any online 
> documentation that you can refer to here?
You can refer: 
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/download/v1.0/riscv-abi.pdf
  `8.1. File Header` `e_flags` section


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[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce marked 5 inline comments as done.
sunshaoce added inline comments.



Comment at: flang/test/Driver/target-cpu-features.f90:33
 ! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-CPU
 
 ! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-feature +superspeed \

Without `REQUIRES` line, test will be failed here.

Due to this patch has little to do with CPU-feature, I think we can only add 
`code-gen-rv64.f90`. How about that?


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[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 504756.
sunshaoce marked 2 inline comments as done.
sunshaoce added a comment.

Add `target-cpu-features-invalid.f90`


Repository:
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Files:
  clang/lib/Driver/ToolChains/Flang.cpp
  flang/test/Driver/code-gen-rv64.f90
  flang/test/Driver/target-cpu-features-invalid.f90
  flang/test/Driver/target-cpu-features.f90


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -1,5 +1,3 @@
-! REQUIRES: aarch64-registered-target, x86-registered-target
-
 ! Test that -mcpu/march are used and that the -target-cpu and -target-features
 ! are also added to the fc1 command.
 
@@ -22,14 +20,8 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
-
-! Test that invalid cpu and features are ignored.
-
-! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-cpu supercpu \
-! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-CPU
-
-! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-feature +superspeed \
-! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s 
-check-prefix=CHECK-INVALID-FEATURE
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
 
 
 ! CHECK-A57: "-fc1" "-triple" "aarch64-unknown-linux-gnu"
@@ -52,5 +44,5 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" 
"-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" 
"-target-feature" "-fsgsbase"
 
-! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target 
(ignoring processor)
-! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this 
target (ignoring feature)
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" 
"-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 
"-target-feature" "+c"
Index: flang/test/Driver/target-cpu-features-invalid.f90
===
--- /dev/null
+++ flang/test/Driver/target-cpu-features-invalid.f90
@@ -0,0 +1,13 @@
+! REQUIRES: aarch64-registered-target
+
+! Test that invalid cpu and features are ignored.
+
+! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-cpu supercpu \
+! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-CPU
+
+! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-feature +superspeed \
+! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s 
-check-prefix=CHECK-INVALID-FEATURE
+
+
+! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target 
(ignoring processor)
+! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this 
target (ignoring feature)
Index: flang/test/Driver/code-gen-rv64.f90
===
--- /dev/null
+++ flang/test/Driver/code-gen-rv64.f90
@@ -0,0 +1,17 @@
+! Test -emit-obj (RISC-V 64)
+
+! REQUIRES: riscv-registered-target
+
+! RUN: rm -f %t.o
+! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \
+! RUN:   -target-feature +d -target-feature +c -emit-obj %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! RUN: rm -f %t.o
+! RUN: %flang --target=riscv64-unknown-linux-gnu -c %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! If Flang failed to emit target-feature info, then Flags will be 0x0.
+! 0x5 means set EF_RISCV_RVC (0x1) and EF_RISCV_FLOAT_ABI_DOUBLE (0x4)
+! CHECK: Flags: 0x5, RVC, double-float ABI
+end program
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -106,6 +106,8 @@
 break;
   case llvm::Triple::aarch64:
 [[fallthrough]];
+  case llvm::Triple::riscv64:
+[[fallthrough]];
   case llvm::Triple::x86_64:
 getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
 break;


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -1,5 +1,3 @@
-! REQUIRES: aarch64-registered-target, x86-registered-target
-
 ! Test that -mcpu/march are used and that the -target-cpu and -target-features
 ! are also added to the fc1 command.
 
@@ -22,14 +20,8 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
-
-! Test that invalid cpu and features are ignored.
-
-! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-cpu supercpu \
-! RUN: -o /dev/null -S %s 2>&1 | FileChe

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce added inline comments.



Comment at: flang/test/Driver/code-gen-rv64.f90:7
+! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \
+! RUN:   -target-feature +d -target-feature +c -emit-obj %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s

awarzynski wrote:
> jrtc27 wrote:
> > Why do we need to go to an object file??? That's terrible practice in Clang 
> > tests, and the same should be true of Flang. Test the IR, that is 
> > sufficient, and decouples you from the backend.
> > That's terrible practice in Clang tests, and the same should be true of 
> > Flang. Test the IR, that is sufficient, and decouples you from the backend.
> 
> I disagree. 
> 
> A compiler driver is responsible for creating a correct backend/LLVM 
> invocation. Is there some other way to verify that the backend invocation is 
> correct? (other then inspecting the generated machine code file).
> 
> I agree that it is desirable to avoid any architectural details leaking 
> outside of LLVM (into e.g. Clang and/or Flang), but IMHO it's very hard to 
> avoid in practice.
After my test, there is no difference between the LLVM IR generated before and 
after modification. These tests are also from or similar to those that already 
exist.

So I think we can land this patch first. Then fix these in a new patch.


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[PATCH] D143478: [RFC][Flang][driver] Try to support `flang -fc1as`

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce created this revision.
sunshaoce added reviewers: rovka, kiranchandramohan, Leporacanthicus, 
awarzynski, sscalpone, liaolucy.
Herald added projects: Flang, All.
sunshaoce requested review of this revision.
Herald added subscribers: cfe-commits, jdoerfert, MaskRay.
Herald added a project: clang.

I'm trying to support `flang-new *.s`. Since I'm new to flang, I'm not sure if 
this is the right way to do it.


Repository:
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https://reviews.llvm.org/D143478

Files:
  clang/include/clang/Driver/Options.h
  clang/include/clang/Driver/Options.td
  clang/include/clang/Driver/ToolChain.h
  clang/lib/Driver/ToolChain.cpp
  clang/lib/Driver/ToolChains/Flang.cpp
  clang/lib/Driver/ToolChains/Flang.h
  flang/tools/flang-driver/CMakeLists.txt
  flang/tools/flang-driver/driver.cpp
  flang/tools/flang-driver/fc1as_main.cpp

Index: flang/tools/flang-driver/fc1as_main.cpp
===
--- /dev/null
+++ flang/tools/flang-driver/fc1as_main.cpp
@@ -0,0 +1,672 @@
+//===-- fc1as_main.cpp - Flang Assembler  -===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This is the entry point to the flang -fc1as functionality, which implements
+// the direct interface to the LLVM MC based assembler.
+//
+//===--===//
+
+#include "clang/Basic/Diagnostic.h"
+#include "clang/Basic/DiagnosticOptions.h"
+#include "clang/Driver/DriverDiagnostic.h"
+#include "clang/Driver/Options.h"
+#include "clang/Frontend/FrontendDiagnostic.h"
+#include "clang/Frontend/TextDiagnosticPrinter.h"
+#include "clang/Frontend/Utils.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringSwitch.h"
+#include "llvm/ADT/Triple.h"
+#include "llvm/IR/DataLayout.h"
+#include "llvm/MC/MCAsmBackend.h"
+#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/MC/MCCodeEmitter.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCObjectFileInfo.h"
+#include "llvm/MC/MCObjectWriter.h"
+#include "llvm/MC/MCParser/MCAsmParser.h"
+#include "llvm/MC/MCParser/MCTargetAsmParser.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCSectionMachO.h"
+#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetOptions.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Option/Arg.h"
+#include "llvm/Option/ArgList.h"
+#include "llvm/Option/OptTable.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/FileSystem.h"
+#include "llvm/Support/FormattedStream.h"
+#include "llvm/Support/Host.h"
+#include "llvm/Support/MemoryBuffer.h"
+#include "llvm/Support/Path.h"
+#include "llvm/Support/Process.h"
+#include "llvm/Support/Signals.h"
+#include "llvm/Support/SourceMgr.h"
+#include "llvm/Support/TargetSelect.h"
+#include "llvm/Support/Timer.h"
+#include "llvm/Support/raw_ostream.h"
+#include 
+#include 
+#include 
+using namespace clang;
+using namespace clang::driver;
+using namespace clang::driver::options;
+using namespace llvm;
+using namespace llvm::opt;
+
+namespace {
+
+/// Helper class for representing a single invocation of the assembler.
+struct AssemblerInvocation {
+  /// @name Target Options
+  /// @{
+
+  /// The name of the target triple to assemble for.
+  std::string triple;
+
+  /// If given, the name of the target CPU to determine which instructions
+  /// are legal.
+  std::string cpu;
+
+  /// The list of target specific features to enable or disable -- this should
+  /// be a list of strings starting with '+' or '-'.
+  std::vector features;
+
+  /// The list of symbol definitions.
+  std::vector symbolDefs;
+
+  /// @}
+  /// @name Language Options
+  /// @{
+
+  std::vector includePaths;
+  unsigned noInitialTextSection : 1;
+  unsigned saveTemporaryLabels : 1;
+  unsigned genDwarfForAssembly : 1;
+  unsigned relaxElfRelocations : 1;
+  unsigned dwarf64 : 1;
+  unsigned dwarfVersion;
+  std::string dwarfDebugFlags;
+  std::string dwarfDebugProducer;
+  std::string debugCompilationDir;
+  std::map debugPrefixMap;
+  llvm::DebugCompressionType compressDebugSections =
+  llvm::DebugCompressionType::None;
+  std::string mainFileName;
+  std::string splitDwarfOutput;
+
+  /// @}
+  /// @name Frontend Options
+  /// @{
+
+  std::string inputFile;
+  std::vector llvmArgs;
+  std::string outputPath;
+  enum FileType {
+FT_Asm,  ///< Assembly (.s) output, transliterate mode.
+FT_Null, ///< No output, for timing purposes.
+FT_Obj   ///< Object file output.
+  };
+  FileType outputType;
+  unsigned showHelp : 1;
+  unsigned showVersion : 1;
+
+  /// @}
+  /// @name Transliterate Options
+  /// @{
+
+

[PATCH] D143478: [RFC][Flang][driver] Try to support `flang -fc1as`

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce added a comment.

In D143478#4109479 , @awarzynski 
wrote:

> Thanks for working on this! Before diving any deeper
>
> - Does LLVM Flang require `flang-new -fc1as`?
> - If yes, why can't Flang and Clang share it?
>
> For better visibility, I suggest raising these questions on Discourse 
> . As this could potentially affect both Flang 
> and Clang, could you post in one of the generic sections? Thanks!

Thanks! I opened a topic: 
https://discourse.llvm.org/t/rfc-flang-driver-try-to-support-flang-fc1as/68267


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[PATCH] D143478: [RFC][Flang][driver] Try to support `flang -fc1as`

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce added a comment.

In D143478#4109412 , @clementval 
wrote:

> There should be some tests.

I'm not sure how to check the generated binaries, can you provide a test case 
for reference? Thanks!


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[PATCH] D143478: [RFC][Flang][driver] Try to support `flang -fc1as`

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 495522.
sunshaoce added a comment.

Add a test


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Files:
  clang/include/clang/Driver/Options.h
  clang/include/clang/Driver/Options.td
  clang/include/clang/Driver/ToolChain.h
  clang/lib/Driver/ToolChain.cpp
  clang/lib/Driver/ToolChains/Flang.cpp
  clang/lib/Driver/ToolChains/Flang.h
  flang/test/Driver/asm-code-gen-x86.s
  flang/test/lit.cfg.py
  flang/tools/flang-driver/CMakeLists.txt
  flang/tools/flang-driver/driver.cpp
  flang/tools/flang-driver/fc1as_main.cpp

Index: flang/tools/flang-driver/fc1as_main.cpp
===
--- /dev/null
+++ flang/tools/flang-driver/fc1as_main.cpp
@@ -0,0 +1,672 @@
+//===-- fc1as_main.cpp - Flang Assembler  -===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This is the entry point to the flang -fc1as functionality, which implements
+// the direct interface to the LLVM MC based assembler.
+//
+//===--===//
+
+#include "clang/Basic/Diagnostic.h"
+#include "clang/Basic/DiagnosticOptions.h"
+#include "clang/Driver/DriverDiagnostic.h"
+#include "clang/Driver/Options.h"
+#include "clang/Frontend/FrontendDiagnostic.h"
+#include "clang/Frontend/TextDiagnosticPrinter.h"
+#include "clang/Frontend/Utils.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringSwitch.h"
+#include "llvm/ADT/Triple.h"
+#include "llvm/IR/DataLayout.h"
+#include "llvm/MC/MCAsmBackend.h"
+#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/MC/MCCodeEmitter.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCObjectFileInfo.h"
+#include "llvm/MC/MCObjectWriter.h"
+#include "llvm/MC/MCParser/MCAsmParser.h"
+#include "llvm/MC/MCParser/MCTargetAsmParser.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCSectionMachO.h"
+#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetOptions.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Option/Arg.h"
+#include "llvm/Option/ArgList.h"
+#include "llvm/Option/OptTable.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/FileSystem.h"
+#include "llvm/Support/FormattedStream.h"
+#include "llvm/Support/Host.h"
+#include "llvm/Support/MemoryBuffer.h"
+#include "llvm/Support/Path.h"
+#include "llvm/Support/Process.h"
+#include "llvm/Support/Signals.h"
+#include "llvm/Support/SourceMgr.h"
+#include "llvm/Support/TargetSelect.h"
+#include "llvm/Support/Timer.h"
+#include "llvm/Support/raw_ostream.h"
+#include 
+#include 
+#include 
+using namespace clang;
+using namespace clang::driver;
+using namespace clang::driver::options;
+using namespace llvm;
+using namespace llvm::opt;
+
+namespace {
+
+/// Helper class for representing a single invocation of the assembler.
+struct AssemblerInvocation {
+  /// @name Target Options
+  /// @{
+
+  /// The name of the target triple to assemble for.
+  std::string triple;
+
+  /// If given, the name of the target CPU to determine which instructions
+  /// are legal.
+  std::string cpu;
+
+  /// The list of target specific features to enable or disable -- this should
+  /// be a list of strings starting with '+' or '-'.
+  std::vector features;
+
+  /// The list of symbol definitions.
+  std::vector symbolDefs;
+
+  /// @}
+  /// @name Language Options
+  /// @{
+
+  std::vector includePaths;
+  unsigned noInitialTextSection : 1;
+  unsigned saveTemporaryLabels : 1;
+  unsigned genDwarfForAssembly : 1;
+  unsigned relaxElfRelocations : 1;
+  unsigned dwarf64 : 1;
+  unsigned dwarfVersion;
+  std::string dwarfDebugFlags;
+  std::string dwarfDebugProducer;
+  std::string debugCompilationDir;
+  std::map debugPrefixMap;
+  llvm::DebugCompressionType compressDebugSections =
+  llvm::DebugCompressionType::None;
+  std::string mainFileName;
+  std::string splitDwarfOutput;
+
+  /// @}
+  /// @name Frontend Options
+  /// @{
+
+  std::string inputFile;
+  std::vector llvmArgs;
+  std::string outputPath;
+  enum FileType {
+FT_Asm,  ///< Assembly (.s) output, transliterate mode.
+FT_Null, ///< No output, for timing purposes.
+FT_Obj   ///< Object file output.
+  };
+  FileType outputType;
+  unsigned showHelp : 1;
+  unsigned showVersion : 1;
+
+  /// @}
+  /// @name Transliterate Options
+  /// @{
+
+  unsigned outputAsmVariant;
+  unsigned showEncoding : 1;
+  unsigned showInst : 1;
+
+  /// @}
+  /// @name Assembler Options
+  /// @{
+
+  unsigned relaxAll : 1;
+  unsigned noExecStack : 1;
+  unsig

[PATCH] D143478: [RFC][Flang][driver] Try to support `flang -fc1as`

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce abandoned this revision.
sunshaoce added a comment.

A better implementation is in D143572 


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