[clang] ecfd6d3 - [clang] Set function attributes on SEH filter functions correctly.
Author: Sanne Wouda
Date: 2020-01-17T18:09:42Z
New Revision: ecfd6d3e84185127fb836d6fe62564456be3a9cd
URL:
https://github.com/llvm/llvm-project/commit/ecfd6d3e84185127fb836d6fe62564456be3a9cd
DIFF:
https://github.com/llvm/llvm-project/commit/ecfd6d3e84185127fb836d6fe62564456be3a9cd.diff
LOG: [clang] Set function attributes on SEH filter functions correctly.
Summary:
When compiling with -munwind-tables, the SEH filter funclet needs the uwtable
function attribute, which gets automatically added if we use
SetInternalFunctionAttributes. The filter funclet is internal so this seems
appropriate.
Reviewers: rnk
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72786
Added:
clang/test/CodeGenCXX/exceptions-seh-filter-uwtable.cpp
Modified:
clang/lib/CodeGen/CGException.cpp
clang/test/CodeGen/exceptions-seh-finally.c
Removed:
diff --git a/clang/lib/CodeGen/CGException.cpp
b/clang/lib/CodeGen/CGException.cpp
index 53fafab3e0e6..fffd9897270e 100644
--- a/clang/lib/CodeGen/CGException.cpp
+++ b/clang/lib/CodeGen/CGException.cpp
@@ -1885,7 +1885,7 @@ void
CodeGenFunction::startOutlinedSEHHelper(CodeGenFunction &ParentCGF,
OutlinedStmt->getBeginLoc(), OutlinedStmt->getBeginLoc());
CurSEHParent = ParentCGF.CurSEHParent;
- CGM.SetLLVMFunctionAttributes(GlobalDecl(), FnInfo, CurFn);
+ CGM.SetInternalFunctionAttributes(GlobalDecl(), CurFn, FnInfo);
EmitCapturedLocals(ParentCGF, OutlinedStmt, IsFilter);
}
diff --git a/clang/test/CodeGen/exceptions-seh-finally.c
b/clang/test/CodeGen/exceptions-seh-finally.c
index 3e10d15debcc..8aafeb23090d 100644
--- a/clang/test/CodeGen/exceptions-seh-finally.c
+++ b/clang/test/CodeGen/exceptions-seh-finally.c
@@ -1,6 +1,7 @@
-// RUN: %clang_cc1 %s -triple x86_64-pc-win32 -fms-extensions -emit-llvm -o -
| FileCheck %s
-// RUN: %clang_cc1 %s -triple i686-pc-win32 -fms-extensions -emit-llvm -o - |
FileCheck %s
-// RUN: %clang_cc1 %s -triple aarch64-windows -fms-extensions -emit-llvm -o -
| FileCheck %s
+// RUN: %clang_cc1 %s -triple x86_64-pc-win32 -fms-extensions -emit-llvm -O1
-disable-llvm-passes -o - | FileCheck %s
+// RUN: %clang_cc1 %s -triple i686-pc-win32 -fms-extensions -emit-llvm -O1
-disable-llvm-passes -o - | FileCheck %s
+// RUN: %clang_cc1 %s -triple aarch64-windows -fms-extensions -emit-llvm -O1
-disable-llvm-passes -o - | FileCheck %s
+// NOTE: we're passing "-O1 -disable-llvm-passes" to avoid adding optnone and
noinline everywhere.
void abort(void) __attribute__((noreturn));
void might_crash(void);
@@ -281,7 +282,6 @@ void finally_with_func() {
// CHECK-LABEL: define internal void @"?fin$0@0@finally_with_func@@"({{[^)]*}})
// CHECK: call void @cleanup_with_func(i8* getelementptr inbounds ([18 x i8],
[18 x i8]* @"??_C@_0BC@COAGBPGM@finally_with_func?$AA@", i{{32|64}} 0,
i{{32|64}} 0))
-// Look for the absence of noinline. Enum attributes come first, so check that
-// a string attribute is the first to verify that no enum attributes are
-// present.
-// CHECK: attributes [[finally_attrs]] = { "{{.*}}" }
+// Look for the absence of noinline. nounwind is expected; any further
+// attributes should be string attributes.
+// CHECK: attributes [[finally_attrs]] = { nounwind "{{.*}}" }
diff --git a/clang/test/CodeGenCXX/exceptions-seh-filter-uwtable.cpp
b/clang/test/CodeGenCXX/exceptions-seh-filter-uwtable.cpp
new file mode 100644
index ..f09c6a39c7f5
--- /dev/null
+++ b/clang/test/CodeGenCXX/exceptions-seh-filter-uwtable.cpp
@@ -0,0 +1,48 @@
+// RUN: %clang_cc1 "-triple" "arm64-windows" "-munwind-tables"
"-fms-compatibility" -emit-llvm -O1 -disable-llvm-passes %s -o - | FileCheck %s
+// NOTE: we're passing "-O1 -disable-llvm-passes" to avoid adding optnone and
noinline everywhere.
+
+# 0 "" 3
+#define a(b, c) d() & b
+#define f(c) a(e(0, 0, #c).b(), )
+
+struct e {
+ e(int, int, char *);
+ int b();
+};
+
+struct d {
+ void operator&(int);
+};
+
+struct h;
+
+struct i {
+ h *operator->();
+ h &operator*() { f(); }
+};
+
+typedef int g;
+
+struct h {
+ void ad();
+};
+
+g aq(h j, g k, int, int) {
+ if (k)
+return;
+ j.ad();
+}
+
+// Check for the uwtable attribute on the filter funclet.
+// CHECK: define internal i32 @"?filt$0@0@at@@"(i8* %exception_pointers, i8*
%frame_pointer) #[[MD:[0-9]+]]
+// CHECK: attributes #[[MD]] = { nounwind uwtable
+
+void at() {
+ i ar;
+
+ __try {
+ar->ad();
+ } __except (aq(*ar, _exception_code(), 0, 0)) {
+ }
+
+}
___
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[clang] 4ec2a26 - Fix clang test build
Author: Sanne Wouda
Date: 2020-01-29T13:03:27Z
New Revision: 4ec2a267321124a7fe8efe794ce40da67ce1d6bd
URL:
https://github.com/llvm/llvm-project/commit/4ec2a267321124a7fe8efe794ce40da67ce1d6bd
DIFF:
https://github.com/llvm/llvm-project/commit/4ec2a267321124a7fe8efe794ce40da67ce1d6bd.diff
LOG: Fix clang test build
Added:
Modified:
clang/unittests/Format/FormatTest.cpp
Removed:
diff --git a/clang/unittests/Format/FormatTest.cpp
b/clang/unittests/Format/FormatTest.cpp
index 63f83f7ca23c..ea064305091a 100644
--- a/clang/unittests/Format/FormatTest.cpp
+++ b/clang/unittests/Format/FormatTest.cpp
@@ -13036,7 +13036,7 @@ TEST_F(FormatTest, ParsesConfigurationWithLanguages) {
EXPECT_EQ(parseConfiguration("BinPackArguments: true\n"
"InsertTrailingCommas: Wrapped",
&BinPackedTCS),
-ParseError::BinBackTrailingCommaConflict);
+ParseError::BinPackTrailingCommaConflict);
EXPECT_EQ(12u, Style.IndentWidth);
CHECK_PARSE("IndentWidth: 56", IndentWidth, 56u);
EXPECT_EQ(FormatStyle::LK_Cpp, Style.Language);
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[clang] 2939fc1 - [AArch64] Add IR intrinsics for sq(r)dmulh_lane(q)
Author: Sanne Wouda
Date: 2020-01-29T13:25:23Z
New Revision: 2939fc13c8f6a5dbd1be77c1d19dc2720253b8c5
URL:
https://github.com/llvm/llvm-project/commit/2939fc13c8f6a5dbd1be77c1d19dc2720253b8c5
DIFF:
https://github.com/llvm/llvm-project/commit/2939fc13c8f6a5dbd1be77c1d19dc2720253b8c5.diff
LOG: [AArch64] Add IR intrinsics for sq(r)dmulh_lane(q)
Summary:
Currently, sqdmulh_lane and friends from the ACLE (implemented in arm_neon.h),
are represented in LLVM IR as a (by vector) sqdmulh and a vector of (repeated)
indices, like so:
%shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32>
%vqdmulh2.i = tail call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16>
%a, <4 x i16> %shuffle)
When %v's values are known, the shufflevector is optimized away and we are no
longer able to select the lane variant of sqdmulh in the backend.
This defeats a (hand-coded) optimization that packs several constants into a
single vector and uses the lane intrinsics to reduce register pressure and
trade-off materialising several constants for a single vector load from the
constant pool, like so:
int16x8_t v = {2,3,4,5,6,7,8,9};
a = vqdmulh_laneq_s16(a, v, 0);
b = vqdmulh_laneq_s16(b, v, 1);
c = vqdmulh_laneq_s16(c, v, 2);
d = vqdmulh_laneq_s16(d, v, 3);
[...]
In one microbenchmark from libjpeg-turbo this accounts for a 2.5% to 4%
performance difference.
We could teach the compiler to recover the lane variants, but this would likely
require its own pass. (Alternatively, "volatile" could be used on the constants
vector, but this is a bit ugly.)
This patch instead implements the following LLVM IR intrinsics for AArch64 to
maintain the original structure through IR optmization and into instruction
selection:
- sqdmulh_lane
- sqdmulh_laneq
- sqrdmulh_lane
- sqrdmulh_laneq.
These 'lane' variants need an additional register class. The second argument
must be in the lower half of the 64-bit NEON register file, but only when
operating on i16 elements.
Note that the existing patterns for shufflevector and sqdmulh into sqdmulh_lane
(etc.) remain, so code that does not rely on NEON intrinsics to generate these
instructions is not affected.
This patch also changes clang to emit these IR intrinsics for the corresponding
NEON intrinsics (AArch64 only).
Reviewers: SjoerdMeijer, dmgreen, t.p.northover, rovka, rengolin, efriedma
Reviewed By: efriedma
Subscribers: kristof.beyls, hiraditya, jdoerfert, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D71469
Added:
Modified:
clang/include/clang/Basic/arm_neon.td
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/aarch64-neon-2velem.c
llvm/include/llvm/IR/IntrinsicsAArch64.td
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
llvm/lib/Target/AArch64/AArch64RegisterInfo.td
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll
Removed:
diff --git a/clang/include/clang/Basic/arm_neon.td
b/clang/include/clang/Basic/arm_neon.td
index a4dc21b64311..380a2a0a5fa6 100644
--- a/clang/include/clang/Basic/arm_neon.td
+++ b/clang/include/clang/Basic/arm_neon.td
@@ -528,9 +528,16 @@ def VMULL_LANE: SOpInst<"vmull_lane", "(>Q)..I",
"siUsUi", OP_MULL_LN>;
def VQDMULL_N : SOpInst<"vqdmull_n", "(>Q).1", "si", OP_QDMULL_N>;
def VQDMULL_LANE : SOpInst<"vqdmull_lane", "(>Q)..I", "si", OP_QDMULL_LN>;
def VQDMULH_N : SOpInst<"vqdmulh_n", "..1", "siQsQi", OP_QDMULH_N>;
-def VQDMULH_LANE : SOpInst<"vqdmulh_lane", "..qI", "siQsQi", OP_QDMULH_LN>;
def VQRDMULH_N: SOpInst<"vqrdmulh_n", "..1", "siQsQi", OP_QRDMULH_N>;
+
+let ArchGuard = "!defined(__aarch64__)" in {
+def VQDMULH_LANE : SOpInst<"vqdmulh_lane", "..qI", "siQsQi", OP_QDMULH_LN>;
def VQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "..qI", "siQsQi", OP_QRDMULH_LN>;
+}
+let ArchGuard = "defined(__aarch64__)" in {
+def A64_VQDMULH_LANE : SInst<"vqdmulh_lane", "..qI", "siQsQi">;
+def A64_VQRDMULH_LANE : SInst<"vqrdmulh_lane", "..qI", "siQsQi">;
+}
let ArchGuard = "defined(__ARM_FEATURE_QRDMX)" in {
def VQRDMLAH_LANE : SOpInst<"vqrdmlah_lane", "...qI", "siQsQi", OP_QRDMLAH_LN>;
@@ -951,9 +958,10 @@ def VQDMULL_HIGH_LANE : SOpInst<"vqdmull_high_lane",
"(>Q)Q.I", "si",
def VQDMULL_HIGH_LANEQ : SOpInst<"vqdmull_high_laneq", "(>Q)QQI", "si",
OP_QDMULLHi_LN>;
-def VQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "..QI", "siQsQi", OP_QDMULH_LN>;
-def VQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "..QI", "siQsQi",
OP_QRDMULH_LN>;
-
+let isLaneQ = 1 in {
+def VQDMULH_LANEQ : SInst<"vqdmulh_laneq", "..QI", "siQsQi">;
+def VQRDMULH_LANEQ : SInst<"vqrdmulh_laneq", "..QI", "siQsQi">;
+}
let ArchGuard = "defi
r298850 - [ARM] Add a driver option for +no-neg-immediates
Author: sanwou01
Date: Mon Mar 27 10:34:52 2017
New Revision: 298850
URL: http://llvm.org/viewvc/llvm-project?rev=298850&view=rev
Log:
[ARM] Add a driver option for +no-neg-immediates
Reviewers: olista01, rengolin, javed.absar, samparker
Reviewed By: samparker
Subscribers: samparker, llvm-commits, aemerson
Differential Revision: https://reviews.llvm.org/D31197
Added:
cfe/trunk/test/Driver/arm-no-neg-immediates.c
Modified:
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Driver/ToolChains/Arch/AArch64.cpp
cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp
Modified: cfe/trunk/include/clang/Driver/Options.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=298850&r1=298849&r2=298850&view=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Mon Mar 27 10:34:52 2017
@@ -1760,6 +1760,8 @@ def mcrc : Flag<["-"], "mcrc">, Group;
def mnocrc : Flag<["-"], "mnocrc">, Group,
HelpText<"Disallow use of CRC instructions (ARM only)">;
+def mno_neg_immediates: Flag<["-"], "mno-neg-immediates">,
Group,
+ HelpText<"Disallow converting instructions with negative immediates to their
negation or inversion.">;
def mgeneral_regs_only : Flag<["-"], "mgeneral-regs-only">,
Group,
HelpText<"Generate code which only uses the general purpose registers
(AArch64 only)">;
Modified: cfe/trunk/lib/Driver/ToolChains/Arch/AArch64.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Arch/AArch64.cpp?rev=298850&r1=298849&r2=298850&view=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Arch/AArch64.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Arch/AArch64.cpp Mon Mar 27 10:34:52 2017
@@ -193,4 +193,7 @@ void aarch64::getAArch64TargetFeatures(c
if (Args.hasArg(options::OPT_ffixed_x18))
Features.push_back("+reserve-x18");
+
+ if (Args.hasArg(options::OPT_mno_neg_immediates))
+Features.push_back("+no-neg-immediates");
}
Modified: cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp?rev=298850&r1=298849&r2=298850&view=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp Mon Mar 27 10:34:52 2017
@@ -449,6 +449,9 @@ void arm::getARMTargetFeatures(const Too
// The kext linker doesn't know how to deal with movw/movt.
if (KernelOrKext || Args.hasArg(options::OPT_mno_movt))
Features.push_back("+no-movt");
+
+ if (Args.hasArg(options::OPT_mno_neg_immediates))
+Features.push_back("+no-neg-immediates");
}
const std::string arm::getARMArch(StringRef Arch, const llvm::Triple &Triple) {
Added: cfe/trunk/test/Driver/arm-no-neg-immediates.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/arm-no-neg-immediates.c?rev=298850&view=auto
==
--- cfe/trunk/test/Driver/arm-no-neg-immediates.c (added)
+++ cfe/trunk/test/Driver/arm-no-neg-immediates.c Mon Mar 27 10:34:52 2017
@@ -0,0 +1,8 @@
+// RUN: %clang -target arm-none-gnueabi -### %s 2>&1 | FileCheck %s
--check-prefix=CHECK-DEFAULT
+// RUN: %clang -target arm-none-gnueabi -mno-neg-immediates -### %s 2>&1 |
FileCheck %s
+
+// RUN: %clang -target aarch64-none-gnueabi -### %s 2>&1 | FileCheck %s
--check-prefix=CHECK-DEFAULT
+// RUN: %clang -target aarch64-none-gnueabi -mno-neg-immediates -### %s 2>&1 |
FileCheck %s
+
+// CHECK: "-target-feature" "+no-neg-immediates"
+// CHECK-DEFAULT-NOT: "+no-neg-immediates"
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r299754 - Skip Unicode character expansion in assembly files
Author: sanwou01
Date: Fri Apr 7 05:13:00 2017
New Revision: 299754
URL: http://llvm.org/viewvc/llvm-project?rev=299754&view=rev
Log:
Skip Unicode character expansion in assembly files
Summary: When using the C preprocessor with assembly files, either with a
capital `S` file extension, or with `-xassembler-with-cpp`, the Unicode escape
sequence `\u` is ignored. The `\u` pattern can be used for expanding a macro
argument that starts with `u`.
Author: Salman Arif
Reviewers: rengolin, olista01
Reviewed By: olista01
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D31765
Added:
cfe/trunk/test/Lexer/asm-preproc-no-unicode.s
Modified:
cfe/trunk/lib/Lex/Lexer.cpp
Modified: cfe/trunk/lib/Lex/Lexer.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Lex/Lexer.cpp?rev=299754&r1=299753&r2=299754&view=diff
==
--- cfe/trunk/lib/Lex/Lexer.cpp (original)
+++ cfe/trunk/lib/Lex/Lexer.cpp Fri Apr 7 05:13:00 2017
@@ -3603,17 +3603,19 @@ LexNextToken:
// UCNs (C99 6.4.3, C++11 [lex.charset]p2)
case '\\':
-if (uint32_t CodePoint = tryReadUCN(CurPtr, BufferPtr, &Result)) {
- if (CheckUnicodeWhitespace(Result, CodePoint, CurPtr)) {
-if (SkipWhitespace(Result, CurPtr, TokAtPhysicalStartOfLine))
- return true; // KeepWhitespaceMode
+if (!LangOpts.AsmPreprocessor) {
+ if (uint32_t CodePoint = tryReadUCN(CurPtr, BufferPtr, &Result)) {
+if (CheckUnicodeWhitespace(Result, CodePoint, CurPtr)) {
+ if (SkipWhitespace(Result, CurPtr, TokAtPhysicalStartOfLine))
+return true; // KeepWhitespaceMode
-// We only saw whitespace, so just try again with this lexer.
-// (We manually eliminate the tail call to avoid recursion.)
-goto LexNextToken;
- }
+ // We only saw whitespace, so just try again with this lexer.
+ // (We manually eliminate the tail call to avoid recursion.)
+ goto LexNextToken;
+}
- return LexUnicode(Result, CodePoint, CurPtr);
+return LexUnicode(Result, CodePoint, CurPtr);
+ }
}
Kind = tok::unknown;
Added: cfe/trunk/test/Lexer/asm-preproc-no-unicode.s
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Lexer/asm-preproc-no-unicode.s?rev=299754&view=auto
==
--- cfe/trunk/test/Lexer/asm-preproc-no-unicode.s (added)
+++ cfe/trunk/test/Lexer/asm-preproc-no-unicode.s Fri Apr 7 05:13:00 2017
@@ -0,0 +1,8 @@
+// RUN: %clang -E -xassembler-with-cpp %s -o - 2>&1 | FileCheck %s
+
+// CHECK-NOT: warning: \u used with no following hex digits
+// CHECK: .word \u
+
+.macro foo, u
+.word \u
+.endm
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r295647 - [ARM] Add regression tests for Cortex-M23 and Cortex-M33
Author: sanwou01
Date: Mon Feb 20 04:37:01 2017
New Revision: 295647
URL: http://llvm.org/viewvc/llvm-project?rev=295647&view=rev
Log:
[ARM] Add regression tests for Cortex-M23 and Cortex-M33
Reviewers: rengolin, t.p.northover
Reviewed By: t.p.northover
Subscribers: aemerson, llvm-commits
Differential Revision: https://reviews.llvm.org/D30100
Modified:
cfe/trunk/test/Driver/arm-cortex-cpus.c
cfe/trunk/test/Preprocessor/arm-target-features.c
Modified: cfe/trunk/test/Driver/arm-cortex-cpus.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/arm-cortex-cpus.c?rev=295647&r1=295646&r2=295647&view=diff
==
--- cfe/trunk/test/Driver/arm-cortex-cpus.c (original)
+++ cfe/trunk/test/Driver/arm-cortex-cpus.c Mon Feb 20 04:37:01 2017
@@ -579,6 +579,12 @@
// CHECK-CORTEX-A73-SOFT: "-target-feature" "+soft-float"
// CHECK-CORTEX-A73-SOFT: "-target-feature" "+soft-float-abi"
+// RUN: %clang -target arm -mcpu=cortex-m23 -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-CPUV8MBASE %s
+// CHECK-CPUV8MBASE: "-cc1"{{.*}} "-triple" "thumbv8m.base-
+
+// RUN: %clang -target arm -mcpu=cortex-m33 -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-CPUV8MMAIN %s
+// CHECK-CPUV8MMAIN: "-cc1"{{.*}} "-triple" "thumbv8m.main-
+
// == Check whether -mcpu accepts mixed-case values.
// RUN: %clang -target arm-linux-gnueabi -mcpu=Cortex-a5 -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-CASE-INSENSITIVE-CPUV7A %s
// RUN: %clang -target arm-linux-gnueabi -mcpu=cortex-A7 -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-CASE-INSENSITIVE-CPUV7A %s
Modified: cfe/trunk/test/Preprocessor/arm-target-features.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Preprocessor/arm-target-features.c?rev=295647&r1=295646&r2=295647&view=diff
==
--- cfe/trunk/test/Preprocessor/arm-target-features.c (original)
+++ cfe/trunk/test/Preprocessor/arm-target-features.c Mon Feb 20 04:37:01 2017
@@ -398,6 +398,31 @@
// M7-THUMB:#define __ARM_FP 0xE
// M7-THUMB:#define __ARM_FPV5__ 1
+// Test whether predefines are as expected when targeting v8m cores
+// RUN: %clang -target arm -mcpu=cortex-m23 -x c -E -dM %s -o - | FileCheck
-match-full-lines --check-prefix=M23 %s
+// M23: #define __ARM_ARCH 8
+// M23: #define __ARM_ARCH_8M_BASE__ 1
+// M23: #define __ARM_ARCH_EXT_IDIV__ 1
+// M23-NOT: __ARM_ARCH_ISA_ARM
+// M23: #define __ARM_ARCH_ISA_THUMB 1
+// M23: #define __ARM_ARCH_PROFILE 'M'
+// M23-NOT: __ARM_FEATURE_CRC32
+// M23-NOT: __ARM_FEATURE_DSP
+// M23-NOT: __ARM_FP 0x{{.*}}
+// M23-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+
+// RUN: %clang -target arm -mcpu=cortex-m33 -x c -E -dM %s -o - | FileCheck
-match-full-lines --check-prefix=M33 %s
+// M33: #define __ARM_ARCH 8
+// M33: #define __ARM_ARCH_8M_MAIN__ 1
+// M33: #define __ARM_ARCH_EXT_IDIV__ 1
+// M33-NOT: __ARM_ARCH_ISA_ARM
+// M33: #define __ARM_ARCH_ISA_THUMB 2
+// M33: #define __ARM_ARCH_PROFILE 'M'
+// M33-NOT: __ARM_FEATURE_CRC32
+// M33: #define __ARM_FEATURE_DSP 1
+// M33: #define __ARM_FP 0x6
+// M33: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
+
// Test whether predefines are as expected when targeting krait.
// RUN: %clang -target armv7 -mcpu=krait -x c -E -dM %s -o - | FileCheck
-match-full-lines --check-prefix=KRAIT %s
// RUN: %clang -target armv7 -mthumb -mcpu=krait -x c -E -dM %s -o - |
FileCheck -match-full-lines --check-prefix=KRAIT %s
___
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