[PATCH] D128288: [PowerPC] Fix signatures for vec_replace_unaligned builtin

[Quinn Pham via Phabricator via cfe-commits]

quinnp accepted this revision.
quinnp added a comment.
This revision is now accepted and ready to land.

LGTM. Thanks!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128288/new/

https://reviews.llvm.org/D128288

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15208
-  for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
-if (E->getArg(i)->getType()->isArrayType())
-  Ops.push_back(EmitArrayToPointerDecay(E->getArg(i)).getPointer());

amyk wrote:
> A question I have is do we not need to consider 
> this/`EmitArrayToPointerDecay()` anymore? Was this not used for anything?
Thanks for your comment! I could not find any builtins that used this case in 
the loop for emitting their arguments and did not see any failures when I 
removed it. I am going to look into this now and verify whether or not this is 
needed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121637/new/

https://reviews.llvm.org/D121637

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 419126.
quinnp added a comment.

Moving testcases that require code generation from 
`clang/test/Sema/ppc-pair-mma-types.c` to 
`clang/test/CodeGen/PowerPC/ppc-mma-types.c` and 
`clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c`. This is because 
some of these tests use the line 
`Ops.push_back(EmitArrayToPointerDecay(E->getArg(i)).getPointer());` which I 
initially removed from EmitPPCbuiltinExpr. I have added this back in the switch 
statement where it is needed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121637/new/

https://reviews.llvm.org/D121637

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c
  clang/test/CodeGen/PowerPC/builtins-ppc-int128.c
  clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cas.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fetch.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
  clang/test/CodeGen/PowerPC/ppc-mma-types.c
  clang/test/Sema/ppc-pair-mma-types.c

Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -12,11 +12,6 @@
 
 // typedef
 typedef __vector_quad vq_t;
-void testVQTypedef(int *inp, int *outp) {
-  vq_t *vqin = (vq_t *)inp;
-  vq_t *vqout = (vq_t *)outp;
-  *vqout = *vqin;
-}
 
 // function argument
 void testVQArg1(__vector_quad vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
@@ -29,57 +24,22 @@
   *vqp = vq;
 }
 
-void testVQArg3(__vector_quad *vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
-void testVQArg4(const __vector_quad *const vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
-void testVQArg5(__vector_quad vqa[], int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = vqa[0];
-}
-
 void testVQArg6(const vq_t vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   *vqp = vq;
 }
 
-void testVQArg7(const vq_t *vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
 // function return
 __vector_quad testVQRet1(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   return *vqp; // expected-error {{invalid use of PPC MMA type}}
 }
 
-__vector_quad *testVQRet2(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
-const __vector_quad *testVQRet3(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
 const vq_t testVQRet4(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   return *vqp; // expected-error {{invalid use of PPC MMA type}}
 }
 
-const vq_t *testVQRet5(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
 // global
 __vector_quad globalvq;// expected-error {{invalid use of PPC MMA type}}
 const __vector_quad globalvq2; // expected-error {{invalid use of PPC MMA type}}
@@ -87,16 +47,6 @@
 const __vector_quad *const globalvqp2;
 vq_t globalvq_t; // expected-error {{invalid use of PPC MMA type}}
 
-// local
-void testVQLocal(int *ptr, vector unsigned char vc) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  __vector_quad vq1 = *vqp;
-  __vector_quad vq2;
-  __builtin_mma_xxsetaccz(&vq2);
-  __vector_quad vq3;
-  __builtin_mma_xvi4ger8(&vq3, vc, vc);
-  *vqp = vq3;
-}
 
 // struct field
 struct TestVQStruct {
@@ -106,17 +56,6 @@
   __vector_quad *vq;
 };
 
-// sizeof / alignof
-int testVQSizeofAlignof(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  __vector_quad vq = *vqp;
-  unsigned sizet = sizeof(__vector_quad);
-  unsigned alignt = __alignof__(__vector_quad);
-  unsigned sizev = sizeof(vq);
-  unsigned alignv = __alignof__(vq);
-  return sizet + alignt + sizev + alignv;
-}
-
 // operators
 int testVQOperators1(int *ptr) {
   __vector_quad *vqp = (__vector_quad *)ptr;
@@ -168,11 +107,6 @@
 
 // typedef
 typedef __vector_pair vp_t;
-void testVPTypedef(int *inp, int *outp) {
-  vp_t *vpin = (vp_t *)inp;
-  vp_t *vpout = (vp_t *)outp;
-  *vpout = *vpin;
-}
 
 // function argument
 void testVPArg1(__vector_pair vp, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
@@ -185,57 +119,22 @@
   *vpp = vp;
 }
 
-void testVPArg3(__vector_pair *vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
-void testVPArg4(const __vector_pair *const vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
-void testVPArg5(__vector_pair v

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp marked an inline comment as done.
quinnp added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15208
-  for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
-if (E->getArg(i)->getType()->isArrayType())
-  Ops.push_back(EmitArrayToPointerDecay(E->getArg(i)).getPointer());

quinnp wrote:
> amyk wrote:
> > A question I have is do we not need to consider 
> > this/`EmitArrayToPointerDecay()` anymore? Was this not used for anything?
> Thanks for your comment! I could not find any builtins that used this case in 
> the loop for emitting their arguments and did not see any failures when I 
> removed it. I am going to look into this now and verify whether or not this 
> is needed.
I've updated the patch to include `EmitArrayToPointerDecay()` where it is 
needed and add code generation testcases to test this functionality.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121637/new/

https://reviews.llvm.org/D121637

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 448016.
quinnp marked 5 inline comments as done.
quinnp added a comment.

Addressing review comments: fixing test cases and improving test case clarity.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129401/new/

https://reviews.llvm.org/D129401

Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/function-sections.c
  clang/test/Driver/gold-lto-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,20 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   g O .bss.var [[#%x,]] var
+
+; CHECK-NO-DATA-SECTIONS:  g O .bss [[#%x,]] var
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,20 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK-NOT:   g O .data (csect: .data) [[#%x,]] var
+
+; CHECK-NO-DATA-SECTIONS:  g O .data (csect: .data) [[#%x,]] var
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,11 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default to match the behaviour of lld and gold plugin.
+  if (!codegen::getExplicitDataSections())
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/gold-lto-sections.c
===
--- clang/test/Driver/gold-lto-sections.c
+++ /dev/null
@@ -1,8 +0,0 @@
-// RUN: touch %t.o
-//
-// RUN: %clang -target x86_64-unknown-linux -### %t.o -flto 2>&1 \
-// RUN: -Wl,-plugin-opt=foo -O3 \
-// RUN: -ffunction-sections -fdata-sections \
-// RUN: | FileCheck %s
-// CHECK: "-plugin-opt=-function-sections"
-// CHECK: "-plugin-opt=-data-sections"
Index: clang/test/Driver/function-sections.c
===
--- clang/test/Driver/function-sections.c
+++ clang/test/Driver/function-sections.c
@@ -6,6 +6,12 @@
 // CHECK-NODS-NOT: -fdata-sections
 // CHECK-US-NOT: -fno-unique-section-names
 // CHECK-NOUS: -fno-unique-section-names
+// CHECK-PLUGIN-DEFAULT-NOT: "-plugin-opt=-function-sections
+// CHECK-PLUGIN-DEFAULT-NOT: "-plugin-opt=-data-sections
+// CHECK-PLUGIN-SECTIONS: "-plugin-opt=-function-sections=1"
+// CHECK-PLUGIN-SECTIONS: "-plugin-opt=-data-sections=1"
+// CHECK-PLUGIN-NO-SECTIONS: "-plugin-opt=-function-sections=0"
+// CHECK-PLUGIN-NO-SECTIONS: "-plugin-opt=-data-sections=0"
 
 // RUN: %clang -### %s -fsyntax-only 2>&1   \
 // RUN: --target=i386-unknown-linux \
@@ -72,3 +78,18 @@
 // RUN: --target=i386-unknown-linux \
 // RUN: -fno-unique-section-names \
 // RUN:   | FileCheck --check-prefix=CHECK-NOUS %s
+
+
+// RUN: %clang -### %s -flto 2>&1\
+// RUN: --target=x86_64-unknown-linux \
+// RUN:   | FileCheck --check-prefix=

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO.

[Quinn Pham via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf565444b486d: [libLTO] Set data-sections by default in 
libLTO. (authored by quinnp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129401/new/

https://reviews.llvm.org/D129401

Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/function-sections.c
  clang/test/Driver/gold-lto-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,20 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   g O .bss.var [[#%x,]] var
+
+; CHECK-NO-DATA-SECTIONS:  g O .bss [[#%x,]] var
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,20 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK-NOT:   g O .data (csect: .data) [[#%x,]] var
+
+; CHECK-NO-DATA-SECTIONS:  g O .data (csect: .data) [[#%x,]] var
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,11 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default to match the behaviour of lld and gold plugin.
+  if (!codegen::getExplicitDataSections())
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/gold-lto-sections.c
===
--- clang/test/Driver/gold-lto-sections.c
+++ /dev/null
@@ -1,8 +0,0 @@
-// RUN: touch %t.o
-//
-// RUN: %clang -target x86_64-unknown-linux -### %t.o -flto 2>&1 \
-// RUN: -Wl,-plugin-opt=foo -O3 \
-// RUN: -ffunction-sections -fdata-sections \
-// RUN: | FileCheck %s
-// CHECK: "-plugin-opt=-function-sections"
-// CHECK: "-plugin-opt=-data-sections"
Index: clang/test/Driver/function-sections.c
===
--- clang/test/Driver/function-sections.c
+++ clang/test/Driver/function-sections.c
@@ -6,6 +6,12 @@
 // CHECK-NODS-NOT: -fdata-sections
 // CHECK-US-NOT: -fno-unique-section-names
 // CHECK-NOUS: -fno-unique-section-names
+// CHECK-PLUGIN-DEFAULT-NOT: "-plugin-opt=-function-sections
+// CHECK-PLUGIN-DEFAULT-NOT: "-plugin-opt=-data-sections
+// CHECK-PLUGIN-SECTIONS: "-plugin-opt=-function-sections=1"
+// CHECK-PLUGIN-SECTIONS: "-plugin-opt=-data-sections=1"
+// CHECK-PLUGIN-NO-SECTIONS: "-plugin-opt=-function-sections=0"
+// CHECK-PLUGIN-NO-SECTIONS: "-plugin-opt=-data-sections=0"
 
 // RUN: %clang -### %s -fsyntax-only 2>&1   \
 // RUN: --target=i386-unknown-linux \
@@ -72,3 +78,18 @@
 // RUN: --target=i386-unknown-linux \
 // RUN: -fno-unique-section-names \
 // RUN:   | FileCheck --check-prefix=CHECK-NOUS %s
+
+
+// RUN: %clang -### %s -flto 2>&1\
+// RUN: --target=x86_64-unknown-li

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 448036.
quinnp added a comment.

Adding lit config to mark tests as unsupported for non PPC targets.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129401/new/

https://reviews.llvm.org/D129401

Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/function-sections.c
  clang/test/Driver/gold-lto-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll
  llvm/test/LTO/PowerPC/lit.local.cfg

Index: llvm/test/LTO/PowerPC/lit.local.cfg
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'PowerPC' in config.root.targets:
+  config.unsupported = True
Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,20 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   g O .bss.var [[#%x,]] var
+
+; CHECK-NO-DATA-SECTIONS:  g O .bss [[#%x,]] var
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,20 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK-NOT:   g O .data (csect: .data) [[#%x,]] var
+
+; CHECK-NO-DATA-SECTIONS:  g O .data (csect: .data) [[#%x,]] var
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,11 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default to match the behaviour of lld and gold plugin.
+  if (!codegen::getExplicitDataSections())
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/gold-lto-sections.c
===
--- clang/test/Driver/gold-lto-sections.c
+++ /dev/null
@@ -1,8 +0,0 @@
-// RUN: touch %t.o
-//
-// RUN: %clang -target x86_64-unknown-linux -### %t.o -flto 2>&1 \
-// RUN: -Wl,-plugin-opt=foo -O3 \
-// RUN: -ffunction-sections -fdata-sections \
-// RUN: | FileCheck %s
-// CHECK: "-plugin-opt=-function-sections"
-// CHECK: "-plugin-opt=-data-sections"
Index: clang/test/Driver/function-sections.c
===
--- clang/test/Driver/function-sections.c
+++ clang/test/Driver/function-sections.c
@@ -6,6 +6,12 @@
 // CHECK-NODS-NOT: -fdata-sections
 // CHECK-US-NOT: -fno-unique-section-names
 // CHECK-NOUS: -fno-unique-section-names
+// CHECK-PLUGIN-DEFAULT-NOT: "-plugin-opt=-function-sections
+// CHECK-PLUGIN-DEFAULT-NOT: "-plugin-opt=-data-sections
+// CHECK-PLUGIN-SECTIONS: "-plugin-opt=-function-sections=1"
+// CHECK-PLUGIN-SECTIONS: "-plugin-opt=-data-sections=1"
+// CHECK-PLUGIN-NO-SECTIONS: "-plugin-opt=-function-sections=0"
+// CHECK-PLUGIN-NO-SECTIONS: "-plugin-opt=-data-sections=0"
 
 // RUN: %clang -### %s -fsyntax-only 2>&1   \
 // RUN: --target=i386-unknown-linux \
@@ -72,3 +78,18 @@
 // RUN: --target=i386-unknown-li

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO.

[Quinn Pham via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb6cc5ddc9478: [libLTO] Set data-sections by default in 
libLTO. (authored by quinnp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129401/new/

https://reviews.llvm.org/D129401

Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/function-sections.c
  clang/test/Driver/gold-lto-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll
  llvm/test/LTO/PowerPC/lit.local.cfg

Index: llvm/test/LTO/PowerPC/lit.local.cfg
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'PowerPC' in config.root.targets:
+  config.unsupported = True
Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,20 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   g O .bss.var [[#%x,]] var
+
+; CHECK-NO-DATA-SECTIONS:  g O .bss [[#%x,]] var
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,20 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK-NOT:   g O .data (csect: .data) [[#%x,]] var
+
+; CHECK-NO-DATA-SECTIONS:  g O .data (csect: .data) [[#%x,]] var
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,11 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default to match the behaviour of lld and gold plugin.
+  if (!codegen::getExplicitDataSections())
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/gold-lto-sections.c
===
--- clang/test/Driver/gold-lto-sections.c
+++ /dev/null
@@ -1,8 +0,0 @@
-// RUN: touch %t.o
-//
-// RUN: %clang -target x86_64-unknown-linux -### %t.o -flto 2>&1 \
-// RUN: -Wl,-plugin-opt=foo -O3 \
-// RUN: -ffunction-sections -fdata-sections \
-// RUN: | FileCheck %s
-// CHECK: "-plugin-opt=-function-sections"
-// CHECK: "-plugin-opt=-data-sections"
Index: clang/test/Driver/function-sections.c
===
--- clang/test/Driver/function-sections.c
+++ clang/test/Driver/function-sections.c
@@ -6,6 +6,12 @@
 // CHECK-NODS-NOT: -fdata-sections
 // CHECK-US-NOT: -fno-unique-section-names
 // CHECK-NOUS: -fno-unique-section-names
+// CHECK-PLUGIN-DEFAULT-NOT: "-plugin-opt=-function-sections
+// CHECK-PLUGIN-DEFAULT-NOT: "-plugin-opt=-data-sections
+// CHECK-PLUGIN-SECTIONS: "-plugin-opt=-function-sections=1"
+// CHECK-PLUGIN-SECTIONS: "-plugin-opt=-data-sections=1"
+// CHECK-PLUGIN-NO-SECTIONS: "-plugin-opt=-function-sections=0"
+// CHECK-PLUGIN-NO-SECTIONS: "-plugin-opt=-data-sections=0"
 
 // RUN: %clang -### %s -fsyntax-only 2>&1   \
 //

[PATCH] D105834: [PowerPC] Semachecking for XL compat builtin icbt

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 359077.
quinnp added a comment.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Removing some FIXME comments and tests that are handled elsewhere with 
semachecking.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105834/new/

https://reviews.llvm.org/D105834

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
  clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
@@ -94,7 +94,6 @@
 }
 declare void @llvm.ppc.iospace.sync()
 
-; FIXME: __icbt is only valid for pwr8 and up.
 define dso_local void @test_builtin_ppc_icbt() {
 ; CHECK-LABEL: test_builtin_ppc_icbt:
 ; CHECK:   # %bb.0: # %entry
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
@@ -15,6 +15,7 @@
 
 define dso_local void @test_builtin_ppc_eieio() {
 ; CHECK-LABEL: test_builtin_ppc_eieio:
+1
 ; CHECK:   # %bb.0: # %entry
 ; CHECK-NEXT:ori 2, 2, 0
 ; CHECK-NEXT:ori 2, 2, 0
@@ -60,18 +61,3 @@
   ret void
 }
 declare void @llvm.ppc.iospace.sync()
-
-; FIXME: __icbt is only valid for pwr8 and up.
-define dso_local void @test_builtin_ppc_icbt() {
-; CHECK-LABEL: test_builtin_ppc_icbt:
-; CHECK:   # %bb.0: # %entry
-; CHECK-NEXT:lwz 3, -8(1)
-; CHECK-NEXT:icbt 0, 0, 3
-; CHECK-NEXT:blr
-entry:
-  %a = alloca i8*, align 8
-  %0 = load i8*, i8** %a, align 8
-  call void @llvm.ppc.icbt(i8* %0)
-  ret void
-}
-declare void @llvm.ppc.icbt(i8*)
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1534,7 +1534,6 @@
 [IntrArgMemOnly, NoCapture>]>;
   def int_ppc_dcbz  : GCCBuiltin<"__builtin_ppc_dcbz">,
   Intrinsic<[], [llvm_ptr_ty], []>;
-// FIXME: __icbt is only valid for pwr8 and up.
   def int_ppc_icbt : GCCBuiltin<"__builtin_ppc_icbt">,
  Intrinsic<[], [llvm_ptr_ty], []>;
   
Index: clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
@@ -224,23 +224,6 @@
   __dcbz(c);
 }
 
-// FIXME: __icbt is only valid for pwr8 and up.
-// CHECK-LABEL: @test_icbt(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = load i8*, i8** @c, align 8
-// CHECK-NEXT:call void @llvm.ppc.icbt(i8* [[TMP0]])
-// CHECK-NEXT:ret void
-//
-// CHECK-32-LABEL: @test_icbt(
-// CHECK-32-NEXT:  entry:
-// CHECK-32-NEXT:[[TMP0:%.*]] = load i8*, i8** @c, align 4
-// CHECK-32-NEXT:call void @llvm.ppc.icbt(i8* [[TMP0]])
-// CHECK-32-NEXT:ret void
-//
-void test_icbt() {
-  __icbt(c);
-}
-
 // CHECK-LABEL: @test_builtin_ppc_popcntb(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = load i64, i64* @a, align 8
@@ -452,20 +435,3 @@
 void test_builtin_ppc_dcbz() {
   __builtin_ppc_dcbz(c);
 }
-
-// FIXME: __icbt is only valid for pwr8 and up.
-// CHECK-LABEL: @test_builtin_ppc_icbt(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = load i8*, i8** @c, align 8
-// CHECK-NEXT:call void @llvm.ppc.icbt(i8* [[TMP0]])
-// CHECK-NEXT:ret void
-//
-// CHECK-32-LABEL: @test_builtin_ppc_icbt(
-// CHECK-32-NEXT:  entry:
-// CHECK-32-NEXT:[[TMP0:%.*]] = load i8*, i8** @c, align 4
-// CHECK-32-NEXT:call void @llvm.ppc.icbt(i8* [[TMP0]])
-// CHECK-32-NEXT:ret void
-//
-void test_builtin_ppc_icbt() {
-  __builtin_ppc_icbt(c);
-}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
@@ -0,0 +1,32 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s -check-prefix=CHECK-PWR8
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s -check-prefix=CHECK-PWR8
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s -check-prefix=CHECK-PWR8
+// RUN: %clang_cc1 -triple powerpc-unknown-aix %s -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s -check-prefix=CHECK-PWR8
+// RUN:

[PATCH] D105834: [PowerPC] Semachecking for XL compat builtin icbt

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 359079.
quinnp added a comment.

Typo.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105834/new/

https://reviews.llvm.org/D105834

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
  clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
@@ -94,7 +94,6 @@
 }
 declare void @llvm.ppc.iospace.sync()
 
-; FIXME: __icbt is only valid for pwr8 and up.
 define dso_local void @test_builtin_ppc_icbt() {
 ; CHECK-LABEL: test_builtin_ppc_icbt:
 ; CHECK:   # %bb.0: # %entry
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
@@ -60,18 +60,3 @@
   ret void
 }
 declare void @llvm.ppc.iospace.sync()
-
-; FIXME: __icbt is only valid for pwr8 and up.
-define dso_local void @test_builtin_ppc_icbt() {
-; CHECK-LABEL: test_builtin_ppc_icbt:
-; CHECK:   # %bb.0: # %entry
-; CHECK-NEXT:lwz 3, -8(1)
-; CHECK-NEXT:icbt 0, 0, 3
-; CHECK-NEXT:blr
-entry:
-  %a = alloca i8*, align 8
-  %0 = load i8*, i8** %a, align 8
-  call void @llvm.ppc.icbt(i8* %0)
-  ret void
-}
-declare void @llvm.ppc.icbt(i8*)
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1534,7 +1534,6 @@
 [IntrArgMemOnly, NoCapture>]>;
   def int_ppc_dcbz  : GCCBuiltin<"__builtin_ppc_dcbz">,
   Intrinsic<[], [llvm_ptr_ty], []>;
-// FIXME: __icbt is only valid for pwr8 and up.
   def int_ppc_icbt : GCCBuiltin<"__builtin_ppc_icbt">,
  Intrinsic<[], [llvm_ptr_ty], []>;
   
Index: clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
@@ -224,23 +224,6 @@
   __dcbz(c);
 }
 
-// FIXME: __icbt is only valid for pwr8 and up.
-// CHECK-LABEL: @test_icbt(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = load i8*, i8** @c, align 8
-// CHECK-NEXT:call void @llvm.ppc.icbt(i8* [[TMP0]])
-// CHECK-NEXT:ret void
-//
-// CHECK-32-LABEL: @test_icbt(
-// CHECK-32-NEXT:  entry:
-// CHECK-32-NEXT:[[TMP0:%.*]] = load i8*, i8** @c, align 4
-// CHECK-32-NEXT:call void @llvm.ppc.icbt(i8* [[TMP0]])
-// CHECK-32-NEXT:ret void
-//
-void test_icbt() {
-  __icbt(c);
-}
-
 // CHECK-LABEL: @test_builtin_ppc_popcntb(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = load i64, i64* @a, align 8
@@ -452,20 +435,3 @@
 void test_builtin_ppc_dcbz() {
   __builtin_ppc_dcbz(c);
 }
-
-// FIXME: __icbt is only valid for pwr8 and up.
-// CHECK-LABEL: @test_builtin_ppc_icbt(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = load i8*, i8** @c, align 8
-// CHECK-NEXT:call void @llvm.ppc.icbt(i8* [[TMP0]])
-// CHECK-NEXT:ret void
-//
-// CHECK-32-LABEL: @test_builtin_ppc_icbt(
-// CHECK-32-NEXT:  entry:
-// CHECK-32-NEXT:[[TMP0:%.*]] = load i8*, i8** @c, align 4
-// CHECK-32-NEXT:call void @llvm.ppc.icbt(i8* [[TMP0]])
-// CHECK-32-NEXT:ret void
-//
-void test_builtin_ppc_icbt() {
-  __builtin_ppc_icbt(c);
-}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
@@ -0,0 +1,32 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s -check-prefix=CHECK-PWR8
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s -check-prefix=CHECK-PWR8
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s -check-prefix=CHECK-PWR8
+// RUN: %clang_cc1 -triple powerpc-unknown-aix %s -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s -check-prefix=CHECK-PWR8
+// RUN: not %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm %s \
+// RUN:   -target-cpu pwr7 2>&1 | FileCheck %s -check-prefix=CHECK-NOPWR8
+// RUN: not %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm %s \
+// RUN:   -target-cpu pwr7 2>&1 | FileCheck %s -check-prefix=CHECK-NOPWR8
+// RUN: not %clang_cc1 -triple powerpc-unknown-aix %s -emit-llvm %s \
+/

[PATCH] D105834: [PowerPC] Semachecking for XL compat builtin icbt

[Quinn Pham via Phabricator via cfe-commits]

quinnp added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c:1
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s -check-prefix=CHECK-PWR8

nemanjai wrote:
> Oh, I believe you're missing `REQUIRES: powerpc-registered-target` in this 
> test case (please look at the requirements in the other builtins tests).
I don't think I need `REQUIRES: powerpc-registered-target`, I am copying 
`clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c` which was committed here 
https://reviews.llvm.org/D102875#change-CGl81jJwEOZy. Although I may be wrong.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105834/new/

https://reviews.llvm.org/D105834

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D105984: [PowerPC] Restore FastMathFlags of Builder for Vector FDiv Builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 359093.
quinnp marked an inline comment as done.
quinnp added a comment.

Adressing review comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105984/new/

https://reviews.llvm.org/D105984

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-fastmath.c

Index: clang/test/CodeGen/builtins-ppc-fastmath.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-fastmath.c
@@ -0,0 +1,74 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern vector float a;
+extern vector float b;
+extern vector float c;
+extern vector double d;
+extern vector double e;
+extern vector double f;
+
+// CHECK-LABEL: @test_flags_recipdivf(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <4 x float>, <4 x float>* @b, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP3:%.*]] = load <4 x float>, <4 x float>* @b, align 16
+// CHECK-NEXT:[[RECIPDIV:%.*]] = fdiv fast <4 x float> [[TMP2]], [[TMP3]]
+// CHECK-NEXT:[[TMP4:%.*]] = load <4 x float>, <4 x float>* @c, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <4 x float> [[RECIPDIV]], [[TMP4]]
+// CHECK-NEXT:ret <4 x float> [[ADD]]
+//
+vector float test_flags_recipdivf() {
+  return __builtin_ppc_recipdivf(a, b) + c;
+}
+
+// CHECK-LABEL: @test_flags_recipdivd(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <2 x double>, <2 x double>* @e, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP3:%.*]] = load <2 x double>, <2 x double>* @e, align 16
+// CHECK-NEXT:[[RECIPDIV:%.*]] = fdiv fast <2 x double> [[TMP2]], [[TMP3]]
+// CHECK-NEXT:[[TMP4:%.*]] = load <2 x double>, <2 x double>* @f, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <2 x double> [[RECIPDIV]], [[TMP4]]
+// CHECK-NEXT:ret <2 x double> [[ADD]]
+//
+vector double test_flags_recipdivd() {
+  return __builtin_ppc_recipdivd(d, e) + f;
+}
+
+// CHECK-LABEL: @test_flags_rsqrtf(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> [[TMP1]])
+// CHECK-NEXT:[[RSQRT:%.*]] = fdiv fast <4 x float> , [[TMP2]]
+// CHECK-NEXT:[[TMP3:%.*]] = load <4 x float>, <4 x float>* @b, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <4 x float> [[RSQRT]], [[TMP3]]
+// CHECK-NEXT:ret <4 x float> [[ADD]]
+//
+vector float test_flags_rsqrtf() {
+  return __builtin_ppc_rsqrtf(a) + b;
+}
+
+// CHECK-LABEL: @test_flags_rsqrtd(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = call fast <2 x double> @llvm.sqrt.v2f64(<2 x double> [[TMP1]])
+// CHECK-NEXT:[[RSQRT:%.*]] = fdiv fast <2 x double> , [[TMP2]]
+// CHECK-NEXT:[[TMP3:%.*]] = load <2 x double>, <2 x double>* @e, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <2 x double> [[RSQRT]], [[TMP3]]
+// CHECK-NEXT:ret <2 x double> [[ADD]]
+//
+vector double test_flags_rsqrtd() {
+  return __builtin_ppc_rsqrtd(d) + e;
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15128,6 +15128,7 @@
   case PPC::BI__builtin_ppc_recipdivd:
   case PPC::BI__builtin_ppc_rsqrtf:
   case PPC::BI__builtin_ppc_rsqrtd: {
+FastMathFlags FMF = Builder.getFastMathFlags();
 Builder.getFastMathFlags().setFast();
 llvm::Type *ResultType = ConvertType(E->getType());
 Value *X = EmitScalarExpr(E->getArg(0));
@@ -15135,11 +15136,15 @@
 if (BuiltinID == PPC::BI__builtin_ppc_recipdivf ||
 BuiltinID == PPC::BI__builtin_ppc_recipdivd) {
   Value *Y = EmitScalarExpr(E->getArg(1));
-  return Builder.CreateFDiv(X, Y, "recipdiv");
+  Value *fdiv = Builder.CreateFDiv(X, Y, "recipdiv");
+  Builder.getFastMathFlags() &= (FMF);
+  return fdiv;
 }
 auto *One = ConstantFP::get(Result

[PATCH] D105984: [PowerPC] Restore FastMathFlags of Builder for Vector FDiv Builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 359116.
quinnp added a comment.

Adding `REQUIRES: powerpc-registered target` to front end test case`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105984/new/

https://reviews.llvm.org/D105984

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-fastmath.c

Index: clang/test/CodeGen/builtins-ppc-fastmath.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-fastmath.c
@@ -0,0 +1,76 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern vector float a;
+extern vector float b;
+extern vector float c;
+extern vector double d;
+extern vector double e;
+extern vector double f;
+
+// CHECK-LABEL: @test_flags_recipdivf(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <4 x float>, <4 x float>* @b, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP3:%.*]] = load <4 x float>, <4 x float>* @b, align 16
+// CHECK-NEXT:[[RECIPDIV:%.*]] = fdiv fast <4 x float> [[TMP2]], [[TMP3]]
+// CHECK-NEXT:[[TMP4:%.*]] = load <4 x float>, <4 x float>* @c, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <4 x float> [[RECIPDIV]], [[TMP4]]
+// CHECK-NEXT:ret <4 x float> [[ADD]]
+//
+vector float test_flags_recipdivf() {
+  return __builtin_ppc_recipdivf(a, b) + c;
+}
+
+// CHECK-LABEL: @test_flags_recipdivd(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <2 x double>, <2 x double>* @e, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP3:%.*]] = load <2 x double>, <2 x double>* @e, align 16
+// CHECK-NEXT:[[RECIPDIV:%.*]] = fdiv fast <2 x double> [[TMP2]], [[TMP3]]
+// CHECK-NEXT:[[TMP4:%.*]] = load <2 x double>, <2 x double>* @f, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <2 x double> [[RECIPDIV]], [[TMP4]]
+// CHECK-NEXT:ret <2 x double> [[ADD]]
+//
+vector double test_flags_recipdivd() {
+  return __builtin_ppc_recipdivd(d, e) + f;
+}
+
+// CHECK-LABEL: @test_flags_rsqrtf(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> [[TMP1]])
+// CHECK-NEXT:[[RSQRT:%.*]] = fdiv fast <4 x float> , [[TMP2]]
+// CHECK-NEXT:[[TMP3:%.*]] = load <4 x float>, <4 x float>* @b, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <4 x float> [[RSQRT]], [[TMP3]]
+// CHECK-NEXT:ret <4 x float> [[ADD]]
+//
+vector float test_flags_rsqrtf() {
+  return __builtin_ppc_rsqrtf(a) + b;
+}
+
+// CHECK-LABEL: @test_flags_rsqrtd(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = call fast <2 x double> @llvm.sqrt.v2f64(<2 x double> [[TMP1]])
+// CHECK-NEXT:[[RSQRT:%.*]] = fdiv fast <2 x double> , [[TMP2]]
+// CHECK-NEXT:[[TMP3:%.*]] = load <2 x double>, <2 x double>* @e, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <2 x double> [[RSQRT]], [[TMP3]]
+// CHECK-NEXT:ret <2 x double> [[ADD]]
+//
+vector double test_flags_rsqrtd() {
+  return __builtin_ppc_rsqrtd(d) + e;
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15128,6 +15128,7 @@
   case PPC::BI__builtin_ppc_recipdivd:
   case PPC::BI__builtin_ppc_rsqrtf:
   case PPC::BI__builtin_ppc_rsqrtd: {
+FastMathFlags FMF = Builder.getFastMathFlags();
 Builder.getFastMathFlags().setFast();
 llvm::Type *ResultType = ConvertType(E->getType());
 Value *X = EmitScalarExpr(E->getArg(0));
@@ -15135,11 +15136,15 @@
 if (BuiltinID == PPC::BI__builtin_ppc_recipdivf ||
 BuiltinID == PPC::BI__builtin_ppc_recipdivd) {
   Value *Y = EmitScalarExpr(E->getArg(1));
-  return Builder.CreateFDiv(X, Y, "recipdiv");
+  Value *fdiv = Builder.CreateFDiv(X, Y, "recipdiv");
+  Builder.getFastMathFlags() &= (FMF);
+  return fdiv;
 

[PATCH] D105984: [PowerPC] Restore FastMathFlags of Builder for Vector FDiv Builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 359118.
quinnp added a comment.

Removing a newline.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105984/new/

https://reviews.llvm.org/D105984

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-fastmath.c

Index: clang/test/CodeGen/builtins-ppc-fastmath.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-fastmath.c
@@ -0,0 +1,75 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern vector float a;
+extern vector float b;
+extern vector float c;
+extern vector double d;
+extern vector double e;
+extern vector double f;
+
+// CHECK-LABEL: @test_flags_recipdivf(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <4 x float>, <4 x float>* @b, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP3:%.*]] = load <4 x float>, <4 x float>* @b, align 16
+// CHECK-NEXT:[[RECIPDIV:%.*]] = fdiv fast <4 x float> [[TMP2]], [[TMP3]]
+// CHECK-NEXT:[[TMP4:%.*]] = load <4 x float>, <4 x float>* @c, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <4 x float> [[RECIPDIV]], [[TMP4]]
+// CHECK-NEXT:ret <4 x float> [[ADD]]
+//
+vector float test_flags_recipdivf() {
+  return __builtin_ppc_recipdivf(a, b) + c;
+}
+
+// CHECK-LABEL: @test_flags_recipdivd(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <2 x double>, <2 x double>* @e, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP3:%.*]] = load <2 x double>, <2 x double>* @e, align 16
+// CHECK-NEXT:[[RECIPDIV:%.*]] = fdiv fast <2 x double> [[TMP2]], [[TMP3]]
+// CHECK-NEXT:[[TMP4:%.*]] = load <2 x double>, <2 x double>* @f, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <2 x double> [[RECIPDIV]], [[TMP4]]
+// CHECK-NEXT:ret <2 x double> [[ADD]]
+//
+vector double test_flags_recipdivd() {
+  return __builtin_ppc_recipdivd(d, e) + f;
+}
+
+// CHECK-LABEL: @test_flags_rsqrtf(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> [[TMP1]])
+// CHECK-NEXT:[[RSQRT:%.*]] = fdiv fast <4 x float> , [[TMP2]]
+// CHECK-NEXT:[[TMP3:%.*]] = load <4 x float>, <4 x float>* @b, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <4 x float> [[RSQRT]], [[TMP3]]
+// CHECK-NEXT:ret <4 x float> [[ADD]]
+//
+vector float test_flags_rsqrtf() {
+  return __builtin_ppc_rsqrtf(a) + b;
+}
+
+// CHECK-LABEL: @test_flags_rsqrtd(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = call fast <2 x double> @llvm.sqrt.v2f64(<2 x double> [[TMP1]])
+// CHECK-NEXT:[[RSQRT:%.*]] = fdiv fast <2 x double> , [[TMP2]]
+// CHECK-NEXT:[[TMP3:%.*]] = load <2 x double>, <2 x double>* @e, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <2 x double> [[RSQRT]], [[TMP3]]
+// CHECK-NEXT:ret <2 x double> [[ADD]]
+//
+vector double test_flags_rsqrtd() {
+  return __builtin_ppc_rsqrtd(d) + e;
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15128,6 +15128,7 @@
   case PPC::BI__builtin_ppc_recipdivd:
   case PPC::BI__builtin_ppc_rsqrtf:
   case PPC::BI__builtin_ppc_rsqrtd: {
+FastMathFlags FMF = Builder.getFastMathFlags();
 Builder.getFastMathFlags().setFast();
 llvm::Type *ResultType = ConvertType(E->getType());
 Value *X = EmitScalarExpr(E->getArg(0));
@@ -15135,11 +15136,15 @@
 if (BuiltinID == PPC::BI__builtin_ppc_recipdivf ||
 BuiltinID == PPC::BI__builtin_ppc_recipdivd) {
   Value *Y = EmitScalarExpr(E->getArg(1));
-  return Builder.CreateFDiv(X, Y, "recipdiv");
+  Value *fdiv = Builder.CreateFDiv(X, Y, "recipdiv");
+  Builder.getFastMathFlags() &= (FMF);
+  return fdiv;
 }
 auto *One = ConstantFP::get(ResultType, 1

[PATCH] D106150: [PowerPC] swdiv_nochk Builtins for XL Compat

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added subscribers: shchenz, kbarton, nemanjai.
quinnp requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

This patch is in a series of patches to provide builtins for
compatibility with the XL compiler. This patch adds software divide
builtins with no checking. These builtins are each emitted as a fast
fdiv.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106150

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-swdiv_nochk.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-swdiv_nochk.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-swdiv_nochk.c
@@ -0,0 +1,113 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern double a;
+extern double b;
+extern double c;
+extern float d;
+extern float e;
+extern float f;
+
+// CHECK-LABEL: @test_swdiv_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV_NOCHK]]
+//
+double test_swdiv_nochk() {
+  return __swdiv_nochk(a, b);
+}
+
+// CHECK-LABEL: @test_swdivs_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIV_NOCHK]]
+//
+float test_swdivs_nochk() {
+  return __swdivs_nochk(d, e);
+}
+
+// CHECK-LABEL: @test_flags_swdiv_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP2:%.*]] = load double, double* @c, align 8
+// CHECK-NEXT:[[ADD:%.*]] = fadd double [[SWDIV_NOCHK]], [[TMP2]]
+// CHECK-NEXT:ret double [[ADD]]
+//
+double test_flags_swdiv_nochk() {
+  return __swdiv_nochk(a, b) + c;
+}
+
+// CHECK-LABEL: @test_flags_swdivs_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP2:%.*]] = load float, float* @f, align 4
+// CHECK-NEXT:[[ADD:%.*]] = fadd float [[SWDIV_NOCHK]], [[TMP2]]
+// CHECK-NEXT:ret float [[ADD]]
+//
+float test_flags_swdivs_nochk() {
+  return __swdivs_nochk(d, e) + f;
+}
+
+// CHECK-LABEL: @test_builtin_ppc_swdiv_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV_NOCHK]]
+//
+double test_builtin_ppc_swdiv_nochk() {
+  return __builtin_ppc_swdiv_nochk(a, b);
+}
+
+// CHECK-LABEL: @test_builtin_ppc_swdivs_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIV_NOCHK]]
+//
+float test_builtin_ppc_swdivs_nochk() {
+  return __builtin_ppc_swdivs_nochk(d, e);
+}
+
+// CHECK-LABEL: @test_flags_builtin_ppc_swdiv_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP2:%.*]] = load double, double* @c, align 8
+// CHECK-NEXT:[[ADD:%.*]] = fadd double [[SWDIV_NOCHK]], [[TMP2]]
+// CHECK-NEXT:ret double [[ADD]]
+//
+double test_flags_builtin_ppc_swdiv_nochk() {
+  return __builtin_ppc_swdiv_nochk(a, b) + c;
+}
+
+// CHECK-LABEL: @test_flags_builtin_ppc_swdivs_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e

[PATCH] D106150: [PowerPC] swdiv_nochk Builtins for XL Compat

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 359310.
quinnp added a comment.

Adressing review comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106150/new/

https://reviews.llvm.org/D106150

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-swdiv_nochk.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-swdiv_nochk.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-swdiv_nochk.c
@@ -0,0 +1,109 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern double a;
+extern double b;
+extern double c;
+extern float d;
+extern float e;
+extern float f;
+
+// CHECK-LABEL: @test_swdiv_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV_NOCHK]]
+//
+double test_swdiv_nochk() {
+  return __swdiv_nochk(a, b);
+}
+
+// CHECK-LABEL: @test_swdivs_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIV_NOCHK]]
+//
+float test_swdivs_nochk() {
+  return __swdivs_nochk(d, e);
+}
+
+// CHECK-LABEL: @test_flags_swdiv_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP2:%.*]] = load double, double* @c, align 8
+// CHECK-NEXT:[[ADD:%.*]] = fadd double [[SWDIV_NOCHK]], [[TMP2]]
+// CHECK-NEXT:ret double [[ADD]]
+//
+double test_flags_swdiv_nochk() {
+  return __swdiv_nochk(a, b) + c;
+}
+
+// CHECK-LABEL: @test_flags_swdivs_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP2:%.*]] = load float, float* @f, align 4
+// CHECK-NEXT:[[ADD:%.*]] = fadd float [[SWDIV_NOCHK]], [[TMP2]]
+// CHECK-NEXT:ret float [[ADD]]
+//
+float test_flags_swdivs_nochk() {
+  return __swdivs_nochk(d, e) + f;
+}
+
+// CHECK-LABEL: @test_builtin_ppc_swdiv_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV_NOCHK]]
+//
+double test_builtin_ppc_swdiv_nochk() {
+  return __builtin_ppc_swdiv_nochk(a, b);
+}
+
+// CHECK-LABEL: @test_builtin_ppc_swdivs_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIV_NOCHK]]
+//
+float test_builtin_ppc_swdivs_nochk() {
+  return __builtin_ppc_swdivs_nochk(d, e);
+}
+
+// CHECK-LABEL: @test_flags_builtin_ppc_swdiv_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP2:%.*]] = load double, double* @c, align 8
+// CHECK-NEXT:[[ADD:%.*]] = fadd double [[SWDIV_NOCHK]], [[TMP2]]
+// CHECK-NEXT:ret double [[ADD]]
+//
+double test_flags_builtin_ppc_swdiv_nochk() {
+  return __builtin_ppc_swdiv_nochk(a, b) + c;
+}
+
+// CHECK-LABEL: @test_flags_builtin_ppc_swdivs_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP2:%.*]] = load float, float* @f, align 4
+// CHECK-NEXT:[[ADD:%.*]] = fadd float [[SWDIV_NOCHK]], [[TMP2]]
+// CHECK-NEXT:ret float [[ADD]]
+//
+float test_flags_builtin_ppc_swdivs_nochk() {
+  return __builtin_ppc_swdivs_nochk(d, e) + f;
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
---

[PATCH] D106150: [PowerPC] swdiv_nochk Builtins for XL Compat

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 359325.
quinnp added a comment.

Fixing a syntax error.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106150/new/

https://reviews.llvm.org/D106150

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-swdiv_nochk.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-swdiv_nochk.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-swdiv_nochk.c
@@ -0,0 +1,109 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern double a;
+extern double b;
+extern double c;
+extern float d;
+extern float e;
+extern float f;
+
+// CHECK-LABEL: @test_swdiv_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV_NOCHK]]
+//
+double test_swdiv_nochk() {
+  return __swdiv_nochk(a, b);
+}
+
+// CHECK-LABEL: @test_swdivs_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIV_NOCHK]]
+//
+float test_swdivs_nochk() {
+  return __swdivs_nochk(d, e);
+}
+
+// CHECK-LABEL: @test_flags_swdiv_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP2:%.*]] = load double, double* @c, align 8
+// CHECK-NEXT:[[ADD:%.*]] = fadd double [[SWDIV_NOCHK]], [[TMP2]]
+// CHECK-NEXT:ret double [[ADD]]
+//
+double test_flags_swdiv_nochk() {
+  return __swdiv_nochk(a, b) + c;
+}
+
+// CHECK-LABEL: @test_flags_swdivs_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP2:%.*]] = load float, float* @f, align 4
+// CHECK-NEXT:[[ADD:%.*]] = fadd float [[SWDIV_NOCHK]], [[TMP2]]
+// CHECK-NEXT:ret float [[ADD]]
+//
+float test_flags_swdivs_nochk() {
+  return __swdivs_nochk(d, e) + f;
+}
+
+// CHECK-LABEL: @test_builtin_ppc_swdiv_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV_NOCHK]]
+//
+double test_builtin_ppc_swdiv_nochk() {
+  return __builtin_ppc_swdiv_nochk(a, b);
+}
+
+// CHECK-LABEL: @test_builtin_ppc_swdivs_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIV_NOCHK]]
+//
+float test_builtin_ppc_swdivs_nochk() {
+  return __builtin_ppc_swdivs_nochk(d, e);
+}
+
+// CHECK-LABEL: @test_flags_builtin_ppc_swdiv_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP2:%.*]] = load double, double* @c, align 8
+// CHECK-NEXT:[[ADD:%.*]] = fadd double [[SWDIV_NOCHK]], [[TMP2]]
+// CHECK-NEXT:ret double [[ADD]]
+//
+double test_flags_builtin_ppc_swdiv_nochk() {
+  return __builtin_ppc_swdiv_nochk(a, b) + c;
+}
+
+// CHECK-LABEL: @test_flags_builtin_ppc_swdivs_nochk(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP2:%.*]] = load float, float* @f, align 4
+// CHECK-NEXT:[[ADD:%.*]] = fadd float [[SWDIV_NOCHK]], [[TMP2]]
+// CHECK-NEXT:ret float [[ADD]]
+//
+float test_flags_builtin_ppc_swdivs_nochk() {
+  return __builtin_ppc_swdivs_nochk(d, e) + f;
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- cla

[PATCH] D106150: [PowerPC] swdiv_nochk Builtins for XL Compat

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 359327.
quinnp added a comment.

Removing entry checks from front end test.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106150/new/

https://reviews.llvm.org/D106150

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-swdiv_nochk.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-swdiv_nochk.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-swdiv_nochk.c
@@ -0,0 +1,100 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern double a;
+extern double b;
+extern double c;
+extern float d;
+extern float e;
+extern float f;
+
+// CHECK-LABEL: @test_swdiv_nochk(
+// CHECK:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV_NOCHK]]
+//
+double test_swdiv_nochk() {
+  return __swdiv_nochk(a, b);
+}
+
+// CHECK-LABEL: @test_swdivs_nochk(
+// CHECK:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIV_NOCHK]]
+//
+float test_swdivs_nochk() {
+  return __swdivs_nochk(d, e);
+}
+
+// CHECK-LABEL: @test_flags_swdiv_nochk(
+// CHECK:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP2:%.*]] = load double, double* @c, align 8
+// CHECK-NEXT:[[ADD:%.*]] = fadd double [[SWDIV_NOCHK]], [[TMP2]]
+// CHECK-NEXT:ret double [[ADD]]
+//
+double test_flags_swdiv_nochk() {
+  return __swdiv_nochk(a, b) + c;
+}
+
+// CHECK-LABEL: @test_flags_swdivs_nochk(
+// CHECK:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP2:%.*]] = load float, float* @f, align 4
+// CHECK-NEXT:[[ADD:%.*]] = fadd float [[SWDIV_NOCHK]], [[TMP2]]
+// CHECK-NEXT:ret float [[ADD]]
+//
+float test_flags_swdivs_nochk() {
+  return __swdivs_nochk(d, e) + f;
+}
+
+// CHECK-LABEL: @test_builtin_ppc_swdiv_nochk(
+// CHECK:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV_NOCHK]]
+//
+double test_builtin_ppc_swdiv_nochk() {
+  return __builtin_ppc_swdiv_nochk(a, b);
+}
+
+// CHECK-LABEL: @test_builtin_ppc_swdivs_nochk(
+// CHECK:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIV_NOCHK]]
+//
+float test_builtin_ppc_swdivs_nochk() {
+  return __builtin_ppc_swdivs_nochk(d, e);
+}
+
+// CHECK-LABEL: @test_flags_builtin_ppc_swdiv_nochk(
+// CHECK:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP2:%.*]] = load double, double* @c, align 8
+// CHECK-NEXT:[[ADD:%.*]] = fadd double [[SWDIV_NOCHK]], [[TMP2]]
+// CHECK-NEXT:ret double [[ADD]]
+//
+double test_flags_builtin_ppc_swdiv_nochk() {
+  return __builtin_ppc_swdiv_nochk(a, b) + c;
+}
+
+// CHECK-LABEL: @test_flags_builtin_ppc_swdivs_nochk(
+// CHECK:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP2:%.*]] = load float, float* @f, align 4
+// CHECK-NEXT:[[ADD:%.*]] = fadd float [[SWDIV_NOCHK]], [[TMP2]]
+// CHECK-NEXT:ret float [[ADD]]
+//
+float test_flags_builtin_ppc_swdivs_nochk() {
+  return __builtin_ppc_swdivs_nochk(d, e) + f;
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15620,6 +15620,15 @@
 Function *F = CGM.getIntrinsic(Intrinsic::ppc_popcntb, {ArgType, ArgType});
 return Builder.CreateCall(F, Ops, "popcntb");
   }
+
+  case PPC::BI__builtin_ppc_swdiv_nochk:
+  case PPC::BI__bui

[PATCH] D105984: [PowerPC] Restore FastMathFlags of Builder for Vector FDiv Builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 359338.
quinnp added a comment.

Removing entry checks from front end test and renaming a variable.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105984/new/

https://reviews.llvm.org/D105984

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-fastmath.c

Index: clang/test/CodeGen/builtins-ppc-fastmath.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-fastmath.c
@@ -0,0 +1,70 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern vector float a;
+extern vector float b;
+extern vector float c;
+extern vector double d;
+extern vector double e;
+extern vector double f;
+
+// CHECK-LABEL: @test_flags_recipdivf(
+// CHECK:[[TMP0:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <4 x float>, <4 x float>* @b, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP3:%.*]] = load <4 x float>, <4 x float>* @b, align 16
+// CHECK-NEXT:[[RECIPDIV:%.*]] = fdiv fast <4 x float> [[TMP2]], [[TMP3]]
+// CHECK-NEXT:[[TMP4:%.*]] = load <4 x float>, <4 x float>* @c, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <4 x float> [[RECIPDIV]], [[TMP4]]
+// CHECK-NEXT:ret <4 x float> [[ADD]]
+//
+vector float test_flags_recipdivf() {
+  return __builtin_ppc_recipdivf(a, b) + c;
+}
+
+// CHECK-LABEL: @test_flags_recipdivd(
+// CHECK:[[TMP0:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <2 x double>, <2 x double>* @e, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP3:%.*]] = load <2 x double>, <2 x double>* @e, align 16
+// CHECK-NEXT:[[RECIPDIV:%.*]] = fdiv fast <2 x double> [[TMP2]], [[TMP3]]
+// CHECK-NEXT:[[TMP4:%.*]] = load <2 x double>, <2 x double>* @f, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <2 x double> [[RECIPDIV]], [[TMP4]]
+// CHECK-NEXT:ret <2 x double> [[ADD]]
+//
+vector double test_flags_recipdivd() {
+  return __builtin_ppc_recipdivd(d, e) + f;
+}
+
+// CHECK-LABEL: @test_flags_rsqrtf(
+// CHECK:[[TMP0:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> [[TMP1]])
+// CHECK-NEXT:[[RSQRT:%.*]] = fdiv fast <4 x float> , [[TMP2]]
+// CHECK-NEXT:[[TMP3:%.*]] = load <4 x float>, <4 x float>* @b, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <4 x float> [[RSQRT]], [[TMP3]]
+// CHECK-NEXT:ret <4 x float> [[ADD]]
+//
+vector float test_flags_rsqrtf() {
+  return __builtin_ppc_rsqrtf(a) + b;
+}
+
+// CHECK-LABEL: @test_flags_rsqrtd(
+// CHECK:[[TMP0:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = call fast <2 x double> @llvm.sqrt.v2f64(<2 x double> [[TMP1]])
+// CHECK-NEXT:[[RSQRT:%.*]] = fdiv fast <2 x double> , [[TMP2]]
+// CHECK-NEXT:[[TMP3:%.*]] = load <2 x double>, <2 x double>* @e, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <2 x double> [[RSQRT]], [[TMP3]]
+// CHECK-NEXT:ret <2 x double> [[ADD]]
+//
+vector double test_flags_rsqrtd() {
+  return __builtin_ppc_rsqrtd(d) + e;
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15128,6 +15128,7 @@
   case PPC::BI__builtin_ppc_recipdivd:
   case PPC::BI__builtin_ppc_rsqrtf:
   case PPC::BI__builtin_ppc_rsqrtd: {
+FastMathFlags FMF = Builder.getFastMathFlags();
 Builder.getFastMathFlags().setFast();
 llvm::Type *ResultType = ConvertType(E->getType());
 Value *X = EmitScalarExpr(E->getArg(0));
@@ -15135,11 +15136,15 @@
 if (BuiltinID == PPC::BI__builtin_ppc_recipdivf ||
 BuiltinID == PPC::BI__builtin_ppc_recipdivd) {
   Value *Y = EmitScalarExpr(E->getArg(1));
-  return Builder.CreateFDiv(X, Y, "recipdiv");
+  Value *FDiv = Builder.CreateFDiv(X, Y, "recipdiv");
+  Builder.getFastMathFlags() &= (FMF);
+  return FDiv;
 }
 auto *One = ConstantFP::get(ResultType, 1.0);
 llvm::Function *F = CGM.getIntrinsic(Intrinsic::sqrt, ResultType);
-return Builder.CreateFDiv(One, Builder.CreateCall(F, X), "rsqrt");

[PATCH] D105834: [PowerPC] Semachecking for XL compat builtin icbt

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 359398.
quinnp added a comment.

Adding a `REQUIRES: powerpc-registered-target` to a testcase and removing 
checks for `entry:` in front end test case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105834/new/

https://reviews.llvm.org/D105834

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
  clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
@@ -94,7 +94,6 @@
 }
 declare void @llvm.ppc.iospace.sync()
 
-; FIXME: __icbt is only valid for pwr8 and up.
 define dso_local void @test_builtin_ppc_icbt() {
 ; CHECK-LABEL: test_builtin_ppc_icbt:
 ; CHECK:   # %bb.0: # %entry
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
@@ -60,18 +60,3 @@
   ret void
 }
 declare void @llvm.ppc.iospace.sync()
-
-; FIXME: __icbt is only valid for pwr8 and up.
-define dso_local void @test_builtin_ppc_icbt() {
-; CHECK-LABEL: test_builtin_ppc_icbt:
-; CHECK:   # %bb.0: # %entry
-; CHECK-NEXT:lwz 3, -8(1)
-; CHECK-NEXT:icbt 0, 0, 3
-; CHECK-NEXT:blr
-entry:
-  %a = alloca i8*, align 8
-  %0 = load i8*, i8** %a, align 8
-  call void @llvm.ppc.icbt(i8* %0)
-  ret void
-}
-declare void @llvm.ppc.icbt(i8*)
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1534,7 +1534,6 @@
 [IntrArgMemOnly, NoCapture>]>;
   def int_ppc_dcbz  : GCCBuiltin<"__builtin_ppc_dcbz">,
   Intrinsic<[], [llvm_ptr_ty], []>;
-// FIXME: __icbt is only valid for pwr8 and up.
   def int_ppc_icbt : GCCBuiltin<"__builtin_ppc_icbt">,
  Intrinsic<[], [llvm_ptr_ty], []>;
   
Index: clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
@@ -1,4 +1,3 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
 // RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
@@ -14,15 +13,13 @@
 extern void *c;
 
 // CHECK-LABEL: @test_popcntb(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = load i64, i64* @a, align 8
+// CHECK:[[TMP0:%.*]] = load i64, i64* @a, align 8
 // CHECK-NEXT:[[TMP1:%.*]] = load i64, i64* @a, align 8
 // CHECK-NEXT:[[POPCNTB:%.*]] = call i64 @llvm.ppc.popcntb.i64.i64(i64 [[TMP0]])
 // CHECK-NEXT:ret i64 [[POPCNTB]]
 //
 // CHECK-32-LABEL: @test_popcntb(
-// CHECK-32-NEXT:  entry:
-// CHECK-32-NEXT:[[TMP0:%.*]] = load i32, i32* @a, align 4
+// CHECK-32:[[TMP0:%.*]] = load i32, i32* @a, align 4
 // CHECK-32-NEXT:[[TMP1:%.*]] = load i32, i32* @a, align 4
 // CHECK-32-NEXT:[[POPCNTB:%.*]] = call i32 @llvm.ppc.popcntb.i32.i32(i32 [[TMP0]])
 // CHECK-32-NEXT:ret i32 [[POPCNTB]]
@@ -32,13 +29,11 @@
 }
 
 // CHECK-LABEL: @test_eieio(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:call void @llvm.ppc.eieio()
+// CHECK:call void @llvm.ppc.eieio()
 // CHECK-NEXT:ret void
 //
 // CHECK-32-LABEL: @test_eieio(
-// CHECK-32-NEXT:  entry:
-// CHECK-32-NEXT:call void @llvm.ppc.eieio()
+// CHECK-32:call void @llvm.ppc.eieio()
 // CHECK-32-NEXT:ret void
 //
 void test_eieio() {
@@ -46,13 +41,11 @@
 }
 
 // CHECK-LABEL: @test_iospace_eieio(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:call void @llvm.ppc.iospace.eieio()
+// CHECK:call void @llvm.ppc.iospace.eieio()
 // CHECK-NEXT:ret void
 //
 // CHECK-32-LABEL: @test_iospace_eieio(
-// CHECK-32-NEXT:  entry:
-// CHECK-32-NEXT:call void @llvm.ppc.iospace.eieio()
+// CHECK-32:call void @llvm.ppc.iospace.eieio()
 // CHECK-32-NEXT:ret void
 //
 void test_iospace_eieio() {
@@ -60,13 +53,11 @@
 }
 
 // CHECK-LABEL: @test_isync(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:call void @llvm.ppc.isync()
+// CHECK:call void @llvm.ppc.isync()
 // CHECK-NEXT:ret void
 //
 // CHECK-32-LABEL: @test_isync(
-// CHECK-32-NEXT:  entry:
-// CHECK-32-NEXT:call void @llvm.ppc.isync()
+// CHECK-32:call void @llvm.ppc.isync()
 // CHECK-32-NEXT:ret void
 //
 void test_isync() {
@@ -74,13 +65,11 @@
 }
 

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 359426.
quinnp marked 8 inline comments as done.
quinnp added a comment.

Addressing some review comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103986/new/

https://reviews.llvm.org/D103986

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-fp.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
@@ -0,0 +1,101 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mattr=-vsx -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+define dso_local double @test_fsel(double %a, double %b, double %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsel:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_fsel:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fsel:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call double @llvm.ppc.fsel(double %a, double %b, double %c)
+  ret double %0
+}
+
+declare double @llvm.ppc.fsel(double, double, double)
+
+define dso_local float @test_fsels(float %a, float %b, float %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsels:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_fsels:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fsels:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call float @llvm.ppc.fsels(float %a, float %b, float %c)
+  ret float %0
+}
+
+declare float @llvm.ppc.fsels(float, float, float)
+
+define dso_local double @test_frsqrte(double %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrte:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:xsrsqrtedp 1, 1
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_frsqrte:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsrsqrtedp 1, 1
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrte:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:frsqrte 1, 1
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call double @llvm.ppc.frsqrte(double %a)
+  ret double %0
+}
+
+declare double @llvm.ppc.frsqrte(double)
+
+define dso_local float @test_frsqrtes(float %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrtes:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:frsqrtes 1, 1
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_frsqrtes:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsrsqrtesp 1, 1
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrtes:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:frsqrtes 1, 1
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call float @llvm.ppc.frsqrtes(float %a)
+  ret float %0
+}
+
+declare float @llvm.ppc.frsqrtes(float)
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -2850,6 +2850,8 @@
 def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 199)),
   (VCMPGTUB_rec DblwdCmp.MRGEQ, (v2i64 (XXLXORz)))>;
 } // AddedComplexity = 0
+
+def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
 } // HasVSX
 
 // Any big endian VSX subtarget.
@@ -3240,6 +3242,8 @@
   (v8i16 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
 def : Pat<(v16i8 (bitconvert (v16i8 immAllOnesV))),
   (v16i8 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
+
+def : Pat<(int_ppc_frsqrtes vssrc:$XB), (XSRSQRTESP $XB)>;
 } // HasVSX, HasP8Vector
 
 // Any big endian Power8 VSX subtarget.
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 359437.
quinnp added a comment.

Adding a better comment for the handling of the ppc_fsels intrinsic.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103986/new/

https://reviews.llvm.org/D103986

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-fp.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
@@ -0,0 +1,101 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mattr=-vsx -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+define dso_local double @test_fsel(double %a, double %b, double %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsel:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_fsel:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fsel:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call double @llvm.ppc.fsel(double %a, double %b, double %c)
+  ret double %0
+}
+
+declare double @llvm.ppc.fsel(double, double, double)
+
+define dso_local float @test_fsels(float %a, float %b, float %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsels:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_fsels:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fsels:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call float @llvm.ppc.fsels(float %a, float %b, float %c)
+  ret float %0
+}
+
+declare float @llvm.ppc.fsels(float, float, float)
+
+define dso_local double @test_frsqrte(double %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrte:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:xsrsqrtedp 1, 1
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_frsqrte:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsrsqrtedp 1, 1
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrte:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:frsqrte 1, 1
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call double @llvm.ppc.frsqrte(double %a)
+  ret double %0
+}
+
+declare double @llvm.ppc.frsqrte(double)
+
+define dso_local float @test_frsqrtes(float %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrtes:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:frsqrtes 1, 1
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_frsqrtes:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsrsqrtesp 1, 1
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrtes:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:frsqrtes 1, 1
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call float @llvm.ppc.frsqrtes(float %a)
+  ret float %0
+}
+
+declare float @llvm.ppc.frsqrtes(float)
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -2850,6 +2850,8 @@
 def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 199)),
   (VCMPGTUB_rec DblwdCmp.MRGEQ, (v2i64 (XXLXORz)))>;
 } // AddedComplexity = 0
+
+def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
 } // HasVSX
 
 // Any big endian VSX subtarget.
@@ -3240,6 +3242,8 @@
   (v8i16 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
 def : Pat<(v16i8 (bitconvert (v16i8 immAllOnesV))),
   (v16i8 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
+
+def : Pat<(int_ppc_frsqrtes vssrc:$XB), (XSRSQRTESP $XB)>;
 } // HasVSX, HasP8Vector
 
 // Any big endian Power8 VSX subtarget.
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 359441.
quinnp added a comment.

Fixing a run line in a test.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103986/new/

https://reviews.llvm.org/D103986

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-fp.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
@@ -0,0 +1,101 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mattr=-vsx -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+define dso_local double @test_fsel(double %a, double %b, double %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsel:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_fsel:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fsel:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call double @llvm.ppc.fsel(double %a, double %b, double %c)
+  ret double %0
+}
+
+declare double @llvm.ppc.fsel(double, double, double)
+
+define dso_local float @test_fsels(float %a, float %b, float %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsels:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_fsels:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fsels:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call float @llvm.ppc.fsels(float %a, float %b, float %c)
+  ret float %0
+}
+
+declare float @llvm.ppc.fsels(float, float, float)
+
+define dso_local double @test_frsqrte(double %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrte:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:xsrsqrtedp 1, 1
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_frsqrte:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsrsqrtedp 1, 1
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrte:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:frsqrte 1, 1
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call double @llvm.ppc.frsqrte(double %a)
+  ret double %0
+}
+
+declare double @llvm.ppc.frsqrte(double)
+
+define dso_local float @test_frsqrtes(float %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrtes:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:frsqrtes 1, 1
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_frsqrtes:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsrsqrtesp 1, 1
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrtes:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:frsqrtes 1, 1
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call float @llvm.ppc.frsqrtes(float %a)
+  ret float %0
+}
+
+declare float @llvm.ppc.frsqrtes(float)
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -2850,6 +2850,8 @@
 def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 199)),
   (VCMPGTUB_rec DblwdCmp.MRGEQ, (v2i64 (XXLXORz)))>;
 } // AddedComplexity = 0
+
+def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
 } // HasVSX
 
 // Any big endian VSX subtarget.
@@ -3240,6 +3242,8 @@
   (v8i16 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
 def : Pat<(v16i8 (bitconvert (v16i8 immAllOnesV))),
   (v16i8 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
+
+def : Pat<(int_ppc_frsqrtes vssrc:$XB), (XSRSQRTESP $XB)>;
 } // HasVSX, HasP8Vector
 
 // Any big endian Power8 VSX subtarget.
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Tar

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 359783.
quinnp added a comment.

Addressing review comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103986/new/

https://reviews.llvm.org/D103986

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-fp.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
@@ -0,0 +1,101 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mattr=-vsx -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+define dso_local double @test_fsel(double %a, double %b, double %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsel:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_fsel:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fsel:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call double @llvm.ppc.fsel(double %a, double %b, double %c)
+  ret double %0
+}
+
+declare double @llvm.ppc.fsel(double, double, double)
+
+define dso_local float @test_fsels(float %a, float %b, float %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsels:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_fsels:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fsels:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call float @llvm.ppc.fsels(float %a, float %b, float %c)
+  ret float %0
+}
+
+declare float @llvm.ppc.fsels(float, float, float)
+
+define dso_local double @test_frsqrte(double %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrte:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:xsrsqrtedp 1, 1
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_frsqrte:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsrsqrtedp 1, 1
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrte:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:frsqrte 1, 1
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call double @llvm.ppc.frsqrte(double %a)
+  ret double %0
+}
+
+declare double @llvm.ppc.frsqrte(double)
+
+define dso_local float @test_frsqrtes(float %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrtes:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:frsqrtes 1, 1
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_frsqrtes:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsrsqrtesp 1, 1
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrtes:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:frsqrtes 1, 1
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call float @llvm.ppc.frsqrtes(float %a)
+  ret float %0
+}
+
+declare float @llvm.ppc.frsqrtes(float)
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -2850,6 +2850,8 @@
 def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 199)),
   (VCMPGTUB_rec DblwdCmp.MRGEQ, (v2i64 (XXLXORz)))>;
 } // AddedComplexity = 0
+
+def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
 } // HasVSX
 
 // Any big endian VSX subtarget.
@@ -3240,6 +3242,8 @@
   (v8i16 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
 def : Pat<(v16i8 (bitconvert (v16i8 immAllOnesV))),
   (v16i8 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
+
+def : Pat<(int_ppc_frsqrtes vssrc:$XB), (XSRSQRTESP $XB)>;
 } // HasVSX, HasP8Vector
 
 // Any big endian Power8 VSX subtarget.
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Targe

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 360128.
quinnp added a comment.

Rebasing patch. Moving macro definitions from a header file to a src file.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103986/new/

https://reviews.llvm.org/D103986

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-fp.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
@@ -0,0 +1,101 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mattr=-vsx -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+define dso_local double @test_fsel(double %a, double %b, double %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsel:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_fsel:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fsel:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call double @llvm.ppc.fsel(double %a, double %b, double %c)
+  ret double %0
+}
+
+declare double @llvm.ppc.fsel(double, double, double)
+
+define dso_local float @test_fsels(float %a, float %b, float %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsels:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_fsels:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fsels:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call float @llvm.ppc.fsels(float %a, float %b, float %c)
+  ret float %0
+}
+
+declare float @llvm.ppc.fsels(float, float, float)
+
+define dso_local double @test_frsqrte(double %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrte:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:xsrsqrtedp 1, 1
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_frsqrte:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsrsqrtedp 1, 1
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrte:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:frsqrte 1, 1
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call double @llvm.ppc.frsqrte(double %a)
+  ret double %0
+}
+
+declare double @llvm.ppc.frsqrte(double)
+
+define dso_local float @test_frsqrtes(float %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrtes:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:frsqrtes 1, 1
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_frsqrtes:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsrsqrtesp 1, 1
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrtes:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:frsqrtes 1, 1
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call float @llvm.ppc.frsqrtes(float %a)
+  ret float %0
+}
+
+declare float @llvm.ppc.frsqrtes(float)
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -2857,6 +2857,7 @@
 def : Pat<(int_ppc_fnmsub f64:$A, f64:$B, f64:$C), (XSNMSUBMDP $A, $B, $C)>;
 def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (XSNMADDMDP $A, $B, $C)>;
 def : Pat<(int_ppc_fre f64:$A), (XSREDP $A)>;
+def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
 } // HasVSX
 
 // Any big endian VSX subtarget.
@@ -3264,6 +3265,7 @@
   (XSXSIGDP (COPY_TO_REGCLASS $A, VSFRC))>;
 def : Pat<(f64 (int_ppc_insert_exp f64:$A, i64:$B)),
   (COPY_TO_REGCLASS (XSIEXPDP (COPY_TO_REGCLASS $A, G8RC), $B), F8RC)>;
+def : Pat<(int_ppc_frsqrtes vssrc:$XB), (XSRSQRTESP $XB)>;
 } // HasVSX, HasP8Vector
 
 // Any big endian Power8 VSX subtarget.
Index: llvm/l

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 360261.
quinnp added a comment.

Rebasing to ToT


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103986/new/

https://reviews.llvm.org/D103986

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-fp.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
@@ -0,0 +1,101 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mattr=-vsx -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+define dso_local double @test_fsel(double %a, double %b, double %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsel:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_fsel:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fsel:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call double @llvm.ppc.fsel(double %a, double %b, double %c)
+  ret double %0
+}
+
+declare double @llvm.ppc.fsel(double, double, double)
+
+define dso_local float @test_fsels(float %a, float %b, float %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsels:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_fsels:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fsels:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call float @llvm.ppc.fsels(float %a, float %b, float %c)
+  ret float %0
+}
+
+declare float @llvm.ppc.fsels(float, float, float)
+
+define dso_local double @test_frsqrte(double %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrte:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:xsrsqrtedp 1, 1
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_frsqrte:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsrsqrtedp 1, 1
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrte:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:frsqrte 1, 1
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call double @llvm.ppc.frsqrte(double %a)
+  ret double %0
+}
+
+declare double @llvm.ppc.frsqrte(double)
+
+define dso_local float @test_frsqrtes(float %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrtes:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:frsqrtes 1, 1
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_frsqrtes:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsrsqrtesp 1, 1
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrtes:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:frsqrtes 1, 1
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call float @llvm.ppc.frsqrtes(float %a)
+  ret float %0
+}
+
+declare float @llvm.ppc.frsqrtes(float)
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -2857,6 +2857,7 @@
 def : Pat<(int_ppc_fnmsub f64:$A, f64:$B, f64:$C), (XSNMSUBMDP $A, $B, $C)>;
 def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (XSNMADDMDP $A, $B, $C)>;
 def : Pat<(int_ppc_fre f64:$A), (XSREDP $A)>;
+def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
 } // HasVSX
 
 // Any big endian VSX subtarget.
@@ -3267,6 +3268,7 @@
 
 def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT),
   (STXSIWX f64:$XT, ForceXForm:$dst)>;
+def : Pat<(int_ppc_frsqrtes vssrc:$XB), (XSRSQRTESP $XB)>;
 } // HasVSX, HasP8Vector
 
 // Any big endian Power8 VSX subtarget.
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.t

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 360408.
quinnp added a comment.

Rebasing to ToT.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103986/new/

https://reviews.llvm.org/D103986

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-fp.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
@@ -0,0 +1,101 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mattr=-vsx -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+define dso_local double @test_fsel(double %a, double %b, double %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsel:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_fsel:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fsel:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call double @llvm.ppc.fsel(double %a, double %b, double %c)
+  ret double %0
+}
+
+declare double @llvm.ppc.fsel(double, double, double)
+
+define dso_local float @test_fsels(float %a, float %b, float %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsels:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_fsels:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fsels:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call float @llvm.ppc.fsels(float %a, float %b, float %c)
+  ret float %0
+}
+
+declare float @llvm.ppc.fsels(float, float, float)
+
+define dso_local double @test_frsqrte(double %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrte:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:xsrsqrtedp 1, 1
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_frsqrte:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsrsqrtedp 1, 1
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrte:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:frsqrte 1, 1
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call double @llvm.ppc.frsqrte(double %a)
+  ret double %0
+}
+
+declare double @llvm.ppc.frsqrte(double)
+
+define dso_local float @test_frsqrtes(float %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrtes:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:frsqrtes 1, 1
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_frsqrtes:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsrsqrtesp 1, 1
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrtes:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:frsqrtes 1, 1
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call float @llvm.ppc.frsqrtes(float %a)
+  ret float %0
+}
+
+declare float @llvm.ppc.frsqrtes(float)
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -2857,6 +2857,7 @@
 def : Pat<(int_ppc_fnmsub f64:$A, f64:$B, f64:$C), (XSNMSUBMDP $A, $B, $C)>;
 def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (XSNMADDMDP $A, $B, $C)>;
 def : Pat<(int_ppc_fre f64:$A), (XSREDP $A)>;
+def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
 } // HasVSX
 
 // Any big endian VSX subtarget.
@@ -3267,6 +3268,7 @@
 
 def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT),
   (STXSIWX f64:$XT, ForceXForm:$dst)>;
+def : Pat<(int_ppc_frsqrtes vssrc:$XB), (XSRSQRTESP $XB)>;
 } // HasVSX, HasP8Vector
 
 // Any big endian Power8 VSX subtarget.
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Quinn Pham via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe002d251dd34: [PowerPC] Floating Point Builtins for XL 
Compat. (authored by quinnp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103986/new/

https://reviews.llvm.org/D103986

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-fp.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
@@ -0,0 +1,101 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mattr=-vsx -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+define dso_local double @test_fsel(double %a, double %b, double %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsel:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_fsel:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fsel:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call double @llvm.ppc.fsel(double %a, double %b, double %c)
+  ret double %0
+}
+
+declare double @llvm.ppc.fsel(double, double, double)
+
+define dso_local float @test_fsels(float %a, float %b, float %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsels:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_fsels:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fsels:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call float @llvm.ppc.fsels(float %a, float %b, float %c)
+  ret float %0
+}
+
+declare float @llvm.ppc.fsels(float, float, float)
+
+define dso_local double @test_frsqrte(double %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrte:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:xsrsqrtedp 1, 1
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_frsqrte:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsrsqrtedp 1, 1
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrte:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:frsqrte 1, 1
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call double @llvm.ppc.frsqrte(double %a)
+  ret double %0
+}
+
+declare double @llvm.ppc.frsqrte(double)
+
+define dso_local float @test_frsqrtes(float %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrtes:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:frsqrtes 1, 1
+; CHECK-PWR7-NEXT:blr
+;
+; CHECK-PWR8-LABEL: test_frsqrtes:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsrsqrtesp 1, 1
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrtes:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:frsqrtes 1, 1
+; CHECK-NOVSX-NEXT:blr
+
+entry:
+  %0 = tail call float @llvm.ppc.frsqrtes(float %a)
+  ret float %0
+}
+
+declare float @llvm.ppc.frsqrtes(float)
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -2857,6 +2857,7 @@
 def : Pat<(int_ppc_fnmsub f64:$A, f64:$B, f64:$C), (XSNMSUBMDP $A, $B, $C)>;
 def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (XSNMADDMDP $A, $B, $C)>;
 def : Pat<(int_ppc_fre f64:$A), (XSREDP $A)>;
+def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
 } // HasVSX
 
 // Any big endian VSX subtarget.
@@ -3267,6 +3268,7 @@
 
 def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT),
   (STXSIWX f64:$XT, ForceXForm:$dst)>;
+def : Pat<(int_ppc_frsqrtes vssrc:$XB), (XSRSQRTESP $XB)>;
 } // HasVSX, HasP8Vector
 
 // Any big endian Power8 VSX subtarget.
Index: ll

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Quinn Pham via Phabricator via cfe-commits]

quinnp added a comment.

In D103986#2893177 , @DavidSpickett 
wrote:

> You missed a REQUIRES for the llvm test, I added one in: 
> https://reviews.llvm.org/rG2404834c206a8930b0c420d94f4941b31c355de5
>
> So if you see Arm-AArch64 quick bot failures, that was the reason.

Right, sorry about that. Thank you, I will also move the test to 
`llvm/test/CodeGen/PowerPC`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103986/new/

https://reviews.llvm.org/D103986

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility]

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added subscribers: shchenz, kbarton, hiraditya, mgorny, nemanjai.
quinnp requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This patch is in a series of patches to provide builtins for compatibility with
the XL compiler. This patch adds software divide builtins with checking.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106959

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/CMakeLists.txt
  llvm/lib/Target/PowerPC/PPC.h
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/lib/Target/PowerPC/PPCLowerCheckedFPArith.cpp
  llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
  llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll
  llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll

Index: llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll
@@ -0,0 +1,30 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mattr=-vsx -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+define dso_local i32 @test_ftdivdp(double %a, double %b) local_unnamed_addr {
+; CHECK-LABEL: test_ftdivdp:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xstdivdp 0, 1, 2
+; CHECK-NEXT:mfocrf 3, 128
+; CHECK-NEXT:srwi 3, 3, 28
+; CHECK-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_ftdivdp:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:ftdiv 0, 1, 2
+; CHECK-NOVSX-NEXT:mfocrf 3, 128
+; CHECK-NOVSX-NEXT:srwi 3, 3, 28
+; CHECK-NOVSX-NEXT:blr
+entry:
+  %c = tail call i32 @llvm.ppc.ftdivdp(double %a, double %b)
+  ret i32 %c
+}
+
+declare i32 @llvm.ppc.ftdivdp(double, double)
Index: llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll
@@ -0,0 +1,53 @@
+; RUN: opt -ppc-lower-checked-fp-arith -S -o - < %s | FileCheck %s
+
+@a = external local_unnamed_addr global double
+@b = external local_unnamed_addr global double
+@c = external local_unnamed_addr global float
+@d = external local_unnamed_addr global float
+
+; CHECK-LABEL: @test_swdiv(
+; CHECK:  %0 = load double, double* @a, align 8
+; CHECK-NEXT:  %1 = load double, double* @b, align 8
+; CHECK-NEXT:  %2 = call i32 @llvm.ppc.ftdivdp(double %0, double %1)
+; CHECK-NEXT:  %3 = icmp eq i32 %2, 0
+; CHECK-NEXT:  %4 = fdiv fast double %0, %1
+; CHECK-NEXT:  br i1 %3, label %swdiv_HWDIV, label %swdiv_MERGE
+
+; CHECK:  %5 = fdiv double %0, %1
+; CHECK-NEXT:  br label %swdiv_MERGE
+
+; CHECK:  %6 = phi double [ %4, %entry ], [ %5, %swdiv_HWDIV ]
+; CHECK-NEXT:  ret double %6
+
+define dso_local double @test_swdiv() local_unnamed_addr {
+entry:
+  %0 = load double, double* @a
+  %1 = load double, double* @b
+  %2 = tail call double @llvm.ppc.swdiv(double %0, double %1)
+  ret double %2
+}
+
+declare double @llvm.ppc.swdiv(double, double)
+
+; CHECK-LABEL: @test_swdivs(
+; CHECK:  %0 = load float, float* @c, align 4
+; CHECK-NEXT:  %1 = load float, float* @d, align 4
+; CHECK-NEXT:  %2 = fdiv fast float %0, %1
+; CHECK-NEXT:  %3 = fcmp une float %2, %2
+; CHECK-NEXT:  br i1 %3, label %swdiv_HWDIV, label %swdiv_MERGE
+
+; CHECK:  %4 = fdiv float %0, %1
+; CHECK-NEXT:  br label %swdiv_MERGE
+
+; CHECK:  %5 = phi float [ %2, %entry ], [ %4, %swdiv_HWDIV ]
+; CHECK-NEXT:  ret float %5
+
+define dso_local float @test_swdivs() local_unnamed_addr {
+entry:
+  %0 = load float, float* @c
+  %1 = load float, float* @d
+  %2 = tail call float @llvm.ppc.swdivs(float %0, float %1)
+  ret float %2
+}
+
+declare float @llvm.ppc.swdivs(float, float)
Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
===
--- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -125,6 +125,7 @@
   initializePPCLowerMASSVEntriesPass(PR);
   initializePPCExpandAtomicPseudoPass(PR);
   initializeGlobalISel(PR);
+  initializePPCLowerCheckedFPArithPass(PR);
 }
 
 static bool isLittleEndianTriple(const Triple &T) {
@@ -447,6 +448,8 @@
   }
 
   TargetPassConfig::addIRPasses();
+
+  addPass(createPPCLowerCheckedFPArithPass());
 }
 
 bool PPCPassConfig::addPreISel() {
Index: llvm/lib/Target/PowerPC/PPCL

[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 362400.
quinnp added a comment.

Fixing a failing test case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106959/new/

https://reviews.llvm.org/D106959

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/CMakeLists.txt
  llvm/lib/Target/PowerPC/PPC.h
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/lib/Target/PowerPC/PPCLowerCheckedFPArith.cpp
  llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
  llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll
  llvm/test/CodeGen/PowerPC/O3-pipeline.ll
  llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll

Index: llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll
@@ -0,0 +1,30 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mattr=-vsx -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+define dso_local i32 @test_ftdivdp(double %a, double %b) local_unnamed_addr {
+; CHECK-LABEL: test_ftdivdp:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xstdivdp 0, 1, 2
+; CHECK-NEXT:mfocrf 3, 128
+; CHECK-NEXT:srwi 3, 3, 28
+; CHECK-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_ftdivdp:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:ftdiv 0, 1, 2
+; CHECK-NOVSX-NEXT:mfocrf 3, 128
+; CHECK-NOVSX-NEXT:srwi 3, 3, 28
+; CHECK-NOVSX-NEXT:blr
+entry:
+  %c = tail call i32 @llvm.ppc.ftdivdp(double %a, double %b)
+  ret i32 %c
+}
+
+declare i32 @llvm.ppc.ftdivdp(double, double)
Index: llvm/test/CodeGen/PowerPC/O3-pipeline.ll
===
--- llvm/test/CodeGen/PowerPC/O3-pipeline.ll
+++ llvm/test/CodeGen/PowerPC/O3-pipeline.ll
@@ -63,6 +63,8 @@
 ; CHECK-NEXT:   Expand vector predication intrinsics
 ; CHECK-NEXT:   Scalarize Masked Memory Intrinsics
 ; CHECK-NEXT:   Expand reduction intrinsics
+; CHECK-NEXT:   Lower Checked Floating Point Arithmetic
+; CHECK-NEXT:   Dominator Tree Construction
 ; CHECK-NEXT:   Natural Loop Information
 ; CHECK-NEXT:   CodeGen Prepare
 ; CHECK-NEXT:   Dominator Tree Construction
@@ -206,4 +208,4 @@
 
 define void @f() {
   ret void
-}
\ No newline at end of file
+}
Index: llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll
@@ -0,0 +1,53 @@
+; RUN: opt -ppc-lower-checked-fp-arith -S -o - < %s | FileCheck %s
+
+@a = external local_unnamed_addr global double
+@b = external local_unnamed_addr global double
+@c = external local_unnamed_addr global float
+@d = external local_unnamed_addr global float
+
+; CHECK-LABEL: @test_swdiv(
+; CHECK:  %0 = load double, double* @a, align 8
+; CHECK-NEXT:  %1 = load double, double* @b, align 8
+; CHECK-NEXT:  %2 = call i32 @llvm.ppc.ftdivdp(double %0, double %1)
+; CHECK-NEXT:  %3 = icmp eq i32 %2, 0
+; CHECK-NEXT:  %4 = fdiv fast double %0, %1
+; CHECK-NEXT:  br i1 %3, label %swdiv_HWDIV, label %swdiv_MERGE
+
+; CHECK:  %5 = fdiv double %0, %1
+; CHECK-NEXT:  br label %swdiv_MERGE
+
+; CHECK:  %6 = phi double [ %4, %entry ], [ %5, %swdiv_HWDIV ]
+; CHECK-NEXT:  ret double %6
+
+define dso_local double @test_swdiv() local_unnamed_addr {
+entry:
+  %0 = load double, double* @a
+  %1 = load double, double* @b
+  %2 = tail call double @llvm.ppc.swdiv(double %0, double %1)
+  ret double %2
+}
+
+declare double @llvm.ppc.swdiv(double, double)
+
+; CHECK-LABEL: @test_swdivs(
+; CHECK:  %0 = load float, float* @c, align 4
+; CHECK-NEXT:  %1 = load float, float* @d, align 4
+; CHECK-NEXT:  %2 = fdiv fast float %0, %1
+; CHECK-NEXT:  %3 = fcmp une float %2, %2
+; CHECK-NEXT:  br i1 %3, label %swdiv_HWDIV, label %swdiv_MERGE
+
+; CHECK:  %4 = fdiv float %0, %1
+; CHECK-NEXT:  br label %swdiv_MERGE
+
+; CHECK:  %5 = phi float [ %2, %entry ], [ %4, %swdiv_HWDIV ]
+; CHECK-NEXT:  ret float %5
+
+define dso_local float @test_swdivs() local_unnamed_addr {
+entry:
+  %0 = load float, float* @c
+  %1 = load float, float* @d
+  %2 = tail call float @llvm.ppc.swdivs(float %0, float %1)
+  ret float %2
+}
+
+declare float @llvm.ppc.swdivs(float, float)
Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
=

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added subscribers: shchenz, kbarton, nemanjai.
Herald added a project: All.
quinnp requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

This patch refactors `EmitPPCBuiltinExpr` in `CGBuiltin.cpp` to remove
the loop at the begining of the function that emits the arguments and
to delay emitting the arguments until inside the switch statement. This
refactor will put `EmitPPCBuiltinExpr` in line with the strategy of the
target independent function `EmitBuiltinExpr`. Also, this refactor
ensures that arguments are only emitted once.

Tests that included builtins affected by the refactor have been modified
to match expected behaviour.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D121637

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c
  clang/test/CodeGen/PowerPC/builtins-ppc-int128.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cas.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fetch.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c

Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
@@ -14,13 +14,11 @@
 
 // CHECK-LABEL: @test_popcntb(
 // CHECK:[[TMP0:%.*]] = load i64, i64* @a, align 8
-// CHECK-NEXT:[[TMP1:%.*]] = load i64, i64* @a, align 8
 // CHECK-NEXT:[[POPCNTB:%.*]] = call i64 @llvm.ppc.popcntb.i64.i64(i64 [[TMP0]])
 // CHECK-NEXT:ret i64 [[POPCNTB]]
 //
 // CHECK-32-LABEL: @test_popcntb(
 // CHECK-32:[[TMP0:%.*]] = load i32, i32* @a, align 4
-// CHECK-32-NEXT:[[TMP1:%.*]] = load i32, i32* @a, align 4
 // CHECK-32-NEXT:[[POPCNTB:%.*]] = call i32 @llvm.ppc.popcntb.i32.i32(i32 [[TMP0]])
 // CHECK-32-NEXT:ret i32 [[POPCNTB]]
 //
@@ -198,13 +196,11 @@
 
 // CHECK-LABEL: @test_builtin_ppc_popcntb(
 // CHECK:[[TMP0:%.*]] = load i64, i64* @a, align 8
-// CHECK-NEXT:[[TMP1:%.*]] = load i64, i64* @a, align 8
 // CHECK-NEXT:[[POPCNTB:%.*]] = call i64 @llvm.ppc.popcntb.i64.i64(i64 [[TMP0]])
 // CHECK-NEXT:ret i64 [[POPCNTB]]
 //
 // CHECK-32-LABEL: @test_builtin_ppc_popcntb(
 // CHECK-32:[[TMP0:%.*]] = load i32, i32* @a, align 4
-// CHECK-32-NEXT:[[TMP1:%.*]] = load i32, i32* @a, align 4
 // CHECK-32-NEXT:[[POPCNTB:%.*]] = call i32 @llvm.ppc.popcntb.i32.i32(i32 [[TMP0]])
 // CHECK-32-NEXT:ret i32 [[POPCNTB]]
 //
Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
@@ -15,11 +15,11 @@
   // CHECK-LABEL: test_builtin_ppc_rldimi
   // CHECK:   %res = alloca i64, align 8
   // CHECK-NEXT:  [[RA:%[0-9]+]] = load i64, i64* @ull, align 8
-  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i64, i64* @ull, align 8
-  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i64 @llvm.fshl.i64(i64 [[RA]], i64 [[RA]], i64 63)
-  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i64 [[RC]], 72057593769492480
-  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i64 [[RB]], -72057593769492481
-  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i64 [[RD]], [[RE]]
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = call i64 @llvm.fshl.i64(i64 [[RA]], i64 [[RA]], i64 63)
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = and i64 [[RB]], 72057593769492480
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = load i64, i64* @ull, align 8
+  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i64 [[RD]], -72057593769492481
+  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i64 [[RC]], [[RE]]
   // CHECK-NEXT:  store i64 [[RF]], i64* %res, align 8
   // CHECK-NEXT:  ret void
 
@@ -31,11 +31,11 @@
   // CHECK-LABEL: test_builtin_ppc_rlwimi
   // CHECK:   %res = alloca i32, align 4
   // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
-  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i32, i32* @ui, align 4
-  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
-  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i32 [[RC]], 16776960
-  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i32 [[RB]], -16776961
-  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i32 [[RD]], [[RE]]
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = and i32 [[RB]], 16776960
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i32 [[RD]], -16776961
+  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i32 [[RC]], [[RE]]
   // CHECK-NEXT:  store i32 [[RF]], i32* %res, align 4
   // CHECK-NEXT:  ret void
 
Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
==

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 415412.
quinnp added a comment.

Minor formatting update.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121637/new/

https://reviews.llvm.org/D121637

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c
  clang/test/CodeGen/PowerPC/builtins-ppc-int128.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cas.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fetch.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c

Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
@@ -14,13 +14,11 @@
 
 // CHECK-LABEL: @test_popcntb(
 // CHECK:[[TMP0:%.*]] = load i64, i64* @a, align 8
-// CHECK-NEXT:[[TMP1:%.*]] = load i64, i64* @a, align 8
 // CHECK-NEXT:[[POPCNTB:%.*]] = call i64 @llvm.ppc.popcntb.i64.i64(i64 [[TMP0]])
 // CHECK-NEXT:ret i64 [[POPCNTB]]
 //
 // CHECK-32-LABEL: @test_popcntb(
 // CHECK-32:[[TMP0:%.*]] = load i32, i32* @a, align 4
-// CHECK-32-NEXT:[[TMP1:%.*]] = load i32, i32* @a, align 4
 // CHECK-32-NEXT:[[POPCNTB:%.*]] = call i32 @llvm.ppc.popcntb.i32.i32(i32 [[TMP0]])
 // CHECK-32-NEXT:ret i32 [[POPCNTB]]
 //
@@ -198,13 +196,11 @@
 
 // CHECK-LABEL: @test_builtin_ppc_popcntb(
 // CHECK:[[TMP0:%.*]] = load i64, i64* @a, align 8
-// CHECK-NEXT:[[TMP1:%.*]] = load i64, i64* @a, align 8
 // CHECK-NEXT:[[POPCNTB:%.*]] = call i64 @llvm.ppc.popcntb.i64.i64(i64 [[TMP0]])
 // CHECK-NEXT:ret i64 [[POPCNTB]]
 //
 // CHECK-32-LABEL: @test_builtin_ppc_popcntb(
 // CHECK-32:[[TMP0:%.*]] = load i32, i32* @a, align 4
-// CHECK-32-NEXT:[[TMP1:%.*]] = load i32, i32* @a, align 4
 // CHECK-32-NEXT:[[POPCNTB:%.*]] = call i32 @llvm.ppc.popcntb.i32.i32(i32 [[TMP0]])
 // CHECK-32-NEXT:ret i32 [[POPCNTB]]
 //
Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
@@ -15,11 +15,11 @@
   // CHECK-LABEL: test_builtin_ppc_rldimi
   // CHECK:   %res = alloca i64, align 8
   // CHECK-NEXT:  [[RA:%[0-9]+]] = load i64, i64* @ull, align 8
-  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i64, i64* @ull, align 8
-  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i64 @llvm.fshl.i64(i64 [[RA]], i64 [[RA]], i64 63)
-  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i64 [[RC]], 72057593769492480
-  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i64 [[RB]], -72057593769492481
-  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i64 [[RD]], [[RE]]
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = call i64 @llvm.fshl.i64(i64 [[RA]], i64 [[RA]], i64 63)
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = and i64 [[RB]], 72057593769492480
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = load i64, i64* @ull, align 8
+  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i64 [[RD]], -72057593769492481
+  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i64 [[RC]], [[RE]]
   // CHECK-NEXT:  store i64 [[RF]], i64* %res, align 8
   // CHECK-NEXT:  ret void
 
@@ -31,11 +31,11 @@
   // CHECK-LABEL: test_builtin_ppc_rlwimi
   // CHECK:   %res = alloca i32, align 4
   // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
-  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i32, i32* @ui, align 4
-  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
-  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i32 [[RC]], 16776960
-  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i32 [[RB]], -16776961
-  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i32 [[RD]], [[RE]]
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = and i32 [[RB]], 16776960
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i32 [[RD]], -16776961
+  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i32 [[RC]], [[RE]]
   // CHECK-NEXT:  store i32 [[RF]], i32* %res, align 4
   // CHECK-NEXT:  ret void
 
Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
@@ -15,9 +15,8 @@
 
 // CHECK-LABEL: @test_fric(
 // CHECK:[[TMP0:%.*]] = load double, double* @a, align 8
-// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @a, align 8
-// CHECK-NEXT:[[TMP2:%.*]] = call double @llvm.rint.f64(double [[TMP1]])
-// CHECK-NEXT:ret double [[TMP2]]
+// CHECK-NEXT:[[TMP1:%.*]] = call double @llvm.rint.f64(double [[TMP0]])
+// CHECK-NEXT:ret double [[TMP

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 416917.
quinnp added a comment.

Fixing a failing test case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121637/new/

https://reviews.llvm.org/D121637

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c
  clang/test/CodeGen/PowerPC/builtins-ppc-int128.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cas.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fetch.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c

Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
@@ -14,13 +14,11 @@
 
 // CHECK-LABEL: @test_popcntb(
 // CHECK:[[TMP0:%.*]] = load i64, i64* @a, align 8
-// CHECK-NEXT:[[TMP1:%.*]] = load i64, i64* @a, align 8
 // CHECK-NEXT:[[POPCNTB:%.*]] = call i64 @llvm.ppc.popcntb.i64.i64(i64 [[TMP0]])
 // CHECK-NEXT:ret i64 [[POPCNTB]]
 //
 // CHECK-32-LABEL: @test_popcntb(
 // CHECK-32:[[TMP0:%.*]] = load i32, i32* @a, align 4
-// CHECK-32-NEXT:[[TMP1:%.*]] = load i32, i32* @a, align 4
 // CHECK-32-NEXT:[[POPCNTB:%.*]] = call i32 @llvm.ppc.popcntb.i32.i32(i32 [[TMP0]])
 // CHECK-32-NEXT:ret i32 [[POPCNTB]]
 //
@@ -198,13 +196,11 @@
 
 // CHECK-LABEL: @test_builtin_ppc_popcntb(
 // CHECK:[[TMP0:%.*]] = load i64, i64* @a, align 8
-// CHECK-NEXT:[[TMP1:%.*]] = load i64, i64* @a, align 8
 // CHECK-NEXT:[[POPCNTB:%.*]] = call i64 @llvm.ppc.popcntb.i64.i64(i64 [[TMP0]])
 // CHECK-NEXT:ret i64 [[POPCNTB]]
 //
 // CHECK-32-LABEL: @test_builtin_ppc_popcntb(
 // CHECK-32:[[TMP0:%.*]] = load i32, i32* @a, align 4
-// CHECK-32-NEXT:[[TMP1:%.*]] = load i32, i32* @a, align 4
 // CHECK-32-NEXT:[[POPCNTB:%.*]] = call i32 @llvm.ppc.popcntb.i32.i32(i32 [[TMP0]])
 // CHECK-32-NEXT:ret i32 [[POPCNTB]]
 //
Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-rotate.c
@@ -15,11 +15,11 @@
   // CHECK-LABEL: test_builtin_ppc_rldimi
   // CHECK:   %res = alloca i64, align 8
   // CHECK-NEXT:  [[RA:%[0-9]+]] = load i64, i64* @ull, align 8
-  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i64, i64* @ull, align 8
-  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i64 @llvm.fshl.i64(i64 [[RA]], i64 [[RA]], i64 63)
-  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i64 [[RC]], 72057593769492480
-  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i64 [[RB]], -72057593769492481
-  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i64 [[RD]], [[RE]]
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = call i64 @llvm.fshl.i64(i64 [[RA]], i64 [[RA]], i64 63)
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = and i64 [[RB]], 72057593769492480
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = load i64, i64* @ull, align 8
+  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i64 [[RD]], -72057593769492481
+  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i64 [[RC]], [[RE]]
   // CHECK-NEXT:  store i64 [[RF]], i64* %res, align 8
   // CHECK-NEXT:  ret void
 
@@ -31,11 +31,11 @@
   // CHECK-LABEL: test_builtin_ppc_rlwimi
   // CHECK:   %res = alloca i32, align 4
   // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
-  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i32, i32* @ui, align 4
-  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
-  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i32 [[RC]], 16776960
-  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i32 [[RB]], -16776961
-  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i32 [[RD]], [[RE]]
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = and i32 [[RB]], 16776960
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RE:%[0-9]+]] = and i32 [[RD]], -16776961
+  // CHECK-NEXT:  [[RF:%[0-9]+]] = or i32 [[RC]], [[RE]]
   // CHECK-NEXT:  store i32 [[RF]], i32* %res, align 4
   // CHECK-NEXT:  ret void
 
Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
@@ -95,7 +95,6 @@
 // CHECK-LABEL: @fnmsub(
 // CHECK: [[D_ADDR:%.*]] = alloca double, align 8
 // CHECK-NEXT:store double [[D:%.*]], double* [[D_ADDR]], align 8
-// CHECK-COUNT-3:load double, double* [[D_ADDR]], align 8
 // CHECK-NEXT:[[TMP0:%.*]] = load double, double* [[D_ADDR]], align 8
 // CHECK-NEXT:[[TMP1:%.*

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 421279.
quinnp marked an inline comment as done.
quinnp added a comment.

Fixing some testcases that broke due to re-ordering IR in my last update.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121637/new/

https://reviews.llvm.org/D121637

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c
  clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
  clang/test/CodeGen/PowerPC/builtins-ppc-stmtexpr-argument.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cas.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fetch.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
  clang/test/CodeGen/PowerPC/ppc-mma-types.c
  clang/test/Sema/ppc-pair-mma-types.c

Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -12,11 +12,6 @@
 
 // typedef
 typedef __vector_quad vq_t;
-void testVQTypedef(int *inp, int *outp) {
-  vq_t *vqin = (vq_t *)inp;
-  vq_t *vqout = (vq_t *)outp;
-  *vqout = *vqin;
-}
 
 // function argument
 void testVQArg1(__vector_quad vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
@@ -29,57 +24,22 @@
   *vqp = vq;
 }
 
-void testVQArg3(__vector_quad *vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
-void testVQArg4(const __vector_quad *const vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
-void testVQArg5(__vector_quad vqa[], int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = vqa[0];
-}
-
 void testVQArg6(const vq_t vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   *vqp = vq;
 }
 
-void testVQArg7(const vq_t *vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
 // function return
 __vector_quad testVQRet1(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   return *vqp; // expected-error {{invalid use of PPC MMA type}}
 }
 
-__vector_quad *testVQRet2(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
-const __vector_quad *testVQRet3(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
 const vq_t testVQRet4(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   return *vqp; // expected-error {{invalid use of PPC MMA type}}
 }
 
-const vq_t *testVQRet5(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
 // global
 __vector_quad globalvq;// expected-error {{invalid use of PPC MMA type}}
 const __vector_quad globalvq2; // expected-error {{invalid use of PPC MMA type}}
@@ -87,16 +47,6 @@
 const __vector_quad *const globalvqp2;
 vq_t globalvq_t; // expected-error {{invalid use of PPC MMA type}}
 
-// local
-void testVQLocal(int *ptr, vector unsigned char vc) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  __vector_quad vq1 = *vqp;
-  __vector_quad vq2;
-  __builtin_mma_xxsetaccz(&vq2);
-  __vector_quad vq3;
-  __builtin_mma_xvi4ger8(&vq3, vc, vc);
-  *vqp = vq3;
-}
 
 // struct field
 struct TestVQStruct {
@@ -106,17 +56,6 @@
   __vector_quad *vq;
 };
 
-// sizeof / alignof
-int testVQSizeofAlignof(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  __vector_quad vq = *vqp;
-  unsigned sizet = sizeof(__vector_quad);
-  unsigned alignt = __alignof__(__vector_quad);
-  unsigned sizev = sizeof(vq);
-  unsigned alignv = __alignof__(vq);
-  return sizet + alignt + sizev + alignv;
-}
-
 // operators
 int testVQOperators1(int *ptr) {
   __vector_quad *vqp = (__vector_quad *)ptr;
@@ -168,11 +107,6 @@
 
 // typedef
 typedef __vector_pair vp_t;
-void testVPTypedef(int *inp, int *outp) {
-  vp_t *vpin = (vp_t *)inp;
-  vp_t *vpout = (vp_t *)outp;
-  *vpout = *vpin;
-}
 
 // function argument
 void testVPArg1(__vector_pair vp, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
@@ -185,57 +119,22 @@
   *vpp = vp;
 }
 
-void testVPArg3(__vector_pair *vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
-void testVPArg4(const __vector_pair *const vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
-void testVPArg5(__vector_pair vpa[], int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = vpa[0];
-}
-
 void testVPArg6(const vp_t vp, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_pair *vpp = (__vector_pair *)ptr;
   *vpp = vp;
 }
 
-void testVPArg7(const vp_t *vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
 // function return
 _

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15627
+Value *Y =
+Builder.CreateAnd(EmitScalarExpr(E->getArg(1)), 
Builder.CreateNot(Op3));
 return Builder.CreateOr(X, Y);

nemanjai wrote:
> Nit: I understand that we only have one use of `E->getArg(1)`, but might as 
> well initialize `Op1` as above just for consistency.
I've fixed all the instances of this.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121637/new/

https://reviews.llvm.org/D121637

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 421286.
quinnp added a comment.

Rebasing with main.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121637/new/

https://reviews.llvm.org/D121637

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c
  clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
  clang/test/CodeGen/PowerPC/builtins-ppc-stmtexpr-argument.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cas.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fetch.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
  clang/test/CodeGen/PowerPC/ppc-mma-types.c
  clang/test/Sema/ppc-pair-mma-types.c

Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -12,11 +12,6 @@
 
 // typedef
 typedef __vector_quad vq_t;
-void testVQTypedef(int *inp, int *outp) {
-  vq_t *vqin = (vq_t *)inp;
-  vq_t *vqout = (vq_t *)outp;
-  *vqout = *vqin;
-}
 
 // function argument
 void testVQArg1(__vector_quad vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
@@ -29,57 +24,22 @@
   *vqp = vq;
 }
 
-void testVQArg3(__vector_quad *vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
-void testVQArg4(const __vector_quad *const vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
-void testVQArg5(__vector_quad vqa[], int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = vqa[0];
-}
-
 void testVQArg6(const vq_t vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   *vqp = vq;
 }
 
-void testVQArg7(const vq_t *vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
 // function return
 __vector_quad testVQRet1(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   return *vqp; // expected-error {{invalid use of PPC MMA type}}
 }
 
-__vector_quad *testVQRet2(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
-const __vector_quad *testVQRet3(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
 const vq_t testVQRet4(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   return *vqp; // expected-error {{invalid use of PPC MMA type}}
 }
 
-const vq_t *testVQRet5(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
 // global
 __vector_quad globalvq;// expected-error {{invalid use of PPC MMA type}}
 const __vector_quad globalvq2; // expected-error {{invalid use of PPC MMA type}}
@@ -87,16 +47,6 @@
 const __vector_quad *const globalvqp2;
 vq_t globalvq_t; // expected-error {{invalid use of PPC MMA type}}
 
-// local
-void testVQLocal(int *ptr, vector unsigned char vc) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  __vector_quad vq1 = *vqp;
-  __vector_quad vq2;
-  __builtin_mma_xxsetaccz(&vq2);
-  __vector_quad vq3;
-  __builtin_mma_xvi4ger8(&vq3, vc, vc);
-  *vqp = vq3;
-}
 
 // struct field
 struct TestVQStruct {
@@ -106,17 +56,6 @@
   __vector_quad *vq;
 };
 
-// sizeof / alignof
-int testVQSizeofAlignof(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  __vector_quad vq = *vqp;
-  unsigned sizet = sizeof(__vector_quad);
-  unsigned alignt = __alignof__(__vector_quad);
-  unsigned sizev = sizeof(vq);
-  unsigned alignv = __alignof__(vq);
-  return sizet + alignt + sizev + alignv;
-}
-
 // operators
 int testVQOperators1(int *ptr) {
   __vector_quad *vqp = (__vector_quad *)ptr;
@@ -168,11 +107,6 @@
 
 // typedef
 typedef __vector_pair vp_t;
-void testVPTypedef(int *inp, int *outp) {
-  vp_t *vpin = (vp_t *)inp;
-  vp_t *vpout = (vp_t *)outp;
-  *vpout = *vpin;
-}
 
 // function argument
 void testVPArg1(__vector_pair vp, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
@@ -185,57 +119,22 @@
   *vpp = vp;
 }
 
-void testVPArg3(__vector_pair *vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
-void testVPArg4(const __vector_pair *const vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
-void testVPArg5(__vector_pair vpa[], int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = vpa[0];
-}
-
 void testVPArg6(const vp_t vp, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_pair *vpp = (__vector_pair *)ptr;
   *vpp = vp;
 }
 
-void testVPArg7(const vp_t *vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
 // function return
 __vector_pair testVPRet1(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vect

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 421303.
quinnp added a comment.

Fixing a set of builtins added by the rebase with main.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121637/new/

https://reviews.llvm.org/D121637

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c
  clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
  clang/test/CodeGen/PowerPC/builtins-ppc-stmtexpr-argument.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cas.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fetch.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
  clang/test/CodeGen/PowerPC/ppc-mma-types.c
  clang/test/Sema/ppc-pair-mma-types.c

Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -12,11 +12,6 @@
 
 // typedef
 typedef __vector_quad vq_t;
-void testVQTypedef(int *inp, int *outp) {
-  vq_t *vqin = (vq_t *)inp;
-  vq_t *vqout = (vq_t *)outp;
-  *vqout = *vqin;
-}
 
 // function argument
 void testVQArg1(__vector_quad vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
@@ -29,57 +24,22 @@
   *vqp = vq;
 }
 
-void testVQArg3(__vector_quad *vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
-void testVQArg4(const __vector_quad *const vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
-void testVQArg5(__vector_quad vqa[], int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = vqa[0];
-}
-
 void testVQArg6(const vq_t vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   *vqp = vq;
 }
 
-void testVQArg7(const vq_t *vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
 // function return
 __vector_quad testVQRet1(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   return *vqp; // expected-error {{invalid use of PPC MMA type}}
 }
 
-__vector_quad *testVQRet2(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
-const __vector_quad *testVQRet3(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
 const vq_t testVQRet4(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   return *vqp; // expected-error {{invalid use of PPC MMA type}}
 }
 
-const vq_t *testVQRet5(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
 // global
 __vector_quad globalvq;// expected-error {{invalid use of PPC MMA type}}
 const __vector_quad globalvq2; // expected-error {{invalid use of PPC MMA type}}
@@ -87,16 +47,6 @@
 const __vector_quad *const globalvqp2;
 vq_t globalvq_t; // expected-error {{invalid use of PPC MMA type}}
 
-// local
-void testVQLocal(int *ptr, vector unsigned char vc) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  __vector_quad vq1 = *vqp;
-  __vector_quad vq2;
-  __builtin_mma_xxsetaccz(&vq2);
-  __vector_quad vq3;
-  __builtin_mma_xvi4ger8(&vq3, vc, vc);
-  *vqp = vq3;
-}
 
 // struct field
 struct TestVQStruct {
@@ -106,17 +56,6 @@
   __vector_quad *vq;
 };
 
-// sizeof / alignof
-int testVQSizeofAlignof(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  __vector_quad vq = *vqp;
-  unsigned sizet = sizeof(__vector_quad);
-  unsigned alignt = __alignof__(__vector_quad);
-  unsigned sizev = sizeof(vq);
-  unsigned alignv = __alignof__(vq);
-  return sizet + alignt + sizev + alignv;
-}
-
 // operators
 int testVQOperators1(int *ptr) {
   __vector_quad *vqp = (__vector_quad *)ptr;
@@ -168,11 +107,6 @@
 
 // typedef
 typedef __vector_pair vp_t;
-void testVPTypedef(int *inp, int *outp) {
-  vp_t *vpin = (vp_t *)inp;
-  vp_t *vpout = (vp_t *)outp;
-  *vpout = *vpin;
-}
 
 // function argument
 void testVPArg1(__vector_pair vp, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
@@ -185,57 +119,22 @@
   *vpp = vp;
 }
 
-void testVPArg3(__vector_pair *vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
-void testVPArg4(const __vector_pair *const vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
-void testVPArg5(__vector_pair vpa[], int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = vpa[0];
-}
-
 void testVPArg6(const vp_t vp, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_pair *vpp = (__vector_pair *)ptr;
   *vpp = vp;
 }
 
-void testVPArg7(const vp_t *vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
 // function return
 __vector_pair testVPRet1(int *ptr) { // expected-error {{inv

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2aae5b1fac38: [PowerPC] Fix EmitPPCBuiltinExpr to emit 
arguments once (authored by quinnp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121637/new/

https://reviews.llvm.org/D121637

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c
  clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
  clang/test/CodeGen/PowerPC/builtins-ppc-stmtexpr-argument.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cas.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fetch.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.c
  clang/test/CodeGen/PowerPC/ppc-mma-types.c
  clang/test/Sema/ppc-pair-mma-types.c

Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -12,11 +12,6 @@
 
 // typedef
 typedef __vector_quad vq_t;
-void testVQTypedef(int *inp, int *outp) {
-  vq_t *vqin = (vq_t *)inp;
-  vq_t *vqout = (vq_t *)outp;
-  *vqout = *vqin;
-}
 
 // function argument
 void testVQArg1(__vector_quad vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
@@ -29,57 +24,22 @@
   *vqp = vq;
 }
 
-void testVQArg3(__vector_quad *vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
-void testVQArg4(const __vector_quad *const vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
-void testVQArg5(__vector_quad vqa[], int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = vqa[0];
-}
-
 void testVQArg6(const vq_t vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   *vqp = vq;
 }
 
-void testVQArg7(const vq_t *vq, int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  *vqp = *vq;
-}
-
 // function return
 __vector_quad testVQRet1(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   return *vqp; // expected-error {{invalid use of PPC MMA type}}
 }
 
-__vector_quad *testVQRet2(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
-const __vector_quad *testVQRet3(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
 const vq_t testVQRet4(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_quad *vqp = (__vector_quad *)ptr;
   return *vqp; // expected-error {{invalid use of PPC MMA type}}
 }
 
-const vq_t *testVQRet5(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  return vqp + 2;
-}
-
 // global
 __vector_quad globalvq;// expected-error {{invalid use of PPC MMA type}}
 const __vector_quad globalvq2; // expected-error {{invalid use of PPC MMA type}}
@@ -87,16 +47,6 @@
 const __vector_quad *const globalvqp2;
 vq_t globalvq_t; // expected-error {{invalid use of PPC MMA type}}
 
-// local
-void testVQLocal(int *ptr, vector unsigned char vc) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  __vector_quad vq1 = *vqp;
-  __vector_quad vq2;
-  __builtin_mma_xxsetaccz(&vq2);
-  __vector_quad vq3;
-  __builtin_mma_xvi4ger8(&vq3, vc, vc);
-  *vqp = vq3;
-}
 
 // struct field
 struct TestVQStruct {
@@ -106,17 +56,6 @@
   __vector_quad *vq;
 };
 
-// sizeof / alignof
-int testVQSizeofAlignof(int *ptr) {
-  __vector_quad *vqp = (__vector_quad *)ptr;
-  __vector_quad vq = *vqp;
-  unsigned sizet = sizeof(__vector_quad);
-  unsigned alignt = __alignof__(__vector_quad);
-  unsigned sizev = sizeof(vq);
-  unsigned alignv = __alignof__(vq);
-  return sizet + alignt + sizev + alignv;
-}
-
 // operators
 int testVQOperators1(int *ptr) {
   __vector_quad *vqp = (__vector_quad *)ptr;
@@ -168,11 +107,6 @@
 
 // typedef
 typedef __vector_pair vp_t;
-void testVPTypedef(int *inp, int *outp) {
-  vp_t *vpin = (vp_t *)inp;
-  vp_t *vpout = (vp_t *)outp;
-  *vpout = *vpin;
-}
 
 // function argument
 void testVPArg1(__vector_pair vp, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
@@ -185,57 +119,22 @@
   *vpp = vp;
 }
 
-void testVPArg3(__vector_pair *vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
-void testVPArg4(const __vector_pair *const vp, int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = *vp;
-}
-
-void testVPArg5(__vector_pair vpa[], int *ptr) {
-  __vector_pair *vpp = (__vector_pair *)ptr;
-  *vpp = vpa[0];
-}
-
 void testVPArg6(const vp_t vp, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
   __vector_pair *vpp = (__vector_pair *)ptr;
   *vpp = vp;
 }
 
-void testVPArg7(const vp_t *vp, int *ptr) {
-  __vector_pair *vpp = (__vecto

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp added a comment.

In D121637#3437371 , @thakis wrote:

> Looks like this breaks tests on windows: 
> http://45.33.8.238/win/55893/step_7.txt
>
> Please take a look and revert for now if it takes a while to fix.

Thanks for finding this, not sure what the cause is. I reverted the commit 
here: https://reviews.llvm.org/rGfef56f79ac8c4a4985774ea9fb1faa83a74866d3.

I'll look into a fix.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121637/new/

https://reviews.llvm.org/D121637

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

[Quinn Pham via Phabricator via cfe-commits]

quinnp reopened this revision.
quinnp added a comment.
This revision is now accepted and ready to land.

Re-opening the revision so that I can update it with a fix.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121637/new/

https://reviews.llvm.org/D121637

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D124389: [clang][NFC] Inclusive language: remove use of Whitelist in clang/lib/Analysis/

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added a project: All.
quinnp requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

[NFC] As part of using inclusive language within the llvm project, this patch
rewords a comment to replace Whitelist with Allowlist in
`RetainSummaryManager.cpp`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124389

Files:
  clang/lib/Analysis/RetainSummaryManager.cpp


Index: clang/lib/Analysis/RetainSummaryManager.cpp
===
--- clang/lib/Analysis/RetainSummaryManager.cpp
+++ clang/lib/Analysis/RetainSummaryManager.cpp
@@ -398,7 +398,7 @@
   } else if (FName.startswith("NSLog")) {
 return getDoNothingSummary();
   } else if (FName.startswith("NS") && FName.contains("Insert")) {
-// Whitelist NSXXInsertXX, for example NSMapInsertIfAbsent, since they can
+// Allowlist NSXXInsertXX, for example NSMapInsertIfAbsent, since they can
 // be deallocated by NSMapRemove. (radar://11152419)
 ScratchArgs = AF.add(ScratchArgs, 1, ArgEffect(StopTracking));
 ScratchArgs = AF.add(ScratchArgs, 2, ArgEffect(StopTracking));


Index: clang/lib/Analysis/RetainSummaryManager.cpp
===
--- clang/lib/Analysis/RetainSummaryManager.cpp
+++ clang/lib/Analysis/RetainSummaryManager.cpp
@@ -398,7 +398,7 @@
   } else if (FName.startswith("NSLog")) {
 return getDoNothingSummary();
   } else if (FName.startswith("NS") && FName.contains("Insert")) {
-// Whitelist NSXXInsertXX, for example NSMapInsertIfAbsent, since they can
+// Allowlist NSXXInsertXX, for example NSMapInsertIfAbsent, since they can
 // be deallocated by NSMapRemove. (radar://11152419)
 ScratchArgs = AF.add(ScratchArgs, 1, ArgEffect(StopTracking));
 ScratchArgs = AF.add(ScratchArgs, 2, ArgEffect(StopTracking));
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D124389: [clang][NFC] Inclusive language: remove use of Whitelist in clang/lib/Analysis/

[Quinn Pham via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG0386213352ec: [clang][NFC] Inclusive language: remove use of 
Whitelist in clang/lib/Analysis/ (authored by quinnp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124389/new/

https://reviews.llvm.org/D124389

Files:
  clang/lib/Analysis/RetainSummaryManager.cpp


Index: clang/lib/Analysis/RetainSummaryManager.cpp
===
--- clang/lib/Analysis/RetainSummaryManager.cpp
+++ clang/lib/Analysis/RetainSummaryManager.cpp
@@ -398,7 +398,7 @@
   } else if (FName.startswith("NSLog")) {
 return getDoNothingSummary();
   } else if (FName.startswith("NS") && FName.contains("Insert")) {
-// Whitelist NSXXInsertXX, for example NSMapInsertIfAbsent, since they can
+// Allowlist NSXXInsertXX, for example NSMapInsertIfAbsent, since they can
 // be deallocated by NSMapRemove. (radar://11152419)
 ScratchArgs = AF.add(ScratchArgs, 1, ArgEffect(StopTracking));
 ScratchArgs = AF.add(ScratchArgs, 2, ArgEffect(StopTracking));


Index: clang/lib/Analysis/RetainSummaryManager.cpp
===
--- clang/lib/Analysis/RetainSummaryManager.cpp
+++ clang/lib/Analysis/RetainSummaryManager.cpp
@@ -398,7 +398,7 @@
   } else if (FName.startswith("NSLog")) {
 return getDoNothingSummary();
   } else if (FName.startswith("NS") && FName.contains("Insert")) {
-// Whitelist NSXXInsertXX, for example NSMapInsertIfAbsent, since they can
+// Allowlist NSXXInsertXX, for example NSMapInsertIfAbsent, since they can
 // be deallocated by NSMapRemove. (radar://11152419)
 ScratchArgs = AF.add(ScratchArgs, 1, ArgEffect(StopTracking));
 ScratchArgs = AF.add(ScratchArgs, 2, ArgEffect(StopTracking));
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D129855: [clang][PowerPC] Set lld as clang's default linker for PowerPC Linux

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added subscribers: steven.zhang, shchenz, kbarton, nemanjai.
Herald added a project: All.
quinnp requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

This patch changes the default linker for `clang` on PowerPC Linux to `lld`.
Here is a summary of the expected behaviour before and after this patch:

To use `lld` as the linker before this patch:

- build with `lld` in `LLVM_ENABLE_PROJECTS`
- build with `-DCLANG_DEFAULT_LINKER=lld`

To use `lld` as the linker after this patch:

- build with `lld` in `LLVM_ENABLE_PROJECTS`

To use `ld` as the linker before this patch:

- default behaviour

To use `ld` as the linker after this patch:

- build with `-DCLANG_DEFAULT_LINKER=`

Note: After this patch, if you build `clang` for PowerPC Linux and `lld` is not
included in `LLVM_ENABLE_PROJECTS`, the built compiler will report an error
during linking on PowerPC Linux. Therefore, anyone using the default behaviour
before this patch will need to modify their build configuration to either:

- include `-DCLANG_DEFAULT_LINKER=` to continue using `ld` or
- `lld` in `LLVM_ENABLE_PROJECTS` to switch to `lld`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129855

Files:
  clang/lib/Driver/ToolChains/PPCLinux.h


Index: clang/lib/Driver/ToolChains/PPCLinux.h
===
--- clang/lib/Driver/ToolChains/PPCLinux.h
+++ clang/lib/Driver/ToolChains/PPCLinux.h
@@ -24,6 +24,8 @@
   AddClangSystemIncludeArgs(const llvm::opt::ArgList &DriverArgs,
 llvm::opt::ArgStringList &CC1Args) const override;
 
+  const char *getDefaultLinker() const override { return "ld.lld"; }
+
 private:
   bool SupportIEEEFloat128(const Driver &D, const llvm::Triple &Triple,
const llvm::opt::ArgList &Args) const;


Index: clang/lib/Driver/ToolChains/PPCLinux.h
===
--- clang/lib/Driver/ToolChains/PPCLinux.h
+++ clang/lib/Driver/ToolChains/PPCLinux.h
@@ -24,6 +24,8 @@
   AddClangSystemIncludeArgs(const llvm::opt::ArgList &DriverArgs,
 llvm::opt::ArgStringList &CC1Args) const override;
 
+  const char *getDefaultLinker() const override { return "ld.lld"; }
+
 private:
   bool SupportIEEEFloat128(const Driver &D, const llvm::Triple &Triple,
const llvm::opt::ArgList &Args) const;
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO for ELF and XCOFF.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 445628.
quinnp added a comment.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Updating patch with a `clang` change to properly forward `-data-sections=0` to 
`libLTO`/`gold` when `-fno-data-sections` is explicitly specified.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129401/new/

https://reviews.llvm.org/D129401

Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/lto-data-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,26 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=true %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=false %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   Symbols:
+; CHECK: - Name:var
+; CHECK-NEXT:  Type:STT_OBJECT
+; CHECK-NEXT:  Section: .bss.var
+
+; CHECK-NO-DATA-SECTIONS:  Symbols:
+; CHECK-NO-DATA-SECTIONS:- Name:var
+; CHECK-NO-DATA-SECTIONS-NEXT: Type:STT_OBJECT
+; CHECK-NO-DATA-SECTIONS-NEXT: Section: .bss
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,22 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=true %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=false %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK:  Symbols:
+; CHECK-NOT:- Name: .data
+
+; CHECK-NO-DATA-SECTIONS: Symbols:
+; CHECK-NO-DATA-SECTIONS:   - Name: .data
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,14 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default for ELF and XCOFF to match the behaviour of lld and gold plugin.
+  llvm::Triple::ObjectFormatType ObjectFormat = Triple.getObjectFormat();
+  if (!codegen::getExplicitDataSections() &&
+  (ObjectFormat == llvm::Triple::ObjectFormatType::ELF ||
+   ObjectFormat == llvm::Triple::ObjectFormatType::XCOFF))
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/lto-data-sections.c
===
--- /dev/null
+++ clang/test/Driver/lto-data-sections.c
@@ -0,0 +1,11 @@
+// RUN: touch %t.o
+// RUN: %clang %t.o -### -flto 2>&1 | FileCheck %s
+// RUN: %clang %t.o -### -flto 2>&1 -fdata-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-DATA-SECTIONS
+// RUN: %clang %t.o -### -flto 2>&1 -fno-data-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-NO-DATA-SECTIONS
+
+// CHECK-NOT: "-plugin-opt=-data-sections"
+// CHECK-NOT: "-plugin-opt=-data-sections=0"
+// CHECK-DATA-SECTIONS: "-plugin-opt=-data-sections"
+// CHECK-NO-DATA-SECTIONS: "-plugin-opt=-data-sections=0"
Index: clang/lib/Driver/ToolChains/CommonArgs.cpp
===
--- clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -576,6 +576

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO for ELF and XCOFF.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 445631.
quinnp added a comment.

Updating patch to forward `-data-sections=1` to `libLTO`/`gold` instead of just 
`-data-sections` when `-fdata-sections` is explicitly specified in `clang`. 
This is to be more explicit since `-data-sections=0` is now being forwared when 
`-fno-data-sections` is explicitly specified.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129401/new/

https://reviews.llvm.org/D129401

Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/lto-data-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,26 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=true %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=false %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   Symbols:
+; CHECK: - Name:var
+; CHECK-NEXT:  Type:STT_OBJECT
+; CHECK-NEXT:  Section: .bss.var
+
+; CHECK-NO-DATA-SECTIONS:  Symbols:
+; CHECK-NO-DATA-SECTIONS:- Name:var
+; CHECK-NO-DATA-SECTIONS-NEXT: Type:STT_OBJECT
+; CHECK-NO-DATA-SECTIONS-NEXT: Section: .bss
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,22 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=true %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=false %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK:  Symbols:
+; CHECK-NOT:- Name: .data
+
+; CHECK-NO-DATA-SECTIONS: Symbols:
+; CHECK-NO-DATA-SECTIONS:   - Name: .data
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,14 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default for ELF and XCOFF to match the behaviour of lld and gold plugin.
+  llvm::Triple::ObjectFormatType ObjectFormat = Triple.getObjectFormat();
+  if (!codegen::getExplicitDataSections() &&
+  (ObjectFormat == llvm::Triple::ObjectFormatType::ELF ||
+   ObjectFormat == llvm::Triple::ObjectFormatType::XCOFF))
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/lto-data-sections.c
===
--- /dev/null
+++ clang/test/Driver/lto-data-sections.c
@@ -0,0 +1,10 @@
+// RUN: touch %t.o
+// RUN: %clang %t.o -### -flto 2>&1 | FileCheck %s
+// RUN: %clang %t.o -### -flto 2>&1 -fdata-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-DATA-SECTIONS
+// RUN: %clang %t.o -### -flto 2>&1 -fno-data-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-NO-DATA-SECTIONS
+
+// CHECK-NOT: "-plugin-opt=-data-sections"
+// CHECK-DATA-SECTIONS: "-plugin-opt=-data-sections=1"
+// CHECK-NO-DATA-SECTIONS: "-plugin-opt=-data-sections=0"
Index: clang/lib/Driver/ToolChains/CommonArgs.cpp
===
--- clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ clang/lib/Driver/ToolChains/CommonArgs.cpp

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO for ELF and XCOFF.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 445634.
quinnp added a comment.

Addressing review comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129401/new/

https://reviews.llvm.org/D129401

Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/lto-data-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,26 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=true %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=false %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   Symbols:
+; CHECK: - Name:var
+; CHECK-NEXT:  Type:STT_OBJECT
+; CHECK-NEXT:  Section: .bss.var
+
+; CHECK-NO-DATA-SECTIONS:  Symbols:
+; CHECK-NO-DATA-SECTIONS:- Name:var
+; CHECK-NO-DATA-SECTIONS-NEXT: Type:STT_OBJECT
+; CHECK-NO-DATA-SECTIONS-NEXT: Section: .bss
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,22 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=true %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=false %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK:  Symbols:
+; CHECK-NOT:- Name: .data
+
+; CHECK-NO-DATA-SECTIONS: Symbols:
+; CHECK-NO-DATA-SECTIONS:   - Name: .data
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,14 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default for ELF and XCOFF to match the behaviour of lld and gold plugin.
+  llvm::Triple::ObjectFormatType ObjectFormat = Triple.getObjectFormat();
+  if (!codegen::getExplicitDataSections() &&
+  (ObjectFormat == llvm::Triple::ObjectFormatType::ELF ||
+   ObjectFormat == llvm::Triple::ObjectFormatType::XCOFF))
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/lto-data-sections.c
===
--- /dev/null
+++ clang/test/Driver/lto-data-sections.c
@@ -0,0 +1,10 @@
+// RUN: touch %t.o
+// RUN: %clang %t.o -### -flto 2>&1 | FileCheck %s
+// RUN: %clang %t.o -### -flto 2>&1 -fdata-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-DATA-SECTIONS
+// RUN: %clang %t.o -### -flto 2>&1 -fno-data-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-NO-DATA-SECTIONS
+
+// CHECK-NOT: "-plugin-opt=-data-sections"
+// CHECK-DATA-SECTIONS: "-plugin-opt=-data-sections=1"
+// CHECK-NO-DATA-SECTIONS: "-plugin-opt=-data-sections=0"
Index: clang/lib/Driver/ToolChains/CommonArgs.cpp
===
--- clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -572,9 +572,10 @@
   }
 
   if (Args.hasFlag(options::OPT_fdata_sections, options::OPT_fno_data_sections,
-   UseSeparateSections)) {
-CmdArgs.push_back("-plugin-opt=-data-sections");
-  }
+   UseSeparateSections))
+  

[PATCH] D129855: [clang][PowerPC] Set lld as clang's default linker for PowerPC Linux

[Quinn Pham via Phabricator via cfe-commits]

quinnp added a comment.

In D129855#3657006 , @MaskRay wrote:

> This is not right as using `ld.lld` as the default linker isn't the majority 
> case. If you want to change the default for your distribution, set 
> `-DCLANG_DEFAULT_LINKER=lld`.
> (Alternatively, you can have a `ld` symlink pointing to `lld`.)

Hi @MaskRay! Do you mean I should abandon this change or find a way to set the 
CMake variable `CLANG_DEFAULT_LINKER` to `lld` as default when building for 
PowerPC Linux? I wasn't able to find any examples of people setting CMake 
variables for specific distributions.

Thanks!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129855/new/

https://reviews.llvm.org/D129855

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO for ELF and XCOFF.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 445835.
quinnp marked an inline comment as done.
quinnp added a comment.

Fixing test case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129401/new/

https://reviews.llvm.org/D129401

Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/gold-lto-sections.c
  clang/test/Driver/lto-data-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,26 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=true %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=false %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   Symbols:
+; CHECK: - Name:var
+; CHECK-NEXT:  Type:STT_OBJECT
+; CHECK-NEXT:  Section: .bss.var
+
+; CHECK-NO-DATA-SECTIONS:  Symbols:
+; CHECK-NO-DATA-SECTIONS:- Name:var
+; CHECK-NO-DATA-SECTIONS-NEXT: Type:STT_OBJECT
+; CHECK-NO-DATA-SECTIONS-NEXT: Section: .bss
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,22 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=true %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=false %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK:  Symbols:
+; CHECK-NOT:- Name: .data
+
+; CHECK-NO-DATA-SECTIONS: Symbols:
+; CHECK-NO-DATA-SECTIONS:   - Name: .data
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,14 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default for ELF and XCOFF to match the behaviour of lld and gold plugin.
+  llvm::Triple::ObjectFormatType ObjectFormat = Triple.getObjectFormat();
+  if (!codegen::getExplicitDataSections() &&
+  (ObjectFormat == llvm::Triple::ObjectFormatType::ELF ||
+   ObjectFormat == llvm::Triple::ObjectFormatType::XCOFF))
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/lto-data-sections.c
===
--- /dev/null
+++ clang/test/Driver/lto-data-sections.c
@@ -0,0 +1,10 @@
+// RUN: touch %t.o
+// RUN: %clang %t.o -### -flto 2>&1 | FileCheck %s
+// RUN: %clang %t.o -### -flto 2>&1 -fdata-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-DATA-SECTIONS
+// RUN: %clang %t.o -### -flto 2>&1 -fno-data-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-NO-DATA-SECTIONS
+
+// CHECK-NOT: "-plugin-opt=-data-sections"
+// CHECK-DATA-SECTIONS: "-plugin-opt=-data-sections=1"
+// CHECK-NO-DATA-SECTIONS: "-plugin-opt=-data-sections=0"
Index: clang/test/Driver/gold-lto-sections.c
===
--- clang/test/Driver/gold-lto-sections.c
+++ clang/test/Driver/gold-lto-sections.c
@@ -5,4 +5,4 @@
 // RUN: -ffunction-sections -fdata-sections \
 // RUN: | FileCheck %s
 // CHECK: "-plugin-opt=-function-sections"
-// CHECK: "-plugin-opt=-data-sections"
+// CHECK: "-plugin-o

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO for ELF and XCOFF.

[Quinn Pham via Phabricator via cfe-commits]

quinnp added a comment.

> If this is for the legacy LTO interface, please state so.  `lld/*/LTO.cpp` 
> sets `c.Options.DataSections = true;` to enable data sections by default.

Hey @MaskRay, I'm not sure what is considered the legacy LTO interface, but 
this change is to make the `libLTO` codegen match the behaviour of `LTO` used 
through `lld` and `gold plugin`. Both `lld` and `gold plugin` turn on 
`data-sections` for `LTO` by default:

- as you mentioned `lld/*/LTO.cpp` sets `c.Options.DataSections = true;` by 
default.
- and `llvm/tools/gold/gold-plugin.cpp` sets `Conf.Options.DataSections = 
SplitSections;` provided that the user did not explicitly set/unset 
`data-sections` where `SplitSections` is `true` unless `gold plugin` is doing a 
relocatable link.

@hubert.reinterpretcast please correct me if I am wrong about why this change 
is needed.




Comment at: llvm/lib/LTO/LTOCodeGenerator.cpp:351
+  llvm::Triple::ObjectFormatType ObjectFormat = Triple.getObjectFormat();
+  if (!codegen::getExplicitDataSections() &&
+  (ObjectFormat == llvm::Triple::ObjectFormatType::ELF ||

hubert.reinterpretcast wrote:
> w2yehia wrote:
> > quinnp wrote:
> > > w2yehia wrote:
> > > > any reason we do this for ELF and XCOFF only?
> > > I don't think there is a particular reason that we do this for ELF and 
> > > XCOFF only. We needed this fixed for `AIX` (`XCOFF`) and wanted to change 
> > > `Linux` (`ELF`) to match the behaviour of `lld`/`gold` at the same time. 
> > > I'm not sure what other file formats need for this so I did not include 
> > > them.
> > > 
> > > @hubert.reinterpretcast might have a better answer for this.
> > I don't know either about the other formats, was just wondering.
> > I think it's safe to do it for the file formats that we know are currently 
> > different between libLTO and lld/gold. The proposed change is an 
> > improvement with minimal risk.
> I agree with @w2yehia that we should change the data-sections to "on" by 
> default in libLTO for the other file formats where one of lld/the gold plugin 
> sets it to "on".
@hubert.reinterpretcast I think that if we want to change `data-sections` to 
"on" by default for any file format which  `lld` or `gold plugin` set 
data-sections to "on", we would set `data-sections` to "on" for all file 
formats. This is because `gold plugin` does not check the file format when it 
is setting `data-sections`. You can see where `gold plugin` sets 
`data-sections` here: 
https://github.com/llvm/llvm-project/blob/main/llvm/tools/gold/gold-plugin.cpp#L893

Do you suggest that we remove the checks for file format when setting 
`data-sections` in `libLTO`? ie. change the `if` statement to this:
```
if (!codegen::getExplicitDataSections())
  Config.Options.DataSections = true;
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129401/new/

https://reviews.llvm.org/D129401

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO for ELF and XCOFF.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 445839.
quinnp added a comment.

Modifying a test to fix check lines.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129401/new/

https://reviews.llvm.org/D129401

Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/gold-lto-sections.c
  clang/test/Driver/lto-data-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,26 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=true %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=false %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   Symbols:
+; CHECK: - Name:var
+; CHECK-NEXT:  Type:STT_OBJECT
+; CHECK-NEXT:  Section: .bss.var
+
+; CHECK-NO-DATA-SECTIONS:  Symbols:
+; CHECK-NO-DATA-SECTIONS:- Name:var
+; CHECK-NO-DATA-SECTIONS-NEXT: Type:STT_OBJECT
+; CHECK-NO-DATA-SECTIONS-NEXT: Section: .bss
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,22 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=true %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=false %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK:  Symbols:
+; CHECK-NOT:- Name: .data
+
+; CHECK-NO-DATA-SECTIONS: Symbols:
+; CHECK-NO-DATA-SECTIONS:   - Name: .data
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,14 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default for ELF and XCOFF to match the behaviour of lld and gold plugin.
+  llvm::Triple::ObjectFormatType ObjectFormat = Triple.getObjectFormat();
+  if (!codegen::getExplicitDataSections() &&
+  (ObjectFormat == llvm::Triple::ObjectFormatType::ELF ||
+   ObjectFormat == llvm::Triple::ObjectFormatType::XCOFF))
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/lto-data-sections.c
===
--- /dev/null
+++ clang/test/Driver/lto-data-sections.c
@@ -0,0 +1,11 @@
+// RUN: touch %t.o
+// RUN: %clang %t.o -### -flto 2>&1 | FileCheck %s
+// RUN: %clang %t.o -### -flto 2>&1 -fdata-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-DATA-SECTIONS
+// RUN: %clang %t.o -### -flto 2>&1 -fno-data-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-NO-DATA-SECTIONS
+
+// CHECK-NOT: "-plugin-opt=-data-sections=1"
+// CHECK-NOT: "-plugin-opt=-data-sections=0"
+// CHECK-DATA-SECTIONS: "-plugin-opt=-data-sections=1"
+// CHECK-NO-DATA-SECTIONS: "-plugin-opt=-data-sections=0"
Index: clang/test/Driver/gold-lto-sections.c
===
--- clang/test/Driver/gold-lto-sections.c
+++ clang/test/Driver/gold-lto-sections.c
@@ -5,4 +5,4 @@
 // RUN: -ffunction-sections -fdata-sections \
 // RUN: | FileCheck %s
 // CHECK: "-plugin-opt=-function-sections"
-// CHECK: "-plugin-opt=-data-secti

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 446147.
quinnp marked 6 inline comments as done.
quinnp added a comment.

Addressing review comments. Fixing the forwarding for -fno-function-sectons and 
removing the ObjectFormatType check.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129401/new/

https://reviews.llvm.org/D129401

Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/forwarding-sections-liblto.c
  clang/test/Driver/gold-lto-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,26 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   Symbols:
+; CHECK: - Name:var
+; CHECK-NEXT:  Type:STT_OBJECT
+; CHECK-NEXT:  Section: .bss.var
+
+; CHECK-NO-DATA-SECTIONS:  Symbols:
+; CHECK-NO-DATA-SECTIONS:- Name:var
+; CHECK-NO-DATA-SECTIONS-NEXT: Type:STT_OBJECT
+; CHECK-NO-DATA-SECTIONS-NEXT: Section: .bss
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,22 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: obj2yaml %t/default.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/data-sections.o | FileCheck --match-full-lines %s
+; RUN: obj2yaml %t/no-data-sections.o | FileCheck --match-full-lines \
+; RUN:   --check-prefix CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK:  Symbols:
+; CHECK-NOT:- Name: .data
+
+; CHECK-NO-DATA-SECTIONS: Symbols:
+; CHECK-NO-DATA-SECTIONS:   - Name: .data
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,11 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default to match the behaviour of lld and gold plugin.
+  if (!codegen::getExplicitDataSections())
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/gold-lto-sections.c
===
--- clang/test/Driver/gold-lto-sections.c
+++ clang/test/Driver/gold-lto-sections.c
@@ -4,5 +4,5 @@
 // RUN: -Wl,-plugin-opt=foo -O3 \
 // RUN: -ffunction-sections -fdata-sections \
 // RUN: | FileCheck %s
-// CHECK: "-plugin-opt=-function-sections"
-// CHECK: "-plugin-opt=-data-sections"
+// CHECK: "-plugin-opt=-function-sections=1"
+// CHECK: "-plugin-opt=-data-sections=1"
Index: clang/test/Driver/forwarding-sections-liblto.c
===
--- /dev/null
+++ clang/test/Driver/forwarding-sections-liblto.c
@@ -0,0 +1,15 @@
+// RUN: touch %t.o
+// RUN: %clang %t.o -### -flto 2>&1 | FileCheck %s
+// RUN: %clang %t.o -### -flto 2>&1 -ffunction-sections -fdata-sections | \
+// RUN:   FileCheck %s --check-prefix=CHECK-SECTIONS
+// RUN: %clang %t.o -### -flto 2>&1 -fno-function-sections -fno-data-sections \
+// RUN:   | FileCheck %s --check-prefix=CHECK-NO-SECTIONS
+
+// CHECK-NOT: "-plugin-opt=-function-sections=1"
+// CHECK-NOT: "-plugin-opt=-function-sections=0"
+// CHECK-NOT: "-plugin-opt=-

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 446228.
quinnp marked an inline comment as done.
quinnp added a comment.

Addressing review comments. Changing test cases to use `llvm-objdump -t` 
instead of `obj2yaml`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129401/new/

https://reviews.llvm.org/D129401

Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/forwarding-sections-liblto.c
  clang/test/Driver/gold-lto-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,25 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:  SYMBOL TABLE:
+; CHECK:  .bss.var
+; CHECK-SAME: var
+
+; CHECK-NO-DATA-SECTIONS:  SYMBOL TABLE:
+; CHECK-NO-DATA-SECTIONS:  .bss
+; CHECK-NO-DATA-SECTIONS-NOT:  .var
+; CHECK-NO-DATA-SECTIONS-SAME: var
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,25 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK:  SYMBOL TABLE:
+; CHECK:  .data
+; CHECK-NOT:  (csect: .data)
+; CHECK-SAME: var
+
+; CHECK-NO-DATA-SECTIONS:  SYMBOL TABLE:
+; CHECK-NO-DATA-SECTIONS:  .data (csect: .data)
+; CHECK-NO-DATA-SECTIONS-SAME: var
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,11 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default to match the behaviour of lld and gold plugin.
+  if (!codegen::getExplicitDataSections())
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/gold-lto-sections.c
===
--- clang/test/Driver/gold-lto-sections.c
+++ clang/test/Driver/gold-lto-sections.c
@@ -4,5 +4,5 @@
 // RUN: -Wl,-plugin-opt=foo -O3 \
 // RUN: -ffunction-sections -fdata-sections \
 // RUN: | FileCheck %s
-// CHECK: "-plugin-opt=-function-sections"
-// CHECK: "-plugin-opt=-data-sections"
+// CHECK: "-plugin-opt=-function-sections=1"
+// CHECK: "-plugin-opt=-data-sections=1"
Index: clang/test/Driver/forwarding-sections-liblto.c
===
--- /dev/null
+++ clang/test/Driver/forwarding-sections-liblto.c
@@ -0,0 +1,15 @@
+// RUN: touch %t.o
+// RUN: %clang %t.o -### -flto 2>&1 | FileCheck %s
+// RUN: %clang %t.o -### -flto 2>&1 -ffunction-sections -fdata-sections | \
+// RUN:   FileCheck %s --check-prefix=CHECK-SECTIONS
+// RUN: %clang %t.o -### -flto 2>&1 -fno-function-sections -fno-data-sections \
+// RUN:   | FileCheck %s --check-prefix=CHECK-NO-SECTIONS
+
+// CHECK-NOT: "-plugin-opt=-function-sections=1"
+// CHECK-NOT: "-plugin-opt=-function-sections=0"
+// CHECK-NOT: "-plugin-opt=-data-sections=1"
+// CHECK-NOT: "-plugin-opt=-data-sections=0"
+// CHECK-SECTIONS: "-plugin-opt=-function-sections=1"
+// CHECK-SECTIONS: "-plugin-opt=-data-sections=1"
+// CHECK-NO-SEC

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO.

[Quinn Pham via Phabricator via cfe-commits]

quinnp added a comment.

In D129401#3666238 , @MaskRay wrote:

> Mostly looks good, with a nit in the test and some suggestion to the summary.
>
> In D129401#3662857 , @quinnp wrote:
>
>>> If this is for the legacy LTO interface, please state so.  `lld/*/LTO.cpp` 
>>> sets `c.Options.DataSections = true;` to enable data sections by default.
>>
>> Hey @MaskRay, I'm not sure what is considered the legacy LTO interface, but 
>> this change is to make the `libLTO` codegen match the behaviour of `LTO` 
>> used through `lld` and `gold plugin`. Both `lld` and `gold plugin` turn on 
>> `data-sections` for `LTO` by default:
>>
>> - as you mentioned `lld/*/LTO.cpp` sets `c.Options.DataSections = true;` by 
>> default.
>> - and `llvm/tools/gold/gold-plugin.cpp` sets `Conf.Options.DataSections = 
>> SplitSections;` provided that the user did not explicitly set/unset 
>> `data-sections` where `SplitSections` is `true` unless `gold plugin` is 
>> doing a relocatable link.
>
> There is a legacy LTO interface (see 
> llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h) and a resolution-based 
> interface.
> Change libLTO in "This patch changes libLTO to set data-sections by default." 
> to legacy LTO.
>
>> This patch also fixes the forwarding of the clang options -fno-data-sections 
>> and -fno-function-sections to libLTO
>
> This sentence can keep using libLTO or LLVMLTO (the library is LLVMLTO per 
> llvm/lib/LTO/CMakeLists.txt)

Ah I see, thank you @MaskRay! I've updated the testcases and the summary.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129401/new/

https://reviews.llvm.org/D129401

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 446597.
quinnp marked 3 inline comments as done.
quinnp added a comment.

Adressed review comments.

- Modified how `llvm-lto` test-cases check the `llvm-objdump -t` output.
- Renamed `gold-lto-sections.c` to `forwarding-sections-liblto.c` and modified 
the test to use the `RUN` lines from `forwarding-sections-liblto.c` with the 
target specified using `--target=`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129401/new/

https://reviews.llvm.org/D129401

Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/forwarding-sections-liblto.c
  clang/test/Driver/gold-lto-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,21 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   g O .bss.var {{.*}} var
+
+; CHECK-NO-DATA-SECTIONS-NOT: .var
+; CHECK-NO-DATA-SECTIONS:  g O .bss {{.*}} var
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,21 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK-NOT:  (csect: .data)
+; CHECK:   g O .data {{.*}} var
+
+; CHECK-NO-DATA-SECTIONS:  g O .data (csect: .data) {{.*}} var
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,11 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default to match the behaviour of lld and gold plugin.
+  if (!codegen::getExplicitDataSections())
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/gold-lto-sections.c
===
--- clang/test/Driver/gold-lto-sections.c
+++ /dev/null
@@ -1,8 +0,0 @@
-// RUN: touch %t.o
-//
-// RUN: %clang -target x86_64-unknown-linux -### %t.o -flto 2>&1 \
-// RUN: -Wl,-plugin-opt=foo -O3 \
-// RUN: -ffunction-sections -fdata-sections \
-// RUN: | FileCheck %s
-// CHECK: "-plugin-opt=-function-sections"
-// CHECK: "-plugin-opt=-data-sections"
Index: clang/test/Driver/forwarding-sections-liblto.c
===
--- /dev/null
+++ clang/test/Driver/forwarding-sections-liblto.c
@@ -0,0 +1,17 @@
+// RUN: touch %t.o
+// RUN: %clang --target=x86_64-unknown-linux -### %t.o -flto 2>&1 | FileCheck %s
+// RUN: %clang --target=x86_64-unknown-linux -### %t.o -flto 2>&1 \
+// RUN:   -ffunction-sections -fdata-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-SECTIONS
+// RUN: %clang --target=x86_64-unknown-linux -### %t.o -flto 2>&1 \
+// RUN:   -fno-function-sections -fno-data-sections | FileCheck %s \
+// RUN:   --check-prefix=CHECK-NO-SECTIONS
+
+// CHECK-NOT: "-plugin-opt=-function-sections=1"
+// CHECK-NOT: "-plugin-opt=-function-sections=0"
+// CHECK-NOT: "-plugin-opt=-data-sectio

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO.

[Quinn Pham via Phabricator via cfe-commits]

quinnp added inline comments.



Comment at: clang/lib/Driver/ToolChains/CommonArgs.cpp:579
+  else if (Args.hasArg(options::OPT_fno_data_sections))
+CmdArgs.push_back("-plugin-opt=-data-sections=0");
 

MaskRay wrote:
> Is -plugin-opt=-data-sections=0 a problem for `!UseSeparateSections` targets?
I don't think `-plugin-opt=-data-sections=0` is a problem for 
`!UseSeparateSections` targets because we only add 
`"-plugin-opt=-data-sections=0"` if the user explicitly specified 
`-fno-data-sections`.  
- If `UseSeparateSections` is `true`, we will enter the  `if` block unless 
`-fno-data-sections` is explicitly set.
- If `UseSeparateSections` is `false`, we will enter the `if` block only if  
`-fdata-sections` is explicitly set.

Then, if we did not enter the `if` block, we will only enter the `else if` 
block when `-fno-data-sections` is explicitly set.



Comment at: llvm/test/LTO/PowerPC/data-sections-linux.ll:20
+
+; CHECK-NO-DATA-SECTIONS-NOT: .var
+; CHECK-NO-DATA-SECTIONS:  g O .bss {{.*}} var

MaskRay wrote:
> What does this `...-NOT: .var` do?
The line `; CHECK-NO-DATA-SECTIONS-NOT: .var` is to ensure that `data-sections` 
is correctly turned off. On Linux, when `data-sections` is on each variable `X` 
will have its own section named `.bss.X`. Here, I am trying to make sure that 
the the `.X` part is not present since it may have been consumed by the 
`{{.*}}` after the check for `.bss` on the next line.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129401/new/

https://reviews.llvm.org/D129401

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D129401: [libLTO] Set data-sections by default in libLTO.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 447336.
quinnp marked 3 inline comments as done.
quinnp added a comment.

Adressing review comments. Moving tests into `function-sections.c`, using `%s` 
instead of creating a new file with `touch`, and modifying some `CHECK` lines 
to simplify checks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129401/new/

https://reviews.llvm.org/D129401

Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/function-sections.c
  clang/test/Driver/gold-lto-sections.c
  llvm/lib/LTO/LTOCodeGenerator.cpp
  llvm/test/LTO/PowerPC/data-sections-aix.ll
  llvm/test/LTO/PowerPC/data-sections-linux.ll

Index: llvm/test/LTO/PowerPC/data-sections-linux.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-linux.ll
@@ -0,0 +1,21 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@var = global i32 0
+
+; CHECK:   g O .bss.var {{.*}} var
+
+; CHECK-NO-DATA-SECTIONS-NOT: .var
+; CHECK-NO-DATA-SECTIONS:  g O .bss {{.*}} var
Index: llvm/test/LTO/PowerPC/data-sections-aix.ll
===
--- /dev/null
+++ llvm/test/LTO/PowerPC/data-sections-aix.ll
@@ -0,0 +1,21 @@
+; RUN: rm -rf %t
+; RUN: mkdir %t
+; RUN: llvm-as %s -o %t/bc.bc
+; RUN: llvm-lto -exported-symbol var -O0 %t/bc.bc -o %t/default.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=1 %t/bc.bc -o \
+; RUN:   %t/data-sections.o
+; RUN: llvm-lto -exported-symbol var -O0 --data-sections=0 %t/bc.bc -o \
+; RUN:   %t/no-data-sections.o
+; RUN: llvm-objdump -t %t/default.o | FileCheck %s
+; RUN: llvm-objdump -t %t/data-sections.o | FileCheck %s
+; RUN: llvm-objdump -t %t/no-data-sections.o | FileCheck --check-prefix \
+; RUN:   CHECK-NO-DATA-SECTIONS %s
+
+target triple = "powerpc-ibm-aix7.2.0.0"
+
+@var = global i32 0
+
+; CHECK-NOT:  (csect: .data)
+; CHECK:   g O .data {{.*}} var
+
+; CHECK-NO-DATA-SECTIONS:  g O .data (csect: .data) {{.*}} var
Index: llvm/lib/LTO/LTOCodeGenerator.cpp
===
--- llvm/lib/LTO/LTOCodeGenerator.cpp
+++ llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
+#include "llvm/CodeGen/CommandFlags.h"
 #include "llvm/CodeGen/ParallelCG.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Config/config.h"
@@ -344,6 +345,11 @@
   Config.CPU = "cyclone";
   }
 
+  // If data-sections is not explicitly set or unset, set data-sections by
+  // default to match the behaviour of lld and gold plugin.
+  if (!codegen::getExplicitDataSections())
+Config.Options.DataSections = true;
+
   TargetMach = createTargetMachine();
   assert(TargetMach && "Unable to create target machine");
 
Index: clang/test/Driver/gold-lto-sections.c
===
--- clang/test/Driver/gold-lto-sections.c
+++ /dev/null
@@ -1,8 +0,0 @@
-// RUN: touch %t.o
-//
-// RUN: %clang -target x86_64-unknown-linux -### %t.o -flto 2>&1 \
-// RUN: -Wl,-plugin-opt=foo -O3 \
-// RUN: -ffunction-sections -fdata-sections \
-// RUN: | FileCheck %s
-// CHECK: "-plugin-opt=-function-sections"
-// CHECK: "-plugin-opt=-data-sections"
Index: clang/test/Driver/function-sections.c
===
--- clang/test/Driver/function-sections.c
+++ clang/test/Driver/function-sections.c
@@ -6,6 +6,12 @@
 // CHECK-NODS-NOT: -fdata-sections
 // CHECK-US-NOT: -fno-unique-section-names
 // CHECK-NOUS: -fno-unique-section-names
+// CHECK-PLUGIN-DEFAULT-NOT: "-plugin-opt=-function-sections
+// CHECK-PLUGIN-DEFAULT-NOT: "-plugin-opt=-data-sections
+// CHECK-PLUGIN-SECTIONS: "-plugin-opt=-function-sections=1"
+// CHECK-PLUGIN-SECTIONS: "-plugin-opt=-data-sections=1"
+// CHECK-PLUGIN-NO-SECTIONS: "-plugin-opt=-function-sections=0"
+// CHECK-PLUGIN-NO-SECTIONS: "-plugin-opt=-data-sections=0"
 
 // RUN: %clang -### %s -fsyntax-only 2>&1   \
 // RUN: --target=i386-unknown-linux \
@@ -72,3 +78,18 @@
 // RUN: --target=i386-unknown-linux \
 // RUN: -fno-unique-section-names \
 // RUN:   | FileCheck --che

[PATCH] D102443: [PowerPC] Added multiple PowerPC builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added subscribers: shchenz, kbarton, hiraditya, nemanjai.
quinnp requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Most of the builtins already had intrinsics and only needed to be
implemented in the front end. Intrinsics were created for the three
iospace builtins, eieio, and icbt. Pseudo instructions were created for
eieio and iospace_eieio to ensure that nops were inserted before the
eieio instruction.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102443

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
  llvm/test/CodeGen/PowerPC/eieio.ll

Index: llvm/test/CodeGen/PowerPC/eieio.ll
===
--- llvm/test/CodeGen/PowerPC/eieio.ll
+++ llvm/test/CodeGen/PowerPC/eieio.ll
@@ -4,7 +4,9 @@
 
 define void @eieio_test() {
 ; CHECK-LABEL: @eieio_test
-; CHECK: eieio
+; CHECK: ori r2, r2, 0
+; CHECK-NEXT: ori r2, r2, 0
+; CHECK-NEXT: eieio
 ; CHECK-NEXT: blr
 
 entry:
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
@@ -0,0 +1,74 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_eieio
+
+entry:
+  call void @llvm.ppc.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_eieio
+
+entry:
+  call void @llvm.ppc.iospace.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.iospace.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: lwsync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.lwsync() #2
+
+define dso_local void @test_builtin_ppc_iospace_sync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: sync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.sync() #2
+
+define dso_local void @test_builtin_ppc_icbt() #0 {
+; CHECK-LABEL: test_builtin_ppc_icbt
+
+entry:
+  %a = alloca i8*, align 8
+  %0 = load i8*, i8** %a, align 8
+  call void @llvm.ppc.icbt(i8* %0)
+; CHECK: icbt 0, 0, 3
+
+  ret void
+}
+
+declare void @llvm.ppc.icbt(i8*) #2
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
@@ -0,0 +1,33 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: msync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.lwsync() #2
+
+define dso_local void @test_builtin_ppc_iospace_sync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: msync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.sync() #2
+
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2019,6 +2019,8 @@
   (DCBTST 0, xoaddr:$dst)>;
 def : Pat<(int_ppc_dcbf xoaddr:$dst),
   (DCBF 0, xoaddr:$dst)>;
+def : Pat<(int_ppc_icbt xoaddr:$dst),
+  (ICBT 0, xoaddr:$dst)>;
 
 def : Pat<(prefetch xoa

[PATCH] D102443: [PowerPC] Added multiple PowerPC builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 345510.
quinnp added a comment.

Fixed some formatting.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102443/new/

https://reviews.llvm.org/D102443

Files:
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp


Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
===
--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -1354,13 +1354,13 @@
   case PPC::PseudoEIEIO:
   case PPC::PseudoIOSPACEEIEIO: {  
 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::ORI)
-  .addReg(PPC::X2)
-  .addReg(PPC::X2)
-  .addImm(0));
+  .addReg(PPC::X2)
+  .addReg(PPC::X2)
+  .addImm(0));
 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::ORI)
-   .addReg(PPC::X2)
-   .addReg(PPC::X2)
-   .addImm(0));
+  .addReg(PPC::X2)
+  .addReg(PPC::X2)
+  .addImm(0));
 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::EnforceIEIO));   
   return;
   }


Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
===
--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -1354,13 +1354,13 @@
   case PPC::PseudoEIEIO:
   case PPC::PseudoIOSPACEEIEIO: {	
 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::ORI)
-		   .addReg(PPC::X2)
-		   .addReg(PPC::X2)
-		   .addImm(0));
+  .addReg(PPC::X2)
+  .addReg(PPC::X2)
+  .addImm(0));
 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::ORI)
-   .addReg(PPC::X2)
-   .addReg(PPC::X2)
-   .addImm(0));
+  .addReg(PPC::X2)
+  .addReg(PPC::X2)
+  .addImm(0));
 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::EnforceIEIO));   
   return;
   }
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D102443: [PowerPC] Added multiple PowerPC builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 345512.
quinnp added a comment.

[PowerPC] Fixing previous update.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102443/new/

https://reviews.llvm.org/D102443

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/test/CodeGen/builtins-ppc-xlcompat.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat.ll
@@ -0,0 +1,67 @@
+; RUN: llc < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_eieio
+
+entry:
+  call void @llvm.ppc.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_eieio
+
+entry:
+  call void @llvm.ppc.iospace.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.iospace.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: lwsync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.lwsync() #2
+
+define dso_local void @test_builtin_ppc_iospace_sync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: sync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.sync() #2
+
+define dso_local void @test_builtin_ppc_icbt() #0 {
+; CHECK-LABEL: test_builtin_ppc_icbt
+
+entry:
+  %a = alloca i8*, align 8
+  %0 = load i8*, i8** %a, align 8
+  call void @llvm.ppc.icbt(i8* %0)
+; CHECK: icbt 0, 0, 3
+
+  ret void
+}
+
+declare void @llvm.ppc.icbt(i8*) #2
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2044,6 +2044,8 @@
   (DCBTST 0, xoaddr:$dst)>;
 def : Pat<(int_ppc_dcbf xoaddr:$dst),
   (DCBF 0, xoaddr:$dst)>;
+def : Pat<(int_ppc_icbt xoaddr:$dst),
+  (ICBT 0, xoaddr:$dst)>;
 
 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
   (DCBT 0, xoaddr:$dst)>;   // data prefetch for loads
@@ -2565,11 +2567,21 @@
 def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
  "eieio", IIC_LdStLoad, []>;
 
+def PseudoEIEIO : PPCEmitTimePseudo<(outs), (ins), "#PPCEIEIO",
+  [(int_ppc_eieio)]>;
+def PseudoIOSPACEEIEIO : PPCEmitTimePseudo<(outs), (ins), "#PPCIOSPACEEIEIO",
+ [(int_ppc_iospace_eieio)]>;
+
 def : Pat<(int_ppc_sync),   (SYNC 0)>, Requires<[HasSYNC]>;
+def : Pat<(int_ppc_iospace_sync),   (SYNC 0)>, Requires<[HasSYNC]>;
 def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
+def : Pat<(int_ppc_iospace_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
 def : Pat<(int_ppc_sync),   (MSYNC)>, Requires<[HasOnlyMSYNC]>;
+def : Pat<(int_ppc_iospace_sync),   (MSYNC)>, Requires<[HasOnlyMSYNC]>;
 def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
+def : Pat<(int_ppc_iospace_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
 def : Pat<(int_ppc_eieio),  (EnforceIEIO)>;
+def : Pat<(int_ppc_iospace_eieio),  (EnforceIEIO)>;
 
 //===--===//
 // PPC32 Arithmetic Instructions.
Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
===
--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -1351,6 +1351,16 @@
 // Now process the instruction normally.
 break;
   }
+  case PPC::PseudoEIEIO:
+  case PPC::PseudoIOSPACEEIEIO:
+EmitToStreamer(
+*OutStreamer,
+MCInstBuilder(PPC::ORI).addReg(PPC::X2).addReg(PPC::X2).addImm(0));
+EmitToStreamer(
+*OutStreamer,
+MCInstBuilder(PPC::ORI).addReg(PPC::X2).addReg(PPC::X2).addImm(0));
+EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::EnforceIEIO));
+break;
   }
 
   LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -20,34 +20,53 @@
   def int_ppc_dcba  : Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbf : GCCBuiltin<"__builtin_dcbf">,
   Intrinsic<[], [llvm_ptr_ty], [IntrArgMemOnly]>;
-  def int_ppc_dcbfl : Intrinsic<[], [llvm_ptr_ty], [IntrArgMemOnly]>;
-  def int_ppc_dcbflp : Intrin

[PATCH] D102443: [PowerPC] Added multiple PowerPC builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 345515.
quinnp added a comment.

Removing redundant tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102443/new/

https://reviews.llvm.org/D102443

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat.ll
@@ -0,0 +1,67 @@
+; RUN: llc < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_eieio
+
+entry:
+  call void @llvm.ppc.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_eieio
+
+entry:
+  call void @llvm.ppc.iospace.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.iospace.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: lwsync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.lwsync() #2
+
+define dso_local void @test_builtin_ppc_iospace_sync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: sync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.sync() #2
+
+define dso_local void @test_builtin_ppc_icbt() #0 {
+; CHECK-LABEL: test_builtin_ppc_icbt
+
+entry:
+  %a = alloca i8*, align 8
+  %0 = load i8*, i8** %a, align 8
+  call void @llvm.ppc.icbt(i8* %0)
+; CHECK: icbt 0, 0, 3
+
+  ret void
+}
+
+declare void @llvm.ppc.icbt(i8*) #2
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2044,6 +2044,8 @@
   (DCBTST 0, xoaddr:$dst)>;
 def : Pat<(int_ppc_dcbf xoaddr:$dst),
   (DCBF 0, xoaddr:$dst)>;
+def : Pat<(int_ppc_icbt xoaddr:$dst),
+  (ICBT 0, xoaddr:$dst)>;
 
 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
   (DCBT 0, xoaddr:$dst)>;   // data prefetch for loads
@@ -2565,11 +2567,21 @@
 def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
  "eieio", IIC_LdStLoad, []>;
 
+def PseudoEIEIO : PPCEmitTimePseudo<(outs), (ins), "#PPCEIEIO",
+  [(int_ppc_eieio)]>;
+def PseudoIOSPACEEIEIO : PPCEmitTimePseudo<(outs), (ins), "#PPCIOSPACEEIEIO",
+ [(int_ppc_iospace_eieio)]>;
+
 def : Pat<(int_ppc_sync),   (SYNC 0)>, Requires<[HasSYNC]>;
+def : Pat<(int_ppc_iospace_sync),   (SYNC 0)>, Requires<[HasSYNC]>;
 def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
+def : Pat<(int_ppc_iospace_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
 def : Pat<(int_ppc_sync),   (MSYNC)>, Requires<[HasOnlyMSYNC]>;
+def : Pat<(int_ppc_iospace_sync),   (MSYNC)>, Requires<[HasOnlyMSYNC]>;
 def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
+def : Pat<(int_ppc_iospace_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
 def : Pat<(int_ppc_eieio),  (EnforceIEIO)>;
+def : Pat<(int_ppc_iospace_eieio),  (EnforceIEIO)>;
 
 //===--===//
 // PPC32 Arithmetic Instructions.
Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
===
--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -1351,6 +1351,16 @@
 // Now process the instruction normally.
 break;
   }
+  case PPC::PseudoEIEIO:
+  case PPC::PseudoIOSPACEEIEIO:
+EmitToStreamer(
+*OutStreamer,
+MCInstBuilder(PPC::ORI).addReg(PPC::X2).addReg(PPC::X2).addImm(0));
+EmitToStreamer(
+*OutStreamer,
+MCInstBuilder(PPC::ORI).addReg(PPC::X2).addReg(PPC::X2).addImm(0));
+EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::EnforceIEIO));
+break;
   }
 
   LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -20,34 +20,53 @@
   def int_ppc_dcba  : Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbf : GCCBuiltin<"__builtin_dcbf">,
   Intrinsic<[], [llvm_ptr_ty], [IntrArgMemOnly]>;
-  def int_ppc_dcbfl : Intrinsic<[], [llvm_ptr_ty], [IntrArgMemOnly]>;
-  def int_ppc_dcbflp : Intrinsic<[], [llvm_ptr_ty], [IntrArgMemOnly]>;
+  def int_

[PATCH] D102443: [PowerPC] Added multiple PowerPC builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 345517.
quinnp added a comment.

Re-added some changes that were lost in the previous updates.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102443/new/

https://reviews.llvm.org/D102443

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
  llvm/test/CodeGen/PowerPC/eieio.ll

Index: llvm/test/CodeGen/PowerPC/eieio.ll
===
--- llvm/test/CodeGen/PowerPC/eieio.ll
+++ llvm/test/CodeGen/PowerPC/eieio.ll
@@ -4,7 +4,9 @@
 
 define void @eieio_test() {
 ; CHECK-LABEL: @eieio_test
-; CHECK: eieio
+; CHECK: ori r2, r2, 0
+; CHECK-NEXT: ori r2, r2, 0
+; CHECK-NEXT: eieio
 ; CHECK-NEXT: blr
 
 entry:
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
@@ -0,0 +1,74 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_eieio
+
+entry:
+  call void @llvm.ppc.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_eieio
+
+entry:
+  call void @llvm.ppc.iospace.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.iospace.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: lwsync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.lwsync() #2
+
+define dso_local void @test_builtin_ppc_iospace_sync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: sync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.sync() #2
+
+define dso_local void @test_builtin_ppc_icbt() #0 {
+; CHECK-LABEL: test_builtin_ppc_icbt
+
+entry:
+  %a = alloca i8*, align 8
+  %0 = load i8*, i8** %a, align 8
+  call void @llvm.ppc.icbt(i8* %0)
+; CHECK: icbt 0, 0, 3
+
+  ret void
+}
+
+declare void @llvm.ppc.icbt(i8*) #2
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
@@ -0,0 +1,33 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: msync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.lwsync() #2
+
+define dso_local void @test_builtin_ppc_iospace_sync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: msync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.sync() #2
+
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2044,6 +2044,8 @@
   (DCBTST 0, xoaddr:$dst)>;
 def : Pat<(int_ppc_dcbf xoaddr:$dst),
   (DCBF 0, xoaddr:$dst)>;
+def : Pat<(int_ppc_icbt xoaddr:$dst),
+  (ICBT 0, xoaddr:$dst)>;
 
 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
   (DCBT 0, xoaddr:$dst)>;   // data prefetch for loads
@@ -2565,11 +2567,21 @@
 def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
  "eieio", IIC_LdStLoad, []>;
 
+def PseudoEIEIO : PPCEmitTimePseudo<(outs), (ins), "#PPCEIEIO",
+

[PATCH] D102443: [PowerPC] Added multiple PowerPC builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 345519.
quinnp added a comment.

Removed some unused checks in a test.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102443/new/

https://reviews.llvm.org/D102443

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
  llvm/test/CodeGen/PowerPC/eieio.ll

Index: llvm/test/CodeGen/PowerPC/eieio.ll
===
--- llvm/test/CodeGen/PowerPC/eieio.ll
+++ llvm/test/CodeGen/PowerPC/eieio.ll
@@ -4,7 +4,9 @@
 
 define void @eieio_test() {
 ; CHECK-LABEL: @eieio_test
-; CHECK: eieio
+; CHECK: ori r2, r2, 0
+; CHECK-NEXT: ori r2, r2, 0
+; CHECK-NEXT: eieio
 ; CHECK-NEXT: blr
 
 entry:
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
@@ -0,0 +1,74 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_eieio
+
+entry:
+  call void @llvm.ppc.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_eieio
+
+entry:
+  call void @llvm.ppc.iospace.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.iospace.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: lwsync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.lwsync() #2
+
+define dso_local void @test_builtin_ppc_iospace_sync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: sync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.sync() #2
+
+define dso_local void @test_builtin_ppc_icbt() #0 {
+; CHECK-LABEL: test_builtin_ppc_icbt
+
+entry:
+  %a = alloca i8*, align 8
+  %0 = load i8*, i8** %a, align 8
+  call void @llvm.ppc.icbt(i8* %0)
+; CHECK: icbt 0, 0, 3
+
+  ret void
+}
+
+declare void @llvm.ppc.icbt(i8*) #2
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
@@ -0,0 +1,33 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: msync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.lwsync() #2
+
+define dso_local void @test_builtin_ppc_iospace_sync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: msync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.sync() #2
+
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2044,6 +2044,8 @@
   (DCBTST 0, xoaddr:$dst)>;
 def : Pat<(int_ppc_dcbf xoaddr:$dst),
   (DCBF 0, xoaddr:$dst)>;
+def : Pat<(int_ppc_icbt xoaddr:$dst),
+  (ICBT 0, xoaddr:$dst)>;
 
 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
   (DCBT 0, xoaddr:$dst)>;   // data prefetch for loads
@@ -2565,11 +2567,21 @@
 def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
  "eieio", IIC_LdStLoad, []>;
 
+def PseudoEIEIO : PPCEmitTimePseudo<(outs), (ins), "#PPCEIEIO",
+  [(int_ppc_eieio)]>

[PATCH] D102443: [PowerPC] Added multiple PowerPC builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 347029.
quinnp added a comment.

Adding a comment in BuiltinsPPC.def for motivation.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102443/new/

https://reviews.llvm.org/D102443

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
  llvm/test/CodeGen/PowerPC/eieio.ll

Index: llvm/test/CodeGen/PowerPC/eieio.ll
===
--- llvm/test/CodeGen/PowerPC/eieio.ll
+++ llvm/test/CodeGen/PowerPC/eieio.ll
@@ -4,7 +4,9 @@
 
 define void @eieio_test() {
 ; CHECK-LABEL: @eieio_test
-; CHECK: eieio
+; CHECK: ori r2, r2, 0
+; CHECK-NEXT: ori r2, r2, 0
+; CHECK-NEXT: eieio
 ; CHECK-NEXT: blr
 
 entry:
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
@@ -0,0 +1,74 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_eieio
+
+entry:
+  call void @llvm.ppc.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_eieio
+
+entry:
+  call void @llvm.ppc.iospace.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.iospace.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: lwsync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.lwsync() #2
+
+define dso_local void @test_builtin_ppc_iospace_sync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: sync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.sync() #2
+
+define dso_local void @test_builtin_ppc_icbt() #0 {
+; CHECK-LABEL: test_builtin_ppc_icbt
+
+entry:
+  %a = alloca i8*, align 8
+  %0 = load i8*, i8** %a, align 8
+  call void @llvm.ppc.icbt(i8* %0)
+; CHECK: icbt 0, 0, 3
+
+  ret void
+}
+
+declare void @llvm.ppc.icbt(i8*) #2
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
@@ -0,0 +1,33 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: msync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.lwsync() #2
+
+define dso_local void @test_builtin_ppc_iospace_sync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: msync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.sync() #2
+
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2044,6 +2044,8 @@
   (DCBTST 0, xoaddr:$dst)>;
 def : Pat<(int_ppc_dcbf xoaddr:$dst),
   (DCBF 0, xoaddr:$dst)>;
+def : Pat<(int_ppc_icbt xoaddr:$dst),
+  (ICBT 0, xoaddr:$dst)>;
 
 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
   (DCBT 0, xoaddr:$dst)>;   // data prefetch for loads
@@ -2565,11 +2567,21 @@
 def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
  "eieio", IIC_LdStLoad, []>;
 
+def PseudoEIEIO : PPCEmitTimePseudo<(outs), (ins), "#PPCEIEIO",
+  [(in

[PATCH] D102443: [PowerPC] Added multiple PowerPC builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 34.
quinnp added a comment.

This update is motivated by comments made by @nemanjai. All of the builtin 
names have been changed to follow the convention of __builtin__. To 
fulfill the original goal of compatibility with the XL compiler, macros have 
been added to map __ to __builtin_ppc_.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102443/new/

https://reviews.llvm.org/D102443

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
  llvm/test/CodeGen/PowerPC/eieio.ll

Index: llvm/test/CodeGen/PowerPC/eieio.ll
===
--- llvm/test/CodeGen/PowerPC/eieio.ll
+++ llvm/test/CodeGen/PowerPC/eieio.ll
@@ -4,7 +4,9 @@
 
 define void @eieio_test() {
 ; CHECK-LABEL: @eieio_test
-; CHECK: eieio
+; CHECK: ori r2, r2, 0
+; CHECK-NEXT: ori r2, r2, 0
+; CHECK-NEXT: eieio
 ; CHECK-NEXT: blr
 
 entry:
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
@@ -0,0 +1,74 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_eieio
+
+entry:
+  call void @llvm.ppc.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_eieio
+
+entry:
+  call void @llvm.ppc.iospace.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.iospace.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: lwsync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.lwsync() #2
+
+define dso_local void @test_builtin_ppc_iospace_sync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: sync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.sync() #2
+
+define dso_local void @test_builtin_ppc_icbt() #0 {
+; CHECK-LABEL: test_builtin_ppc_icbt
+
+entry:
+  %a = alloca i8*, align 8
+  %0 = load i8*, i8** %a, align 8
+  call void @llvm.ppc.icbt(i8* %0)
+; CHECK: icbt 0, 0, 3
+
+  ret void
+}
+
+declare void @llvm.ppc.icbt(i8*) #2
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
@@ -0,0 +1,33 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: msync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.lwsync() #2
+
+define dso_local void @test_builtin_ppc_iospace_sync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: msync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.sync() #2
+
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2044,6 +2044,8 @@
   (DCBTST 0, xoaddr:$dst)>;
 def : Pat<(int_ppc_dcbf xoaddr:$dst),
   (DCBF 0, xoaddr:$dst)>;
+def : Pat<(int_ppc_icbt xoaddr:$dst),
+  (ICBT 0, xoaddr:$dst)>;
 
 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
   (DCBT 0, x

[PATCH] D102443: [PowerPC] Added multiple PowerPC builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 348332.
quinnp added a comment.

Addressing the last comments made by @nemanjai.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102443/new/

https://reviews.llvm.org/D102443

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
  llvm/test/CodeGen/PowerPC/eieio.ll

Index: llvm/test/CodeGen/PowerPC/eieio.ll
===
--- llvm/test/CodeGen/PowerPC/eieio.ll
+++ llvm/test/CodeGen/PowerPC/eieio.ll
@@ -4,7 +4,9 @@
 
 define void @eieio_test() {
 ; CHECK-LABEL: @eieio_test
-; CHECK: eieio
+; CHECK: ori r2, r2, 0
+; CHECK-NEXT: ori r2, r2, 0
+; CHECK-NEXT: eieio
 ; CHECK-NEXT: blr
 
 entry:
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
@@ -0,0 +1,74 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_eieio
+
+entry:
+  call void @llvm.ppc.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_eieio
+
+entry:
+  call void @llvm.ppc.iospace.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.iospace.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: lwsync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.lwsync() #2
+
+define dso_local void @test_builtin_ppc_iospace_sync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: sync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.sync() #2
+
+define dso_local void @test_builtin_ppc_icbt() #0 {
+; CHECK-LABEL: test_builtin_ppc_icbt
+
+entry:
+  %a = alloca i8*, align 8
+  %0 = load i8*, i8** %a, align 8
+  call void @llvm.ppc.icbt(i8* %0)
+; CHECK: icbt 0, 0, 3
+
+  ret void
+}
+
+declare void @llvm.ppc.icbt(i8*) #2
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
@@ -0,0 +1,33 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: msync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.lwsync() #2
+
+define dso_local void @test_builtin_ppc_iospace_sync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: msync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.sync() #2
+
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2044,6 +2044,8 @@
   (DCBTST 0, xoaddr:$dst)>;
 def : Pat<(int_ppc_dcbf xoaddr:$dst),
   (DCBF 0, xoaddr:$dst)>;
+def : Pat<(int_ppc_icbt xoaddr:$dst),
+  (ICBT 0, xoaddr:$dst)>;
 
 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
   (DCBT 0, xoaddr:$dst)>;   // data prefetch for loads
@@ -2565,11 +2567,19 @@
 def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
  "eieio", IIC_LdStLoad, []>;
 
+def PseudoEIEIO : PPCEmit

[PATCH] D109996: [PowerPC] Fix signature of lxvp and stxvp builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added subscribers: shchenz, kbarton, nemanjai.
quinnp requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

This patch changes the signature of the load and store vector pair
builtins to match their documentation. The type of the `signed long long`
argument is changed to `signed long`. This patch also changes existing testcases
to match the signature change.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109996

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/test/CodeGen/builtins-ppc-pair-mma.c
  clang/test/Sema/ppc-pair-mma-types.c

Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -322,16 +322,16 @@
 }
 
 void testBuiltinTypes1(const __vector_pair *vpp, const __vector_pair *vp2, float f) {
-  __vector_pair vp = __builtin_vsx_lxvp(f, vpp); // expected-error {{passing 'float' to parameter of incompatible type 'long long'}}
-  __builtin_vsx_stxvp(vp, 32799, vp2);   // expected-error {{passing 'int' to parameter of incompatible type 'long long'}}
+  __vector_pair vp = __builtin_vsx_lxvp(f, vpp); // expected-error {{passing 'float' to parameter of incompatible type 'long'}}
+  __builtin_vsx_stxvp(vp, 32799, vp2);   // expected-error {{passing 'int' to parameter of incompatible type 'long'}}
 }
 
 void testBuiltinTypes2(__vector_pair *vpp, const __vector_pair *vp2, unsigned char c) {
-  __vector_pair vp = __builtin_vsx_lxvp(6LL, vpp); // expected-error {{passing '__vector_pair *' to parameter of incompatible type 'const __vector_pair *'}}
-  __builtin_vsx_stxvp(vp, c, vp2); // expected-error {{passing 'unsigned char' to parameter of incompatible type 'long long'}}
+  __vector_pair vp = __builtin_vsx_lxvp(6L, vpp); // expected-error {{passing '__vector_pair *' to parameter of incompatible type 'const __vector_pair *'}}
+  __builtin_vsx_stxvp(vp, c, vp2);// expected-error {{passing 'unsigned char' to parameter of incompatible type 'long'}}
 }
 
-void testBuiltinTypes3(vector int v, __vector_pair *vp2, signed long long ll, unsigned short s) {
-  __vector_pair vp = __builtin_vsx_lxvp(ll, v); // expected-error {{passing '__vector int' (vector of 4 'int' values) to parameter of incompatible type 'const __vector_pair *'}}
-  __builtin_vsx_stxvp(vp, ll, s);   // expected-error {{passing 'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
+void testBuiltinTypes3(vector int v, __vector_pair *vp2, signed long l, unsigned short s) {
+  __vector_pair vp = __builtin_vsx_lxvp(l, v); // expected-error {{passing '__vector int' (vector of 4 'int' values) to parameter of incompatible type 'const __vector_pair *'}}
+  __builtin_vsx_stxvp(vp, l, s);   // expected-error {{passing 'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
 }
Index: clang/test/CodeGen/builtins-ppc-pair-mma.c
===
--- clang/test/CodeGen/builtins-ppc-pair-mma.c
+++ clang/test/CodeGen/builtins-ppc-pair-mma.c
@@ -1049,8 +1049,8 @@
 // CHECK-NEXT:ret void
 //
 void test66(const __vector_pair *vpp, const __vector_pair *vp2) {
-  __vector_pair vp = __builtin_vsx_lxvp(0LL, vpp);
-  __builtin_vsx_stxvp(vp, 0LL, vp2);
+  __vector_pair vp = __builtin_vsx_lxvp(0L, vpp);
+  __builtin_vsx_stxvp(vp, 0L, vp2);
 }
 
 // CHECK-LABEL: @test67(
@@ -1063,7 +1063,7 @@
 // CHECK-NEXT:tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]])
 // CHECK-NEXT:ret void
 //
-void test67(const __vector_pair *vpp, signed long long offset, const __vector_pair *vp2) {
+void test67(const __vector_pair *vpp, signed long offset, const __vector_pair *vp2) {
   __vector_pair vp = __builtin_vsx_lxvp(offset, vpp);
   __builtin_vsx_stxvp(vp, offset, vp2);
 }
@@ -1079,8 +1079,8 @@
 // CHECK-NEXT:ret void
 //
 void test68(const __vector_pair *vpp, const __vector_pair *vp2) {
-  __vector_pair vp = __builtin_vsx_lxvp(18LL, vpp);
-  __builtin_vsx_stxvp(vp, 18LL, vp2);
+  __vector_pair vp = __builtin_vsx_lxvp(18L, vpp);
+  __builtin_vsx_stxvp(vp, 18L, vp2);
 }
 
 // CHECK-LABEL: @test69(
@@ -1094,8 +1094,8 @@
 // CHECK-NEXT:ret void
 //
 void test69(const __vector_pair *vpp, const __vector_pair *vp2) {
-  __vector_pair vp = __builtin_vsx_lxvp(1LL, vpp);
-  __builtin_vsx_stxvp(vp, 1LL, vp2);
+  __vector_pair vp = __builtin_vsx_lxvp(1L, vpp);
+  __builtin_vsx_stxvp(vp, 1L, vp2);
 }
 
 // CHECK-LABEL: @test70(
@@ -1109,8 +1109,8 @@
 // CHECK-NEXT:ret void
 //
 void test70(const __vector_pair *vpp, const __vector_pair *vp2) {
-  __vector_pair vp = __builtin_vsx_lxvp(42LL, vpp);
-  __builtin_vsx_stxvp(vp, 42LL, vp2);
+  __vector_pair vp = __builtin_vsx_lxvp(42L, vpp);
+  __builtin_vsx_stxvp(vp, 42L, vp2);
 }
 
 // CHECK-LABEL: 

[PATCH] D109996: [PowerPC] Fix signature of lxvp and stxvp builtins

[Quinn Pham via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG57939309501c: [PowerPC] Fix signature of lxvp and stxvp 
builtins (authored by quinnp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109996/new/

https://reviews.llvm.org/D109996

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/test/CodeGen/builtins-ppc-pair-mma.c
  clang/test/Sema/ppc-pair-mma-types.c

Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -322,16 +322,16 @@
 }
 
 void testBuiltinTypes1(const __vector_pair *vpp, const __vector_pair *vp2, float f) {
-  __vector_pair vp = __builtin_vsx_lxvp(f, vpp); // expected-error {{passing 'float' to parameter of incompatible type 'long long'}}
-  __builtin_vsx_stxvp(vp, 32799, vp2);   // expected-error {{passing 'int' to parameter of incompatible type 'long long'}}
+  __vector_pair vp = __builtin_vsx_lxvp(f, vpp); // expected-error {{passing 'float' to parameter of incompatible type 'long'}}
+  __builtin_vsx_stxvp(vp, 32799, vp2);   // expected-error {{passing 'int' to parameter of incompatible type 'long'}}
 }
 
 void testBuiltinTypes2(__vector_pair *vpp, const __vector_pair *vp2, unsigned char c) {
-  __vector_pair vp = __builtin_vsx_lxvp(6LL, vpp); // expected-error {{passing '__vector_pair *' to parameter of incompatible type 'const __vector_pair *'}}
-  __builtin_vsx_stxvp(vp, c, vp2); // expected-error {{passing 'unsigned char' to parameter of incompatible type 'long long'}}
+  __vector_pair vp = __builtin_vsx_lxvp(6L, vpp); // expected-error {{passing '__vector_pair *' to parameter of incompatible type 'const __vector_pair *'}}
+  __builtin_vsx_stxvp(vp, c, vp2);// expected-error {{passing 'unsigned char' to parameter of incompatible type 'long'}}
 }
 
-void testBuiltinTypes3(vector int v, __vector_pair *vp2, signed long long ll, unsigned short s) {
-  __vector_pair vp = __builtin_vsx_lxvp(ll, v); // expected-error {{passing '__vector int' (vector of 4 'int' values) to parameter of incompatible type 'const __vector_pair *'}}
-  __builtin_vsx_stxvp(vp, ll, s);   // expected-error {{passing 'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
+void testBuiltinTypes3(vector int v, __vector_pair *vp2, signed long l, unsigned short s) {
+  __vector_pair vp = __builtin_vsx_lxvp(l, v); // expected-error {{passing '__vector int' (vector of 4 'int' values) to parameter of incompatible type 'const __vector_pair *'}}
+  __builtin_vsx_stxvp(vp, l, s);   // expected-error {{passing 'unsigned short' to parameter of incompatible type 'const __vector_pair *'}}
 }
Index: clang/test/CodeGen/builtins-ppc-pair-mma.c
===
--- clang/test/CodeGen/builtins-ppc-pair-mma.c
+++ clang/test/CodeGen/builtins-ppc-pair-mma.c
@@ -1049,8 +1049,8 @@
 // CHECK-NEXT:ret void
 //
 void test66(const __vector_pair *vpp, const __vector_pair *vp2) {
-  __vector_pair vp = __builtin_vsx_lxvp(0LL, vpp);
-  __builtin_vsx_stxvp(vp, 0LL, vp2);
+  __vector_pair vp = __builtin_vsx_lxvp(0L, vpp);
+  __builtin_vsx_stxvp(vp, 0L, vp2);
 }
 
 // CHECK-LABEL: @test67(
@@ -1063,7 +1063,7 @@
 // CHECK-NEXT:tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]])
 // CHECK-NEXT:ret void
 //
-void test67(const __vector_pair *vpp, signed long long offset, const __vector_pair *vp2) {
+void test67(const __vector_pair *vpp, signed long offset, const __vector_pair *vp2) {
   __vector_pair vp = __builtin_vsx_lxvp(offset, vpp);
   __builtin_vsx_stxvp(vp, offset, vp2);
 }
@@ -1079,8 +1079,8 @@
 // CHECK-NEXT:ret void
 //
 void test68(const __vector_pair *vpp, const __vector_pair *vp2) {
-  __vector_pair vp = __builtin_vsx_lxvp(18LL, vpp);
-  __builtin_vsx_stxvp(vp, 18LL, vp2);
+  __vector_pair vp = __builtin_vsx_lxvp(18L, vpp);
+  __builtin_vsx_stxvp(vp, 18L, vp2);
 }
 
 // CHECK-LABEL: @test69(
@@ -1094,8 +1094,8 @@
 // CHECK-NEXT:ret void
 //
 void test69(const __vector_pair *vpp, const __vector_pair *vp2) {
-  __vector_pair vp = __builtin_vsx_lxvp(1LL, vpp);
-  __builtin_vsx_stxvp(vp, 1LL, vp2);
+  __vector_pair vp = __builtin_vsx_lxvp(1L, vpp);
+  __builtin_vsx_stxvp(vp, 1L, vp2);
 }
 
 // CHECK-LABEL: @test70(
@@ -1109,8 +1109,8 @@
 // CHECK-NEXT:ret void
 //
 void test70(const __vector_pair *vpp, const __vector_pair *vp2) {
-  __vector_pair vp = __builtin_vsx_lxvp(42LL, vpp);
-  __builtin_vsx_stxvp(vp, 42LL, vp2);
+  __vector_pair vp = __builtin_vsx_lxvp(42L, vpp);
+  __builtin_vsx_stxvp(vp, 42L, vp2);
 }
 
 // CHECK-LABEL: @test71(
@@ -1124,8 +1124,8 @@
 // CHECK-NEXT:ret void
 //
 void test71(const __vector_pair *vpp, const __vector_pair *vp2) {
-  __vector_pair vp = __builtin_vsx_lxvp(32768LL, vpp);
-  __builtin_vsx_s

[PATCH] D109710: [PowerPC] Add range checks for P10 Vector Builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374000.
quinnp added a comment.

Adding a testcase where the second parameter of vec_splati_ins is out of the 
range 0,1.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109710/new/

https://reviews.llvm.org/D109710

Files:
  clang/lib/Headers/altivec.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-p10vector-error.c
  clang/test/CodeGen/builtins-ppc-p10vector.c

Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -1370,10 +1370,12 @@
 }
 
 vector signed int test_vec_vec_splati_ins_si(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1383,10 +1385,12 @@
 }
 
 vector unsigned int test_vec_vec_splati_ins_ui(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1396,10 +1400,12 @@
 }
 
 vector float test_vec_vec_splati_ins_f(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x float>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1408,6 +1414,21 @@
   return vec_splati_ins(vfa, 0, 1.0f);
 }
 
+vector signed int test_vec_vec_splati_ins_range(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
+  // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
+  // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
+  // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+  // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
+  // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
+  // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+  // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
+  // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]]
+  // CHECK-LE: ret <4 x i32>
+  return vec_splati_ins(vsia, 2, -17);
+}
+
 void test_vec_xst_trunc_sc(vector signed __int128 __a, signed long long __b,
signed char *__c) {
   // CHECK: store i8 %{{.+}}, i8* %{{.+}}, align 1
Index: clang/test/CodeGen/builtins-ppc-p10vector-error.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-p10vector-error.c
@@ -0,0 +1,32 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+
+#include 
+
+vector unsigned char vuca;
+vector unsigned short vusa;
+vector unsigned int vuia;
+vector unsigned long long vulla;
+
+unsigned long long test_vec_cntm_uc(void) {
+  return vec_cntm(vuca, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_us(void) {
+  return vec_cntm(vusa, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_ui(void) {
+  return vec_cntm(vuia, 2); // expected-error 1+ {{argument value 2 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_ull(void) {
+  return vec_cntm(vulla, 2); // expected-error 1+ {{argument value 2 is outside the valid range [0, 1]}}
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaCh

[PATCH] D109437: [PowerPC] FP compare and test XL compat builtins.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374064.
quinnp added a comment.

Separating the switch case in ISelLowering into two switch cases. One for 
`compare_exp_` and another for `test_data_class`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109437/new/

https://reviews.llvm.org/D109437

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-test.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define i32 @test_builtin_ppc_compare_exp_eq(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_eq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.eq(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.eq(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_lt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_lt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isellt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.lt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.lt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_gt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_gt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iselgt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.gt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.gt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_uo(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_uo:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isel 3, 4, 3, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.uo(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.uo(double, double)
+
+define i32 @test_builtin_ppc_test_data_class_d(double %d) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcdp 0, 1, 0
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.d(double %d, i32 0)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.d(double, i32 immarg)
+
+define i32 @test_builtin_ppc_test_data_class_f(float %f) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_f:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcsp 0, 1, 127
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f(float %f, i32 127)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.f(float, i32 immarg)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10373,6 +10373,56 @@
 }
 return DAG.getMergeValues(RetOps, dl);
   }
+  case Intrinsic::ppc_compare_exp_lt:
+  case Intrinsic::ppc_compare_exp_gt:
+  case Intrinsic::ppc_compare_exp_eq:
+  case Intrinsic::ppc_compare_exp_uo: {
+unsigned Pred;
+switch (IntrinsicID) {
+default:
+  llvm_unreachable("Unknown Intrinsic");
+case Intrinsic::ppc_compare_exp_lt:
+  Pred = PPC::PRED_LT;
+  break;
+case Intrinsic::ppc_compare_exp_gt:
+  Pred = PPC::PRED_GT;
+  break

[PATCH] D109437: [PowerPC] FP compare and test XL compat builtins.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374312.
quinnp added a comment.

Moving the semachecking of `test_data_class` from the function to the switch 
case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109437/new/

https://reviews.llvm.org/D109437

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-test.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define i32 @test_builtin_ppc_compare_exp_eq(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_eq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.eq(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.eq(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_lt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_lt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isellt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.lt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.lt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_gt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_gt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iselgt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.gt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.gt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_uo(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_uo:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isel 3, 4, 3, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.uo(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.uo(double, double)
+
+define i32 @test_builtin_ppc_test_data_class_d(double %d) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcdp 0, 1, 0
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.d(double %d, i32 0)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.d(double, i32 immarg)
+
+define i32 @test_builtin_ppc_test_data_class_f(float %f) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_f:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcsp 0, 1, 127
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f(float %f, i32 127)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.f(float, i32 immarg)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10373,6 +10373,56 @@
 }
 return DAG.getMergeValues(RetOps, dl);
   }
+  case Intrinsic::ppc_compare_exp_lt:
+  case Intrinsic::ppc_compare_exp_gt:
+  case Intrinsic::ppc_compare_exp_eq:
+  case Intrinsic::ppc_compare_exp_uo: {
+unsigned Pred;
+switch (IntrinsicID) {
+default:
+  llvm_unreachable("Unknown Intrinsic");
+case Intrinsic::ppc_compare_exp_lt:
+  Pred = PPC::PRED_LT;
+  break;
+case Intrinsic::ppc_compare_exp_gt:
+  Pred = PPC::PRED_GT;
+  break;
+case Intrinsic::ppc_compare_exp_eq

[PATCH] D109710: [PowerPC] Add range checks for P10 Vector Builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374561.
quinnp added a comment.

Added a comment to the out-of-range argument test case to describe the 
behaviour.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109710/new/

https://reviews.llvm.org/D109710

Files:
  clang/lib/Headers/altivec.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-p10vector-error.c
  clang/test/CodeGen/builtins-ppc-p10vector.c

Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -1370,10 +1370,12 @@
 }
 
 vector signed int test_vec_vec_splati_ins_si(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1383,10 +1385,12 @@
 }
 
 vector unsigned int test_vec_vec_splati_ins_ui(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1396,10 +1400,12 @@
 }
 
 vector float test_vec_vec_splati_ins_f(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x float>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1408,6 +1414,24 @@
   return vec_splati_ins(vfa, 0, 1.0f);
 }
 
+// In this test case, the second argument of vec_splati_ins is outside of the 
+// valid range [0,1]. A mask of 0x01 is applied to obtain an in-range value for 
+// the second argument.
+vector signed int test_vec_vec_splati_ins_range(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
+  // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
+  // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
+  // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+  // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
+  // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
+  // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+  // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
+  // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]]
+  // CHECK-LE: ret <4 x i32>
+  return vec_splati_ins(vsia, 2, -17);
+}
+
 void test_vec_xst_trunc_sc(vector signed __int128 __a, signed long long __b,
signed char *__c) {
   // CHECK: store i8 %{{.+}}, i8* %{{.+}}, align 1
Index: clang/test/CodeGen/builtins-ppc-p10vector-error.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-p10vector-error.c
@@ -0,0 +1,32 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+
+#include 
+
+vector unsigned char vuca;
+vector unsigned short vusa;
+vector unsigned int vuia;
+vector unsigned long long vulla;
+
+unsigned long long test_vec_cntm_uc(void) {
+  return vec_cntm(vuca, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_us(void) {
+  return vec_cntm(vusa, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_ui(void) {
+  return vec_cntm(vuia, 2); // expected-error 1+ {{argument value 2 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_ull(void) {
+  return vec_cntm(vulla, 2); // expected-error 1+ {{argumen

[PATCH] D109710: [PowerPC] Add range checks for P10 Vector Builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374563.
quinnp added a comment.

Word change. valid -> expected


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109710/new/

https://reviews.llvm.org/D109710

Files:
  clang/lib/Headers/altivec.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-p10vector-error.c
  clang/test/CodeGen/builtins-ppc-p10vector.c

Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -1370,10 +1370,12 @@
 }
 
 vector signed int test_vec_vec_splati_ins_si(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1383,10 +1385,12 @@
 }
 
 vector unsigned int test_vec_vec_splati_ins_ui(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1396,10 +1400,12 @@
 }
 
 vector float test_vec_vec_splati_ins_f(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x float>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1408,6 +1414,24 @@
   return vec_splati_ins(vfa, 0, 1.0f);
 }
 
+// In this test case, the second argument of vec_splati_ins is outside of the 
+// expected range [0,1]. A mask of 0x01 is applied to obtain an in-range value 
+// for the second argument.
+vector signed int test_vec_vec_splati_ins_range(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
+  // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
+  // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
+  // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+  // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
+  // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
+  // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+  // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
+  // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]]
+  // CHECK-LE: ret <4 x i32>
+  return vec_splati_ins(vsia, 2, -17);
+}
+
 void test_vec_xst_trunc_sc(vector signed __int128 __a, signed long long __b,
signed char *__c) {
   // CHECK: store i8 %{{.+}}, i8* %{{.+}}, align 1
Index: clang/test/CodeGen/builtins-ppc-p10vector-error.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-p10vector-error.c
@@ -0,0 +1,32 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+
+#include 
+
+vector unsigned char vuca;
+vector unsigned short vusa;
+vector unsigned int vuia;
+vector unsigned long long vulla;
+
+unsigned long long test_vec_cntm_uc(void) {
+  return vec_cntm(vuca, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_us(void) {
+  return vec_cntm(vusa, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_ui(void) {
+  return vec_cntm(vuia, 2); // expected-error 1+ {{argument value 2 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_ull(void) {
+  return vec_cntm(vulla, 2); // expected-error 1+ {{argument value 2 is outside the valid range [0, 1]}}
+}

[PATCH] D109710: [PowerPC] Add range checks for P10 Vector Builtins

[Quinn Pham via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf9912fe4eac9: [PowerPC] Add range checks for P10 Vector 
Builtins (authored by quinnp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109710/new/

https://reviews.llvm.org/D109710

Files:
  clang/lib/Headers/altivec.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-p10vector-error.c
  clang/test/CodeGen/builtins-ppc-p10vector.c

Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -1371,10 +1371,12 @@
 }
 
 vector signed int test_vec_vec_splati_ins_si(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1384,10 +1386,12 @@
 }
 
 vector unsigned int test_vec_vec_splati_ins_ui(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1397,10 +1401,12 @@
 }
 
 vector float test_vec_vec_splati_ins_f(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 %{{.+}}
   // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
   // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-BE: ret <4 x float>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
   // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK-LE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
@@ -1409,6 +1415,24 @@
   return vec_splati_ins(vfa, 0, 1.0f);
 }
 
+// In this test case, the second argument of vec_splati_ins is outside of the 
+// expected range [0,1]. A mask of 0x01 is applied to obtain an in-range value 
+// for the second argument.
+vector signed int test_vec_vec_splati_ins_range(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1
+  // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
+  // CHECK-BE:  [[T1:%.+]] = add i32 2, %{{.+}}
+  // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+  // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: [[T0:%.+]] = and i32 %{{.+}}, 1
+  // CHECK-LE:  [[T1:%.+]] = sub i32 1, %{{.+}}
+  // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+  // CHECK-LE:  [[T2:%.+]] = sub i32 3, %{{.+}}
+  // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]]
+  // CHECK-LE: ret <4 x i32>
+  return vec_splati_ins(vsia, 2, -17);
+}
+
 void test_vec_xst_trunc_sc(vector signed __int128 __a, signed long long __b,
signed char *__c) {
   // CHECK: store i8 %{{.+}}, i8* %{{.+}}, align 1
Index: clang/test/CodeGen/builtins-ppc-p10vector-error.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-p10vector-error.c
@@ -0,0 +1,32 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-cpu pwr10 \
+// RUN:   -fsyntax-only -Wall -Werror -verify %s
+
+#include 
+
+vector unsigned char vuca;
+vector unsigned short vusa;
+vector unsigned int vuia;
+vector unsigned long long vulla;
+
+unsigned long long test_vec_cntm_uc(void) {
+  return vec_cntm(vuca, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_us(void) {
+  return vec_cntm(vusa, -1); // expected-error 1+ {{argument value 255 is outside the valid range [0, 1]}}
+}
+
+unsigned long long test_vec_cntm_ui(void) {
+  return vec_cntm(vuia, 2); // expected-error 1+ {{argument value 2 is outside the valid range [0, 1]}}
+}
+
+unsigned long long 

[PATCH] D109437: [PowerPC] FP compare and test XL compat builtins.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374605.
quinnp added a comment.

Addressing some review comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109437/new/

https://reviews.llvm.org/D109437

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-test.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define i32 @test_builtin_ppc_compare_exp_eq(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_eq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.eq(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.eq(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_lt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_lt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isellt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.lt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.lt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_gt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_gt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iselgt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.gt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.gt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_uo(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_uo:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isel 3, 4, 3, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.uo(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.uo(double, double)
+
+define i32 @test_builtin_ppc_test_data_class_d(double %d) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcdp 0, 1, 0
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.d(double %d, i32 0)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.d(double, i32 immarg)
+
+define i32 @test_builtin_ppc_test_data_class_f(float %f) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_f:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcsp 0, 1, 127
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f(float %f, i32 127)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.f(float, i32 immarg)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10373,6 +10373,52 @@
 }
 return DAG.getMergeValues(RetOps, dl);
   }
+  case Intrinsic::ppc_compare_exp_lt:
+  case Intrinsic::ppc_compare_exp_gt:
+  case Intrinsic::ppc_compare_exp_eq:
+  case Intrinsic::ppc_compare_exp_uo: {
+unsigned Pred;
+switch (IntrinsicID) {
+case Intrinsic::ppc_compare_exp_lt:
+  Pred = PPC::PRED_LT;
+  break;
+case Intrinsic::ppc_compare_exp_gt:
+  Pred = PPC::PRED_GT;
+  break;
+case Intrinsic::ppc_compare_exp_eq:
+  Pred = PPC::PRED_EQ;
+  break;
+case Intrinsic::ppc_compare_exp_uo:
+  Pred = PPC::PRED_UN;
+  break;
+}
+return

[PATCH] D109437: [PowerPC] FP compare and test XL compat builtins.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374610.
quinnp added a comment.

Addressing review comment about ISelLowering of `test_data_class`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109437/new/

https://reviews.llvm.org/D109437

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-test.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define i32 @test_builtin_ppc_compare_exp_eq(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_eq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.eq(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.eq(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_lt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_lt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isellt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.lt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.lt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_gt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_gt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iselgt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.gt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.gt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_uo(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_uo:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isel 3, 4, 3, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.uo(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.uo(double, double)
+
+define i32 @test_builtin_ppc_test_data_class_d(double %d) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcdp 0, 1, 0
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.d(double %d, i32 0)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.d(double, i32 immarg)
+
+define i32 @test_builtin_ppc_test_data_class_f(float %f) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_f:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcsp 0, 1, 127
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f(float %f, i32 127)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.f(float, i32 immarg)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10373,6 +10373,50 @@
 }
 return DAG.getMergeValues(RetOps, dl);
   }
+  case Intrinsic::ppc_compare_exp_lt:
+  case Intrinsic::ppc_compare_exp_gt:
+  case Intrinsic::ppc_compare_exp_eq:
+  case Intrinsic::ppc_compare_exp_uo: {
+unsigned Pred;
+switch (IntrinsicID) {
+case Intrinsic::ppc_compare_exp_lt:
+  Pred = PPC::PRED_LT;
+  break;
+case Intrinsic::ppc_compare_exp_gt:
+  Pred = PPC::PRED_GT;
+  break;
+case Intrinsic::ppc_compare_exp_eq:
+  Pred = PPC::PRED_EQ;
+  break;
+case Intrinsic::ppc_compare_exp_uo:
+  Pred = PPC::PRED_UN

[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374847.
quinnp marked 7 inline comments as done.
quinnp added a comment.

Updatign the patch to emit a fdiv for each of the builtins without any fast 
math flags. This will be safe and will still emit a software estimate when 
`-Ofast` is used.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106959/new/

https://reviews.llvm.org/D106959

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c


Index: clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
@@ -0,0 +1,54 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern double a;
+extern double b;
+extern float c;
+extern float d;
+
+// CHECK-LABEL:   @test_swdiv(
+// CHECK: [[TMP0:%.*]] = load double, double* @a
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-NEXT:[[SWDIV:%.*]] = fdiv double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV]]
+//
+double test_swdiv() {
+  return __swdiv(a, b);
+}
+
+// CHECK-LABEL:   @test_swdivs(
+// CHECK: [[TMP0:%.*]] = load float, float* @c
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-NEXT:[[SWDIVS:%.*]] = fdiv float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIVS]]
+//
+float test_swdivs() {
+  return __swdivs(c, d);
+}
+
+// CHECK-LABEL:   @test_builtin_ppc_swdiv(
+// CHECK: [[TMP0:%.*]] = load double, double* @a
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-NEXT:[[SWDIV:%.*]] = fdiv double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV]]
+//
+double test_builtin_ppc_swdiv() {
+  return __builtin_ppc_swdiv(a, b);
+}
+
+// CHECK-LABEL:   @test_builtin_ppc_swdivs(
+// CHECK: [[TMP0:%.*]] = load float, float* @c
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-NEXT:[[SWDIVS:%.*]] = fdiv float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIVS]]
+//
+float test_builtin_ppc_swdivs() {
+  return __builtin_ppc_swdivs(c, d);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -16035,6 +16035,9 @@
*this, E, Intrinsic::sqrt,
Intrinsic::experimental_constrained_sqrt))
 .getScalarVal();
+  case PPC::BI__builtin_ppc_swdiv:
+  case PPC::BI__builtin_ppc_swdivs:
+return Builder.CreateFDiv(Ops[0], Ops[1], "swdiv");
   }
 }
 
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -238,6 +238,8 @@
   Builder.defineMacro("__fsqrts", "__builtin_ppc_fsqrts");
   Builder.defineMacro("__addex", "__builtin_ppc_addex");
   Builder.defineMacro("__cmplxl", "__builtin_complex");
+  Builder.defineMacro("__swdiv", "__builtin_ppc_swdiv");
+  Builder.defineMacro("__swdivs", "__builtin_ppc_swdivs");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -96,6 +96,8 @@
 BUILTIN(__builtin_ppc_swdivs_nochk, "fff", "")
 BUILTIN(__builtin_ppc_alignx, "vIivC*", "nc")
 BUILTIN(__builtin_ppc_rdlam, "UWiUWiUWiUWIi", "nc")
+BUILTIN(__builtin_ppc_swdiv, "ddd", "")
+BUILTIN(__builtin_ppc_swdivs, "fff", "")
 // Compare
 BUILTIN(__builtin_ppc_cmpeqb, "LLiLLiLLi", "")
 BUILTIN(__builtin_ppc_cmprb, "iCIiii", "")


Index: clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
@@ -0,0 +1,54 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s 

[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

[Quinn Pham via Phabricator via cfe-commits]

quinnp added inline comments.



Comment at: llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll:36
+; CHECK-NEXT:  %2 = fdiv fast float %0, %1
+; CHECK-NEXT:  %3 = fcmp une float %2, %2
+; CHECK-NEXT:  br i1 %3, label %swdiv_HWDIV, label %swdiv_MERGE

efriedma wrote:
> quinnp wrote:
> > efriedma wrote:
> > > A "fast" fdiv never produces NaN, per LangRef.  Using fcmp like this is 
> > > fragile at best.
> > > 
> > > (Maybe you want "fdiv arcp"?)
> > Thank you, I see what you mean. I have changed it to emit a `fdiv ninf 
> > arcp` instead of a `fdiv fast`. I included the `ninf` flag because without 
> > it the compiler doesn't produce the software div estimate.
> ninf is also an issue, although maybe less likely to bite in practice.  
> Consider what happens if someone passes infinity to swdivs: the fdiv reduces 
> to poison, so the branch is undefined behavior.
We've decided to emit an `fdiv` without any fast math flags for these builtins. 
This will be safe and will emit the software estimate for `-Ofast`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106959/new/

https://reviews.llvm.org/D106959

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D109780: [PowerPC] Add range check for vec_genpcvm builtins

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374854.
quinnp added a comment.

Rebased with main.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109780/new/

https://reviews.llvm.org/D109780

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-p10vector-error.c


Index: clang/test/CodeGen/builtins-ppc-p10vector-error.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector-error.c
+++ clang/test/CodeGen/builtins-ppc-p10vector-error.c
@@ -30,3 +30,19 @@
 unsigned long long test_vec_cntm_ull(void) {
   return vec_cntm(vulla, 2); // expected-error 1+ {{argument value 2 is 
outside the valid range [0, 1]}}
 }
+
+vector unsigned char test_xxgenpcvbm(void) {
+  return vec_genpcvm(vuca, -1); // expected-error 1+ {{argument value -1 is 
outside the valid range [0, 3]}}
+}
+
+vector unsigned short test_xxgenpcvhm(void) {
+  return vec_genpcvm(vusa, -1); // expected-error 1+ {{argument value -1 is 
outside the valid range [0, 3]}}
+}
+
+vector unsigned int test_xxgenpcvwm(void) {
+  return vec_genpcvm(vuia, 4); // expected-error 1+ {{argument value 4 is 
outside the valid range [0, 3]}}
+}
+
+vector unsigned long long test_xxgenpcvdm(void) {
+  return vec_genpcvm(vulla, 4); // expected-error 1+ {{argument value 4 is 
outside the valid range [0, 3]}}
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3485,6 +3485,11 @@
   case PPC::BI__builtin_darn_32:
 return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions",
 diag::err_ppc_builtin_only_on_arch, "9");
+  case PPC::BI__builtin_vsx_xxgenpcvbm:
+  case PPC::BI__builtin_vsx_xxgenpcvhm:
+  case PPC::BI__builtin_vsx_xxgenpcvwm:
+  case PPC::BI__builtin_vsx_xxgenpcvdm:
+return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3);
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);


Index: clang/test/CodeGen/builtins-ppc-p10vector-error.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector-error.c
+++ clang/test/CodeGen/builtins-ppc-p10vector-error.c
@@ -30,3 +30,19 @@
 unsigned long long test_vec_cntm_ull(void) {
   return vec_cntm(vulla, 2); // expected-error 1+ {{argument value 2 is outside the valid range [0, 1]}}
 }
+
+vector unsigned char test_xxgenpcvbm(void) {
+  return vec_genpcvm(vuca, -1); // expected-error 1+ {{argument value -1 is outside the valid range [0, 3]}}
+}
+
+vector unsigned short test_xxgenpcvhm(void) {
+  return vec_genpcvm(vusa, -1); // expected-error 1+ {{argument value -1 is outside the valid range [0, 3]}}
+}
+
+vector unsigned int test_xxgenpcvwm(void) {
+  return vec_genpcvm(vuia, 4); // expected-error 1+ {{argument value 4 is outside the valid range [0, 3]}}
+}
+
+vector unsigned long long test_xxgenpcvdm(void) {
+  return vec_genpcvm(vulla, 4); // expected-error 1+ {{argument value 4 is outside the valid range [0, 3]}}
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3485,6 +3485,11 @@
   case PPC::BI__builtin_darn_32:
 return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions",
 diag::err_ppc_builtin_only_on_arch, "9");
+  case PPC::BI__builtin_vsx_xxgenpcvbm:
+  case PPC::BI__builtin_vsx_xxgenpcvhm:
+  case PPC::BI__builtin_vsx_xxgenpcvwm:
+  case PPC::BI__builtin_vsx_xxgenpcvdm:
+return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3);
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D109780: [PowerPC] Add range check for vec_genpcvm builtins

[Quinn Pham via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG3b0240e6c89d: [PowerPC] Add range check for vec_genpcvm 
builtins (authored by quinnp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109780/new/

https://reviews.llvm.org/D109780

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-p10vector-error.c


Index: clang/test/CodeGen/builtins-ppc-p10vector-error.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector-error.c
+++ clang/test/CodeGen/builtins-ppc-p10vector-error.c
@@ -30,3 +30,19 @@
 unsigned long long test_vec_cntm_ull(void) {
   return vec_cntm(vulla, 2); // expected-error 1+ {{argument value 2 is 
outside the valid range [0, 1]}}
 }
+
+vector unsigned char test_xxgenpcvbm(void) {
+  return vec_genpcvm(vuca, -1); // expected-error 1+ {{argument value -1 is 
outside the valid range [0, 3]}}
+}
+
+vector unsigned short test_xxgenpcvhm(void) {
+  return vec_genpcvm(vusa, -1); // expected-error 1+ {{argument value -1 is 
outside the valid range [0, 3]}}
+}
+
+vector unsigned int test_xxgenpcvwm(void) {
+  return vec_genpcvm(vuia, 4); // expected-error 1+ {{argument value 4 is 
outside the valid range [0, 3]}}
+}
+
+vector unsigned long long test_xxgenpcvdm(void) {
+  return vec_genpcvm(vulla, 4); // expected-error 1+ {{argument value 4 is 
outside the valid range [0, 3]}}
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3485,6 +3485,11 @@
   case PPC::BI__builtin_darn_32:
 return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions",
 diag::err_ppc_builtin_only_on_arch, "9");
+  case PPC::BI__builtin_vsx_xxgenpcvbm:
+  case PPC::BI__builtin_vsx_xxgenpcvhm:
+  case PPC::BI__builtin_vsx_xxgenpcvwm:
+  case PPC::BI__builtin_vsx_xxgenpcvdm:
+return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3);
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);


Index: clang/test/CodeGen/builtins-ppc-p10vector-error.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector-error.c
+++ clang/test/CodeGen/builtins-ppc-p10vector-error.c
@@ -30,3 +30,19 @@
 unsigned long long test_vec_cntm_ull(void) {
   return vec_cntm(vulla, 2); // expected-error 1+ {{argument value 2 is outside the valid range [0, 1]}}
 }
+
+vector unsigned char test_xxgenpcvbm(void) {
+  return vec_genpcvm(vuca, -1); // expected-error 1+ {{argument value -1 is outside the valid range [0, 3]}}
+}
+
+vector unsigned short test_xxgenpcvhm(void) {
+  return vec_genpcvm(vusa, -1); // expected-error 1+ {{argument value -1 is outside the valid range [0, 3]}}
+}
+
+vector unsigned int test_xxgenpcvwm(void) {
+  return vec_genpcvm(vuia, 4); // expected-error 1+ {{argument value 4 is outside the valid range [0, 3]}}
+}
+
+vector unsigned long long test_xxgenpcvdm(void) {
+  return vec_genpcvm(vulla, 4); // expected-error 1+ {{argument value 4 is outside the valid range [0, 3]}}
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3485,6 +3485,11 @@
   case PPC::BI__builtin_darn_32:
 return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions",
 diag::err_ppc_builtin_only_on_arch, "9");
+  case PPC::BI__builtin_vsx_xxgenpcvbm:
+  case PPC::BI__builtin_vsx_xxgenpcvhm:
+  case PPC::BI__builtin_vsx_xxgenpcvwm:
+  case PPC::BI__builtin_vsx_xxgenpcvdm:
+return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3);
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D109437: [PowerPC] FP compare and test XL compat builtins.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374888.
quinnp added a comment.

Addressing nit in SemaChecking.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109437/new/

https://reviews.llvm.org/D109437

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-test.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define i32 @test_builtin_ppc_compare_exp_eq(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_eq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.eq(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.eq(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_lt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_lt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isellt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.lt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.lt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_gt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_gt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iselgt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.gt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.gt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_uo(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_uo:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isel 3, 4, 3, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.uo(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.uo(double, double)
+
+define i32 @test_builtin_ppc_test_data_class_d(double %d) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcdp 0, 1, 0
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.d(double %d, i32 0)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.d(double, i32 immarg)
+
+define i32 @test_builtin_ppc_test_data_class_f(float %f) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_f:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcsp 0, 1, 127
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f(float %f, i32 127)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.f(float, i32 immarg)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10373,6 +10373,50 @@
 }
 return DAG.getMergeValues(RetOps, dl);
   }
+  case Intrinsic::ppc_compare_exp_lt:
+  case Intrinsic::ppc_compare_exp_gt:
+  case Intrinsic::ppc_compare_exp_eq:
+  case Intrinsic::ppc_compare_exp_uo: {
+unsigned Pred;
+switch (IntrinsicID) {
+case Intrinsic::ppc_compare_exp_lt:
+  Pred = PPC::PRED_LT;
+  break;
+case Intrinsic::ppc_compare_exp_gt:
+  Pred = PPC::PRED_GT;
+  break;
+case Intrinsic::ppc_compare_exp_eq:
+  Pred = PPC::PRED_EQ;
+  break;
+case Intrinsic::ppc_compare_exp_uo:
+  Pred = PPC::PRED_UN;
+  break;
+}
+return 

[PATCH] D109437: [PowerPC] FP compare and test XL compat builtins.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 374891.
quinnp added a comment.

Rebase with main.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109437/new/

https://reviews.llvm.org/D109437

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-test.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define i32 @test_builtin_ppc_compare_exp_eq(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_eq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.eq(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.eq(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_lt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_lt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isellt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.lt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.lt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_gt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_gt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iselgt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.gt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.gt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_uo(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_uo:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isel 3, 4, 3, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.uo(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.uo(double, double)
+
+define i32 @test_builtin_ppc_test_data_class_d(double %d) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcdp 0, 1, 0
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.d(double %d, i32 0)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.d(double, i32 immarg)
+
+define i32 @test_builtin_ppc_test_data_class_f(float %f) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_f:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcsp 0, 1, 127
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f(float %f, i32 127)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.f(float, i32 immarg)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10373,6 +10373,50 @@
 }
 return DAG.getMergeValues(RetOps, dl);
   }
+  case Intrinsic::ppc_compare_exp_lt:
+  case Intrinsic::ppc_compare_exp_gt:
+  case Intrinsic::ppc_compare_exp_eq:
+  case Intrinsic::ppc_compare_exp_uo: {
+unsigned Pred;
+switch (IntrinsicID) {
+case Intrinsic::ppc_compare_exp_lt:
+  Pred = PPC::PRED_LT;
+  break;
+case Intrinsic::ppc_compare_exp_gt:
+  Pred = PPC::PRED_GT;
+  break;
+case Intrinsic::ppc_compare_exp_eq:
+  Pred = PPC::PRED_EQ;
+  break;
+case Intrinsic::ppc_compare_exp_uo:
+  Pred = PPC::PRED_UN;
+  break;
+}
+return SDValue(
+

[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 375285.
quinnp added a comment.

Added a backend testcase which goes from `fdiv fast` to software estimate. 
Added a runline in the front end testcase that sets the fast math flags.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106959/new/

https://reviews.llvm.org/D106959

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
  llvm/test/CodeGen/PowerPC/fdiv.ll

Index: llvm/test/CodeGen/PowerPC/fdiv.ll
===
--- llvm/test/CodeGen/PowerPC/fdiv.ll
+++ llvm/test/CodeGen/PowerPC/fdiv.ll
@@ -23,3 +23,16 @@
   %3 = fdiv contract reassoc arcp nsz ninf float %0, %1
   ret float %3
 }
+
+define dso_local float @fdiv_fast(float %0, float %1) local_unnamed_addr {
+; CHECK-LABEL: fdiv_fast:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:xsresp 3, 2
+; CHECK-NEXT:xsmulsp 0, 1, 3
+; CHECK-NEXT:xsnmsubasp 1, 2, 0
+; CHECK-NEXT:xsmaddasp 0, 3, 1
+; CHECK-NEXT:fmr 1, 0
+; CHECK-NEXT:blr
+  %3 = fdiv fast float %0, %1
+  ret float %3
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
@@ -0,0 +1,80 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -ffast-math -ffp-contract=fast \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefix CHECK-OFAST
+
+extern double a;
+extern double b;
+extern float c;
+extern float d;
+
+// CHECK-LABEL:   @test_swdiv(
+// CHECK: [[TMP0:%.*]] = load double, double* @a
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-NEXT:[[SWDIV:%.*]] = fdiv double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV]]
+//
+// CHECK-OFAST-LABEL:   @test_swdiv(
+// CHECK-OFAST: [[TMP0:%.*]] = load double, double* @a
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-OFAST-NEXT:[[SWDIV:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret double [[SWDIV]]
+//
+double test_swdiv() {
+  return __swdiv(a, b);
+}
+
+// CHECK-LABEL:   @test_swdivs(
+// CHECK: [[TMP0:%.*]] = load float, float* @c
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-NEXT:[[SWDIVS:%.*]] = fdiv float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIVS]]
+//
+// CHECK-OFAST-LABEL:   @test_swdivs(
+// CHECK-OFAST: [[TMP0:%.*]] = load float, float* @c
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-OFAST-NEXT:[[SWDIVS:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret float [[SWDIVS]]
+//
+float test_swdivs() {
+  return __swdivs(c, d);
+}
+
+// CHECK-LABEL:   @test_builtin_ppc_swdiv(
+// CHECK: [[TMP0:%.*]] = load double, double* @a
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-NEXT:[[SWDIV:%.*]] = fdiv double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV]]
+//
+// CHECK-OFAST-LABEL:   @test_builtin_ppc_swdiv(
+// CHECK-OFAST: [[TMP0:%.*]] = load double, double* @a
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-OFAST-NEXT:[[SWDIV:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret double [[SWDIV]]
+//
+double test_builtin_ppc_swdiv() {
+  return __builtin_ppc_swdiv(a, b);
+}
+
+// CHECK-LABEL:   @test_builtin_ppc_swdivs(
+// CHECK: [[TMP0:%.*]] = load float, float* @c
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-NEXT:[[SWDIVS:%.*]] = fdiv float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIVS]]
+//
+// CHECK-OFAST-LABEL:   @test_builtin_ppc_swdivs(
+// CHECK-OFAST: [[TMP0:%.*]] = load float, float* @c
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-OFAST-NEXT:[[SWDIVS:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret float [[SWDIVS]]
+//
+float test_builtin_ppc_swdivs() {
+  return __builtin_ppc_swdivs(c, d);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -16035,6 +16035,9 @@
*this, E, Intrinsic::sqrt,
Intrinsic::experimental_constrained_s

[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

[Quinn Pham via Phabricator via cfe-commits]

quinnp added a comment.

In D106959#3021069 , @NeHuang wrote:

> Do we already have a backend test case for `fdiv` emitting a software 
> estimate when `-Ofast` is used?

I've added a testcase in `llvm/test/CodeGen/PowerPC/fdiv.ll` which goes from 
`fdiv fast` to the assembly for the software divide estimate.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106959/new/

https://reviews.llvm.org/D106959

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D109437: [PowerPC] FP compare and test XL compat builtins.

[Quinn Pham via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG70391b3468b8: [PowerPC] FP compare and test XL compat 
builtins. (authored by quinnp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109437/new/

https://reviews.llvm.org/D109437

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-test.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define i32 @test_builtin_ppc_compare_exp_eq(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_eq:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.eq(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.eq(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_lt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_lt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isellt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.lt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.lt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_gt(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_gt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iselgt 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.gt(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.gt(double, double)
+
+define i32 @test_builtin_ppc_compare_exp_uo(double %d) {
+; CHECK-LABEL: test_builtin_ppc_compare_exp_uo:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xscmpexpdp 0, 1, 1
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:isel 3, 4, 3, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.compare.exp.uo(double %d, double %d)
+  ret i32 %0
+}
+
+declare i32 @llvm.ppc.compare.exp.uo(double, double)
+
+define i32 @test_builtin_ppc_test_data_class_d(double %d) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcdp 0, 1, 0
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.d(double %d, i32 0)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.d(double, i32 immarg)
+
+define i32 @test_builtin_ppc_test_data_class_f(float %f) {
+; CHECK-LABEL: test_builtin_ppc_test_data_class_f:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xststdcsp 0, 1, 127
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:li 4, 1
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f(float %f, i32 127)
+  ret i32 %test_data_class
+}
+
+declare i32 @llvm.ppc.test.data.class.f(float, i32 immarg)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10373,6 +10373,50 @@
 }
 return DAG.getMergeValues(RetOps, dl);
   }
+  case Intrinsic::ppc_compare_exp_lt:
+  case Intrinsic::ppc_compare_exp_gt:
+  case Intrinsic::ppc_compare_exp_eq:
+  case Intrinsic::ppc_compare_exp_uo: {
+unsigned Pred;
+switch (IntrinsicID) {
+case Intrinsic::ppc_compare_exp_lt:
+  Pred = PPC::PRED_LT;
+  break;
+case Intrinsic::ppc_compare_exp_gt:
+  Pred = PPC::PRED_GT;
+  break;
+case Intrinsic::ppc_compare_exp_eq:
+  Pred

[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 375912.
quinnp added a comment.

Fixing failing test case after rebasing with https://reviews.llvm.org/D110213.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106959/new/

https://reviews.llvm.org/D106959

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
  llvm/test/CodeGen/PowerPC/fdiv.ll

Index: llvm/test/CodeGen/PowerPC/fdiv.ll
===
--- llvm/test/CodeGen/PowerPC/fdiv.ll
+++ llvm/test/CodeGen/PowerPC/fdiv.ll
@@ -23,3 +23,16 @@
   %3 = fdiv contract reassoc arcp nsz ninf float %0, %1
   ret float %3
 }
+
+define dso_local float @fdiv_fast(float %0, float %1) local_unnamed_addr {
+; CHECK-LABEL: fdiv_fast:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:xsresp 3, 2
+; CHECK-NEXT:xsmulsp 0, 1, 3
+; CHECK-NEXT:xsnmsubasp 1, 2, 0
+; CHECK-NEXT:xsmaddasp 0, 3, 1
+; CHECK-NEXT:fmr 1, 0
+; CHECK-NEXT:blr
+  %3 = fdiv fast float %0, %1
+  ret float %3
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
@@ -0,0 +1,80 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -ffast-math -ffp-contract=fast \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefix CHECK-OFAST
+
+extern double a;
+extern double b;
+extern float c;
+extern float d;
+
+// CHECK-LABEL:   @test_swdiv(
+// CHECK: [[TMP0:%.*]] = load double, double* @a
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-NEXT:[[SWDIV:%.*]] = fdiv double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV]]
+//
+// CHECK-OFAST-LABEL:   @test_swdiv(
+// CHECK-OFAST: [[TMP0:%.*]] = load double, double* @a
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-OFAST-NEXT:[[SWDIV:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret double [[SWDIV]]
+//
+double test_swdiv() {
+  return __swdiv(a, b);
+}
+
+// CHECK-LABEL:   @test_swdivs(
+// CHECK: [[TMP0:%.*]] = load float, float* @c
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-NEXT:[[SWDIVS:%.*]] = fdiv float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIVS]]
+//
+// CHECK-OFAST-LABEL:   @test_swdivs(
+// CHECK-OFAST: [[TMP0:%.*]] = load float, float* @c
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-OFAST-NEXT:[[SWDIVS:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret float [[SWDIVS]]
+//
+float test_swdivs() {
+  return __swdivs(c, d);
+}
+
+// CHECK-LABEL:   @test_builtin_ppc_swdiv(
+// CHECK: [[TMP0:%.*]] = load double, double* @a
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-NEXT:[[SWDIV:%.*]] = fdiv double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV]]
+//
+// CHECK-OFAST-LABEL:   @test_builtin_ppc_swdiv(
+// CHECK-OFAST: [[TMP0:%.*]] = load double, double* @a
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-OFAST-NEXT:[[SWDIV:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret double [[SWDIV]]
+//
+double test_builtin_ppc_swdiv() {
+  return __builtin_ppc_swdiv(a, b);
+}
+
+// CHECK-LABEL:   @test_builtin_ppc_swdivs(
+// CHECK: [[TMP0:%.*]] = load float, float* @c
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-NEXT:[[SWDIVS:%.*]] = fdiv float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIVS]]
+//
+// CHECK-OFAST-LABEL:   @test_builtin_ppc_swdivs(
+// CHECK-OFAST: [[TMP0:%.*]] = load float, float* @c
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-OFAST-NEXT:[[SWDIVS:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret float [[SWDIVS]]
+//
+float test_builtin_ppc_swdivs() {
+  return __builtin_ppc_swdivs(c, d);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -16077,7 +16077,7 @@
*this, E, Intrinsic::sqrt,
Intrinsic::experimental_constrained_sqrt))
 .getScalarVal();
-  case PPC::BI__builtin_ppc_tes

[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

[Quinn Pham via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG67a3d1e27551: [PowerPC] swdiv builtins for XL compatibility 
(authored by quinnp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106959/new/

https://reviews.llvm.org/D106959

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
  llvm/test/CodeGen/PowerPC/fdiv.ll

Index: llvm/test/CodeGen/PowerPC/fdiv.ll
===
--- llvm/test/CodeGen/PowerPC/fdiv.ll
+++ llvm/test/CodeGen/PowerPC/fdiv.ll
@@ -23,3 +23,16 @@
   %3 = fdiv contract reassoc arcp nsz ninf float %0, %1
   ret float %3
 }
+
+define dso_local float @fdiv_fast(float %0, float %1) local_unnamed_addr {
+; CHECK-LABEL: fdiv_fast:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:xsresp 3, 2
+; CHECK-NEXT:xsmulsp 0, 1, 3
+; CHECK-NEXT:xsnmsubasp 1, 2, 0
+; CHECK-NEXT:xsmaddasp 0, 3, 1
+; CHECK-NEXT:fmr 1, 0
+; CHECK-NEXT:blr
+  %3 = fdiv fast float %0, %1
+  ret float %3
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
@@ -0,0 +1,80 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -ffast-math -ffp-contract=fast \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefix CHECK-OFAST
+
+extern double a;
+extern double b;
+extern float c;
+extern float d;
+
+// CHECK-LABEL:   @test_swdiv(
+// CHECK: [[TMP0:%.*]] = load double, double* @a
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-NEXT:[[SWDIV:%.*]] = fdiv double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV]]
+//
+// CHECK-OFAST-LABEL:   @test_swdiv(
+// CHECK-OFAST: [[TMP0:%.*]] = load double, double* @a
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-OFAST-NEXT:[[SWDIV:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret double [[SWDIV]]
+//
+double test_swdiv() {
+  return __swdiv(a, b);
+}
+
+// CHECK-LABEL:   @test_swdivs(
+// CHECK: [[TMP0:%.*]] = load float, float* @c
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-NEXT:[[SWDIVS:%.*]] = fdiv float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIVS]]
+//
+// CHECK-OFAST-LABEL:   @test_swdivs(
+// CHECK-OFAST: [[TMP0:%.*]] = load float, float* @c
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-OFAST-NEXT:[[SWDIVS:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret float [[SWDIVS]]
+//
+float test_swdivs() {
+  return __swdivs(c, d);
+}
+
+// CHECK-LABEL:   @test_builtin_ppc_swdiv(
+// CHECK: [[TMP0:%.*]] = load double, double* @a
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-NEXT:[[SWDIV:%.*]] = fdiv double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV]]
+//
+// CHECK-OFAST-LABEL:   @test_builtin_ppc_swdiv(
+// CHECK-OFAST: [[TMP0:%.*]] = load double, double* @a
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load double, double* @b
+// CHECK-OFAST-NEXT:[[SWDIV:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret double [[SWDIV]]
+//
+double test_builtin_ppc_swdiv() {
+  return __builtin_ppc_swdiv(a, b);
+}
+
+// CHECK-LABEL:   @test_builtin_ppc_swdivs(
+// CHECK: [[TMP0:%.*]] = load float, float* @c
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-NEXT:[[SWDIVS:%.*]] = fdiv float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIVS]]
+//
+// CHECK-OFAST-LABEL:   @test_builtin_ppc_swdivs(
+// CHECK-OFAST: [[TMP0:%.*]] = load float, float* @c
+// CHECK-OFAST-NEXT:[[TMP1:%.*]] = load float, float* @d
+// CHECK-OFAST-NEXT:[[SWDIVS:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-OFAST-NEXT:ret float [[SWDIVS]]
+//
+float test_builtin_ppc_swdivs() {
+  return __builtin_ppc_swdivs(c, d);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -16077,7 +16077,7 @@
*this, E, Intrinsic::sqrt,
Intrinsic::experime

[PATCH] D110935: [NFC] Update vec_extract builtin signatures to take signed int.

[Quinn Pham via Phabricator via cfe-commits]

quinnp added a comment.

lgtm


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110935/new/

https://reviews.llvm.org/D110935

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D110934: [NFC] Update return type of vec_popcnt to vector unsigned.

[Quinn Pham via Phabricator via cfe-commits]

quinnp added a comment.

I think the commit message needs to be updated.

> This patch updates the vec_popcnt builtins to take a signed int as the second 
> parameter...

Should be: This patch updates the return type of the vec_popcnt builtins to 
vector unsigned...

Other than that, lgtm.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110934/new/

https://reviews.llvm.org/D110934

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added subscribers: shchenz, kbarton, hiraditya, nemanjai.
quinnp requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103986

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-fp.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
@@ -0,0 +1,74 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+
+define dso_local double @test_fsel(double %a, double %b, double %c) local_unnamed_addr #0 {
+; CHECK-LABEL: test_fsel 
+
+entry:
+  %0 = tail call double @llvm.ppc.fsel(double %a, double %b, double %c)
+; CHECK: fsel f1, f1, f2, f3
+
+  ret double %0
+; CHECK: blr
+}
+
+declare double @llvm.ppc.fsel(double, double, double) #2
+
+define dso_local float @test_fsels(float %a, float %b, float %c) local_unnamed_addr #0 {
+; CHECK-LABEL: test_fsels
+
+entry:
+  %0 = tail call float @llvm.ppc.fsels(float %a, float %b, float %c)
+; CHECK: fsel f1, f1, f2, f3
+
+  ret float %0
+; CHECK: blr
+}
+
+declare float @llvm.ppc.fsels(float, float, float) #2
+
+define dso_local double @test_frsqrte(double %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test_frsqrte
+
+entry:
+  %0 = tail call double @llvm.ppc.frsqrte(double %a)
+; CHECK: xsrsqrtedp f1, f1
+
+  ret double %0
+; CHECK: blr
+}
+
+declare double @llvm.ppc.frsqrte(double) #2
+
+define dso_local float @test_frsqrtes(float %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test_frsqrtes
+
+entry:
+  %0 = tail call float @llvm.ppc.frsqrtes(float %a)
+; CHECK: frsqrtes f1, f1
+ 
+  ret float %0
+; CHECK: blr
+}
+
+declare float @llvm.ppc.frsqrtes(float) #2
+
+define dso_local float @test_fsqrts(float %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test_fsqrts
+
+entry:
+  %0 = tail call float @llvm.ppc.fsqrts(float %a)
+; CHECK fsqrts f1, f1
+
+  ret float %0
+; CHECK: blr
+}
+
+declare float @llvm.ppc.fsqrts(float) #2
+
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -4954,6 +4954,8 @@
 } // HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian
 } // AddedComplexity = 400
 
+def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
+
 // Instruction aliases ---//
 def : InstAlias<"xvmovdp $XT, $XB",
 (XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3318,6 +3318,10 @@
   }
 }
 
+def : Pat<(int_ppc_fsel f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), (FSELD $FRA, $FRC, $FRB)>;
+def : Pat<(int_ppc_frsqrtes f4rc:$frB), (FRSQRTES $frB)>;  
+def : Pat<(int_ppc_fsqrts f4rc:$frB), (FSQRTS $frB)>;
+
 let hasSideEffects = 0 in {
 let PPC970_Unit = 1 in {  // FXU Operations.
   let isSelect = 1 in
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -4987,6 +4987,13 @@
 break;
 
   case ISD::INTRINSIC_WO_CHAIN: {
+
+if (N->getConstantOperandVal(0) == Intrinsic::ppc_fsels) {
+  SDValue ops[] = {N->getOperand(1), N->getOperand(2), N->getOperand(3)};
+  CurDAG->SelectNodeTo(N, PPC::FSELS, MVT::f32, ops);
+  return;
+}
+
 if (!Subtarget->isISA3_1())
   break;
 unsigned Opcode = 0;
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1523,5 +1523,18 @@
   Intrinsic<[],[],[]>;
   def int_ppc_iospace_eieio : GCCBuiltin<"__builtin_ppc_iospace_eieio">,
   Intrinsic<[],[],[]>;
+
+  def int_ppc_f

[PATCH] D104125: [PowerPC] Moving defineXLCompatMacros() definition

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added subscribers: shchenz, kbarton, nemanjai.
quinnp requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

[NFC] Moving the definition of the defineXLCompatMacros function from
the header file clang/lib/Basic/Targets/PPC.h to the source file
clang/lib/Basic/Targets/PPC.cpp.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D104125

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h


Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -350,24 +350,6 @@
   bool isSPRegName(StringRef RegName) const override {
 return RegName.equals("r1") || RegName.equals("x1");
   }
-
-  void defineXLCompatMacros(MacroBuilder &Builder) const {
-Builder.defineMacro("__popcntb", "__builtin_ppc_popcntb");
-Builder.defineMacro("__eieio", "__builtin_ppc_eieio");
-Builder.defineMacro("__iospace_eieio", "__builtin_ppc_iospace_eieio");
-Builder.defineMacro("__isync", "__builtin_ppc_isync");
-Builder.defineMacro("__lwsync", "__builtin_ppc_lwsync");
-Builder.defineMacro("__iospace_lwsync", "__builtin_ppc_iospace_lwsync");
-Builder.defineMacro("__sync", "__builtin_ppc_sync");
-Builder.defineMacro("__iospace_sync", "__builtin_ppc_iospace_sync");
-Builder.defineMacro("__dcbfl", "__builtin_ppc_dcbfl");
-Builder.defineMacro("__dcbflp", "__builtin_ppc_dcbflp");
-Builder.defineMacro("__dcbst", "__builtin_ppc_dcbst");
-Builder.defineMacro("__dcbt", "__builtin_ppc_dcbt");
-Builder.defineMacro("__dcbtst", "__builtin_ppc_dcbtst");
-Builder.defineMacro("__dcbz", "__builtin_ppc_dcbz");
-Builder.defineMacro("__icbt", "__builtin_ppc_icbt");
-  }
 };
 
 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -81,6 +81,24 @@
   return true;
 }
 
+static void defineXLCompatMacros(MacroBuilder &Builder) {
+  Builder.defineMacro("__popcntb", "__builtin_ppc_popcntb");
+  Builder.defineMacro("__eieio", "__builtin_ppc_eieio");
+  Builder.defineMacro("__iospace_eieio", "__builtin_ppc_iospace_eieio");
+  Builder.defineMacro("__isync", "__builtin_ppc_isync");
+  Builder.defineMacro("__lwsync", "__builtin_ppc_lwsync");
+  Builder.defineMacro("__iospace_lwsync", "__builtin_ppc_iospace_lwsync");
+  Builder.defineMacro("__sync", "__builtin_ppc_sync");
+  Builder.defineMacro("__iospace_sync", "__builtin_ppc_iospace_sync");
+  Builder.defineMacro("__dcbfl", "__builtin_ppc_dcbfl");
+  Builder.defineMacro("__dcbflp", "__builtin_ppc_dcbflp");
+  Builder.defineMacro("__dcbst", "__builtin_ppc_dcbst");
+  Builder.defineMacro("__dcbt", "__builtin_ppc_dcbt");
+  Builder.defineMacro("__dcbtst", "__builtin_ppc_dcbtst");
+  Builder.defineMacro("__dcbz", "__builtin_ppc_dcbz");
+  Builder.defineMacro("__icbt", "__builtin_ppc_icbt");
+}
+
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
 /// #defines that are not tied to a specific subtarget.
 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,


Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -350,24 +350,6 @@
   bool isSPRegName(StringRef RegName) const override {
 return RegName.equals("r1") || RegName.equals("x1");
   }
-
-  void defineXLCompatMacros(MacroBuilder &Builder) const {
-Builder.defineMacro("__popcntb", "__builtin_ppc_popcntb");
-Builder.defineMacro("__eieio", "__builtin_ppc_eieio");
-Builder.defineMacro("__iospace_eieio", "__builtin_ppc_iospace_eieio");
-Builder.defineMacro("__isync", "__builtin_ppc_isync");
-Builder.defineMacro("__lwsync", "__builtin_ppc_lwsync");
-Builder.defineMacro("__iospace_lwsync", "__builtin_ppc_iospace_lwsync");
-Builder.defineMacro("__sync", "__builtin_ppc_sync");
-Builder.defineMacro("__iospace_sync", "__builtin_ppc_iospace_sync");
-Builder.defineMacro("__dcbfl", "__builtin_ppc_dcbfl");
-Builder.defineMacro("__dcbflp", "__builtin_ppc_dcbflp");
-Builder.defineMacro("__dcbst", "__builtin_ppc_dcbst");
-Builder.defineMacro("__dcbt", "__builtin_ppc_dcbt");
-Builder.defineMacro("__dcbtst", "__builtin_ppc_dcbtst");
-Builder.defineMacro("__dcbz", "__builtin_ppc_dcbz");
-Builder.defineMacro("__icbt", "__builtin_ppc_icbt");
-  }
 };
 
 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -81,6 +81,24 @@
   return true;
 }
 
+static void defineXLCompatMacros(MacroBuilder 

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 352240.
quinnp added a comment.

Changed the target architecture of tests to follow the convention: BE-pwr7 
LE-pwr8.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103986/new/

https://reviews.llvm.org/D103986

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-fp.c
  clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
@@ -0,0 +1,74 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+
+define dso_local double @test_fsel(double %a, double %b, double %c) local_unnamed_addr #0 {
+; CHECK-LABEL: test_fsel 
+
+entry:
+  %0 = tail call double @llvm.ppc.fsel(double %a, double %b, double %c)
+; CHECK: fsel f1, f1, f2, f3
+
+  ret double %0
+; CHECK: blr
+}
+
+declare double @llvm.ppc.fsel(double, double, double) #2
+
+define dso_local float @test_fsels(float %a, float %b, float %c) local_unnamed_addr #0 {
+; CHECK-LABEL: test_fsels
+
+entry:
+  %0 = tail call float @llvm.ppc.fsels(float %a, float %b, float %c)
+; CHECK: fsel f1, f1, f2, f3
+
+  ret float %0
+; CHECK: blr
+}
+
+declare float @llvm.ppc.fsels(float, float, float) #2
+
+define dso_local double @test_frsqrte(double %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test_frsqrte
+
+entry:
+  %0 = tail call double @llvm.ppc.frsqrte(double %a)
+; CHECK: xsrsqrtedp f1, f1
+
+  ret double %0
+; CHECK: blr
+}
+
+declare double @llvm.ppc.frsqrte(double) #2
+
+define dso_local float @test_frsqrtes(float %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test_frsqrtes
+
+entry:
+  %0 = tail call float @llvm.ppc.frsqrtes(float %a)
+; CHECK: frsqrtes f1, f1
+ 
+  ret float %0
+; CHECK: blr
+}
+
+declare float @llvm.ppc.frsqrtes(float) #2
+
+define dso_local float @test_fsqrts(float %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test_fsqrts
+
+entry:
+  %0 = tail call float @llvm.ppc.fsqrts(float %a)
+; CHECK fsqrts f1, f1
+
+  ret float %0
+; CHECK: blr
+}
+
+declare float @llvm.ppc.fsqrts(float) #2
+
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
@@ -1,11 +1,11 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
 ; RUN: -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN: -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
 
 define dso_local void @test_builtin_ppc_eieio() #0 {
 ; CHECK-LABEL: test_builtin_ppc_eieio
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
@@ -1,11 +1,11 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
 ; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
-; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN:-mattr=+msync -mcpu=pwr7 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
-; RUN:-mattr=+msync -mcpu=pwr8 < %s | FileCheck %s
+; RUN:-mattr=+msync -mcpu=pwr7 < %s | FileCheck %s
 
 define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
 ; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
Index: llvm/lib/Target/Po

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 353475.
quinnp added a comment.

Addressing comments and updating tests


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103986/new/

https://reviews.llvm.org/D103986

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-fp.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
@@ -0,0 +1,60 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+
+define dso_local double @test_fsel(double %a, double %b, double %c) local_unnamed_addr #0 {
+; CHECK-LABEL: test_fsel 
+
+entry:
+  %0 = tail call double @llvm.ppc.fsel(double %a, double %b, double %c)
+; CHECK: fsel 1, 1, 2, 3
+
+  ret double %0
+; CHECK: blr
+}
+
+declare double @llvm.ppc.fsel(double, double, double) #2
+
+define dso_local float @test_fsels(float %a, float %b, float %c) local_unnamed_addr #0 {
+; CHECK-LABEL: test_fsels
+
+entry:
+  %0 = tail call float @llvm.ppc.fsels(float %a, float %b, float %c)
+; CHECK: fsel 1, 1, 2, 3
+
+  ret float %0
+; CHECK: blr
+}
+
+declare float @llvm.ppc.fsels(float, float, float) #2
+
+define dso_local double @test_frsqrte(double %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test_frsqrte
+
+entry:
+  %0 = tail call double @llvm.ppc.frsqrte(double %a)
+; CHECK: xsrsqrtedp 1, 1
+
+  ret double %0
+; CHECK: blr
+}
+
+declare double @llvm.ppc.frsqrte(double) #2
+
+define dso_local float @test_frsqrtes(float %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test_frsqrtes
+
+entry:
+  %0 = tail call float @llvm.ppc.frsqrtes(float %a)
+; CHECK: xsrsqrtesp 1, 1
+ 
+  ret float %0
+; CHECK: blr
+}
+
+declare float @llvm.ppc.frsqrtes(float) #2
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -4954,6 +4954,9 @@
 } // HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian
 } // AddedComplexity = 400
 
+def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
+def : Pat<(int_ppc_frsqrtes vssrc:$XB), (XSRSQRTESP $XB)>;
+
 // Instruction aliases ---//
 def : InstAlias<"xvmovdp $XT, $XB",
 (XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3318,6 +3318,8 @@
   }
 }
 
+def : Pat<(int_ppc_fsel f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), (FSELD $FRA, $FRC, $FRB)>;
+
 let hasSideEffects = 0 in {
 let PPC970_Unit = 1 in {  // FXU Operations.
   let isSelect = 1 in
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -4987,6 +4987,13 @@
 break;
 
   case ISD::INTRINSIC_WO_CHAIN: {
+
+if (N->getConstantOperandVal(0) == Intrinsic::ppc_fsels) {
+  SDValue ops[] = {N->getOperand(1), N->getOperand(2), N->getOperand(3)};
+  CurDAG->SelectNodeTo(N, PPC::FSELS, MVT::f32, ops);
+  return;
+}
+
 if (!Subtarget->isISA3_1())
   break;
 unsigned Opcode = 0;
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1523,5 +1523,16 @@
   Intrinsic<[],[],[]>;
   def int_ppc_iospace_eieio : GCCBuiltin<"__builtin_ppc_iospace_eieio">,
   Intrinsic<[],[],[]>;
+
+  def int_ppc_fsel : GCCBuiltin<"__builtin_ppc_fsel">,
+ Intrinsic<[llvm_double_ty], [llvm_double_ty, 
+ llvm_double_ty, llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_fsels : GCCBuiltin<"__builtin_ppc_fsels">,
+  Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty,
+  llvm_float_ty], [IntrNoMem]>;
+  def int_ppc_frsqrte : GCCBuiltin<"__builtin_ppc_frsqrte">,
+Intrinsic<[llvm_double_ty], [llvm_doub

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 353716.
quinnp marked 2 inline comments as done.
quinnp added a comment.

Fixing the 32bit AIX run line in the testcases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103986/new/

https://reviews.llvm.org/D103986

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-fp.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
@@ -0,0 +1,60 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+
+define dso_local double @test_fsel(double %a, double %b, double %c) local_unnamed_addr #0 {
+; CHECK-LABEL: test_fsel 
+
+entry:
+  %0 = tail call double @llvm.ppc.fsel(double %a, double %b, double %c)
+; CHECK: fsel 1, 1, 2, 3
+
+  ret double %0
+; CHECK: blr
+}
+
+declare double @llvm.ppc.fsel(double, double, double) #2
+
+define dso_local float @test_fsels(float %a, float %b, float %c) local_unnamed_addr #0 {
+; CHECK-LABEL: test_fsels
+
+entry:
+  %0 = tail call float @llvm.ppc.fsels(float %a, float %b, float %c)
+; CHECK: fsel 1, 1, 2, 3
+
+  ret float %0
+; CHECK: blr
+}
+
+declare float @llvm.ppc.fsels(float, float, float) #2
+
+define dso_local double @test_frsqrte(double %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test_frsqrte
+
+entry:
+  %0 = tail call double @llvm.ppc.frsqrte(double %a)
+; CHECK: xsrsqrtedp 1, 1
+
+  ret double %0
+; CHECK: blr
+}
+
+declare double @llvm.ppc.frsqrte(double) #2
+
+define dso_local float @test_frsqrtes(float %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test_frsqrtes
+
+entry:
+  %0 = tail call float @llvm.ppc.frsqrtes(float %a)
+; CHECK: xsrsqrtesp 1, 1
+ 
+  ret float %0
+; CHECK: blr
+}
+
+declare float @llvm.ppc.frsqrtes(float) #2
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -4954,6 +4954,9 @@
 } // HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian
 } // AddedComplexity = 400
 
+def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
+def : Pat<(int_ppc_frsqrtes vssrc:$XB), (XSRSQRTESP $XB)>;
+
 // Instruction aliases ---//
 def : InstAlias<"xvmovdp $XT, $XB",
 (XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3318,6 +3318,8 @@
   }
 }
 
+def : Pat<(int_ppc_fsel f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), (FSELD $FRA, $FRC, $FRB)>;
+
 let hasSideEffects = 0 in {
 let PPC970_Unit = 1 in {  // FXU Operations.
   let isSelect = 1 in
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -4987,6 +4987,13 @@
 break;
 
   case ISD::INTRINSIC_WO_CHAIN: {
+
+if (N->getConstantOperandVal(0) == Intrinsic::ppc_fsels) {
+  SDValue ops[] = {N->getOperand(1), N->getOperand(2), N->getOperand(3)};
+  CurDAG->SelectNodeTo(N, PPC::FSELS, MVT::f32, ops);
+  return;
+}
+
 if (!Subtarget->isISA3_1())
   break;
 unsigned Opcode = 0;
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1523,5 +1523,16 @@
   Intrinsic<[],[],[]>;
   def int_ppc_iospace_eieio : GCCBuiltin<"__builtin_ppc_iospace_eieio">,
   Intrinsic<[],[],[]>;
+
+  def int_ppc_fsel : GCCBuiltin<"__builtin_ppc_fsel">,
+ Intrinsic<[llvm_double_ty], [llvm_double_ty, 
+ llvm_double_ty, llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_fsels : GCCBuiltin<"__builtin_ppc_fsels">,
+  Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty,
+  llvm_float_ty], [IntrNoMem]>;
+  def int_ppc_frsqrte : GCCBuiltin<"__builtin_ppc_frsqrte">,
+

[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 363189.
quinnp added a comment.

Addressing review comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106959/new/

https://reviews.llvm.org/D106959

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/CMakeLists.txt
  llvm/lib/Target/PowerPC/PPC.h
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/lib/Target/PowerPC/PPCLowerCheckedFPArith.cpp
  llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
  llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll
  llvm/test/CodeGen/PowerPC/O3-pipeline.ll
  llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll

Index: llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mattr=-vsx -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+define dso_local i32 @test_ftdivdp(double %a, double %b) local_unnamed_addr {
+; CHECK-LABEL: test_ftdivdp:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xstdivdp 0, 1, 2
+; CHECK-NEXT:mfocrf 3, 128
+; CHECK-NEXT:srwi 3, 3, 28
+; CHECK-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_ftdivdp:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:ftdiv 0, 1, 2
+; CHECK-NOVSX-NEXT:mfocrf 3, 128
+; CHECK-NOVSX-NEXT:srwi 3, 3, 28
+; CHECK-NOVSX-NEXT:blr
+entry:
+  %c = tail call i32 @llvm.ppc.ftdivdp(double %a, double %b)
+  ret i32 %c
+}
+
+declare i32 @llvm.ppc.ftdivdp(double, double)
Index: llvm/test/CodeGen/PowerPC/O3-pipeline.ll
===
--- llvm/test/CodeGen/PowerPC/O3-pipeline.ll
+++ llvm/test/CodeGen/PowerPC/O3-pipeline.ll
@@ -63,6 +63,8 @@
 ; CHECK-NEXT:   Expand vector predication intrinsics
 ; CHECK-NEXT:   Scalarize Masked Memory Intrinsics
 ; CHECK-NEXT:   Expand reduction intrinsics
+; CHECK-NEXT:   Lower Checked Floating Point Arithmetic
+; CHECK-NEXT:   Dominator Tree Construction
 ; CHECK-NEXT:   Natural Loop Information
 ; CHECK-NEXT:   CodeGen Prepare
 ; CHECK-NEXT:   Dominator Tree Construction
Index: llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll
@@ -0,0 +1,53 @@
+; RUN: opt -ppc-lower-checked-fp-arith -S -o - < %s | FileCheck %s
+
+@a = external local_unnamed_addr global double
+@b = external local_unnamed_addr global double
+@c = external local_unnamed_addr global float
+@d = external local_unnamed_addr global float
+
+; CHECK-LABEL: @test_swdiv(
+; CHECK:  %0 = load double, double* @a, align 8
+; CHECK-NEXT:  %1 = load double, double* @b, align 8
+; CHECK-NEXT:  %2 = call i32 @llvm.ppc.ftdivdp(double %0, double %1)
+; CHECK-NEXT:  %3 = icmp eq i32 %2, 0
+; CHECK-NEXT:  %4 = fdiv ninf arcp double %0, %1
+; CHECK-NEXT:  br i1 %3, label %swdiv_HWDIV, label %swdiv_MERGE
+
+; CHECK:  %5 = fdiv double %0, %1
+; CHECK-NEXT:  br label %swdiv_MERGE
+
+; CHECK:  %6 = phi double [ %4, %entry ], [ %5, %swdiv_HWDIV ]
+; CHECK-NEXT:  ret double %6
+
+define dso_local double @test_swdiv() local_unnamed_addr {
+entry:
+  %0 = load double, double* @a
+  %1 = load double, double* @b
+  %2 = tail call double @llvm.ppc.swdiv(double %0, double %1)
+  ret double %2
+}
+
+declare double @llvm.ppc.swdiv(double, double)
+
+; CHECK-LABEL: @test_swdivs(
+; CHECK:  %0 = load float, float* @c, align 4
+; CHECK-NEXT:  %1 = load float, float* @d, align 4
+; CHECK-NEXT:  %2 = fdiv ninf arcp float %0, %1
+; CHECK-NEXT:  %3 = fcmp une float %2, %2
+; CHECK-NEXT:  br i1 %3, label %swdiv_HWDIV, label %swdiv_MERGE
+
+; CHECK:  %4 = fdiv float %0, %1
+; CHECK-NEXT:  br label %swdiv_MERGE
+
+; CHECK:  %5 = phi float [ %2, %entry ], [ %4, %swdiv_HWDIV ]
+; CHECK-NEXT:  ret float %5
+
+define dso_local float @test_swdivs() local_unnamed_addr {
+entry:
+  %0 = load float, float* @c
+  %1 = load float, float* @d
+  %2 = tail call float @llvm.ppc.swdivs(float %0, float %1)
+  ret float %2
+}
+
+declare float @llvm.ppc.swdivs(float, float)
Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
===

[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

[Quinn Pham via Phabricator via cfe-commits]

quinnp marked an inline comment as done.
quinnp added inline comments.



Comment at: llvm/test/CodeGen/PowerPC/LowerCheckedFPArith.ll:36
+; CHECK-NEXT:  %2 = fdiv fast float %0, %1
+; CHECK-NEXT:  %3 = fcmp une float %2, %2
+; CHECK-NEXT:  br i1 %3, label %swdiv_HWDIV, label %swdiv_MERGE

efriedma wrote:
> A "fast" fdiv never produces NaN, per LangRef.  Using fcmp like this is 
> fragile at best.
> 
> (Maybe you want "fdiv arcp"?)
Thank you, I see what you mean. I have changed it to emit a `fdiv ninf arcp` 
instead of a `fdiv fast`. I included the `ninf` flag because without it the 
compiler doesn't produce the software div estimate.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106959/new/

https://reviews.llvm.org/D106959

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 354498.
quinnp added a comment.

Added non-vsx implementation of builtins and non-vsx backend tests


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103986/new/

https://reviews.llvm.org/D103986

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-fp.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
@@ -0,0 +1,92 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN: -mattr=-vsx -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN: -mattr=-vsx -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mattr=-vsx -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mattr=-vsx -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+define dso_local double @test_fsel(double %a, double %b, double %c) local_unnamed_addr #0 {
+; CHECK-PWR7-LABEL: test_fsel 
+; CHECK-PWR8-LABEL: test_fsel
+; CHECK-NOVSX-LABEL: test_fsel
+
+entry:
+  %0 = tail call double @llvm.ppc.fsel(double %a, double %b, double %c)
+; CHECK-PWR7: fsel 1, 1, 2, 3
+; CHECK-PWR8: fsel 1, 1, 2, 3
+; CHECK-NOVSX: fsel 1, 1, 2, 3
+
+  ret double %0
+; CHECK-PWR7: blr
+; CHECK-PWR8: blr
+; CHECK-NOVSX: blr
+}
+
+declare double @llvm.ppc.fsel(double, double, double) #2
+
+define dso_local float @test_fsels(float %a, float %b, float %c) local_unnamed_addr #0 {
+; CHECK-PWR7-LABEL: test_fsels
+; CHECK-PWR8-LABEL: test_fsels
+; CHECK-NOVSX-LABEL: test_fsels
+
+entry:
+  %0 = tail call float @llvm.ppc.fsels(float %a, float %b, float %c)
+; CHECK-PWR7: fsel 1, 1, 2, 3
+; CHECK-PWR8: fsel 1, 1, 2, 3
+; CHECK-NOVSX: fsel 1, 1, 2, 3
+
+  ret float %0
+; CHECK-PWR7: blr
+; CHECK-PWR8: blr
+; CHECK-NOVSX: blr
+}
+
+declare float @llvm.ppc.fsels(float, float, float) #2
+
+define dso_local double @test_frsqrte(double %a) local_unnamed_addr #0 {
+; CHECK-PWR7-LABEL: test_frsqrte
+; CHECK-PWR8-LABEL: test_frsqrte
+; CHECK-NOVSX-LABEL: test_frsqrte
+
+entry:
+  %0 = tail call double @llvm.ppc.frsqrte(double %a)
+; CHECK-PWR7: xsrsqrtedp 1, 1
+; CHECK-PWR8: xsrsqrtedp 1, 1
+; CHECK-NOVSX: frsqrte 1, 1
+
+  ret double %0
+; CHECK-PWR7: blr
+; CHECK-PWR8: blr
+; CHECK-NOVSX: blr
+}
+
+declare double @llvm.ppc.frsqrte(double) #2
+
+define dso_local float @test_frsqrtes(float %a) local_unnamed_addr #0 {
+; CHECK-PWR7-LABEL: test_frsqrtes
+; CHECK-PWR8-LABEL: test_frsqrtes
+; CHECK-NOVSX-LABEL: test_frsqrtes
+
+entry:
+  %0 = tail call float @llvm.ppc.frsqrtes(float %a)
+; CHECK-PWR7: frsqrtes 1, 1
+; CHECK-PWR8: xsrsqrtesp 1, 1
+; CHECK-NOVSX: frsqrtes 1, 1 
+
+  ret float %0
+; CHECK-PWR7: blr
+; CHECK-PWR8: blr
+; CHECK-NOVSX: blr
+}
+
+declare float @llvm.ppc.frsqrtes(float) #2
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -2850,6 +2850,8 @@
 def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 199)),
   (VCMPGTUB_rec DblwdCmp.MRGEQ, (v2i64 (XXLXORz)))>;
 } // AddedComplexity = 0
+
+def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
 } // HasVSX
 
 // Any big endian VSX subtarget.
@@ -3240,6 +3242,8 @@
   (v8i16 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
 def : Pat<(v16i8 (bitconvert (v16i8 immAllOnesV))),
   (v16i8 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
+
+def : Pat<(int_ppc_frsqrtes vssrc:$XB), (XSRSQRTESP $XB)>;
 } // HasVSX, HasP8Vector
 
 // Any big endian Power8 VSX subtarget.
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -4382,6 +4382,10 @@
 def : Pat<(i1 (not (trunc i64:$in))),
(

[PATCH] D105360: [PowerPC] Fix popcntb XL Compat Builtin for 32bit

[Quinn Pham via Phabricator via cfe-commits]

quinnp created this revision.
Herald added subscribers: shchenz, kbarton, hiraditya, nemanjai.
quinnp requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D105360

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
+++ /dev/null
@@ -1,74 +0,0 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
-
-define dso_local void @test_builtin_ppc_eieio() #0 {
-; CHECK-LABEL: test_builtin_ppc_eieio
-
-entry:
-  call void @llvm.ppc.eieio()
-; CHECK: ori 2, 2, 0
-; CHECK-NEXT: ori 2, 2, 0
-; CHECK-NEXT: eieio
- 
-  ret void
-}
-
-declare void @llvm.ppc.eieio() #2
-
-define dso_local void @test_builtin_ppc_iospace_eieio() #0 {
-; CHECK-LABEL: test_builtin_ppc_iospace_eieio
-
-entry:
-  call void @llvm.ppc.iospace.eieio()
-; CHECK: ori 2, 2, 0
-; CHECK-NEXT: ori 2, 2, 0
-; CHECK-NEXT: eieio
- 
-  ret void
-}
-
-declare void @llvm.ppc.iospace.eieio() #2
-
-define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
-; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
-
-entry:
-  call void @llvm.ppc.iospace.lwsync()
-; CHECK: lwsync
-
-  ret void
-}
-
-declare void @llvm.ppc.iospace.lwsync() #2
-
-define dso_local void @test_builtin_ppc_iospace_sync() #0 {
-; CHECK-LABEL: test_builtin_ppc_iospace_sync
-
-entry:
-  call void @llvm.ppc.iospace.sync()
-; CHECK: sync
-
-  ret void
-}
-
-declare void @llvm.ppc.iospace.sync() #2
-
-define dso_local void @test_builtin_ppc_icbt() #0 {
-; CHECK-LABEL: test_builtin_ppc_icbt
-
-entry:
-  %a = alloca i8*, align 8
-  %0 = load i8*, i8** %a, align 8
-  call void @llvm.ppc.icbt(i8* %0)
-; CHECK: icbt 0, 0, 3
-
-  ret void
-}
-
-declare void @llvm.ppc.icbt(i8*) #2
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
@@ -0,0 +1,90 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+
+define dso_local i64 @test_builtin_ppc_popcntb_i64(i64 %a) local_unnamed_addr {
+; CHECK-LABEL: test_builtin_ppc_popcntb_i64
+
+entry:
+  %popcntb = tail call i64 @llvm.ppc.popcntb.i64.i64(i64 %a)
+; CHECK: popcntb 3, 3
+
+  ret i64 %popcntb
+; CHECK: blr
+}
+
+declare i64 @llvm.ppc.popcntb.i64.i64(i64)
+
+define dso_local void @test_builtin_ppc_eieio() {
+; CHECK-LABEL: test_builtin_ppc_eieio
+
+entry:
+  call void @llvm.ppc.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+; CHECK: blr
+}
+
+declare void @llvm.ppc.eieio()
+
+define dso_local void @test_builtin_ppc_iospace_eieio() {
+; CHECK-LABEL: test_builtin_ppc_iospace_eieio
+
+entry:
+  call void @llvm.ppc.iospace.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+; CHECK: blr
+}
+
+declare void @llvm.ppc.iospace.eieio()
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: lwsync
+
+  ret void
+; CHECK: blr
+}
+
+declare void @llvm.ppc.iospace.lwsync()
+
+define dso_local void @test_builtin_ppc_iospace_sync() {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: sync
+
+  ret void
+; CHECK: blr
+}
+
+declare void @llvm.ppc.iospace.sync()
+
+define dso_local void @test_builtin_ppc_icbt() {
+; CHECK-LABEL: test_builtin_ppc_icbt
+
+entry:
+  %a = alloca i8*, align 8
+  %0 = load i8*, i8** %a, align 8
+  call void @llvm.ppc.icbt(i8* %0)
+; CHECK: icbt 0, 0, 3
+
+  ret void
+; CHECK: blr
+}
+
+declare void @llvm.ppc.icbt(i8

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 356264.
quinnp marked an inline comment as done.
quinnp added a comment.

Addressing review comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103986/new/

https://reviews.llvm.org/D103986

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-fp.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
@@ -0,0 +1,92 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN: -mattr=-vsx -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN: -mattr=-vsx -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mattr=-vsx -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mattr=-vsx -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+define dso_local double @test_fsel(double %a, double %b, double %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsel 
+; CHECK-PWR8-LABEL: test_fsel
+; CHECK-NOVSX-LABEL: test_fsel
+
+entry:
+  %0 = tail call double @llvm.ppc.fsel(double %a, double %b, double %c)
+; CHECK-PWR7: fsel 1, 1, 2, 3
+; CHECK-PWR8: fsel 1, 1, 2, 3
+; CHECK-NOVSX: fsel 1, 1, 2, 3
+
+  ret double %0
+; CHECK-PWR7: blr
+; CHECK-PWR8: blr
+; CHECK-NOVSX: blr
+}
+
+declare double @llvm.ppc.fsel(double, double, double)
+
+define dso_local float @test_fsels(float %a, float %b, float %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsels
+; CHECK-PWR8-LABEL: test_fsels
+; CHECK-NOVSX-LABEL: test_fsels
+
+entry:
+  %0 = tail call float @llvm.ppc.fsels(float %a, float %b, float %c)
+; CHECK-PWR7: fsel 1, 1, 2, 3
+; CHECK-PWR8: fsel 1, 1, 2, 3
+; CHECK-NOVSX: fsel 1, 1, 2, 3
+
+  ret float %0
+; CHECK-PWR7: blr
+; CHECK-PWR8: blr
+; CHECK-NOVSX: blr
+}
+
+declare float @llvm.ppc.fsels(float, float, float)
+
+define dso_local double @test_frsqrte(double %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrte
+; CHECK-PWR8-LABEL: test_frsqrte
+; CHECK-NOVSX-LABEL: test_frsqrte
+
+entry:
+  %0 = tail call double @llvm.ppc.frsqrte(double %a)
+; CHECK-PWR7: xsrsqrtedp 1, 1
+; CHECK-PWR8: xsrsqrtedp 1, 1
+; CHECK-NOVSX: frsqrte 1, 1
+
+  ret double %0
+; CHECK-PWR7: blr
+; CHECK-PWR8: blr
+; CHECK-NOVSX: blr
+}
+
+declare double @llvm.ppc.frsqrte(double)
+
+define dso_local float @test_frsqrtes(float %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrtes
+; CHECK-PWR8-LABEL: test_frsqrtes
+; CHECK-NOVSX-LABEL: test_frsqrtes
+
+entry:
+  %0 = tail call float @llvm.ppc.frsqrtes(float %a)
+; CHECK-PWR7: frsqrtes 1, 1
+; CHECK-PWR8: xsrsqrtesp 1, 1
+; CHECK-NOVSX: frsqrtes 1, 1 
+
+  ret float %0
+; CHECK-PWR7: blr
+; CHECK-PWR8: blr
+; CHECK-NOVSX: blr
+}
+
+declare float @llvm.ppc.frsqrtes(float)
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -2850,6 +2850,8 @@
 def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 199)),
   (VCMPGTUB_rec DblwdCmp.MRGEQ, (v2i64 (XXLXORz)))>;
 } // AddedComplexity = 0
+
+def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
 } // HasVSX
 
 // Any big endian VSX subtarget.
@@ -3240,6 +3242,8 @@
   (v8i16 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
 def : Pat<(v16i8 (bitconvert (v16i8 immAllOnesV))),
   (v16i8 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
+
+def : Pat<(int_ppc_frsqrtes vssrc:$XB), (XSRSQRTESP $XB)>;
 } // HasVSX, HasP8Vector
 
 // Any big endian Power8 VSX subtarget.
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -4382,6 +4382,10 @@
 def : Pat<(i1 (not (trunc i64:$in))),
(ANDI_rec_1_EQ_BIT8 $in

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Quinn Pham via Phabricator via cfe-commits]

quinnp updated this revision to Diff 356272.
quinnp marked 4 inline comments as done.
quinnp added a comment.

Fixing a typo and the format of a test.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103986/new/

https://reviews.llvm.org/D103986

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-fp.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll
@@ -0,0 +1,92 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN: -mattr=-vsx -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN: -mattr=-vsx -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mattr=-vsx -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mattr=-vsx -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+define dso_local double @test_fsel(double %a, double %b, double %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsel 
+; CHECK-PWR8-LABEL: test_fsel
+; CHECK-NOVSX-LABEL: test_fsel
+
+entry:
+  %0 = tail call double @llvm.ppc.fsel(double %a, double %b, double %c)
+; CHECK-PWR7: fsel 1, 1, 2, 3
+; CHECK-PWR8: fsel 1, 1, 2, 3
+; CHECK-NOVSX: fsel 1, 1, 2, 3
+
+  ret double %0
+; CHECK-PWR7: blr
+; CHECK-PWR8: blr
+; CHECK-NOVSX: blr
+}
+
+declare double @llvm.ppc.fsel(double, double, double)
+
+define dso_local float @test_fsels(float %a, float %b, float %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsels
+; CHECK-PWR8-LABEL: test_fsels
+; CHECK-NOVSX-LABEL: test_fsels
+
+entry:
+  %0 = tail call float @llvm.ppc.fsels(float %a, float %b, float %c)
+; CHECK-PWR7: fsel 1, 1, 2, 3
+; CHECK-PWR8: fsel 1, 1, 2, 3
+; CHECK-NOVSX: fsel 1, 1, 2, 3
+
+  ret float %0
+; CHECK-PWR7: blr
+; CHECK-PWR8: blr
+; CHECK-NOVSX: blr
+}
+
+declare float @llvm.ppc.fsels(float, float, float)
+
+define dso_local double @test_frsqrte(double %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrte
+; CHECK-PWR8-LABEL: test_frsqrte
+; CHECK-NOVSX-LABEL: test_frsqrte
+
+entry:
+  %0 = tail call double @llvm.ppc.frsqrte(double %a)
+; CHECK-PWR7: xsrsqrtedp 1, 1
+; CHECK-PWR8: xsrsqrtedp 1, 1
+; CHECK-NOVSX: frsqrte 1, 1
+
+  ret double %0
+; CHECK-PWR7: blr
+; CHECK-PWR8: blr
+; CHECK-NOVSX: blr
+}
+
+declare double @llvm.ppc.frsqrte(double)
+
+define dso_local float @test_frsqrtes(float %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrtes
+; CHECK-PWR8-LABEL: test_frsqrtes
+; CHECK-NOVSX-LABEL: test_frsqrtes
+
+entry:
+  %0 = tail call float @llvm.ppc.frsqrtes(float %a)
+; CHECK-PWR7: frsqrtes 1, 1
+; CHECK-PWR8: xsrsqrtesp 1, 1
+; CHECK-NOVSX: frsqrtes 1, 1 
+
+  ret float %0
+; CHECK-PWR7: blr
+; CHECK-PWR8: blr
+; CHECK-NOVSX: blr
+}
+
+declare float @llvm.ppc.frsqrtes(float)
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -2850,6 +2850,8 @@
 def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 199)),
   (VCMPGTUB_rec DblwdCmp.MRGEQ, (v2i64 (XXLXORz)))>;
 } // AddedComplexity = 0
+
+def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
 } // HasVSX
 
 // Any big endian VSX subtarget.
@@ -3240,6 +3242,8 @@
   (v8i16 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
 def : Pat<(v16i8 (bitconvert (v16i8 immAllOnesV))),
   (v16i8 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
+
+def : Pat<(int_ppc_frsqrtes vssrc:$XB), (XSRSQRTESP $XB)>;
 } // HasVSX, HasP8Vector
 
 // Any big endian Power8 VSX subtarget.
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -4382,6 +4382,10 @@
 def : Pat<(i1 (not (trunc i64:$in))),
(ANDI_rec_1