[llvm] [clang] [AMDGPU] Add an option to disable unsafe uses of atomic xor (PR #69229)
pasaulais wrote: @arsenm, could you share this unfinished patch you were working on? I could start from scratch but I don't want to duplicate the work you've already done. https://github.com/llvm/llvm-project/pull/69229 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [AMDGPU] Add an option to disable unsafe uses of atomic xor (PR #69229)
https://github.com/pasaulais edited https://github.com/llvm/llvm-project/pull/69229 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [AMDGPU] Add an option to disable unsafe uses of atomic xor (PR #69229)
https://github.com/pasaulais updated
https://github.com/llvm/llvm-project/pull/69229
>From 24b0e5204f9eac6efaf502b5aa254f5ff7e11e69 Mon Sep 17 00:00:00 2001
From: Pierre-Andre Saulais
Date: Thu, 23 Nov 2023 17:33:18 +
Subject: [PATCH] [AMDGPU] Add an option to disable unsafe uses of atomic xor
---
clang/include/clang/Basic/TargetInfo.h| 8 +++
clang/include/clang/Basic/TargetOptions.h | 3 +
clang/include/clang/Driver/Options.td | 10 +++
clang/lib/Basic/TargetInfo.cpp| 1 +
clang/lib/Basic/Targets/AMDGPU.cpp| 1 +
clang/lib/CodeGen/Targets/AMDGPU.cpp | 23 +++
clang/lib/Driver/ToolChains/Clang.cpp | 2 +
.../amdgpu-unsafe-int-atomics.cl | 62 +++
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 26
llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll | 24 +--
10 files changed, 156 insertions(+), 4 deletions(-)
create mode 100644 clang/test/CodeGenOpenCL/amdgpu-unsafe-int-atomics.cl
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 41f3c2e403cbe..c222e370442df 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -269,6 +269,9 @@ class TargetInfo : public TransferrableTargetInfo,
LLVM_PREFERRED_TYPE(bool)
unsigned ARMCDECoprocMask : 8;
+ LLVM_PREFERRED_TYPE(bool)
+ unsigned AllowAMDGPUFineGrainedMem : 1;
+
unsigned MaxOpenCLWorkGroupSize;
std::optional MaxBitIntWidth;
@@ -1009,6 +1012,11 @@ class TargetInfo : public TransferrableTargetInfo,
/// allowed.
bool allowAMDGPUUnsafeFPAtomics() const { return AllowAMDGPUUnsafeFPAtomics;
}
+ /// Returns whether or not fine-grained memory access is allowed on AMDGPU.
+ bool allowAMDGPUFineGrainedMem() const {
+return AllowAMDGPUFineGrainedMem;
+ }
+
/// For ARM targets returns a mask defining which coprocessors are configured
/// as Custom Datapath.
uint32_t getARMCDECoprocMask() const { return ARMCDECoprocMask; }
diff --git a/clang/include/clang/Basic/TargetOptions.h
b/clang/include/clang/Basic/TargetOptions.h
index 2049f03b28893..90cfe6d71c6d0 100644
--- a/clang/include/clang/Basic/TargetOptions.h
+++ b/clang/include/clang/Basic/TargetOptions.h
@@ -78,6 +78,9 @@ class TargetOptions {
/// \brief If enabled, allow AMDGPU unsafe floating point atomics.
bool AllowAMDGPUUnsafeFPAtomics = false;
+ /// \brief If enabled, allow fine-grained memory access on AMDGPU.
+ bool AllowAMDGPUFineGrainedMem = false;
+
/// \brief Code object version for AMDGPU.
llvm::CodeObjectVersionKind CodeObjectVersion =
llvm::CodeObjectVersionKind::COV_None;
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 1d04e4f6e7e6d..71cc5aeb5c4e6 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4749,6 +4749,16 @@ defm unsafe_fp_atomics : BoolOption<"m",
"unsafe-fp-atomics",
def faltivec : Flag<["-"], "faltivec">, Group;
def fno_altivec : Flag<["-"], "fno-altivec">, Group;
+
+defm amdgpu_fine_grained_mem : BoolOption<"m", "amdgpu-fine-grained-mem",
+ TargetOpts<"AllowAMDGPUFineGrainedMem">, DefaultFalse,
+ PosFlag,
+ NegFlag>, Group;
+
let Flags = [TargetSpecific] in {
def maltivec : Flag<["-"], "maltivec">, Group,
HelpText<"Enable AltiVec vector initializer syntax">;
diff --git a/clang/lib/Basic/TargetInfo.cpp b/clang/lib/Basic/TargetInfo.cpp
index 6cd5d618a4aca..8e623b59365e5 100644
--- a/clang/lib/Basic/TargetInfo.cpp
+++ b/clang/lib/Basic/TargetInfo.cpp
@@ -157,6 +157,7 @@ TargetInfo::TargetInfo(const llvm::Triple &T) : Triple(T) {
HasAArch64SVETypes = false;
HasRISCVVTypes = false;
AllowAMDGPUUnsafeFPAtomics = false;
+ AllowAMDGPUFineGrainedMem = false;
ARMCDECoprocMask = 0;
// Default to no types using fpret.
diff --git a/clang/lib/Basic/Targets/AMDGPU.cpp
b/clang/lib/Basic/Targets/AMDGPU.cpp
index 409ae32ab4242..cf70d2e267d3e 100644
--- a/clang/lib/Basic/Targets/AMDGPU.cpp
+++ b/clang/lib/Basic/Targets/AMDGPU.cpp
@@ -232,6 +232,7 @@ AMDGPUTargetInfo::AMDGPUTargetInfo(const llvm::Triple
&Triple,
HasFloat16 = true;
WavefrontSize = GPUFeatures & llvm::AMDGPU::FEATURE_WAVE32 ? 32 : 64;
AllowAMDGPUUnsafeFPAtomics = Opts.AllowAMDGPUUnsafeFPAtomics;
+ AllowAMDGPUFineGrainedMem = Opts.AllowAMDGPUFineGrainedMem;
// Set pointer width and alignment for the generic address space.
PointerWidth = PointerAlign = getPointerWidthV(LangAS::Default);
diff --git a/clang/lib/CodeGen/Targets/AMDGPU.cpp
b/clang/lib/CodeGen/Targets/AMDGPU.cpp
index b654e3f12af8d..13bec674db8a4 100644
--- a/clang/lib/CodeGen/Targets/AMDGPU.cpp
+++ b/clang/lib/CodeGen/Targets/AMDGPU.cpp
@@ -392,6 +392,26 @@ void AMDGPUTargetCodeGenInfo::emitTargetGlobals(
}
}
+// Add metadata to specific atomic instructions, to mark them as potentially
+// accessing fine-grained memory locations.
+static void addFineGrainedAto
[llvm] [clang] [AMDGPU] Add an option to disable unsafe uses of atomic xor (PR #69229)
https://github.com/pasaulais updated
https://github.com/llvm/llvm-project/pull/69229
>From cd33e8471ab5e768c1b579f1bec1308c0b322e05 Mon Sep 17 00:00:00 2001
From: Pierre-Andre Saulais
Date: Thu, 23 Nov 2023 17:33:18 +
Subject: [PATCH] [AMDGPU] Add an option to disable unsafe uses of atomic xor
---
clang/include/clang/Basic/TargetInfo.h| 6 ++
clang/include/clang/Basic/TargetOptions.h | 3 +
clang/include/clang/Driver/Options.td | 10 +++
clang/lib/Basic/TargetInfo.cpp| 1 +
clang/lib/Basic/Targets/AMDGPU.cpp| 1 +
clang/lib/CodeGen/Targets/AMDGPU.cpp | 23 +++
clang/lib/Driver/ToolChains/Clang.cpp | 2 +
.../amdgpu-unsafe-int-atomics.cl | 62 +++
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 26
llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll | 24 +--
10 files changed, 154 insertions(+), 4 deletions(-)
create mode 100644 clang/test/CodeGenOpenCL/amdgpu-unsafe-int-atomics.cl
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 41f3c2e403cbe..867c4ebefa933 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -269,6 +269,9 @@ class TargetInfo : public TransferrableTargetInfo,
LLVM_PREFERRED_TYPE(bool)
unsigned ARMCDECoprocMask : 8;
+ LLVM_PREFERRED_TYPE(bool)
+ unsigned AllowAMDGPUFineGrainedMem : 1;
+
unsigned MaxOpenCLWorkGroupSize;
std::optional MaxBitIntWidth;
@@ -1009,6 +1012,9 @@ class TargetInfo : public TransferrableTargetInfo,
/// allowed.
bool allowAMDGPUUnsafeFPAtomics() const { return AllowAMDGPUUnsafeFPAtomics;
}
+ /// Returns whether or not fine-grained memory access is allowed on AMDGPU.
+ bool allowAMDGPUFineGrainedMem() const { return AllowAMDGPUFineGrainedMem; }
+
/// For ARM targets returns a mask defining which coprocessors are configured
/// as Custom Datapath.
uint32_t getARMCDECoprocMask() const { return ARMCDECoprocMask; }
diff --git a/clang/include/clang/Basic/TargetOptions.h
b/clang/include/clang/Basic/TargetOptions.h
index 2049f03b28893..90cfe6d71c6d0 100644
--- a/clang/include/clang/Basic/TargetOptions.h
+++ b/clang/include/clang/Basic/TargetOptions.h
@@ -78,6 +78,9 @@ class TargetOptions {
/// \brief If enabled, allow AMDGPU unsafe floating point atomics.
bool AllowAMDGPUUnsafeFPAtomics = false;
+ /// \brief If enabled, allow fine-grained memory access on AMDGPU.
+ bool AllowAMDGPUFineGrainedMem = false;
+
/// \brief Code object version for AMDGPU.
llvm::CodeObjectVersionKind CodeObjectVersion =
llvm::CodeObjectVersionKind::COV_None;
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 1d04e4f6e7e6d..71cc5aeb5c4e6 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4749,6 +4749,16 @@ defm unsafe_fp_atomics : BoolOption<"m",
"unsafe-fp-atomics",
def faltivec : Flag<["-"], "faltivec">, Group;
def fno_altivec : Flag<["-"], "fno-altivec">, Group;
+
+defm amdgpu_fine_grained_mem : BoolOption<"m", "amdgpu-fine-grained-mem",
+ TargetOpts<"AllowAMDGPUFineGrainedMem">, DefaultFalse,
+ PosFlag,
+ NegFlag>, Group;
+
let Flags = [TargetSpecific] in {
def maltivec : Flag<["-"], "maltivec">, Group,
HelpText<"Enable AltiVec vector initializer syntax">;
diff --git a/clang/lib/Basic/TargetInfo.cpp b/clang/lib/Basic/TargetInfo.cpp
index 6cd5d618a4aca..8e623b59365e5 100644
--- a/clang/lib/Basic/TargetInfo.cpp
+++ b/clang/lib/Basic/TargetInfo.cpp
@@ -157,6 +157,7 @@ TargetInfo::TargetInfo(const llvm::Triple &T) : Triple(T) {
HasAArch64SVETypes = false;
HasRISCVVTypes = false;
AllowAMDGPUUnsafeFPAtomics = false;
+ AllowAMDGPUFineGrainedMem = false;
ARMCDECoprocMask = 0;
// Default to no types using fpret.
diff --git a/clang/lib/Basic/Targets/AMDGPU.cpp
b/clang/lib/Basic/Targets/AMDGPU.cpp
index 409ae32ab4242..cf70d2e267d3e 100644
--- a/clang/lib/Basic/Targets/AMDGPU.cpp
+++ b/clang/lib/Basic/Targets/AMDGPU.cpp
@@ -232,6 +232,7 @@ AMDGPUTargetInfo::AMDGPUTargetInfo(const llvm::Triple
&Triple,
HasFloat16 = true;
WavefrontSize = GPUFeatures & llvm::AMDGPU::FEATURE_WAVE32 ? 32 : 64;
AllowAMDGPUUnsafeFPAtomics = Opts.AllowAMDGPUUnsafeFPAtomics;
+ AllowAMDGPUFineGrainedMem = Opts.AllowAMDGPUFineGrainedMem;
// Set pointer width and alignment for the generic address space.
PointerWidth = PointerAlign = getPointerWidthV(LangAS::Default);
diff --git a/clang/lib/CodeGen/Targets/AMDGPU.cpp
b/clang/lib/CodeGen/Targets/AMDGPU.cpp
index b654e3f12af8d..13bec674db8a4 100644
--- a/clang/lib/CodeGen/Targets/AMDGPU.cpp
+++ b/clang/lib/CodeGen/Targets/AMDGPU.cpp
@@ -392,6 +392,26 @@ void AMDGPUTargetCodeGenInfo::emitTargetGlobals(
}
}
+// Add metadata to specific atomic instructions, to mark them as potentially
+// accessing fine-grained memory locations.
+static void addFineGrainedAtomicMD(llvm
[clang] [llvm] [AMDGPU] Add an option to disable unsafe uses of atomic xor (PR #69229)
pasaulais wrote: > > @arsenm That makes sense, I don't think MMRA fits the fine-grained use case > > either. Does that mean we can stick with the approach from this PR? > > @b-sumner mentioned there was another similar approach being worked on. > > Something like this, but the naming and direction of this PR is backwards. > The default should be assume fine grained memory is possible. We also have > another orthogonal bit we need to track in addition to fine grained memory. I > was envisioning this as a single integer interpreted as bitfields of the two, > but this uses different key:value metadata pairs. It should be named > "amdgpu.no.something" to assert the operation doesn't access fine grained @arsenm I agree that the default should be assuming fine-grained is possible. My thinking behind the original naming and direction was not wanting to introduce an unexpected performance regression by default. I'm happy for both to be changed, and this patch being rebased on top of https://github.com/llvm/llvm-project/pull/85052 once it is merged. One oustanding question for me is, although outside of the scope of this PR, how will the original 'no-unsafe-fp' option fit in the new metadata node in terms of constraints? Would it imply a new constraint or be covered by `no_fine_grained` and `no_remote`? https://github.com/llvm/llvm-project/pull/69229 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AMDGPU] Add an option to disable unsafe uses of atomic xor (PR #69229)
pasaulais wrote: Also, this will need to be extended to other operations that can be impacted by fine-grained and remote access like `add`, `and`, `or`, `sub`, `fpadd` and `fpsub`. https://github.com/llvm/llvm-project/pull/69229 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AMDGPU] Add an option to disable unsafe uses of atomic xor (PR #69229)
pasaulais wrote: > > In this case, MMRAs would only help in the sense that you won't need any > > new attributes and can just add an MMRA such as > > `atomic-lowering:fine-grained`. It's not really what MMRAs were made for > > (because this attribute doesn't affect semantics, just lowering style I > > think?), > > It is semantics. You get undefined behavior if you access fine grained memory > for an atomic where the instruction doesn't handle it. I don't think it quite > fits into the MMRA box, since it isn't about the synchronization properties > of the memory access but where the underlying memory is @arsenm That makes sense, I don't think MMRA fits the fine-grained use case either. Does that mean we can stick with the approach from this PR? @b-sumner mentioned there was another similar approach being worked on. https://github.com/llvm/llvm-project/pull/69229 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [AMDGPU] Add an option to disable unsafe uses of atomic xor (PR #69229)
pasaulais wrote: > The command-line changes look good to me. Adding @arsenm as a reviewer proper. Thanks Jan! https://github.com/llvm/llvm-project/pull/69229 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [AMDGPU] Add an option to disable unsafe uses of atomic xor (PR #69229)
pasaulais wrote: Ping @hdelan https://github.com/llvm/llvm-project/pull/69229 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [AMDGPU] Add an option to disable unsafe uses of atomic xor (PR #69229)
pasaulais wrote: Thanks for the review. I agree that function-level attributes are not ideal for solving this issue and instruction-level metadata would work better with things like inlining. Is the incomplete patch you mentioned something I could take on and complete? Regarding int vs floating-point, I'm afraid there is a need for toggling one independently of the other (or at least special-casing operations like XOR that are not supported by PCIe 3.0). As the link I posted in the description mentions (see this comment https://github.com/RadeonOpenCompute/ROCm/issues/2481#issuecomment-1725874765), there are configurations where using FP atomics like add would work whereas XOR doesn't, due to missing support in the PCIe 3.0 spec. I have reproduced this on a system with a RX 6700 XT GPU, where `global_atomic_add_f32` works as expected using fine-grained allocations, and `global_atomic_xor` doesn't. https://github.com/llvm/llvm-project/pull/69229 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [AMDGPU] Add an option to disable unsafe uses of atomic xor (PR #69229)
https://github.com/pasaulais created
https://github.com/llvm/llvm-project/pull/69229
On some systems and when accessing certain memory areas it is not safe to use
atomic xor with AMDGPU. This may be the case when using fine-grained memory
allocations (e.g. through `hipAllocManaged`) and when the atomic operation
needs to go through the PCIe bus, which does not support atomic xor (PCIe 3.0
does support other atomic operations like fetch_and_add and cmpxchg) [1].
The issue has been worked around in DPC++/HIP by prefetching memory before
executing kernels [2], however this adds an overhead that can outweigh the
performance benefit of using atomic xor over a cmpxchg loop. This is why a way
to switch between 'native' atomic xor and a cmpxchg-loop solution is needed.
These changes add `-munsafe-int-atomics` and `-mno-unsafe-int-atomics` options
to clang that can be used to switch between the two implementations. The
default is the current behaviour of generative 'native' atomic xor
instructions. When `-mno-unsafe-int-atomics` is passed to clang, functions are
marked with the `amdgpu-unsafe-int-atomics` attribute (set to `false`) at the
IR level and this tells the backend to expand atomic xor to a cmpxchg loop. The
options only affect the global and flat address spaces.
[1]: https://github.com/RadeonOpenCompute/ROCm/issues/2481
[2]: https://github.com/intel/llvm/pull/10430
>From 508e577fa67b590ad297e45aeb5210ec3190ebc9 Mon Sep 17 00:00:00 2001
From: Pierre-Andre Saulais
Date: Thu, 12 Oct 2023 16:00:20 +0100
Subject: [PATCH] [AMDGPU] Add an option to disable unsafe uses of atomic xor
---
clang/include/clang/Basic/TargetInfo.h| 7 +++
clang/include/clang/Basic/TargetOptions.h | 3 +
clang/include/clang/Driver/Options.td | 8 +++
clang/lib/Basic/TargetInfo.cpp| 1 +
clang/lib/Basic/Targets/AMDGPU.cpp| 1 +
clang/lib/CodeGen/Targets/AMDGPU.cpp | 3 +
clang/lib/Driver/ToolChains/Clang.cpp | 2 +
.../amdgpu-unsafe-int-atomics.cl | 55 +++
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 15 +
llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll | 23 ++--
10 files changed, 114 insertions(+), 4 deletions(-)
create mode 100644 clang/test/CodeGenOpenCL/amdgpu-unsafe-int-atomics.cl
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 9d56e97a3d4bb88..96416c4405115cd 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -253,6 +253,8 @@ class TargetInfo : public TransferrableTargetInfo,
unsigned AllowAMDGPUUnsafeFPAtomics : 1;
+ unsigned AllowAMDGPUUnsafeIntAtomics : 1;
+
unsigned ARMCDECoprocMask : 8;
unsigned MaxOpenCLWorkGroupSize;
@@ -995,6 +997,11 @@ class TargetInfo : public TransferrableTargetInfo,
/// allowed.
bool allowAMDGPUUnsafeFPAtomics() const { return AllowAMDGPUUnsafeFPAtomics;
}
+ /// Returns whether or not the AMDGPU unsafe integer atomics are allowed.
+ bool allowAMDGPUUnsafeIntAtomics() const {
+return AllowAMDGPUUnsafeIntAtomics;
+ }
+
/// For ARM targets returns a mask defining which coprocessors are configured
/// as Custom Datapath.
uint32_t getARMCDECoprocMask() const { return ARMCDECoprocMask; }
diff --git a/clang/include/clang/Basic/TargetOptions.h
b/clang/include/clang/Basic/TargetOptions.h
index ba3acd029587160..4feb6f2dcd86b83 100644
--- a/clang/include/clang/Basic/TargetOptions.h
+++ b/clang/include/clang/Basic/TargetOptions.h
@@ -78,6 +78,9 @@ class TargetOptions {
/// \brief If enabled, allow AMDGPU unsafe floating point atomics.
bool AllowAMDGPUUnsafeFPAtomics = false;
+ /// \brief If enabled, allow AMDGPU unsafe integer atomics.
+ bool AllowAMDGPUUnsafeIntAtomics = true;
+
/// \brief Enumeration value for AMDGPU code object version, which is the
/// code object version times 100.
enum CodeObjectVersionKind {
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index a89d6b6579f1176..265f5c23e7858ee 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4705,6 +4705,14 @@ defm unsafe_fp_atomics : BoolOption<"m",
"unsafe-fp-atomics",
"for certain memory destinations. (AMDGPU only)">,
NegFlag>, Group;
+defm unsafe_int_atomics : BoolOption<"m", "unsafe-int-atomics",
+ TargetOpts<"AllowAMDGPUUnsafeIntAtomics">, DefaultTrue,
+ PosFlag,
+ NegFlag>, Group;
+
def faltivec : Flag<["-"], "faltivec">, Group, Flags<[NoXarchOption]>;
def fno_altivec : Flag<["-"], "fno-altivec">, Group,
Flags<[NoXarchOption]>;
diff --git a/clang/lib/Basic/TargetInfo.cpp b/clang/lib/Basic/TargetInfo.cpp
index 6cd5d618a4acaa5..06997cc54642623 100644
--- a/clang/lib/Basic/TargetInfo.cpp
+++ b/clang/lib/Basic/TargetInfo.cpp
@@ -157,6 +157,7 @@ TargetInfo::TargetInfo(const llvm::Triple &T) : Triple(T) {
HasAArch64SVETypes = false;
HasRISCV
[clang] [AMDGPU] Add an option to disable unsafe uses of atomic xor (PR #69229)
https://github.com/pasaulais edited https://github.com/llvm/llvm-project/pull/69229 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [AMDGPU] Add an option to disable unsafe uses of atomic xor (PR #69229)
pasaulais wrote: Hi @jansvoboda11, @arsenm, I haven't yet got a commit merged to LLVM and can't request a review through the UI. Could I get a review on this patch? Thanks in advance and apologies if I've missed a step in the submission process. https://github.com/llvm/llvm-project/pull/69229 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AMDGPU] Add an option to disable unsafe uses of atomic xor (PR #69229)
pasaulais wrote: Thanks for the comments @arsenm @yxsamliu @b-sumner. By approaching a similar solution, do you mean MMRAs (https://github.com/llvm/llvm-project/pull/78569) ? If so, should I rebase/adapt my patch to the MMRA PR? Or will this PR be redundant and needs closing? @yxsamliu These concise names look good to me. https://github.com/llvm/llvm-project/pull/69229 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
