[clang] a845d8f - [X86][BF16] Add type mangling for Windows

[Phoebe Wang via cfe-commits]

Author: Phoebe Wang
Date: 2022-08-29T16:12:26+08:00
New Revision: a845d8fc57b6b09198bcb104f060925298034636

URL: 
https://github.com/llvm/llvm-project/commit/a845d8fc57b6b09198bcb104f060925298034636
DIFF: 
https://github.com/llvm/llvm-project/commit/a845d8fc57b6b09198bcb104f060925298034636.diff

LOG: [X86][BF16] Add type mangling for Windows

Reviewed By: FreddyYe

Differential Revision: https://reviews.llvm.org/D132742

Added: 


Modified: 
clang/lib/AST/MicrosoftMangle.cpp
clang/test/CodeGen/X86/bfloat-mangle.cpp

Removed: 




diff  --git a/clang/lib/AST/MicrosoftMangle.cpp 
b/clang/lib/AST/MicrosoftMangle.cpp
index 09075e60142a7..e58fedb6fa54c 100644
--- a/clang/lib/AST/MicrosoftMangle.cpp
+++ b/clang/lib/AST/MicrosoftMangle.cpp
@@ -2469,6 +2469,10 @@ void MicrosoftCXXNameMangler::mangleType(const 
BuiltinType *T, Qualifiers,
   Out << "$halff@";
 break;
 
+  case BuiltinType::BFloat16:
+mangleArtificialTagType(TTK_Struct, "__bf16", {"__clang"});
+break;
+
 #define SVE_TYPE(Name, Id, SingletonId) \
   case BuiltinType::Id:
 #include "clang/Basic/AArch64SVEACLETypes.def"
@@ -2501,7 +2505,6 @@ void MicrosoftCXXNameMangler::mangleType(const 
BuiltinType *T, Qualifiers,
   case BuiltinType::SatUShortFract:
   case BuiltinType::SatUFract:
   case BuiltinType::SatULongFract:
-  case BuiltinType::BFloat16:
   case BuiltinType::Ibm128:
   case BuiltinType::Float128: {
 DiagnosticsEngine &Diags = Context.getDiags();

diff  --git a/clang/test/CodeGen/X86/bfloat-mangle.cpp 
b/clang/test/CodeGen/X86/bfloat-mangle.cpp
index 2892a76d8d910..acc6c280f2e8e 100644
--- a/clang/test/CodeGen/X86/bfloat-mangle.cpp
+++ b/clang/test/CodeGen/X86/bfloat-mangle.cpp
@@ -1,5 +1,8 @@
-// RUN: %clang_cc1 -triple i386-unknown-unknown -target-feature +sse2 
-emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-feature +sse2 
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple i386-unknown-unknown -target-feature +sse2 
-emit-llvm -o - %s | FileCheck %s --check-prefixes=LINUX
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-feature +sse2 
-emit-llvm -o - %s | FileCheck %s --check-prefixes=LINUX
+// RUN: %clang_cc1 -triple i386-windows-msvc -target-feature +sse2 -emit-llvm 
-o - %s | FileCheck %s --check-prefixes=WINDOWS
+// RUN: %clang_cc1 -triple x86_64-windows-msvc -target-feature +sse2 
-emit-llvm -o - %s | FileCheck %s --check-prefixes=WINDOWS
 
-// CHECK: define {{.*}}void @_Z3foou6__bf16(bfloat noundef %b)
+// LINUX: define {{.*}}void @_Z3foou6__bf16(bfloat noundef %b)
+// WINDOWS: define {{.*}}void @"?foo@@YAXU__bf16@__clang@@@Z"(bfloat noundef 
%b)
 void foo(__bf16 b) {}



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[clang] [X86] Add a EVEX256 macro to match with GCC and MSVC (PR #71317)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang closed 
https://github.com/llvm/llvm-project/pull/71317
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[clang] [clang] Fixes compile error that double colon operator cannot resolve macro with parentheses. (PR #68618)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/68618
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[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)

[Phoebe Wang via cfe-commits]

phoebewang wrote:

Ping~

https://github.com/llvm/llvm-project/pull/71318
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[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang updated 
https://github.com/llvm/llvm-project/pull/71318

>From d9ee6309924e7f248695cbd488afe98273432e84 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Sun, 5 Nov 2023 21:15:53 +0800
Subject: [PATCH 1/3] [X86][AVX10] Permit AVX512 options/features used together
 with AVX10

This patch relaxes the driver logic to permit combinations between
AVX512 and AVX10 options and makes sure we have a unified behavior
between options and features combination.

Here are rules we are following when handle these combinations:
1. evex512 can only be used for avx512xxx options/features. It will be
   ignored if used without them;
2. avx512xxx and avx10.xxx are options in two worlds. Avoid to use them
   together in any case. It will enable a common super set when they are
   used together. E.g., "-mavx512f -mavx10.1-256" euqals "-mavx10.1-512".

Compiler emits warnings when user using combinations like
"-mavx512f -mavx10.1-256" in case they won't get unexpected result silently.
---
 .../clang/Basic/DiagnosticCommonKinds.td  |  2 +
 clang/lib/Basic/Targets/X86.cpp   | 57 ---
 clang/lib/Driver/ToolChains/Arch/X86.cpp  |  7 ---
 clang/lib/Headers/avx2intrin.h|  4 +-
 clang/lib/Headers/avx512bf16intrin.h  |  3 +-
 clang/lib/Headers/avx512bwintrin.h|  4 +-
 clang/lib/Headers/avx512dqintrin.h|  4 +-
 clang/lib/Headers/avx512fintrin.h |  8 ++-
 clang/lib/Headers/avx512fp16intrin.h  |  6 +-
 clang/lib/Headers/avx512ifmavlintrin.h| 10 +++-
 clang/lib/Headers/avx512pfintrin.h|  5 --
 clang/lib/Headers/avx512vbmivlintrin.h| 11 +++-
 clang/lib/Headers/avx512vlbf16intrin.h| 14 +++--
 clang/lib/Headers/avx512vlbitalgintrin.h  | 10 +++-
 clang/lib/Headers/avx512vlbwintrin.h  | 10 +++-
 clang/lib/Headers/avx512vlcdintrin.h  | 11 +++-
 clang/lib/Headers/avx512vldqintrin.h  | 10 +++-
 clang/lib/Headers/avx512vlfp16intrin.h|  4 +-
 clang/lib/Headers/avx512vlintrin.h| 10 +++-
 clang/lib/Headers/avx512vlvbmi2intrin.h   | 10 +++-
 clang/lib/Headers/avx512vlvnniintrin.h| 10 +++-
 .../lib/Headers/avx512vlvp2intersectintrin.h  | 10 ++--
 clang/lib/Headers/avx512vpopcntdqvlintrin.h   |  8 ++-
 clang/lib/Headers/avxintrin.h |  4 +-
 clang/lib/Headers/emmintrin.h |  4 +-
 clang/lib/Headers/gfniintrin.h| 14 +++--
 clang/lib/Headers/pmmintrin.h |  2 +-
 clang/lib/Headers/smmintrin.h |  2 +-
 clang/lib/Headers/tmmintrin.h |  4 +-
 clang/lib/Headers/xmmintrin.h |  4 +-
 clang/test/CodeGen/X86/avx512-error.c | 13 +
 clang/test/CodeGen/target-avx-abi-diag.c  | 28 -
 clang/test/Driver/x86-target-features.c   |  6 +-
 33 files changed, 214 insertions(+), 95 deletions(-)

diff --git a/clang/include/clang/Basic/DiagnosticCommonKinds.td 
b/clang/include/clang/Basic/DiagnosticCommonKinds.td
index 9f0ccd255a32148..8084a4ce0d1751b 100644
--- a/clang/include/clang/Basic/DiagnosticCommonKinds.td
+++ b/clang/include/clang/Basic/DiagnosticCommonKinds.td
@@ -346,6 +346,8 @@ def err_opt_not_valid_on_target : Error<
   "option '%0' cannot be specified on this target">;
 def err_invalid_feature_combination : Error<
   "invalid feature combination: %0">;
+def warn_invalid_feature_combination : Warning<
+  "invalid feature combination: %0">, 
InGroup>;
 def warn_target_unrecognized_env : Warning<
   "mismatch between architecture and environment in target triple '%0'; did 
you mean '%1'?">,
   InGroup;
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index eec3cd558435e2a..9cfda95f385d627 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -119,9 +119,13 @@ bool X86TargetInfo::initFeatureMap(
 setFeatureEnabled(Features, F, true);
 
   std::vector UpdatedFeaturesVec;
-  bool HasEVEX512 = true;
+  std::vector UpdatedAVX10FeaturesVec;
+  int HasEVEX512 = -1;
   bool HasAVX512F = false;
   bool HasAVX10 = false;
+  bool HasAVX10_512 = false;
+  std::string LastAVX10;
+  std::string LastAVX512;
   for (const auto &Feature : FeaturesVec) {
 // Expand general-regs-only to -x86, -mmx and -sse
 if (Feature == "+general-regs-only") {
@@ -131,35 +135,50 @@ bool X86TargetInfo::initFeatureMap(
   continue;
 }
 
-if (Feature.substr(0, 7) == "+avx10.") {
-  HasAVX10 = true;
-  HasAVX512F = true;
-  if (Feature.substr(Feature.size() - 3, 3) == "512") {
-HasEVEX512 = true;
-  } else if (Feature.substr(7, 2) == "1-") {
-HasEVEX512 = false;
+if (Feature.substr(1, 6) == "avx10.") {
+  if (Feature[0] == '+') {
+HasAVX10 = true;
+if (Feature.substr(Feature.size() - 3, 3) == "512")
+  HasAVX10_512 = true;
+LastAVX10 = Feature;
+  } else if (HasAVX10 && Feature == "-avx

[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)

[Phoebe Wang via cfe-commits]

@@ -119,9 +119,13 @@ bool X86TargetInfo::initFeatureMap(
 setFeatureEnabled(Features, F, true);
 
   std::vector UpdatedFeaturesVec;
-  bool HasEVEX512 = true;
+  std::vector UpdatedAVX10FeaturesVec;
+  int HasEVEX512 = -1;

phoebewang wrote:

I think it's better to use enum. It's a 3-status flag. std::optional isn't much 
useful here.

https://github.com/llvm/llvm-project/pull/71318
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[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)

[Phoebe Wang via cfe-commits]

@@ -15,8 +15,12 @@
 #define __AVX2INTRIN_H
 
 /* Define the default attributes for the functions in this file. */
-#define __DEFAULT_FN_ATTRS256 __attribute__((__always_inline__, __nodebug__, 
__target__("avx2"), __min_vector_width__(256)))
-#define __DEFAULT_FN_ATTRS128 __attribute__((__always_inline__, __nodebug__, 
__target__("avx2"), __min_vector_width__(128)))
+#define __DEFAULT_FN_ATTRS256  
\
+  __attribute__((__always_inline__, __nodebug__,   
\
+ __target__("avx2,no-evex512"), __min_vector_width__(256)))

phoebewang wrote:

We have defined parts AVX512 intrinsics with `no-evex512` and some of them will 
call into these AVX2 intrinsics.
Then we are facing a problem that we cannot call them in some cases because we 
didn't specify `no-evex512` for them.

https://github.com/llvm/llvm-project/pull/71318
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[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)

[Phoebe Wang via cfe-commits]

@@ -50,11 +50,11 @@ typedef __bf16 __m128bh __attribute__((__vector_size__(16), 
__aligned__(16)));
 
 /* Define the default attributes for the functions in this file. */
 #define __DEFAULT_FN_ATTRS 
\
-  __attribute__((__always_inline__, __nodebug__, __target__("sse2"),   
\
- __min_vector_width__(128)))
+  __attribute__((__always_inline__, __nodebug__,   
\
+ __target__("sse2,no-evex512"), __min_vector_width__(128)))
 #define __DEFAULT_FN_ATTRS_MMX 
\
-  __attribute__((__always_inline__, __nodebug__, __target__("mmx,sse2"),   
\
- __min_vector_width__(64)))
+  __attribute__((__always_inline__, __nodebug__,   
\

phoebewang wrote:

The same reason as above.

https://github.com/llvm/llvm-project/pull/71318
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[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)

[Phoebe Wang via cfe-commits]

@@ -131,35 +135,50 @@ bool X86TargetInfo::initFeatureMap(
   continue;
 }
 
-if (Feature.substr(0, 7) == "+avx10.") {
-  HasAVX10 = true;
-  HasAVX512F = true;
-  if (Feature.substr(Feature.size() - 3, 3) == "512") {
-HasEVEX512 = true;
-  } else if (Feature.substr(7, 2) == "1-") {
-HasEVEX512 = false;
+if (Feature.substr(1, 6) == "avx10.") {
+  if (Feature[0] == '+') {
+HasAVX10 = true;
+if (Feature.substr(Feature.size() - 3, 3) == "512")
+  HasAVX10_512 = true;
+LastAVX10 = Feature;
+  } else if (HasAVX10 && Feature == "-avx10.1-256") {
+HasAVX10 = false;
+HasAVX10_512 = false;
+  } else if (HasAVX10_512 && Feature == "-avx10.1-512") {
+HasAVX10_512 = false;
   }
+  // Postpone AVX10 features handling after AVX512 settled.
+  UpdatedAVX10FeaturesVec.push_back(Feature);
+  continue;
 } else if (!HasAVX512F && Feature.substr(0, 7) == "+avx512") {
   HasAVX512F = true;
+  LastAVX512 = Feature;
 } else if (HasAVX512F && Feature == "-avx512f") {
   HasAVX512F = false;
-} else if (HasAVX10 && Feature == "-avx10.1-256") {
-  HasAVX10 = false;
-  HasAVX512F = false;
-} else if (!HasEVEX512 && Feature == "+evex512") {
+} else if (HasEVEX512 != true && Feature == "+evex512") {

phoebewang wrote:

I think "std::optional" doesn't help here because we need to distinguish the 
uninitialized status and false too.

https://github.com/llvm/llvm-project/pull/71318
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[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)

[Phoebe Wang via cfe-commits]

phoebewang wrote:

> I'm a little bit confused, What's the expected behavior of `+avx10.1-512 
> -avx10.1-256` in codegen aspect? Should we generate only instructions in the 
> difference of sets? Or do we consider `avx10.1-256` as a base of 
> `avx10.1-512` and if it is disabled `avx10.1-512` can't be enabled?

`-avx10.1-256` works like `-avx512f`, that says, they are special as a 
fundamental feature, which will turn off all derivative features for AVX10 and 
AVX512 respectively.
OTOH, derivative features will only turn off the difference set, e.g., 
`+avx10.3-256 -avx10.2-256` equals to `+avx10.1-256`.

https://github.com/llvm/llvm-project/pull/71318
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[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang edited 
https://github.com/llvm/llvm-project/pull/71318
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[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang closed 
https://github.com/llvm/llvm-project/pull/71318
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[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)

[Phoebe Wang via cfe-commits]

phoebewang wrote:

Thanks @KanRobert @e-kud 

https://github.com/llvm/llvm-project/pull/71318
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[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)

[Phoebe Wang via cfe-commits]

phoebewang wrote:

@ronlieb Do you have a reproducer for this problem? I just checked the 
definition of both intrinsics have `no-evex512` already, so shouldn't have such 
problem.
You can use -mno-evex512 as workaround for the problem anyway.

https://github.com/llvm/llvm-project/pull/71318
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[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)

[Phoebe Wang via cfe-commits]

phoebewang wrote:

@ronlieb The reproducer can compile successfully in trunk: 
https://godbolt.org/z/hvKhGq9bq
Are you using a downstream compiler? You can check if the "emmintrin.h" has the 
same change as main trunk.
You can also check it through pre-compile the code:
```
$ clang++ -E fd_log_scalar.cpp -D_CPU | grep '_mm_setzero_pd.*{'
static __inline__ __m128d __attribute__((__always_inline__, __nodebug__, 
__target__("sse2,no-evex512"), __min_vector_width__(128))) _mm_setzero_pd(void) 
{
```
Make sure `no-evex512` is in the attribute too.

https://github.com/llvm/llvm-project/pull/71318
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[clang] [X86][AVX10] Fix a bug when using -march with no-evex512 attribute (PR #72126)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang created 
https://github.com/llvm/llvm-project/pull/72126

failed to clear EVEX512 feature for intended intrinsics.

Fixes #72106

>From a7642c3216cac9901f2e8b2290732ad526406b06 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Mon, 13 Nov 2023 23:21:35 +0800
Subject: [PATCH] [X86][AVX10] Fix a bug when using -march with no-evex512
 attribute

failed to clear EVEX512 feature for intended intrinsics.

Fixes #72106
---
 clang/lib/Basic/Targets/X86.cpp  |  2 +-
 clang/test/CodeGen/X86/pr72106.c | 10 ++
 2 files changed, 11 insertions(+), 1 deletion(-)
 create mode 100644 clang/test/CodeGen/X86/pr72106.c

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index eb127a8a11fffd5..acde3c1661748f0 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -122,7 +122,7 @@ bool X86TargetInfo::initFeatureMap(
   std::vector UpdatedAVX10FeaturesVec;
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
-  bool HasAVX512F = false;
+  bool HasAVX512F = Features["avx512f"];
   bool HasAVX10 = false;
   bool HasAVX10_512 = false;
   std::string LastAVX10;
diff --git a/clang/test/CodeGen/X86/pr72106.c b/clang/test/CodeGen/X86/pr72106.c
new file mode 100644
index 000..7ff4012f319b5b1
--- /dev/null
+++ b/clang/test/CodeGen/X86/pr72106.c
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -ffreestanding -target-cpu cannonlake -emit-llvm < %s | 
FileCheck %s
+
+#include 
+
+int main(int argc, char **argv) {
+  // CHECK-LABEL: @main
+  // CHECK: @llvm.masked.load.v4i64.p0
+  __m256i ptrs = _mm256_maskz_loadu_epi64(0, argv);
+  return 0;
+}

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[clang] [X86][AVX10] Fix a bug when using -march with no-evex512 attribute (PR #72126)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang edited 
https://github.com/llvm/llvm-project/pull/72126
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[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)

[Phoebe Wang via cfe-commits]

phoebewang wrote:

Thanks @ronlieb and @mstorsjo. Created #72126 for it.

https://github.com/llvm/llvm-project/pull/71318
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[clang] [X86][AVX10] Fix a bug when using -march with no-evex512 attribute (PR #72126)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang updated 
https://github.com/llvm/llvm-project/pull/72126

>From a7642c3216cac9901f2e8b2290732ad526406b06 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Mon, 13 Nov 2023 23:21:35 +0800
Subject: [PATCH 1/2] [X86][AVX10] Fix a bug when using -march with no-evex512
 attribute

failed to clear EVEX512 feature for intended intrinsics.

Fixes #72106
---
 clang/lib/Basic/Targets/X86.cpp  |  2 +-
 clang/test/CodeGen/X86/pr72106.c | 10 ++
 2 files changed, 11 insertions(+), 1 deletion(-)
 create mode 100644 clang/test/CodeGen/X86/pr72106.c

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index eb127a8a11fffd5..acde3c1661748f0 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -122,7 +122,7 @@ bool X86TargetInfo::initFeatureMap(
   std::vector UpdatedAVX10FeaturesVec;
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
-  bool HasAVX512F = false;
+  bool HasAVX512F = Features["avx512f"];
   bool HasAVX10 = false;
   bool HasAVX10_512 = false;
   std::string LastAVX10;
diff --git a/clang/test/CodeGen/X86/pr72106.c b/clang/test/CodeGen/X86/pr72106.c
new file mode 100644
index 000..7ff4012f319b5b1
--- /dev/null
+++ b/clang/test/CodeGen/X86/pr72106.c
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -ffreestanding -target-cpu cannonlake -emit-llvm < %s | 
FileCheck %s
+
+#include 
+
+int main(int argc, char **argv) {
+  // CHECK-LABEL: @main
+  // CHECK: @llvm.masked.load.v4i64.p0
+  __m256i ptrs = _mm256_maskz_loadu_epi64(0, argv);
+  return 0;
+}

>From 2124770f737a15c733d024b343583dc8568865f7 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Mon, 13 Nov 2023 23:46:08 +0800
Subject: [PATCH 2/2] Initialize AVX10.1 features too, though we don't have a
 target for test

---
 clang/lib/Basic/Targets/X86.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index acde3c1661748f0..60ca8ff8f681ca0 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -123,8 +123,8 @@ bool X86TargetInfo::initFeatureMap(
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
   bool HasAVX512F = Features["avx512f"];
-  bool HasAVX10 = false;
-  bool HasAVX10_512 = false;
+  bool HasAVX10 = Features["avx10.1-256"];
+  bool HasAVX10_512 = Features["avx10.1-512"];
   std::string LastAVX10;
   std::string LastAVX512;
   for (const auto &Feature : FeaturesVec) {

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[clang] [X86][AVX10] Fix a bug when using -march with no-evex512 attribute (PR #72126)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang updated 
https://github.com/llvm/llvm-project/pull/72126

>From a7642c3216cac9901f2e8b2290732ad526406b06 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Mon, 13 Nov 2023 23:21:35 +0800
Subject: [PATCH 1/3] [X86][AVX10] Fix a bug when using -march with no-evex512
 attribute

failed to clear EVEX512 feature for intended intrinsics.

Fixes #72106
---
 clang/lib/Basic/Targets/X86.cpp  |  2 +-
 clang/test/CodeGen/X86/pr72106.c | 10 ++
 2 files changed, 11 insertions(+), 1 deletion(-)
 create mode 100644 clang/test/CodeGen/X86/pr72106.c

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index eb127a8a11fffd5..acde3c1661748f0 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -122,7 +122,7 @@ bool X86TargetInfo::initFeatureMap(
   std::vector UpdatedAVX10FeaturesVec;
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
-  bool HasAVX512F = false;
+  bool HasAVX512F = Features["avx512f"];
   bool HasAVX10 = false;
   bool HasAVX10_512 = false;
   std::string LastAVX10;
diff --git a/clang/test/CodeGen/X86/pr72106.c b/clang/test/CodeGen/X86/pr72106.c
new file mode 100644
index 000..7ff4012f319b5b1
--- /dev/null
+++ b/clang/test/CodeGen/X86/pr72106.c
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -ffreestanding -target-cpu cannonlake -emit-llvm < %s | 
FileCheck %s
+
+#include 
+
+int main(int argc, char **argv) {
+  // CHECK-LABEL: @main
+  // CHECK: @llvm.masked.load.v4i64.p0
+  __m256i ptrs = _mm256_maskz_loadu_epi64(0, argv);
+  return 0;
+}

>From 2124770f737a15c733d024b343583dc8568865f7 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Mon, 13 Nov 2023 23:46:08 +0800
Subject: [PATCH 2/3] Initialize AVX10.1 features too, though we don't have a
 target for test

---
 clang/lib/Basic/Targets/X86.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index acde3c1661748f0..60ca8ff8f681ca0 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -123,8 +123,8 @@ bool X86TargetInfo::initFeatureMap(
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
   bool HasAVX512F = Features["avx512f"];
-  bool HasAVX10 = false;
-  bool HasAVX10_512 = false;
+  bool HasAVX10 = Features["avx10.1-256"];
+  bool HasAVX10_512 = Features["avx10.1-512"];
   std::string LastAVX10;
   std::string LastAVX512;
   for (const auto &Feature : FeaturesVec) {

>From d072431a86aa811cd7d053f35f8b4939a93216e3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Tue, 14 Nov 2023 00:07:00 +0800
Subject: [PATCH 3/3] Revert "Initialize AVX10.1 features too, though we don't
 have a target for test"

This reverts commit 2124770f737a15c733d024b343583dc8568865f7.

Do not initialize AVX10.1 features for now since it affects other lit tests.
---
 clang/lib/Basic/Targets/X86.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 60ca8ff8f681ca0..acde3c1661748f0 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -123,8 +123,8 @@ bool X86TargetInfo::initFeatureMap(
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
   bool HasAVX512F = Features["avx512f"];
-  bool HasAVX10 = Features["avx10.1-256"];
-  bool HasAVX10_512 = Features["avx10.1-512"];
+  bool HasAVX10 = false;
+  bool HasAVX10_512 = false;
   std::string LastAVX10;
   std::string LastAVX512;
   for (const auto &Feature : FeaturesVec) {

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[clang] [X86][AVX10] Fix a bug when using -march with no-evex512 attribute (PR #72126)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang updated 
https://github.com/llvm/llvm-project/pull/72126

>From a7642c3216cac9901f2e8b2290732ad526406b06 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Mon, 13 Nov 2023 23:21:35 +0800
Subject: [PATCH 1/4] [X86][AVX10] Fix a bug when using -march with no-evex512
 attribute

failed to clear EVEX512 feature for intended intrinsics.

Fixes #72106
---
 clang/lib/Basic/Targets/X86.cpp  |  2 +-
 clang/test/CodeGen/X86/pr72106.c | 10 ++
 2 files changed, 11 insertions(+), 1 deletion(-)
 create mode 100644 clang/test/CodeGen/X86/pr72106.c

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index eb127a8a11fffd5..acde3c1661748f0 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -122,7 +122,7 @@ bool X86TargetInfo::initFeatureMap(
   std::vector UpdatedAVX10FeaturesVec;
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
-  bool HasAVX512F = false;
+  bool HasAVX512F = Features["avx512f"];
   bool HasAVX10 = false;
   bool HasAVX10_512 = false;
   std::string LastAVX10;
diff --git a/clang/test/CodeGen/X86/pr72106.c b/clang/test/CodeGen/X86/pr72106.c
new file mode 100644
index 000..7ff4012f319b5b1
--- /dev/null
+++ b/clang/test/CodeGen/X86/pr72106.c
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -ffreestanding -target-cpu cannonlake -emit-llvm < %s | 
FileCheck %s
+
+#include 
+
+int main(int argc, char **argv) {
+  // CHECK-LABEL: @main
+  // CHECK: @llvm.masked.load.v4i64.p0
+  __m256i ptrs = _mm256_maskz_loadu_epi64(0, argv);
+  return 0;
+}

>From 2124770f737a15c733d024b343583dc8568865f7 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Mon, 13 Nov 2023 23:46:08 +0800
Subject: [PATCH 2/4] Initialize AVX10.1 features too, though we don't have a
 target for test

---
 clang/lib/Basic/Targets/X86.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index acde3c1661748f0..60ca8ff8f681ca0 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -123,8 +123,8 @@ bool X86TargetInfo::initFeatureMap(
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
   bool HasAVX512F = Features["avx512f"];
-  bool HasAVX10 = false;
-  bool HasAVX10_512 = false;
+  bool HasAVX10 = Features["avx10.1-256"];
+  bool HasAVX10_512 = Features["avx10.1-512"];
   std::string LastAVX10;
   std::string LastAVX512;
   for (const auto &Feature : FeaturesVec) {

>From d072431a86aa811cd7d053f35f8b4939a93216e3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Tue, 14 Nov 2023 00:07:00 +0800
Subject: [PATCH 3/4] Revert "Initialize AVX10.1 features too, though we don't
 have a target for test"

This reverts commit 2124770f737a15c733d024b343583dc8568865f7.

Do not initialize AVX10.1 features for now since it affects other lit tests.
---
 clang/lib/Basic/Targets/X86.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 60ca8ff8f681ca0..acde3c1661748f0 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -123,8 +123,8 @@ bool X86TargetInfo::initFeatureMap(
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
   bool HasAVX512F = Features["avx512f"];
-  bool HasAVX10 = Features["avx10.1-256"];
-  bool HasAVX10_512 = Features["avx10.1-512"];
+  bool HasAVX10 = false;
+  bool HasAVX10_512 = false;
   std::string LastAVX10;
   std::string LastAVX512;
   for (const auto &Feature : FeaturesVec) {

>From ec72ea87e792d85e1747ff48da29f72c688c2802 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Tue, 14 Nov 2023 09:29:45 +0800
Subject: [PATCH 4/4] Always append "-evex512" for "no-evex512" feature

---
 clang/lib/Basic/Targets/X86.cpp | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index acde3c1661748f0..7a5587bb70da610 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -122,7 +122,7 @@ bool X86TargetInfo::initFeatureMap(
   std::vector UpdatedAVX10FeaturesVec;
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
-  bool HasAVX512F = Features["avx512f"];
+  bool HasAVX512F = false;
   bool HasAVX10 = false;
   bool HasAVX10_512 = false;
   std::string LastAVX10;
@@ -180,6 +180,8 @@ bool X86TargetInfo::initFeatureMap(
   Diags.Report(diag::warn_invalid_feature_combination)
   << LastAVX10 + (HasEVEX512 == FE_TRUE ? " +evex512" : " -evex512");
 UpdatedFeaturesVec.push_back(HasAVX10_512 ? "+evex512" : "-evex512");
+  } else if (HasEVEX512 == FE_FALSE) {
+UpdatedFeaturesVec.push_back("-evex512");
   }
 
   if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))

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[clang] [X86][AVX10] Fix a bug when using -march with no-evex512 attribute (PR #72126)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang updated 
https://github.com/llvm/llvm-project/pull/72126

>From a7642c3216cac9901f2e8b2290732ad526406b06 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Mon, 13 Nov 2023 23:21:35 +0800
Subject: [PATCH 1/6] [X86][AVX10] Fix a bug when using -march with no-evex512
 attribute

failed to clear EVEX512 feature for intended intrinsics.

Fixes #72106
---
 clang/lib/Basic/Targets/X86.cpp  |  2 +-
 clang/test/CodeGen/X86/pr72106.c | 10 ++
 2 files changed, 11 insertions(+), 1 deletion(-)
 create mode 100644 clang/test/CodeGen/X86/pr72106.c

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index eb127a8a11fffd5..acde3c1661748f0 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -122,7 +122,7 @@ bool X86TargetInfo::initFeatureMap(
   std::vector UpdatedAVX10FeaturesVec;
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
-  bool HasAVX512F = false;
+  bool HasAVX512F = Features["avx512f"];
   bool HasAVX10 = false;
   bool HasAVX10_512 = false;
   std::string LastAVX10;
diff --git a/clang/test/CodeGen/X86/pr72106.c b/clang/test/CodeGen/X86/pr72106.c
new file mode 100644
index 000..7ff4012f319b5b1
--- /dev/null
+++ b/clang/test/CodeGen/X86/pr72106.c
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -ffreestanding -target-cpu cannonlake -emit-llvm < %s | 
FileCheck %s
+
+#include 
+
+int main(int argc, char **argv) {
+  // CHECK-LABEL: @main
+  // CHECK: @llvm.masked.load.v4i64.p0
+  __m256i ptrs = _mm256_maskz_loadu_epi64(0, argv);
+  return 0;
+}

>From 2124770f737a15c733d024b343583dc8568865f7 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Mon, 13 Nov 2023 23:46:08 +0800
Subject: [PATCH 2/6] Initialize AVX10.1 features too, though we don't have a
 target for test

---
 clang/lib/Basic/Targets/X86.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index acde3c1661748f0..60ca8ff8f681ca0 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -123,8 +123,8 @@ bool X86TargetInfo::initFeatureMap(
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
   bool HasAVX512F = Features["avx512f"];
-  bool HasAVX10 = false;
-  bool HasAVX10_512 = false;
+  bool HasAVX10 = Features["avx10.1-256"];
+  bool HasAVX10_512 = Features["avx10.1-512"];
   std::string LastAVX10;
   std::string LastAVX512;
   for (const auto &Feature : FeaturesVec) {

>From d072431a86aa811cd7d053f35f8b4939a93216e3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Tue, 14 Nov 2023 00:07:00 +0800
Subject: [PATCH 3/6] Revert "Initialize AVX10.1 features too, though we don't
 have a target for test"

This reverts commit 2124770f737a15c733d024b343583dc8568865f7.

Do not initialize AVX10.1 features for now since it affects other lit tests.
---
 clang/lib/Basic/Targets/X86.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 60ca8ff8f681ca0..acde3c1661748f0 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -123,8 +123,8 @@ bool X86TargetInfo::initFeatureMap(
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
   bool HasAVX512F = Features["avx512f"];
-  bool HasAVX10 = Features["avx10.1-256"];
-  bool HasAVX10_512 = Features["avx10.1-512"];
+  bool HasAVX10 = false;
+  bool HasAVX10_512 = false;
   std::string LastAVX10;
   std::string LastAVX512;
   for (const auto &Feature : FeaturesVec) {

>From ec72ea87e792d85e1747ff48da29f72c688c2802 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Tue, 14 Nov 2023 09:29:45 +0800
Subject: [PATCH 4/6] Always append "-evex512" for "no-evex512" feature

---
 clang/lib/Basic/Targets/X86.cpp | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index acde3c1661748f0..7a5587bb70da610 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -122,7 +122,7 @@ bool X86TargetInfo::initFeatureMap(
   std::vector UpdatedAVX10FeaturesVec;
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
-  bool HasAVX512F = Features["avx512f"];
+  bool HasAVX512F = false;
   bool HasAVX10 = false;
   bool HasAVX10_512 = false;
   std::string LastAVX10;
@@ -180,6 +180,8 @@ bool X86TargetInfo::initFeatureMap(
   Diags.Report(diag::warn_invalid_feature_combination)
   << LastAVX10 + (HasEVEX512 == FE_TRUE ? " +evex512" : " -evex512");
 UpdatedFeaturesVec.push_back(HasAVX10_512 ? "+evex512" : "-evex512");
+  } else if (HasEVEX512 == FE_FALSE) {
+UpdatedFeaturesVec.push_back("-evex512");
   }
 
   if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))

>From fff4b0e9f42813b2888b42bfed872920aa3af7b8 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Tue, 14 Nov 202

[clang] [X86][AVX10] Fix a bug when using -march with no-evex512 attribute (PR #72126)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang updated 
https://github.com/llvm/llvm-project/pull/72126

>From a7642c3216cac9901f2e8b2290732ad526406b06 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Mon, 13 Nov 2023 23:21:35 +0800
Subject: [PATCH 1/7] [X86][AVX10] Fix a bug when using -march with no-evex512
 attribute

failed to clear EVEX512 feature for intended intrinsics.

Fixes #72106
---
 clang/lib/Basic/Targets/X86.cpp  |  2 +-
 clang/test/CodeGen/X86/pr72106.c | 10 ++
 2 files changed, 11 insertions(+), 1 deletion(-)
 create mode 100644 clang/test/CodeGen/X86/pr72106.c

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index eb127a8a11fffd5..acde3c1661748f0 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -122,7 +122,7 @@ bool X86TargetInfo::initFeatureMap(
   std::vector UpdatedAVX10FeaturesVec;
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
-  bool HasAVX512F = false;
+  bool HasAVX512F = Features["avx512f"];
   bool HasAVX10 = false;
   bool HasAVX10_512 = false;
   std::string LastAVX10;
diff --git a/clang/test/CodeGen/X86/pr72106.c b/clang/test/CodeGen/X86/pr72106.c
new file mode 100644
index 000..7ff4012f319b5b1
--- /dev/null
+++ b/clang/test/CodeGen/X86/pr72106.c
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -ffreestanding -target-cpu cannonlake -emit-llvm < %s | 
FileCheck %s
+
+#include 
+
+int main(int argc, char **argv) {
+  // CHECK-LABEL: @main
+  // CHECK: @llvm.masked.load.v4i64.p0
+  __m256i ptrs = _mm256_maskz_loadu_epi64(0, argv);
+  return 0;
+}

>From 2124770f737a15c733d024b343583dc8568865f7 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Mon, 13 Nov 2023 23:46:08 +0800
Subject: [PATCH 2/7] Initialize AVX10.1 features too, though we don't have a
 target for test

---
 clang/lib/Basic/Targets/X86.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index acde3c1661748f0..60ca8ff8f681ca0 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -123,8 +123,8 @@ bool X86TargetInfo::initFeatureMap(
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
   bool HasAVX512F = Features["avx512f"];
-  bool HasAVX10 = false;
-  bool HasAVX10_512 = false;
+  bool HasAVX10 = Features["avx10.1-256"];
+  bool HasAVX10_512 = Features["avx10.1-512"];
   std::string LastAVX10;
   std::string LastAVX512;
   for (const auto &Feature : FeaturesVec) {

>From d072431a86aa811cd7d053f35f8b4939a93216e3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Tue, 14 Nov 2023 00:07:00 +0800
Subject: [PATCH 3/7] Revert "Initialize AVX10.1 features too, though we don't
 have a target for test"

This reverts commit 2124770f737a15c733d024b343583dc8568865f7.

Do not initialize AVX10.1 features for now since it affects other lit tests.
---
 clang/lib/Basic/Targets/X86.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 60ca8ff8f681ca0..acde3c1661748f0 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -123,8 +123,8 @@ bool X86TargetInfo::initFeatureMap(
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
   bool HasAVX512F = Features["avx512f"];
-  bool HasAVX10 = Features["avx10.1-256"];
-  bool HasAVX10_512 = Features["avx10.1-512"];
+  bool HasAVX10 = false;
+  bool HasAVX10_512 = false;
   std::string LastAVX10;
   std::string LastAVX512;
   for (const auto &Feature : FeaturesVec) {

>From ec72ea87e792d85e1747ff48da29f72c688c2802 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Tue, 14 Nov 2023 09:29:45 +0800
Subject: [PATCH 4/7] Always append "-evex512" for "no-evex512" feature

---
 clang/lib/Basic/Targets/X86.cpp | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index acde3c1661748f0..7a5587bb70da610 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -122,7 +122,7 @@ bool X86TargetInfo::initFeatureMap(
   std::vector UpdatedAVX10FeaturesVec;
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
-  bool HasAVX512F = Features["avx512f"];
+  bool HasAVX512F = false;
   bool HasAVX10 = false;
   bool HasAVX10_512 = false;
   std::string LastAVX10;
@@ -180,6 +180,8 @@ bool X86TargetInfo::initFeatureMap(
   Diags.Report(diag::warn_invalid_feature_combination)
   << LastAVX10 + (HasEVEX512 == FE_TRUE ? " +evex512" : " -evex512");
 UpdatedFeaturesVec.push_back(HasAVX10_512 ? "+evex512" : "-evex512");
+  } else if (HasEVEX512 == FE_FALSE) {
+UpdatedFeaturesVec.push_back("-evex512");
   }
 
   if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))

>From fff4b0e9f42813b2888b42bfed872920aa3af7b8 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Tue, 14 Nov 202

[clang] [X86][AVX10] Fix a bug when using -march with no-evex512 attribute (PR #72126)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang updated 
https://github.com/llvm/llvm-project/pull/72126

>From a7642c3216cac9901f2e8b2290732ad526406b06 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Mon, 13 Nov 2023 23:21:35 +0800
Subject: [PATCH 1/8] [X86][AVX10] Fix a bug when using -march with no-evex512
 attribute

failed to clear EVEX512 feature for intended intrinsics.

Fixes #72106
---
 clang/lib/Basic/Targets/X86.cpp  |  2 +-
 clang/test/CodeGen/X86/pr72106.c | 10 ++
 2 files changed, 11 insertions(+), 1 deletion(-)
 create mode 100644 clang/test/CodeGen/X86/pr72106.c

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index eb127a8a11fffd5..acde3c1661748f0 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -122,7 +122,7 @@ bool X86TargetInfo::initFeatureMap(
   std::vector UpdatedAVX10FeaturesVec;
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
-  bool HasAVX512F = false;
+  bool HasAVX512F = Features["avx512f"];
   bool HasAVX10 = false;
   bool HasAVX10_512 = false;
   std::string LastAVX10;
diff --git a/clang/test/CodeGen/X86/pr72106.c b/clang/test/CodeGen/X86/pr72106.c
new file mode 100644
index 000..7ff4012f319b5b1
--- /dev/null
+++ b/clang/test/CodeGen/X86/pr72106.c
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -ffreestanding -target-cpu cannonlake -emit-llvm < %s | 
FileCheck %s
+
+#include 
+
+int main(int argc, char **argv) {
+  // CHECK-LABEL: @main
+  // CHECK: @llvm.masked.load.v4i64.p0
+  __m256i ptrs = _mm256_maskz_loadu_epi64(0, argv);
+  return 0;
+}

>From 2124770f737a15c733d024b343583dc8568865f7 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Mon, 13 Nov 2023 23:46:08 +0800
Subject: [PATCH 2/8] Initialize AVX10.1 features too, though we don't have a
 target for test

---
 clang/lib/Basic/Targets/X86.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index acde3c1661748f0..60ca8ff8f681ca0 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -123,8 +123,8 @@ bool X86TargetInfo::initFeatureMap(
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
   bool HasAVX512F = Features["avx512f"];
-  bool HasAVX10 = false;
-  bool HasAVX10_512 = false;
+  bool HasAVX10 = Features["avx10.1-256"];
+  bool HasAVX10_512 = Features["avx10.1-512"];
   std::string LastAVX10;
   std::string LastAVX512;
   for (const auto &Feature : FeaturesVec) {

>From d072431a86aa811cd7d053f35f8b4939a93216e3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Tue, 14 Nov 2023 00:07:00 +0800
Subject: [PATCH 3/8] Revert "Initialize AVX10.1 features too, though we don't
 have a target for test"

This reverts commit 2124770f737a15c733d024b343583dc8568865f7.

Do not initialize AVX10.1 features for now since it affects other lit tests.
---
 clang/lib/Basic/Targets/X86.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 60ca8ff8f681ca0..acde3c1661748f0 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -123,8 +123,8 @@ bool X86TargetInfo::initFeatureMap(
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
   bool HasAVX512F = Features["avx512f"];
-  bool HasAVX10 = Features["avx10.1-256"];
-  bool HasAVX10_512 = Features["avx10.1-512"];
+  bool HasAVX10 = false;
+  bool HasAVX10_512 = false;
   std::string LastAVX10;
   std::string LastAVX512;
   for (const auto &Feature : FeaturesVec) {

>From ec72ea87e792d85e1747ff48da29f72c688c2802 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Tue, 14 Nov 2023 09:29:45 +0800
Subject: [PATCH 4/8] Always append "-evex512" for "no-evex512" feature

---
 clang/lib/Basic/Targets/X86.cpp | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index acde3c1661748f0..7a5587bb70da610 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -122,7 +122,7 @@ bool X86TargetInfo::initFeatureMap(
   std::vector UpdatedAVX10FeaturesVec;
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
-  bool HasAVX512F = Features["avx512f"];
+  bool HasAVX512F = false;
   bool HasAVX10 = false;
   bool HasAVX10_512 = false;
   std::string LastAVX10;
@@ -180,6 +180,8 @@ bool X86TargetInfo::initFeatureMap(
   Diags.Report(diag::warn_invalid_feature_combination)
   << LastAVX10 + (HasEVEX512 == FE_TRUE ? " +evex512" : " -evex512");
 UpdatedFeaturesVec.push_back(HasAVX10_512 ? "+evex512" : "-evex512");
+  } else if (HasEVEX512 == FE_FALSE) {
+UpdatedFeaturesVec.push_back("-evex512");
   }
 
   if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))

>From fff4b0e9f42813b2888b42bfed872920aa3af7b8 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Tue, 14 Nov 202

[clang] [X86][AVX10] Fix a bug when using -march with no-evex512 attribute (PR #72126)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang closed 
https://github.com/llvm/llvm-project/pull/72126
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[clang] 17dd0c7 - Revert "[X86][AVX10] Fix a bug when using -march with no-evex512 attribute (#72126)"

[Phoebe Wang via cfe-commits]

Author: Phoebe Wang
Date: 2023-11-14T15:34:38+08:00
New Revision: 17dd0c70c8c3183c62d184de2e91a859c36880e9

URL: 
https://github.com/llvm/llvm-project/commit/17dd0c70c8c3183c62d184de2e91a859c36880e9
DIFF: 
https://github.com/llvm/llvm-project/commit/17dd0c70c8c3183c62d184de2e91a859c36880e9.diff

LOG: Revert "[X86][AVX10] Fix a bug when using -march with no-evex512 attribute 
(#72126)"

This reverts commit 451c594bcbe528a44312cb698d78145c3ef18fa1.

Revert due to buildbot fails.

Added: 


Modified: 
clang/lib/Basic/Targets/X86.cpp

Removed: 
clang/test/CodeGen/X86/pr72106.c



diff  --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 85d0697ad63cae3..eb127a8a11fffd5 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -122,9 +122,9 @@ bool X86TargetInfo::initFeatureMap(
   std::vector UpdatedAVX10FeaturesVec;
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
-  bool HasAVX512F = Features.lookup("avx512f");
-  bool HasAVX10 = Features.lookup("avx10.1-256");
-  bool HasAVX10_512 = Features.lookup("avx10.1-512");
+  bool HasAVX512F = false;
+  bool HasAVX10 = false;
+  bool HasAVX10_512 = false;
   std::string LastAVX10;
   std::string LastAVX512;
   for (const auto &Feature : FeaturesVec) {

diff  --git a/clang/test/CodeGen/X86/pr72106.c 
b/clang/test/CodeGen/X86/pr72106.c
deleted file mode 100644
index 7ff4012f319b5b1..000
--- a/clang/test/CodeGen/X86/pr72106.c
+++ /dev/null
@@ -1,10 +0,0 @@
-// RUN: %clang_cc1 -ffreestanding -target-cpu cannonlake -emit-llvm < %s | 
FileCheck %s
-
-#include 
-
-int main(int argc, char **argv) {
-  // CHECK-LABEL: @main
-  // CHECK: @llvm.masked.load.v4i64.p0
-  __m256i ptrs = _mm256_maskz_loadu_epi64(0, argv);
-  return 0;
-}



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[clang] e96edde - Reland "[X86][AVX10] Fix a bug when using -march with no-evex512 attribute (#72126)"

[Phoebe Wang via cfe-commits]

Author: Phoebe Wang
Date: 2023-11-14T15:39:30+08:00
New Revision: e96eddec5e8ecc0fdab377571aabe85a2ee7617e

URL: 
https://github.com/llvm/llvm-project/commit/e96eddec5e8ecc0fdab377571aabe85a2ee7617e
DIFF: 
https://github.com/llvm/llvm-project/commit/e96eddec5e8ecc0fdab377571aabe85a2ee7617e.diff

LOG: Reland "[X86][AVX10] Fix a bug when using -march with no-evex512 attribute 
(#72126)"

Fixes #72106

Added: 
clang/test/CodeGen/X86/pr72106.c

Modified: 
clang/lib/Basic/Targets/X86.cpp

Removed: 




diff  --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index eb127a8a11fffd5..85d0697ad63cae3 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -122,9 +122,9 @@ bool X86TargetInfo::initFeatureMap(
   std::vector UpdatedAVX10FeaturesVec;
   enum { FE_NOSET = -1, FE_FALSE, FE_TRUE };
   int HasEVEX512 = FE_NOSET;
-  bool HasAVX512F = false;
-  bool HasAVX10 = false;
-  bool HasAVX10_512 = false;
+  bool HasAVX512F = Features.lookup("avx512f");
+  bool HasAVX10 = Features.lookup("avx10.1-256");
+  bool HasAVX10_512 = Features.lookup("avx10.1-512");
   std::string LastAVX10;
   std::string LastAVX512;
   for (const auto &Feature : FeaturesVec) {

diff  --git a/clang/test/CodeGen/X86/pr72106.c 
b/clang/test/CodeGen/X86/pr72106.c
new file mode 100644
index 000..937b74ec58d7b3e
--- /dev/null
+++ b/clang/test/CodeGen/X86/pr72106.c
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -triple x86_64 -ffreestanding -target-cpu cannonlake 
-emit-llvm < %s | FileCheck %s
+
+#include 
+
+int main(int argc, char **argv) {
+  // CHECK-LABEL: @main
+  // CHECK: @llvm.masked.load.v4i64.p0
+  __m256i ptrs = _mm256_maskz_loadu_epi64(0, argv);
+  return 0;
+}



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[clang] [clang] Fixes compile error that double colon operator cannot resolve macro with parentheses. (PR #68618)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang closed 
https://github.com/llvm/llvm-project/pull/68618
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[clang] 0ca80eb - [NFC] Remove duplicated message resulted from a bad merge I think

[Phoebe Wang via cfe-commits]

Author: Phoebe Wang
Date: 2023-12-05T15:58:55+08:00
New Revision: 0ca80eb5e814a6d061556888c9c9fbd04f054a80

URL: 
https://github.com/llvm/llvm-project/commit/0ca80eb5e814a6d061556888c9c9fbd04f054a80
DIFF: 
https://github.com/llvm/llvm-project/commit/0ca80eb5e814a6d061556888c9c9fbd04f054a80.diff

LOG: [NFC] Remove duplicated message resulted from a bad merge I think

Added: 


Modified: 
clang/docs/ReleaseNotes.rst

Removed: 




diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index c46ba0e5cbc21..828dd10e3d6db 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -652,7 +652,7 @@ Bug Fixes in This Version
   lookup and the current class instantiation has dependent bases.
   Fixes (`#13826 `_)
 - Fixes compile error that double colon operator cannot resolve macro with 
parentheses.
-  Fixes (`#64467 `_)- Clang 
now properly diagnoses use of stand-alone OpenMP directives after a
+  Fixes (`#64467 `_)
 - Clang's ``-Wchar-subscripts`` no longer warns on chars whose values are 
known non-negative constants.
   Fixes (`#18763 `_)
 



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[clang] 5237193 - [NFC] Fix typos in comments

[Phoebe Wang via cfe-commits]

Author: Phoebe Wang
Date: 2023-11-19T10:14:34+08:00
New Revision: 5237193b87721134541f228e28edfd544a9c8ac8

URL: 
https://github.com/llvm/llvm-project/commit/5237193b87721134541f228e28edfd544a9c8ac8
DIFF: 
https://github.com/llvm/llvm-project/commit/5237193b87721134541f228e28edfd544a9c8ac8.diff

LOG: [NFC] Fix typos in comments

Added: 


Modified: 
clang/lib/CodeGen/CodeGenFunction.cpp

Removed: 




diff  --git a/clang/lib/CodeGen/CodeGenFunction.cpp 
b/clang/lib/CodeGen/CodeGenFunction.cpp
index 64521ce7182eee6..2199d7b58fb96e6 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -495,12 +495,12 @@ void CodeGenFunction::FinishFunction(SourceLocation 
EndLoc) {
   if (CurFnInfo->getMaxVectorWidth() > LargestVectorWidth)
 LargestVectorWidth = CurFnInfo->getMaxVectorWidth();
 
-  // Add the required-vector-width attribute. This contains the max width from:
+  // Add the min-legal-vector-width attribute. This contains the max width 
from:
   // 1. min-vector-width attribute used in the source program.
   // 2. Any builtins used that have a vector width specified.
   // 3. Values passed in and out of inline assembly.
   // 4. Width of vector arguments and return types for this function.
-  // 5. Width of vector aguments and return types for functions called by this
+  // 5. Width of vector arguments and return types for functions called by this
   //function.
   if (getContext().getTargetInfo().getTriple().isX86())
 CurFn->addFnAttr("min-legal-vector-width",



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[clang] e5cc3da - [X86][AVX10] Add no-evex512 for MMX intrinsics, NFCI

[Phoebe Wang via cfe-commits]

Author: Phoebe Wang
Date: 2023-11-22T21:59:30+08:00
New Revision: e5cc3da6a9077548f613eee3aacc5e7b017c81f3

URL: 
https://github.com/llvm/llvm-project/commit/e5cc3da6a9077548f613eee3aacc5e7b017c81f3
DIFF: 
https://github.com/llvm/llvm-project/commit/e5cc3da6a9077548f613eee3aacc5e7b017c81f3.diff

LOG: [X86][AVX10] Add no-evex512 for MMX intrinsics, NFCI

Some MMX intrinsics like _mm_setzero_si64 will be called by XMM
intrinsics, so need to propagate no-evex512 there.

Checked locally with a lot of modified tests and no side effect with
this change. No extra test needed for the update.

Added: 


Modified: 
clang/lib/Headers/mmintrin.h

Removed: 




diff  --git a/clang/lib/Headers/mmintrin.h b/clang/lib/Headers/mmintrin.h
index 03bac92198ad897..08849f01071aea7 100644
--- a/clang/lib/Headers/mmintrin.h
+++ b/clang/lib/Headers/mmintrin.h
@@ -22,7 +22,9 @@ typedef short __v4hi __attribute__((__vector_size__(8)));
 typedef char __v8qi __attribute__((__vector_size__(8)));
 
 /* Define the default attributes for the functions in this file. */
-#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, 
__target__("mmx"), __min_vector_width__(64)))
+#define __DEFAULT_FN_ATTRS 
\
+  __attribute__((__always_inline__, __nodebug__, __target__("mmx,no-evex512"), 
\
+ __min_vector_width__(64)))
 
 /// Clears the MMX state by setting the state of the x87 stack registers
 ///to empty.
@@ -31,10 +33,10 @@ typedef char __v8qi __attribute__((__vector_size__(8)));
 ///
 /// This intrinsic corresponds to the  EMMS  instruction.
 ///
-static __inline__ void  __attribute__((__always_inline__, __nodebug__, 
__target__("mmx")))
-_mm_empty(void)
-{
-__builtin_ia32_emms();
+static __inline__ void __attribute__((__always_inline__, __nodebug__,
+  __target__("mmx,no-evex512")))
+_mm_empty(void) {
+  __builtin_ia32_emms();
 }
 
 /// Constructs a 64-bit integer vector, setting the lower 32 bits to the



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[clang] [X86] Add a EVEX256 macro to match with GCC and MSVC (PR #71317)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang created 
https://github.com/llvm/llvm-project/pull/71317

None

>From 50fb9c29b16c26e82bbc07ae8a092f572caa73a5 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Sun, 5 Nov 2023 21:50:44 +0800
Subject: [PATCH] [X86] Add a EVEX256 macro to match with GCC and MSVC

---
 clang/lib/Basic/Targets/X86.cpp   |  4 +++-
 .../Preprocessor/predefined-arch-macros.c | 24 +++
 clang/test/Preprocessor/x86_target_features.c | 11 +
 3 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index eec3cd558435e2a..6703e51df5eaa36 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -797,8 +797,10 @@ void X86TargetInfo::getTargetDefines(const LangOptions 
&Opts,
 Builder.defineMacro("__AVX512BITALG__");
   if (HasAVX512BW)
 Builder.defineMacro("__AVX512BW__");
-  if (HasAVX512VL)
+  if (HasAVX512VL) {
 Builder.defineMacro("__AVX512VL__");
+Builder.defineMacro("__EVEX256__");
+  }
   if (HasAVX512VBMI)
 Builder.defineMacro("__AVX512VBMI__");
   if (HasAVX512VBMI2)
diff --git a/clang/test/Preprocessor/predefined-arch-macros.c 
b/clang/test/Preprocessor/predefined-arch-macros.c
index f10793983b5e7c6..1ae6faea7767857 100644
--- a/clang/test/Preprocessor/predefined-arch-macros.c
+++ b/clang/test/Preprocessor/predefined-arch-macros.c
@@ -799,6 +799,7 @@
 // CHECK_KNL_M32: #define __AVX__ 1
 // CHECK_KNL_M32: #define __BMI2__ 1
 // CHECK_KNL_M32: #define __BMI__ 1
+// CHECK_KNL_M32-NOT: #define __EVEX256__ 1
 // CHECK_KNL_M32: #define __EVEX512__ 1
 // CHECK_KNL_M32: #define __F16C__ 1
 // CHECK_KNL_M32: #define __FMA__ 1
@@ -837,6 +838,7 @@
 // CHECK_KNL_M64: #define __AVX__ 1
 // CHECK_KNL_M64: #define __BMI2__ 1
 // CHECK_KNL_M64: #define __BMI__ 1
+// CHECK_KNL_M64-NOT: #define __EVEX256__ 1
 // CHECK_KNL_M64: #define __EVEX512__ 1
 // CHECK_KNL_M64: #define __F16C__ 1
 // CHECK_KNL_M64: #define __FMA__ 1
@@ -879,6 +881,7 @@
 // CHECK_KNM_M32: #define __AVX__ 1
 // CHECK_KNM_M32: #define __BMI2__ 1
 // CHECK_KNM_M32: #define __BMI__ 1
+// CHECK_KNM_M32-NOT: #define __EVEX256__ 1
 // CHECK_KNM_M32: #define __EVEX512__ 1
 // CHECK_KNM_M32: #define __F16C__ 1
 // CHECK_KNM_M32: #define __FMA__ 1
@@ -915,6 +918,7 @@
 // CHECK_KNM_M64: #define __AVX__ 1
 // CHECK_KNM_M64: #define __BMI2__ 1
 // CHECK_KNM_M64: #define __BMI__ 1
+// CHECK_KNM_M64-NOT: #define __EVEX256__ 1
 // CHECK_KNM_M64: #define __EVEX512__ 1
 // CHECK_KNM_M64: #define __F16C__ 1
 // CHECK_KNM_M64: #define __FMA__ 1
@@ -956,6 +960,7 @@
 // CHECK_SKX_M32: #define __BMI__ 1
 // CHECK_SKX_M32: #define __CLFLUSHOPT__ 1
 // CHECK_SKX_M32: #define __CLWB__ 1
+// CHECK_SKX_M32: #define __EVEX256__ 1
 // CHECK_SKX_M32: #define __EVEX512__ 1
 // CHECK_SKX_M32: #define __F16C__ 1
 // CHECK_SKX_M32: #define __FMA__ 1
@@ -1002,6 +1007,7 @@
 // CHECK_SKX_M64: #define __BMI__ 1
 // CHECK_SKX_M64: #define __CLFLUSHOPT__ 1
 // CHECK_SKX_M64: #define __CLWB__ 1
+// CHECK_SKX_M64: #define __EVEX256__ 1
 // CHECK_SKX_M64: #define __EVEX512__ 1
 // CHECK_SKX_M64: #define __F16C__ 1
 // CHECK_SKX_M64: #define __FMA__ 1
@@ -1052,6 +1058,7 @@
 // CHECK_CLX_M32: #define __BMI__ 1
 // CHECK_CLX_M32: #define __CLFLUSHOPT__ 1
 // CHECK_CLX_M32: #define __CLWB__ 1
+// CHECK_CLX_M32: #define __EVEX256__ 1
 // CHECK_CLX_M32: #define __EVEX512__ 1
 // CHECK_CLX_M32: #define __F16C__ 1
 // CHECK_CLX_M32: #define __FMA__ 1
@@ -1099,6 +1106,7 @@
 // CHECK_CLX_M64: #define __BMI__ 1
 // CHECK_CLX_M64: #define __CLFLUSHOPT__ 1
 // CHECK_CLX_M64: #define __CLWB__ 1
+// CHECK_CLX_M64: #define __EVEX256__ 1
 // CHECK_CLX_M64: #define __EVEX512__ 1
 // CHECK_CLX_M64: #define __F16C__ 1
 // CHECK_CLX_M64: #define __FMA__ 1
@@ -1150,6 +1158,7 @@
 // CHECK_CPX_M32: #define __BMI__ 1
 // CHECK_CPX_M32: #define __CLFLUSHOPT__ 1
 // CHECK_CPX_M32: #define __CLWB__ 1
+// CHECK_CPX_M32: #define __EVEX256__ 1
 // CHECK_CPX_M32: #define __EVEX512__ 1
 // CHECK_CPX_M32: #define __F16C__ 1
 // CHECK_CPX_M32: #define __FMA__ 1
@@ -1198,6 +1207,7 @@
 // CHECK_CPX_M64: #define __BMI__ 1
 // CHECK_CPX_M64: #define __CLFLUSHOPT__ 1
 // CHECK_CPX_M64: #define __CLWB__ 1
+// CHECK_CPX_M64: #define __EVEX256__ 1
 // CHECK_CPX_M64: #define __EVEX512__ 1
 // CHECK_CPX_M64: #define __F16C__ 1
 // CHECK_CPX_M64: #define __FMA__ 1
@@ -1249,6 +1259,7 @@
 // CHECK_CNL_M32: #define __BMI__ 1
 // CHECK_CNL_M32: #define __CLFLUSHOPT__ 1
 // CHECK_CNL_M32-NOT: #define __CLWB__ 1
+// CHECK_CNL_M32: #define __EVEX256__ 1
 // CHECK_CNL_M32: #define __EVEX512__ 1
 // CHECK_CNL_M32: #define __F16C__ 1
 // CHECK_CNL_M32: #define __FMA__ 1
@@ -1298,6 +1309,7 @@
 // CHECK_CNL_M64: #define __BMI__ 1
 // CHECK_CNL_M64: #define __CLFLUSHOPT__ 1
 // CHECK_CNL_M64-NOT: #define __CLWB__ 1
+// CHECK_CNL_M64: #define __EVEX256__ 1
 // CHECK_CNL_M64: #define __EVEX512__ 1
 // CHECK_CNL_M64: #define __F16C__ 1
 // CHECK_CNL_M64: #define __FMA__ 1
@@ -1355,6 +136

[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang created 
https://github.com/llvm/llvm-project/pull/71318

This patch relaxes the driver logic to permit combinations between AVX512 and 
AVX10 options and makes sure we have a unified behavior between options and 
features combination.

Here are rules we are following when handle these combinations:
1. evex512 can only be used for avx512xxx options/features. It will be ignored 
if used without them;
2. avx512xxx and avx10.xxx are options in two worlds. Avoid to use them 
together in any case. It will enable a common super set when they are used 
together. E.g., "-mavx512f -mavx10.1-256" euqals "-mavx10.1-512".

Compiler emits warnings when user using combinations like "-mavx512f 
-mavx10.1-256" in case they won't get unexpected result silently.

>From d9ee6309924e7f248695cbd488afe98273432e84 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Sun, 5 Nov 2023 21:15:53 +0800
Subject: [PATCH] [X86][AVX10] Permit AVX512 options/features used together
 with AVX10

This patch relaxes the driver logic to permit combinations between
AVX512 and AVX10 options and makes sure we have a unified behavior
between options and features combination.

Here are rules we are following when handle these combinations:
1. evex512 can only be used for avx512xxx options/features. It will be
   ignored if used without them;
2. avx512xxx and avx10.xxx are options in two worlds. Avoid to use them
   together in any case. It will enable a common super set when they are
   used together. E.g., "-mavx512f -mavx10.1-256" euqals "-mavx10.1-512".

Compiler emits warnings when user using combinations like
"-mavx512f -mavx10.1-256" in case they won't get unexpected result silently.
---
 .../clang/Basic/DiagnosticCommonKinds.td  |  2 +
 clang/lib/Basic/Targets/X86.cpp   | 57 ---
 clang/lib/Driver/ToolChains/Arch/X86.cpp  |  7 ---
 clang/lib/Headers/avx2intrin.h|  4 +-
 clang/lib/Headers/avx512bf16intrin.h  |  3 +-
 clang/lib/Headers/avx512bwintrin.h|  4 +-
 clang/lib/Headers/avx512dqintrin.h|  4 +-
 clang/lib/Headers/avx512fintrin.h |  8 ++-
 clang/lib/Headers/avx512fp16intrin.h  |  6 +-
 clang/lib/Headers/avx512ifmavlintrin.h| 10 +++-
 clang/lib/Headers/avx512pfintrin.h|  5 --
 clang/lib/Headers/avx512vbmivlintrin.h| 11 +++-
 clang/lib/Headers/avx512vlbf16intrin.h| 14 +++--
 clang/lib/Headers/avx512vlbitalgintrin.h  | 10 +++-
 clang/lib/Headers/avx512vlbwintrin.h  | 10 +++-
 clang/lib/Headers/avx512vlcdintrin.h  | 11 +++-
 clang/lib/Headers/avx512vldqintrin.h  | 10 +++-
 clang/lib/Headers/avx512vlfp16intrin.h|  4 +-
 clang/lib/Headers/avx512vlintrin.h| 10 +++-
 clang/lib/Headers/avx512vlvbmi2intrin.h   | 10 +++-
 clang/lib/Headers/avx512vlvnniintrin.h| 10 +++-
 .../lib/Headers/avx512vlvp2intersectintrin.h  | 10 ++--
 clang/lib/Headers/avx512vpopcntdqvlintrin.h   |  8 ++-
 clang/lib/Headers/avxintrin.h |  4 +-
 clang/lib/Headers/emmintrin.h |  4 +-
 clang/lib/Headers/gfniintrin.h| 14 +++--
 clang/lib/Headers/pmmintrin.h |  2 +-
 clang/lib/Headers/smmintrin.h |  2 +-
 clang/lib/Headers/tmmintrin.h |  4 +-
 clang/lib/Headers/xmmintrin.h |  4 +-
 clang/test/CodeGen/X86/avx512-error.c | 13 +
 clang/test/CodeGen/target-avx-abi-diag.c  | 28 -
 clang/test/Driver/x86-target-features.c   |  6 +-
 33 files changed, 214 insertions(+), 95 deletions(-)

diff --git a/clang/include/clang/Basic/DiagnosticCommonKinds.td 
b/clang/include/clang/Basic/DiagnosticCommonKinds.td
index 9f0ccd255a32148..8084a4ce0d1751b 100644
--- a/clang/include/clang/Basic/DiagnosticCommonKinds.td
+++ b/clang/include/clang/Basic/DiagnosticCommonKinds.td
@@ -346,6 +346,8 @@ def err_opt_not_valid_on_target : Error<
   "option '%0' cannot be specified on this target">;
 def err_invalid_feature_combination : Error<
   "invalid feature combination: %0">;
+def warn_invalid_feature_combination : Warning<
+  "invalid feature combination: %0">, 
InGroup>;
 def warn_target_unrecognized_env : Warning<
   "mismatch between architecture and environment in target triple '%0'; did 
you mean '%1'?">,
   InGroup;
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index eec3cd558435e2a..9cfda95f385d627 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -119,9 +119,13 @@ bool X86TargetInfo::initFeatureMap(
 setFeatureEnabled(Features, F, true);
 
   std::vector UpdatedFeaturesVec;
-  bool HasEVEX512 = true;
+  std::vector UpdatedAVX10FeaturesVec;
+  int HasEVEX512 = -1;
   bool HasAVX512F = false;
   bool HasAVX10 = false;
+  bool HasAVX10_512 = false;
+  std::string LastAVX10;
+  std::string LastAVX512;
   for (const auto &Feature : FeaturesVec) {
 // Expand general-reg

[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang updated 
https://github.com/llvm/llvm-project/pull/71318

>From d9ee6309924e7f248695cbd488afe98273432e84 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Sun, 5 Nov 2023 21:15:53 +0800
Subject: [PATCH 1/2] [X86][AVX10] Permit AVX512 options/features used together
 with AVX10

This patch relaxes the driver logic to permit combinations between
AVX512 and AVX10 options and makes sure we have a unified behavior
between options and features combination.

Here are rules we are following when handle these combinations:
1. evex512 can only be used for avx512xxx options/features. It will be
   ignored if used without them;
2. avx512xxx and avx10.xxx are options in two worlds. Avoid to use them
   together in any case. It will enable a common super set when they are
   used together. E.g., "-mavx512f -mavx10.1-256" euqals "-mavx10.1-512".

Compiler emits warnings when user using combinations like
"-mavx512f -mavx10.1-256" in case they won't get unexpected result silently.
---
 .../clang/Basic/DiagnosticCommonKinds.td  |  2 +
 clang/lib/Basic/Targets/X86.cpp   | 57 ---
 clang/lib/Driver/ToolChains/Arch/X86.cpp  |  7 ---
 clang/lib/Headers/avx2intrin.h|  4 +-
 clang/lib/Headers/avx512bf16intrin.h  |  3 +-
 clang/lib/Headers/avx512bwintrin.h|  4 +-
 clang/lib/Headers/avx512dqintrin.h|  4 +-
 clang/lib/Headers/avx512fintrin.h |  8 ++-
 clang/lib/Headers/avx512fp16intrin.h  |  6 +-
 clang/lib/Headers/avx512ifmavlintrin.h| 10 +++-
 clang/lib/Headers/avx512pfintrin.h|  5 --
 clang/lib/Headers/avx512vbmivlintrin.h| 11 +++-
 clang/lib/Headers/avx512vlbf16intrin.h| 14 +++--
 clang/lib/Headers/avx512vlbitalgintrin.h  | 10 +++-
 clang/lib/Headers/avx512vlbwintrin.h  | 10 +++-
 clang/lib/Headers/avx512vlcdintrin.h  | 11 +++-
 clang/lib/Headers/avx512vldqintrin.h  | 10 +++-
 clang/lib/Headers/avx512vlfp16intrin.h|  4 +-
 clang/lib/Headers/avx512vlintrin.h| 10 +++-
 clang/lib/Headers/avx512vlvbmi2intrin.h   | 10 +++-
 clang/lib/Headers/avx512vlvnniintrin.h| 10 +++-
 .../lib/Headers/avx512vlvp2intersectintrin.h  | 10 ++--
 clang/lib/Headers/avx512vpopcntdqvlintrin.h   |  8 ++-
 clang/lib/Headers/avxintrin.h |  4 +-
 clang/lib/Headers/emmintrin.h |  4 +-
 clang/lib/Headers/gfniintrin.h| 14 +++--
 clang/lib/Headers/pmmintrin.h |  2 +-
 clang/lib/Headers/smmintrin.h |  2 +-
 clang/lib/Headers/tmmintrin.h |  4 +-
 clang/lib/Headers/xmmintrin.h |  4 +-
 clang/test/CodeGen/X86/avx512-error.c | 13 +
 clang/test/CodeGen/target-avx-abi-diag.c  | 28 -
 clang/test/Driver/x86-target-features.c   |  6 +-
 33 files changed, 214 insertions(+), 95 deletions(-)

diff --git a/clang/include/clang/Basic/DiagnosticCommonKinds.td 
b/clang/include/clang/Basic/DiagnosticCommonKinds.td
index 9f0ccd255a32148..8084a4ce0d1751b 100644
--- a/clang/include/clang/Basic/DiagnosticCommonKinds.td
+++ b/clang/include/clang/Basic/DiagnosticCommonKinds.td
@@ -346,6 +346,8 @@ def err_opt_not_valid_on_target : Error<
   "option '%0' cannot be specified on this target">;
 def err_invalid_feature_combination : Error<
   "invalid feature combination: %0">;
+def warn_invalid_feature_combination : Warning<
+  "invalid feature combination: %0">, 
InGroup>;
 def warn_target_unrecognized_env : Warning<
   "mismatch between architecture and environment in target triple '%0'; did 
you mean '%1'?">,
   InGroup;
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index eec3cd558435e2a..9cfda95f385d627 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -119,9 +119,13 @@ bool X86TargetInfo::initFeatureMap(
 setFeatureEnabled(Features, F, true);
 
   std::vector UpdatedFeaturesVec;
-  bool HasEVEX512 = true;
+  std::vector UpdatedAVX10FeaturesVec;
+  int HasEVEX512 = -1;
   bool HasAVX512F = false;
   bool HasAVX10 = false;
+  bool HasAVX10_512 = false;
+  std::string LastAVX10;
+  std::string LastAVX512;
   for (const auto &Feature : FeaturesVec) {
 // Expand general-regs-only to -x86, -mmx and -sse
 if (Feature == "+general-regs-only") {
@@ -131,35 +135,50 @@ bool X86TargetInfo::initFeatureMap(
   continue;
 }
 
-if (Feature.substr(0, 7) == "+avx10.") {
-  HasAVX10 = true;
-  HasAVX512F = true;
-  if (Feature.substr(Feature.size() - 3, 3) == "512") {
-HasEVEX512 = true;
-  } else if (Feature.substr(7, 2) == "1-") {
-HasEVEX512 = false;
+if (Feature.substr(1, 6) == "avx10.") {
+  if (Feature[0] == '+') {
+HasAVX10 = true;
+if (Feature.substr(Feature.size() - 3, 3) == "512")
+  HasAVX10_512 = true;
+LastAVX10 = Feature;
+  } else if (HasAVX10 && Feature == "-avx

[clang] [X86] Add ABI handling for fp128 (PR #75156)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang created 
https://github.com/llvm/llvm-project/pull/75156

Fixes #74601

>From 9860e5454bdf3ee3a4283ab7102a8d70c3ebcbbc Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Tue, 12 Dec 2023 17:27:33 +0800
Subject: [PATCH] [X86] Add ABI handling for fp128

Fixes #74601
---
 clang/lib/CodeGen/Targets/X86.cpp  |  3 ++-
 clang/test/CodeGen/X86/fp128-abi.c | 35 ++
 2 files changed, 37 insertions(+), 1 deletion(-)
 create mode 100644 clang/test/CodeGen/X86/fp128-abi.c

diff --git a/clang/lib/CodeGen/Targets/X86.cpp 
b/clang/lib/CodeGen/Targets/X86.cpp
index 2af2403504388..c4bf38056a673 100644
--- a/clang/lib/CodeGen/Targets/X86.cpp
+++ b/clang/lib/CodeGen/Targets/X86.cpp
@@ -1795,7 +1795,8 @@ void X86_64ABIInfo::classify(QualType Ty, uint64_t 
OffsetBase, Class &Lo,
 } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
   Current = Integer;
 } else if (k == BuiltinType::Float || k == BuiltinType::Double ||
-   k == BuiltinType::Float16 || k == BuiltinType::BFloat16) {
+   k == BuiltinType::Float16 || k == BuiltinType::BFloat16 ||
+   k == BuiltinType::Float128) {
   Current = SSE;
 } else if (k == BuiltinType::LongDouble) {
   const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
diff --git a/clang/test/CodeGen/X86/fp128-abi.c 
b/clang/test/CodeGen/X86/fp128-abi.c
new file mode 100644
index 0..1c5d7cf1166ee
--- /dev/null
+++ b/clang/test/CodeGen/X86/fp128-abi.c
@@ -0,0 +1,35 @@
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm  -target-feature +sse2 < %s 
| FileCheck %s --check-prefixes=CHECK
+
+struct st1 {
+  __float128 a;
+};
+
+struct st1 h1(__float128 a) {
+  // CHECK: define{{.*}}fp128 @h1(fp128
+  struct st1 x;
+  x.a = a;
+  return x;
+}
+
+__float128 h2(struct st1 x) {
+  // CHECK: define{{.*}}fp128 @h2(fp128
+  return x.a;
+}
+
+struct st2 {
+  __float128 a;
+  int b;
+};
+
+struct st2 h3(__float128 a, int b) {
+  // CHECK: define{{.*}}void @h3(ptr {{.*}}sret(%struct.st2)
+  struct st2 x;
+  x.a = a;
+  x.b = b;
+  return x;
+}
+
+__float128 h4(struct st2 x) {
+  // CHECK: define{{.*}}fp128 @h4(ptr {{.*}}byval(%struct.st2)
+  return x.a;
+}

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[clang] [X86] Add ABI handling for __float128 (PR #75156)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang edited 
https://github.com/llvm/llvm-project/pull/75156
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[clang] [clang][sema] forbid '+f' on output register (PR #75208)

[Phoebe Wang via cfe-commits]

@@ -717,8 +717,15 @@ bool TargetInfo::validateOutputConstraint(ConstraintInfo 
&Info) const {
   if (*Name != '=' && *Name != '+')
 return false;
 
-  if (*Name == '+')
+  if (*Name == '+') {
 Info.setIsReadWrite();
+// To align with GCC asm: "=f" is not allowed, the
+// operand constraints must select a class with a single reg.
+auto Flag = Name + 1;
+if (Flag && *Flag == 'f') {
+  return false;
+}
+  }

phoebewang wrote:

Need to change from here: 
https://github.com/llvm/llvm-project/blob/main/clang/lib/Basic/Targets/X86.cpp#L1436

https://github.com/llvm/llvm-project/pull/75208
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[clang] [clang][sema] forbid vector_size attr when specify `-mgeneral-regs-only` on x86 (PR #75350)

[Phoebe Wang via cfe-commits]

@@ -8251,6 +8251,25 @@ static void HandleVectorSizeAttr(QualType &CurType, 
const ParsedAttr &Attr,
 return;
   }
 
+  // check -mgeneral-regs-only is specified
+  const TargetInfo &targetInfo = S.getASTContext().getTargetInfo();
+  llvm::Triple::ArchType arch = targetInfo.getTriple().getArch();
+  const auto HasFeature = [](const clang::TargetOptions &targetOpts,
+ const std::string &feature) {
+return std::find(targetOpts.Features.begin(), targetOpts.Features.end(),
+ feature) != targetOpts.Features.end();
+  };
+  if (CurType->isSpecificBuiltinType(BuiltinType::LongDouble)) {

phoebewang wrote:

`LongDouble` is not the only problem. GCC simply disallows any vector return 
type without SSE (`sse` feature) and gives error like `SSE register return with 
SSE disabled` and give warnings to vector argument type. 
https://godbolt.org/z/fhG76nqYo
LLVM behaves differently from GCC. It can generate code for any vector types 
expect `LongDouble` with `-mgeneral-regs-only`.
I think it would be incorrect but I'm not sure if we want to make it such 
strict.
`LongDouble` cannot be supported without `x87` feature. I'd expect something 
like https://reviews.llvm.org/D98895. It would be good if you can add vector 
type check there.
And you need to add test case for this scenario.

https://github.com/llvm/llvm-project/pull/75350
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[llvm] [clang] [IR] Fix GEP offset computations for vector GEPs (PR #75448)

[Phoebe Wang via cfe-commits]

phoebewang wrote:

Can this solve https://github.com/llvm/llvm-project/issues/68566 too?

https://github.com/llvm/llvm-project/pull/75448
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[clang] [X86] Add ABI handling for __float128 (PR #75156)

[Phoebe Wang via cfe-commits]

@@ -0,0 +1,35 @@
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm  -target-feature +sse2 < %s 
| FileCheck %s --check-prefixes=CHECK

phoebewang wrote:

This patch only changes for 64-bit ABI, non-SSE is not a valid case for 64-bit.
OTOH, -sse just generate identical output with +sse2, which doesn't match with 
GCC https://godbolt.org/z/4nxnhnovd
I think we may need to add a semacheck for it. Do you think we should add it 
with this patch or a follow up?

https://github.com/llvm/llvm-project/pull/75156
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[clang] [llvm] [X86][AVX10] Allow 64-bit mask register used without EVEX512 (PR #75571)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang updated 
https://github.com/llvm/llvm-project/pull/75571

>From 2e31cbd1a0b5b9c1689f664c6c261cabbc656f2a Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Fri, 15 Dec 2023 16:11:02 +0800
Subject: [PATCH 1/2] [X86][AVX10] Allow 64-bit mask register used without
 EVEX512

This is to reflect new document change that 64-bit mask is support by
AVX10 256-bit targets.

Latest documents can be found in:
https://cdrdv2.intel.com/v1/dl/getContent/784267
https://cdrdv2.intel.com/v1/dl/getContent/784343
---
 clang/include/clang/Basic/BuiltinsX86.def | 30 +++
 clang/lib/Headers/avx512bwintrin.h| 37 +-
 clang/test/CodeGen/X86/avx512-error.c | 46 +++
 llvm/lib/Target/X86/X86RegisterInfo.cpp   |  6 ---
 4 files changed, 47 insertions(+), 72 deletions(-)

diff --git a/clang/include/clang/Basic/BuiltinsX86.def 
b/clang/include/clang/Basic/BuiltinsX86.def
index e4802f8ab1c156..60b752ad48548f 100644
--- a/clang/include/clang/Basic/BuiltinsX86.def
+++ b/clang/include/clang/Basic/BuiltinsX86.def
@@ -979,7 +979,7 @@ TARGET_BUILTIN(__builtin_ia32_scatterpfqps, 
"vUcV8Oiv*IiIi", "nV:512:", "avx512p
 TARGET_BUILTIN(__builtin_ia32_knotqi, "UcUc", "nc", "avx512dq")
 TARGET_BUILTIN(__builtin_ia32_knothi, "UsUs", "nc", "avx512f")
 TARGET_BUILTIN(__builtin_ia32_knotsi, "UiUi", "nc", "avx512bw")
-TARGET_BUILTIN(__builtin_ia32_knotdi, "UOiUOi", "nc", "avx512bw,evex512")
+TARGET_BUILTIN(__builtin_ia32_knotdi, "UOiUOi", "nc", "avx512bw")
 
 TARGET_BUILTIN(__builtin_ia32_cmpb128_mask, "UsV16cV16cIiUs", "ncV:128:", 
"avx512vl,avx512bw")
 TARGET_BUILTIN(__builtin_ia32_cmpd128_mask, "UcV4iV4iIiUc", "ncV:128:", 
"avx512vl")
@@ -1349,7 +1349,7 @@ TARGET_BUILTIN(__builtin_ia32_vpmadd52luq128, 
"V2OiV2OiV2OiV2Oi", "ncV:128:", "a
 TARGET_BUILTIN(__builtin_ia32_vpmadd52luq256, "V4OiV4OiV4OiV4Oi", "ncV:256:", 
"avx512ifma,avx512vl|avxifma")
 TARGET_BUILTIN(__builtin_ia32_vcomisd, "iV2dV2dIiIi", "ncV:128:", "avx512f")
 TARGET_BUILTIN(__builtin_ia32_vcomiss, "iV4fV4fIiIi", "ncV:128:", "avx512f")
-TARGET_BUILTIN(__builtin_ia32_kunpckdi, "UOiUOiUOi", "nc", "avx512bw,evex512")
+TARGET_BUILTIN(__builtin_ia32_kunpckdi, "UOiUOiUOi", "nc", "avx512bw")
 TARGET_BUILTIN(__builtin_ia32_kunpcksi, "UiUiUi", "nc", "avx512bw")
 TARGET_BUILTIN(__builtin_ia32_loaddquhi512_mask, "V32sV32sC*V32sUi", 
"nV:512:", "avx512bw,evex512")
 TARGET_BUILTIN(__builtin_ia32_loaddquqi512_mask, "V64cV64cC*V64cUOi", 
"nV:512:", "avx512bw,evex512")
@@ -1665,56 +1665,56 @@ TARGET_BUILTIN(__builtin_ia32_fpcla_mask, 
"UcV4fIiUc", "ncV:128:", "avx512dq
 TARGET_BUILTIN(__builtin_ia32_kaddqi, "UcUcUc", "nc", "avx512dq")
 TARGET_BUILTIN(__builtin_ia32_kaddhi, "UsUsUs", "nc", "avx512dq")
 TARGET_BUILTIN(__builtin_ia32_kaddsi, "UiUiUi", "nc", "avx512bw")
-TARGET_BUILTIN(__builtin_ia32_kadddi, "UOiUOiUOi", "nc", "avx512bw,evex512")
+TARGET_BUILTIN(__builtin_ia32_kadddi, "UOiUOiUOi", "nc", "avx512bw")
 TARGET_BUILTIN(__builtin_ia32_kandqi, "UcUcUc", "nc", "avx512dq")
 TARGET_BUILTIN(__builtin_ia32_kandhi, "UsUsUs", "nc", "avx512f")
 TARGET_BUILTIN(__builtin_ia32_kandsi, "UiUiUi", "nc", "avx512bw")
-TARGET_BUILTIN(__builtin_ia32_kanddi, "UOiUOiUOi", "nc", "avx512bw,evex512")
+TARGET_BUILTIN(__builtin_ia32_kanddi, "UOiUOiUOi", "nc", "avx512bw")
 TARGET_BUILTIN(__builtin_ia32_kandnqi, "UcUcUc", "nc", "avx512dq")
 TARGET_BUILTIN(__builtin_ia32_kandnhi, "UsUsUs", "nc", "avx512f")
 TARGET_BUILTIN(__builtin_ia32_kandnsi, "UiUiUi", "nc", "avx512bw")
-TARGET_BUILTIN(__builtin_ia32_kandndi, "UOiUOiUOi", "nc", "avx512bw,evex512")
+TARGET_BUILTIN(__builtin_ia32_kandndi, "UOiUOiUOi", "nc", "avx512bw")
 TARGET_BUILTIN(__builtin_ia32_korqi, "UcUcUc", "nc", "avx512dq")
 TARGET_BUILTIN(__builtin_ia32_korhi, "UsUsUs", "nc", "avx512f")
 TARGET_BUILTIN(__builtin_ia32_korsi, "UiUiUi", "nc", "avx512bw")
-TARGET_BUILTIN(__builtin_ia32_kordi, "UOiUOiUOi", "nc", "avx512bw,evex512")
+TARGET_BUILTIN(__builtin_ia32_kordi, "UOiUOiUOi", "nc", "avx512bw")
 TARGET_BUILTIN(__builtin_ia32_kortestcqi, "iUcUc", "nc", "avx512dq")
 TARGET_BUILTIN(__builtin_ia32_kortestzqi, "iUcUc", "nc", "avx512dq")
 TARGET_BUILTIN(__builtin_ia32_kortestchi, "iUsUs", "nc", "avx512f")
 TARGET_BUILTIN(__builtin_ia32_kortestzhi, "iUsUs", "nc", "avx512f")
 TARGET_BUILTIN(__builtin_ia32_kortestcsi, "iUiUi", "nc", "avx512bw")
 TARGET_BUILTIN(__builtin_ia32_kortestzsi, "iUiUi", "nc", "avx512bw")
-TARGET_BUILTIN(__builtin_ia32_kortestcdi, "iUOiUOi", "nc", "avx512bw,evex512")
-TARGET_BUILTIN(__builtin_ia32_kortestzdi, "iUOiUOi", "nc", "avx512bw,evex512")
+TARGET_BUILTIN(__builtin_ia32_kortestcdi, "iUOiUOi", "nc", "avx512bw")
+TARGET_BUILTIN(__builtin_ia32_kortestzdi, "iUOiUOi", "nc", "avx512bw")
 TARGET_BUILTIN(__builtin_ia32_ktestcqi, "iUcUc", "nc", "avx512dq")
 TARGET_BUILTIN(__builtin_ia32_ktestzqi, "iUcUc", "nc", "avx512dq")
 TARGET_BUILTIN(__builtin_ia32_ktestchi, "iUsUs", "nc", "avx512dq")
 TARGET_BUILTIN(__builtin_ia32_ktestzhi, "iUsUs", "nc", "avx512dq")
 TARGE

[clang] [X86] Emit Warnings for frontend options to enable knl/knm. (PR #75580)

[Phoebe Wang via cfe-commits]

phoebewang wrote:

One more reason I can think of is with KNL/KNM removal, we can simplify 
supporting widen 128/256-bit vector to 512-bit without AVX512VL feature since 
all reset targets support AVX512VL. The test cases can be simplified too.

https://github.com/llvm/llvm-project/pull/75580
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[clang] [llvm] [X86][AVX10] Allow 64-bit mask register used without EVEX512 (PR #75571)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang closed 
https://github.com/llvm/llvm-project/pull/75571
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[clang] [X86] Emit Warnings for frontend options to enable knl/knm. (PR #75580)

[Phoebe Wang via cfe-commits]

phoebewang wrote:

> Can you give me a better idea of the stages you intend to follow with this. 
> The patch title suggests removing all KNL/KNM handling but the patch itself 
> looks to be just about the KNL/KNM specific features.
> 
> Removing the (incomplete) KNL/KNM specific features (ER/PF/etc) I don't think 
> will be any major cause for concern, ideally we'd keep support at the 
> assembly level only (which has been suggested for MMX as well at some point). 
> But even that might not be necessary.


It's a good idea to preserve the assembly level support. I think GCC's proposal 
just wants to deprecate GCC support rather than remove support from binutils 
too.

> But what do you expect to happen if a KNL workstation attempts to use clang 
> 19 with `-march=native`? Do we still enable it as a AVX512F+AVX512CD target 
> or are you suggesting we degrade it to match x86-64-v3 arch spec?

There're discussions in GCC mailing loop about `-mtune/arch=knl`. IIUC, the 
final decision is to remove the march support too. For `-march=native`, I'm not 
sure whether we detect it by CPU model or feature list. For the former, we 
didn't remove the KNL/KNM model, we can emit error for it; for the latter, we 
can return an approaching target has the same (remaining) features.

> How can the test cases then can be simplified? Are you suggesting that we 
> merge more of the AVX512 attributes in X86.td (e.g. AVX512VL always enables 
> BW/DQ / VBMI2 enables VBMI etc?).

I think we can't make AVX512VL being implied by default, but can gradually 
relax a lot of `Subtarget.hasVLX()` in CPP and TD files. We don't need to test 
the combinations that have AVX512 features but no AVX512VL and remove them from 
existing tests gradually.

>From the developmental trend of HW design, I don't think we will fall back to 
>support 512-bit only features in the future. So from my point of view, 
>simplifying backend design and testing would be the major benefit we can 
>achieve.

https://github.com/llvm/llvm-project/pull/75580
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[clang] [clang] Add `intrin0.h` header to mimic `intrin0.h` used by MSVC STL for clang-cl (PR #75711)

[Phoebe Wang via cfe-commits]

@@ -0,0 +1,160 @@
+/*=== adxintrin.h - ADX intrinsics -===

phoebewang wrote:

adx -> adc

https://github.com/llvm/llvm-project/pull/75711
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[clang] [clang] Separate Intel ADC instrinsics from ADX intrinsics (PR #75992)

[Phoebe Wang via cfe-commits]

@@ -0,0 +1,160 @@
+/*=== adxintrin.h - ADX intrinsics -===

phoebewang wrote:

adx -> adc

https://github.com/llvm/llvm-project/pull/75992
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[clang] [clang] Separate Intel ADC instrinsics from ADX intrinsics (PR #75992)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/75992
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[clang] [clang] Separate Intel ADC instrinsics from ADX intrinsics (PR #75992)

[Phoebe Wang via cfe-commits]

@@ -92,136 +92,11 @@ __INLINE unsigned char
 }
 #endif
 
-/* Intrinsics that are also available if __ADX__ is undefined. */
-
-/// Adds unsigned 32-bit integers \a __x and \a __y, plus 0 or 1 as indicated
-///by the carry flag \a __cf. Stores the unsigned 32-bit sum in the memory
-///at \a __p, and returns the 8-bit carry-out (carry flag).
-///
-/// \code{.operation}
-/// temp := (__cf == 0) ? 0 : 1
-/// Store32(__p, __x + __y + temp)
-/// result := CF
-/// \endcode
-///
-/// \headerfile 
-///
-/// This intrinsic corresponds to the \c ADC instruction.
-///
-/// \param __cf
-///The 8-bit unsigned carry flag; any non-zero value indicates carry.
-/// \param __x
-///A 32-bit unsigned addend.
-/// \param __y
-///A 32-bit unsigned addend.
-/// \param __p
-///Pointer to memory for storing the sum.
-/// \returns The 8-bit unsigned carry-out value.
-__INLINE unsigned char __DEFAULT_FN_ATTRS _addcarry_u32(unsigned char __cf,

phoebewang wrote:

`__DEFAULT_FN_ATTRS` is not used in this file, remove it or replace it with 
`__attribute__((__always_inline__, __nodebug__, __target__("adx")))` for the 
rest functions.

https://github.com/llvm/llvm-project/pull/75992
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[clang] [clang] Separate Intel ADC instrinsics from ADX intrinsics (PR #75992)

[Phoebe Wang via cfe-commits]

@@ -580,8 +580,7 @@ _storebe_i64(void * __P, long long __D) {
 #include 
 #endif
 
-/* Some intrinsics inside adxintrin.h are available only on processors with 
ADX,
- * whereas others are also available at all times. */

phoebewang wrote:

Sorry, just noticed this. Since we removed the comments, should we use the same 
format for `adxintrin.h` and add comment for `adcintrin.h`, e.g., 

```
/* Intrinsics inside adcintrin.h are available at all times. */
#include 

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||  \
defined(__ADX__)
#include 
#endif
```

https://github.com/llvm/llvm-project/pull/75992
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[clang] [clang] Separate Intel ADC instrinsics from ADX intrinsics (PR #75992)

[Phoebe Wang via cfe-commits]

@@ -580,8 +580,7 @@ _storebe_i64(void * __P, long long __D) {
 #include 
 #endif
 
-/* Some intrinsics inside adxintrin.h are available only on processors with 
ADX,
- * whereas others are also available at all times. */

phoebewang wrote:

I think comment is good. Without it, people may wonder anything special here.
For ADX, I guess the reason is it mixed with adc intrinsics previously, so 
cannot be guarded. And we should be free to do it now.

https://github.com/llvm/llvm-project/pull/75992
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[clang] [clang] Separate Intel ADC instrinsics from ADX intrinsics (PR #75992)

[Phoebe Wang via cfe-commits]

phoebewang wrote:

Thanks @MaxEW707 ! I don't have other comments now. Do you need help to merge 
it for you?

https://github.com/llvm/llvm-project/pull/75992
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[libc] [llvm] [libcxx] [compiler-rt] [flang] [lld] [clang] Fix ISel crash when lowering BUILD_VECTOR (PR #73186)

[Phoebe Wang via cfe-commits]

@@ -7254,6 +7255,10 @@ static SDValue 
lowerBuildVectorAsBroadcast(BuildVectorSDNode *BVOp,
 EVT CVT = Ld.getValueType();
 assert(!CVT.isVector() && "Must not broadcast a vector type");
 
+// 512 bit vpbroadcastw is only available with AVX512BW
+if (ScalarSize == 16 && IsGT256 && !Subtarget.hasBWI())
+  return SDValue();

phoebewang wrote:

The problem only exists for `v32f16` which is not handled by 
`PreprocessISelDAG`. Maybe we need add `v32f16` support there.

https://github.com/llvm/llvm-project/pull/73186
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[clang] 5237193 - [NFC] Fix typos in comments

[Phoebe Wang via cfe-commits]

Author: Phoebe Wang
Date: 2023-11-19T10:14:34+08:00
New Revision: 5237193b87721134541f228e28edfd544a9c8ac8

URL: 
https://github.com/llvm/llvm-project/commit/5237193b87721134541f228e28edfd544a9c8ac8
DIFF: 
https://github.com/llvm/llvm-project/commit/5237193b87721134541f228e28edfd544a9c8ac8.diff

LOG: [NFC] Fix typos in comments

Added: 


Modified: 
clang/lib/CodeGen/CodeGenFunction.cpp

Removed: 




diff  --git a/clang/lib/CodeGen/CodeGenFunction.cpp 
b/clang/lib/CodeGen/CodeGenFunction.cpp
index 64521ce7182eee6..2199d7b58fb96e6 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -495,12 +495,12 @@ void CodeGenFunction::FinishFunction(SourceLocation 
EndLoc) {
   if (CurFnInfo->getMaxVectorWidth() > LargestVectorWidth)
 LargestVectorWidth = CurFnInfo->getMaxVectorWidth();
 
-  // Add the required-vector-width attribute. This contains the max width from:
+  // Add the min-legal-vector-width attribute. This contains the max width 
from:
   // 1. min-vector-width attribute used in the source program.
   // 2. Any builtins used that have a vector width specified.
   // 3. Values passed in and out of inline assembly.
   // 4. Width of vector arguments and return types for this function.
-  // 5. Width of vector aguments and return types for functions called by this
+  // 5. Width of vector arguments and return types for functions called by this
   //function.
   if (getContext().getTargetInfo().getTriple().isX86())
 CurFn->addFnAttr("min-legal-vector-width",



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[llvm] [clang] [X86] Support CFE flags for APX features (PR #74199)

[Phoebe Wang via cfe-commits]

@@ -5999,6 +5999,12 @@ def mno_gather : Flag<["-"], "mno-gather">, 
Group,
  HelpText<"Disable generation of gather instructions in 
auto-vectorization(x86 only)">;
 def mno_scatter : Flag<["-"], "mno-scatter">, Group,
   HelpText<"Disable generation of scatter instructions in 
auto-vectorization(x86 only)">;
+def mapx_features_EQ : CommaJoined<["-"], "mapx-features=">, 
Group,
+HelpText<"Enable features of APX">, 
Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">;
+def mno_apx_features_EQ : CommaJoined<["-"], "mno-apx-features=">, 
Group,
+HelpText<"Disable features of APX">, 
Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">;
+def mapxf : Flag<["-"], "mapxf">, Alias, 
AliasArgs<["egpr","push2pop2","ppx"]>;
+def mno_apxf : Flag<["-"], "mno-apxf">, Alias, 
AliasArgs<["egpr","push2pop2","ppx"]>;

phoebewang wrote:

The commit message mentions `alias of -m[no-]apx-features=< all APX features 
covered by CPUID APX_F>`, why only 3 here?

https://github.com/llvm/llvm-project/pull/74199
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[llvm] [clang] [X86] Support CFE flags for APX features (PR #74199)

[Phoebe Wang via cfe-commits]

@@ -927,6 +939,16 @@ void X86TargetInfo::getTargetDefines(const LangOptions 
&Opts,
 Builder.defineMacro("__USERMSR__");
   if (HasCRC32)
 Builder.defineMacro("__CRC32__");
+  if (HasEGPR)
+Builder.defineMacro("__EGPR__");
+  if (HasPush2Pop2)
+Builder.defineMacro("__PUSH2POP2__");
+  if (HasNDD)

phoebewang wrote:

Missing PPX?

https://github.com/llvm/llvm-project/pull/74199
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[llvm] [clang] [X86] Support CFE flags for APX features (PR #74199)

[Phoebe Wang via cfe-commits]

@@ -422,3 +422,28 @@
 
 // RUN: touch %t.o
 // RUN: %clang -fdriver-only -Werror --target=x86_64-pc-linux-gnu 
-mharden-sls=all %t.o -o /dev/null 2>&1 | count 0
+// RUN: %clang -target x86_64-unknown-linux-gnu -mapxf %s -### -o %t.o 2>&1 | 
FileCheck -check-prefix=APXF %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mno-apxf %s -### -o %t.o 2>&1 
| FileCheck -check-prefix=NO-APXF %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mno-apxf -mapxf %s -### -o 
%t.o 2>&1 | FileCheck -check-prefix=APXF %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mapxf -mno-apxf %s -### -o 
%t.o 2>&1 | FileCheck -check-prefix=NO-APXF %s
+//
+// APXF: "-target-feature" "+egpr" "-target-feature" "+push2pop2" 
"-target-feature" "+ppx"
+// NO-APXF: "-target-feature" "-egpr" "-target-feature" "-push2pop2" 
"-target-feature" "-ppx"
+
+// RUN: %clang -target x86_64-unknown-linux-gnu -mapx-features=egpr,ndd %s 
-### -o %t.o 2>&1 | FileCheck -check-prefix=EGPR-NDD %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mapx-features=egpr 
-mapx-features=ndd %s -### -o %t.o 2>&1 | FileCheck -check-prefix=EGPR-NDD %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mno-apx-features=egpr 
-mno-apx-features=ndd %s -### -o %t.o 2>&1 | FileCheck 
-check-prefix=NO-EGPR-NO-NDD %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mno-apx-features=egpr 
-mapx-features=egpr,ndd %s -### -o %t.o 2>&1 | FileCheck -check-prefix=EGPR-NDD 
%s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mno-apx-features=egpr,ndd 
-mapx-features=egpr %s -### -o %t.o 2>&1 | FileCheck -check-prefix=EGPR-NO-NDD 
%s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mapx-features=egpr,ndd 
-mno-apx-features=egpr %s -### -o %t.o 2>&1 | FileCheck 
-check-prefix=NO-EGPR-NDD %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mapx-features=egpr 
-mno-apx-features=egpr,ndd %s -### -o %t.o 2>&1 | FileCheck 
-check-prefix=NO-EGPR-NO-NDD %s
+//
+// EGPR-NDD: "-target-feature" "+egpr" "-target-feature" "+ndd"
+// EGPR-NO-NDD: "-target-feature" "-ndd" "-target-feature" "+egpr"
+// NO-EGPR-NDD: "-target-feature" "+ndd" "-target-feature" "-egpr"
+// NO-EGPR-NO-NDD: "-target-feature" "-egpr" "-target-feature" "-ndd"
+

phoebewang wrote:

Missing tests for "push2pop2", "ppx", "ccmp" and "cf"

https://github.com/llvm/llvm-project/pull/74199
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[llvm] [clang] [X86] Support CFE flags for APX features (PR #74199)

[Phoebe Wang via cfe-commits]

@@ -422,3 +422,28 @@
 
 // RUN: touch %t.o
 // RUN: %clang -fdriver-only -Werror --target=x86_64-pc-linux-gnu 
-mharden-sls=all %t.o -o /dev/null 2>&1 | count 0
+// RUN: %clang -target x86_64-unknown-linux-gnu -mapxf %s -### -o %t.o 2>&1 | 
FileCheck -check-prefix=APXF %s

phoebewang wrote:

Missing tests for macro defines

https://github.com/llvm/llvm-project/pull/74199
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[llvm] [clang] [X86] Support CFE flags for APX features (PR #74199)

[Phoebe Wang via cfe-commits]

@@ -5999,6 +5999,12 @@ def mno_gather : Flag<["-"], "mno-gather">, 
Group,
  HelpText<"Disable generation of gather instructions in 
auto-vectorization(x86 only)">;
 def mno_scatter : Flag<["-"], "mno-scatter">, Group,
   HelpText<"Disable generation of scatter instructions in 
auto-vectorization(x86 only)">;
+def mapx_features_EQ : CommaJoined<["-"], "mapx-features=">, 
Group,
+HelpText<"Enable features of APX">, 
Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">;
+def mno_apx_features_EQ : CommaJoined<["-"], "mno-apx-features=">, 
Group,
+HelpText<"Disable features of APX">, 
Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">;
+def mapxf : Flag<["-"], "mapxf">, Alias, 
AliasArgs<["egpr","push2pop2","ppx"]>;
+def mno_apxf : Flag<["-"], "mno-apxf">, Alias, 
AliasArgs<["egpr","push2pop2","ppx"]>;

phoebewang wrote:

You should comment in code for record not commit message.

https://github.com/llvm/llvm-project/pull/74199
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[clang] [llvm] [X86] Support CFE flags for APX features (PR #74199)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/74199
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[clang] [clang] Separate Intel ADC instrinsics from ADX intrinsics (PR #75992)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang closed 
https://github.com/llvm/llvm-project/pull/75992
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[clang] [X86] Add ABI handling for __float128 (PR #75156)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang updated 
https://github.com/llvm/llvm-project/pull/75156

>From 9860e5454bdf3ee3a4283ab7102a8d70c3ebcbbc Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Tue, 12 Dec 2023 17:27:33 +0800
Subject: [PATCH 1/2] [X86] Add ABI handling for fp128

Fixes #74601
---
 clang/lib/CodeGen/Targets/X86.cpp  |  3 ++-
 clang/test/CodeGen/X86/fp128-abi.c | 35 ++
 2 files changed, 37 insertions(+), 1 deletion(-)
 create mode 100644 clang/test/CodeGen/X86/fp128-abi.c

diff --git a/clang/lib/CodeGen/Targets/X86.cpp 
b/clang/lib/CodeGen/Targets/X86.cpp
index 2af24035043884..c4bf38056a673f 100644
--- a/clang/lib/CodeGen/Targets/X86.cpp
+++ b/clang/lib/CodeGen/Targets/X86.cpp
@@ -1795,7 +1795,8 @@ void X86_64ABIInfo::classify(QualType Ty, uint64_t 
OffsetBase, Class &Lo,
 } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
   Current = Integer;
 } else if (k == BuiltinType::Float || k == BuiltinType::Double ||
-   k == BuiltinType::Float16 || k == BuiltinType::BFloat16) {
+   k == BuiltinType::Float16 || k == BuiltinType::BFloat16 ||
+   k == BuiltinType::Float128) {
   Current = SSE;
 } else if (k == BuiltinType::LongDouble) {
   const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
diff --git a/clang/test/CodeGen/X86/fp128-abi.c 
b/clang/test/CodeGen/X86/fp128-abi.c
new file mode 100644
index 00..1c5d7cf1166ee1
--- /dev/null
+++ b/clang/test/CodeGen/X86/fp128-abi.c
@@ -0,0 +1,35 @@
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm  -target-feature +sse2 < %s 
| FileCheck %s --check-prefixes=CHECK
+
+struct st1 {
+  __float128 a;
+};
+
+struct st1 h1(__float128 a) {
+  // CHECK: define{{.*}}fp128 @h1(fp128
+  struct st1 x;
+  x.a = a;
+  return x;
+}
+
+__float128 h2(struct st1 x) {
+  // CHECK: define{{.*}}fp128 @h2(fp128
+  return x.a;
+}
+
+struct st2 {
+  __float128 a;
+  int b;
+};
+
+struct st2 h3(__float128 a, int b) {
+  // CHECK: define{{.*}}void @h3(ptr {{.*}}sret(%struct.st2)
+  struct st2 x;
+  x.a = a;
+  x.b = b;
+  return x;
+}
+
+__float128 h4(struct st2 x) {
+  // CHECK: define{{.*}}fp128 @h4(ptr {{.*}}byval(%struct.st2)
+  return x.a;
+}

>From 2619d6840965fb7447182f2026d5e48eca7b064b Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Thu, 21 Dec 2023 15:33:52 +0800
Subject: [PATCH 2/2] Add non-SSE RUN

---
 clang/lib/CodeGen/Targets/X86.cpp  | 6 --
 clang/test/CodeGen/X86/fp128-abi.c | 1 +
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/clang/lib/CodeGen/Targets/X86.cpp 
b/clang/lib/CodeGen/Targets/X86.cpp
index c4bf38056a673f..d053f41ab168f5 100644
--- a/clang/lib/CodeGen/Targets/X86.cpp
+++ b/clang/lib/CodeGen/Targets/X86.cpp
@@ -1795,9 +1795,11 @@ void X86_64ABIInfo::classify(QualType Ty, uint64_t 
OffsetBase, Class &Lo,
 } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
   Current = Integer;
 } else if (k == BuiltinType::Float || k == BuiltinType::Double ||
-   k == BuiltinType::Float16 || k == BuiltinType::BFloat16 ||
-   k == BuiltinType::Float128) {
+   k == BuiltinType::Float16 || k == BuiltinType::BFloat16) {
   Current = SSE;
+} else if (k == BuiltinType::Float128) {
+  Lo = SSE;
+  Hi = SSEUp;
 } else if (k == BuiltinType::LongDouble) {
   const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
   if (LDF == &llvm::APFloat::IEEEquad()) {
diff --git a/clang/test/CodeGen/X86/fp128-abi.c 
b/clang/test/CodeGen/X86/fp128-abi.c
index 1c5d7cf1166ee1..2a0ae5009338a4 100644
--- a/clang/test/CodeGen/X86/fp128-abi.c
+++ b/clang/test/CodeGen/X86/fp128-abi.c
@@ -1,4 +1,5 @@
 // RUN: %clang_cc1 -triple x86_64-linux -emit-llvm  -target-feature +sse2 < %s 
| FileCheck %s --check-prefixes=CHECK
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm  -target-feature -sse2 < %s 
| FileCheck %s --check-prefixes=CHECK
 
 struct st1 {
   __float128 a;

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[clang] [X86] Add ABI handling for __float128 (PR #75156)

[Phoebe Wang via cfe-commits]

@@ -0,0 +1,35 @@
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm  -target-feature +sse2 < %s 
| FileCheck %s --check-prefixes=CHECK

phoebewang wrote:

I decided not to report error for `-sse` after investigating the current 
diagnosis machinism.
We didn't report the SSE error in semacheck but in backend due to backend crash.
`__float128` doesn't have crash issue and can be passed on GPR registers 
without SSE enabled.
IIUC, we prefer to be compatible with early version rather than always to GCC. 
So I'd like to keep the convention as is.

https://github.com/llvm/llvm-project/pull/75156
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[clang] [X86] Add ABI handling for __float128 (PR #75156)

[Phoebe Wang via cfe-commits]

@@ -0,0 +1,35 @@
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm  -target-feature +sse2 < %s 
| FileCheck %s --check-prefixes=CHECK

phoebewang wrote:

Yes, e.g, `llvm/test/CodeGen/X86/{soft-fp,x87}.ll`, though I doubt if they can 
work in reality since they are calling to the same lib functions.

https://github.com/llvm/llvm-project/pull/75156
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[clang] [X86] Emit Warnings for frontend options to enable knl/knm. (PR #75580)

[Phoebe Wang via cfe-commits]

phoebewang wrote:

> I also think we need a policy regarding what test coverage we need for 
> various avx512 features (when should we assume avx512vl etc.)

Considering the new evolution in AVX10, we should switch testing model from 
`avx512xxx ± avx512vl` to `avx512xxx + avx512vl ± 
 evex512`.
I also imagine we can turn any avx512 feature, e.g., `bool hasBWI() {return 
HasBWI;}` into `bool hasBWI() {return HasBWI & HasVLX;}`, then remove all 
`hasVLX` checks in the code, e.g., `Subtarget.hasVLX() && Subtarget.hasBWI()` 
to `Subtarget.hasBWI()`.

> I think if we have an approach that allows people to emulate a very basic 
> KNL/KNM implementation with the equivalent of "-march=x86-64-v3 -mavx512f 
> -mavx512cd" then that would be sufficient.

This will require compiler and tests continue to handle cases avx512f/avx512cd 
without avx512vl. It conflicts with my expectation for `hasVLX` clean up. But 
maybe we can preserve these handling for few features for a short period.

> We should keep asm handling for avx512er/avx512pf/etc but no need for 
> attributes/intrinsics handling for them - if somebody needs to write assembly 
> for them we shouldn't prevent it.

+1

https://github.com/llvm/llvm-project/pull/75580
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[clang] [X86] Emit Warnings for frontend options to enable knl/knm. (PR #75580)

[Phoebe Wang via cfe-commits]

phoebewang wrote:

> Making avx512f the only case where avx512vl can be disabled doesn't seem like 
> too much of a stretch to me - we'd be merely making all avx512 extension 
> features depend on avx512vl.

Agreed.

https://github.com/llvm/llvm-project/pull/75580
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[clang] [X86] Add ABI handling for __float128 (PR #75156)

[Phoebe Wang via cfe-commits]

phoebewang wrote:

Ping @RKSimon 

https://github.com/llvm/llvm-project/pull/75156
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[libcxx] [flang] [libc] [clang-tools-extra] [llvm] [lldb] [clang] [compiler-rt] [X86][BF16][WIP] Try to use `f16` for lowering (PR #76901)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang updated 
https://github.com/llvm/llvm-project/pull/76901

>From ff9b72bdb5442a037d4325619de66e25ad211586 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Mon, 1 Jan 2024 15:13:38 +0800
Subject: [PATCH] [X86][BF16][WIP] Try to use `f16` for lowering

---
 llvm/lib/Target/X86/X86ISelLowering.cpp |   11 +-
 llvm/lib/Target/X86/X86ISelLowering.h   |   10 -
 llvm/lib/Target/X86/X86ISelLoweringCall.cpp |   37 +-
 llvm/test/CodeGen/X86/bfloat.ll | 1199 +++
 4 files changed, 739 insertions(+), 518 deletions(-)

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp 
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index a90ddf132c3897..6d25992315b2db 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -7475,10 +7475,12 @@ static SDValue buildFromShuffleMostly(SDValue Op, 
SelectionDAG &DAG) {
 static SDValue LowerBUILD_VECTORvXbf16(SDValue Op, SelectionDAG &DAG,
const X86Subtarget &Subtarget) {
   MVT VT = Op.getSimpleValueType();
-  MVT IVT = VT.changeVectorElementTypeToInteger();
+  MVT IVT =
+  VT.changeVectorElementType(Subtarget.hasFP16() ? MVT::f16 : MVT::i16);
   SmallVector NewOps;
   for (unsigned I = 0, E = Op.getNumOperands(); I != E; ++I)
-NewOps.push_back(DAG.getBitcast(MVT::i16, Op.getOperand(I)));
+NewOps.push_back(DAG.getBitcast(Subtarget.hasFP16() ? MVT::f16 : MVT::i16,
+Op.getOperand(I)));
   SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(), IVT, NewOps);
   return DAG.getBitcast(VT, Res);
 }
@@ -21515,9 +21517,8 @@ SDValue X86TargetLowering::LowerFP_TO_BF16(SDValue Op,
   RTLIB::Libcall LC =
   RTLIB::getFPROUND(Op.getOperand(0).getValueType(), MVT::bf16);
   SDValue Res =
-  makeLibCall(DAG, LC, MVT::f32, Op.getOperand(0), CallOptions, DL).first;
-  return DAG.getNode(ISD::TRUNCATE, DL, MVT::i16,
- DAG.getBitcast(MVT::i32, Res));
+  makeLibCall(DAG, LC, MVT::f16, Op.getOperand(0), CallOptions, DL).first;
+  return DAG.getBitcast(MVT::i16, Res);
 }
 
 /// Depending on uarch and/or optimizing for size, we might prefer to use a
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h 
b/llvm/lib/Target/X86/X86ISelLowering.h
index 9bd1622cb0d3a6..32745400a38b7e 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -1714,16 +1714,6 @@ namespace llvm {
   MachineBasicBlock *Entry,
   const SmallVectorImpl &Exits) const override;
 
-bool splitValueIntoRegisterParts(
-SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
-unsigned NumParts, MVT PartVT, std::optional CC)
-const override;
-
-SDValue joinRegisterPartsIntoValue(
-SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
-unsigned NumParts, MVT PartVT, EVT ValueVT,
-std::optional CC) const override;
-
 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
 
 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
diff --git a/llvm/lib/Target/X86/X86ISelLoweringCall.cpp 
b/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
index b8b5421b900501..d75bd4171fde9d 100644
--- a/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
+++ b/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
@@ -127,6 +127,9 @@ MVT 
X86TargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
 return getRegisterTypeForCallingConv(Context, CC,
  VT.changeVectorElementType(MVT::f16));
 
+  if (VT == MVT::bf16)
+return MVT::f16;
+
   return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
 }
 
@@ -421,40 +424,6 @@ unsigned X86TargetLowering::getJumpTableEncoding() const {
   return TargetLowering::getJumpTableEncoding();
 }
 
-bool X86TargetLowering::splitValueIntoRegisterParts(
-SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
-unsigned NumParts, MVT PartVT, std::optional CC) const {
-  bool IsABIRegCopy = CC.has_value();
-  EVT ValueVT = Val.getValueType();
-  if (IsABIRegCopy && ValueVT == MVT::bf16 && PartVT == MVT::f32) {
-unsigned ValueBits = ValueVT.getSizeInBits();
-unsigned PartBits = PartVT.getSizeInBits();
-Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(ValueBits), Val);
-Val = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::getIntegerVT(PartBits), Val);
-Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
-Parts[0] = Val;
-return true;
-  }
-  return false;
-}
-
-SDValue X86TargetLowering::joinRegisterPartsIntoValue(
-SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned 
NumParts,
-MVT PartVT, EVT ValueVT, std::optional CC) const {
-  bool IsABIRegCopy = CC.has_value();
-  if (IsABIRegCopy && ValueVT == MVT::bf16 && PartVT == MVT::f32) {
-unsigned ValueBits = ValueVT.getSizeInBits();
-unsigned PartBits = PartVT.getSizeInBits();
-SDValue Val = Parts[0];
-
-Val

[flang] [clang] [lldb] [libcxx] [llvm] [compiler-rt] [libc] [clang-tools-extra] [X86][BF16][WIP] Try to use `f16` for lowering (PR #76901)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang ready_for_review 
https://github.com/llvm/llvm-project/pull/76901
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[flang] [clang] [lldb] [libcxx] [llvm] [compiler-rt] [libc] [clang-tools-extra] [X86][BF16] Try to use `f16` for lowering (PR #76901)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang edited 
https://github.com/llvm/llvm-project/pull/76901
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[lldb] [compiler-rt] [libc] [flang] [clang-tools-extra] [libcxx] [llvm] [clang] [X86][BF16] Try to use `f16` for lowering (PR #76901)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang edited 
https://github.com/llvm/llvm-project/pull/76901
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[clang] [X86] Add ABI handling for __float128 (PR #75156)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang updated 
https://github.com/llvm/llvm-project/pull/75156

>From 9860e5454bdf3ee3a4283ab7102a8d70c3ebcbbc Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Tue, 12 Dec 2023 17:27:33 +0800
Subject: [PATCH 1/3] [X86] Add ABI handling for fp128

Fixes #74601
---
 clang/lib/CodeGen/Targets/X86.cpp  |  3 ++-
 clang/test/CodeGen/X86/fp128-abi.c | 35 ++
 2 files changed, 37 insertions(+), 1 deletion(-)
 create mode 100644 clang/test/CodeGen/X86/fp128-abi.c

diff --git a/clang/lib/CodeGen/Targets/X86.cpp 
b/clang/lib/CodeGen/Targets/X86.cpp
index 2af24035043884..c4bf38056a673f 100644
--- a/clang/lib/CodeGen/Targets/X86.cpp
+++ b/clang/lib/CodeGen/Targets/X86.cpp
@@ -1795,7 +1795,8 @@ void X86_64ABIInfo::classify(QualType Ty, uint64_t 
OffsetBase, Class &Lo,
 } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
   Current = Integer;
 } else if (k == BuiltinType::Float || k == BuiltinType::Double ||
-   k == BuiltinType::Float16 || k == BuiltinType::BFloat16) {
+   k == BuiltinType::Float16 || k == BuiltinType::BFloat16 ||
+   k == BuiltinType::Float128) {
   Current = SSE;
 } else if (k == BuiltinType::LongDouble) {
   const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
diff --git a/clang/test/CodeGen/X86/fp128-abi.c 
b/clang/test/CodeGen/X86/fp128-abi.c
new file mode 100644
index 00..1c5d7cf1166ee1
--- /dev/null
+++ b/clang/test/CodeGen/X86/fp128-abi.c
@@ -0,0 +1,35 @@
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm  -target-feature +sse2 < %s 
| FileCheck %s --check-prefixes=CHECK
+
+struct st1 {
+  __float128 a;
+};
+
+struct st1 h1(__float128 a) {
+  // CHECK: define{{.*}}fp128 @h1(fp128
+  struct st1 x;
+  x.a = a;
+  return x;
+}
+
+__float128 h2(struct st1 x) {
+  // CHECK: define{{.*}}fp128 @h2(fp128
+  return x.a;
+}
+
+struct st2 {
+  __float128 a;
+  int b;
+};
+
+struct st2 h3(__float128 a, int b) {
+  // CHECK: define{{.*}}void @h3(ptr {{.*}}sret(%struct.st2)
+  struct st2 x;
+  x.a = a;
+  x.b = b;
+  return x;
+}
+
+__float128 h4(struct st2 x) {
+  // CHECK: define{{.*}}fp128 @h4(ptr {{.*}}byval(%struct.st2)
+  return x.a;
+}

>From 2619d6840965fb7447182f2026d5e48eca7b064b Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Thu, 21 Dec 2023 15:33:52 +0800
Subject: [PATCH 2/3] Add non-SSE RUN

---
 clang/lib/CodeGen/Targets/X86.cpp  | 6 --
 clang/test/CodeGen/X86/fp128-abi.c | 1 +
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/clang/lib/CodeGen/Targets/X86.cpp 
b/clang/lib/CodeGen/Targets/X86.cpp
index c4bf38056a673f..d053f41ab168f5 100644
--- a/clang/lib/CodeGen/Targets/X86.cpp
+++ b/clang/lib/CodeGen/Targets/X86.cpp
@@ -1795,9 +1795,11 @@ void X86_64ABIInfo::classify(QualType Ty, uint64_t 
OffsetBase, Class &Lo,
 } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
   Current = Integer;
 } else if (k == BuiltinType::Float || k == BuiltinType::Double ||
-   k == BuiltinType::Float16 || k == BuiltinType::BFloat16 ||
-   k == BuiltinType::Float128) {
+   k == BuiltinType::Float16 || k == BuiltinType::BFloat16) {
   Current = SSE;
+} else if (k == BuiltinType::Float128) {
+  Lo = SSE;
+  Hi = SSEUp;
 } else if (k == BuiltinType::LongDouble) {
   const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
   if (LDF == &llvm::APFloat::IEEEquad()) {
diff --git a/clang/test/CodeGen/X86/fp128-abi.c 
b/clang/test/CodeGen/X86/fp128-abi.c
index 1c5d7cf1166ee1..2a0ae5009338a4 100644
--- a/clang/test/CodeGen/X86/fp128-abi.c
+++ b/clang/test/CodeGen/X86/fp128-abi.c
@@ -1,4 +1,5 @@
 // RUN: %clang_cc1 -triple x86_64-linux -emit-llvm  -target-feature +sse2 < %s 
| FileCheck %s --check-prefixes=CHECK
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm  -target-feature -sse2 < %s 
| FileCheck %s --check-prefixes=CHECK
 
 struct st1 {
   __float128 a;

>From 30db4d0a6d74fdc0642801998c8a734c6c82726d Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Fri, 5 Jan 2024 11:13:46 +0800
Subject: [PATCH 3/3] Added release note

---
 clang/docs/ReleaseNotes.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index b62293a33bb9ff..902f64bc9aa144 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -906,6 +906,7 @@ X86 Support
   * Support intrinsic of ``_uwrmsr``.
 - Support ISA of ``AVX10.1``.
 - ``-march=pantherlake`` and ``-march=clearwaterforest`` are now supported.
+- Added ABI handling for ``fp128``.
 
 Arm and AArch64 Support
 ^^^

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[clang] [X86] Add ABI handling for __float128 (PR #75156)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang updated 
https://github.com/llvm/llvm-project/pull/75156

>From 9860e5454bdf3ee3a4283ab7102a8d70c3ebcbbc Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Tue, 12 Dec 2023 17:27:33 +0800
Subject: [PATCH 1/4] [X86] Add ABI handling for fp128

Fixes #74601
---
 clang/lib/CodeGen/Targets/X86.cpp  |  3 ++-
 clang/test/CodeGen/X86/fp128-abi.c | 35 ++
 2 files changed, 37 insertions(+), 1 deletion(-)
 create mode 100644 clang/test/CodeGen/X86/fp128-abi.c

diff --git a/clang/lib/CodeGen/Targets/X86.cpp 
b/clang/lib/CodeGen/Targets/X86.cpp
index 2af24035043884..c4bf38056a673f 100644
--- a/clang/lib/CodeGen/Targets/X86.cpp
+++ b/clang/lib/CodeGen/Targets/X86.cpp
@@ -1795,7 +1795,8 @@ void X86_64ABIInfo::classify(QualType Ty, uint64_t 
OffsetBase, Class &Lo,
 } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
   Current = Integer;
 } else if (k == BuiltinType::Float || k == BuiltinType::Double ||
-   k == BuiltinType::Float16 || k == BuiltinType::BFloat16) {
+   k == BuiltinType::Float16 || k == BuiltinType::BFloat16 ||
+   k == BuiltinType::Float128) {
   Current = SSE;
 } else if (k == BuiltinType::LongDouble) {
   const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
diff --git a/clang/test/CodeGen/X86/fp128-abi.c 
b/clang/test/CodeGen/X86/fp128-abi.c
new file mode 100644
index 00..1c5d7cf1166ee1
--- /dev/null
+++ b/clang/test/CodeGen/X86/fp128-abi.c
@@ -0,0 +1,35 @@
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm  -target-feature +sse2 < %s 
| FileCheck %s --check-prefixes=CHECK
+
+struct st1 {
+  __float128 a;
+};
+
+struct st1 h1(__float128 a) {
+  // CHECK: define{{.*}}fp128 @h1(fp128
+  struct st1 x;
+  x.a = a;
+  return x;
+}
+
+__float128 h2(struct st1 x) {
+  // CHECK: define{{.*}}fp128 @h2(fp128
+  return x.a;
+}
+
+struct st2 {
+  __float128 a;
+  int b;
+};
+
+struct st2 h3(__float128 a, int b) {
+  // CHECK: define{{.*}}void @h3(ptr {{.*}}sret(%struct.st2)
+  struct st2 x;
+  x.a = a;
+  x.b = b;
+  return x;
+}
+
+__float128 h4(struct st2 x) {
+  // CHECK: define{{.*}}fp128 @h4(ptr {{.*}}byval(%struct.st2)
+  return x.a;
+}

>From 2619d6840965fb7447182f2026d5e48eca7b064b Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Thu, 21 Dec 2023 15:33:52 +0800
Subject: [PATCH 2/4] Add non-SSE RUN

---
 clang/lib/CodeGen/Targets/X86.cpp  | 6 --
 clang/test/CodeGen/X86/fp128-abi.c | 1 +
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/clang/lib/CodeGen/Targets/X86.cpp 
b/clang/lib/CodeGen/Targets/X86.cpp
index c4bf38056a673f..d053f41ab168f5 100644
--- a/clang/lib/CodeGen/Targets/X86.cpp
+++ b/clang/lib/CodeGen/Targets/X86.cpp
@@ -1795,9 +1795,11 @@ void X86_64ABIInfo::classify(QualType Ty, uint64_t 
OffsetBase, Class &Lo,
 } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
   Current = Integer;
 } else if (k == BuiltinType::Float || k == BuiltinType::Double ||
-   k == BuiltinType::Float16 || k == BuiltinType::BFloat16 ||
-   k == BuiltinType::Float128) {
+   k == BuiltinType::Float16 || k == BuiltinType::BFloat16) {
   Current = SSE;
+} else if (k == BuiltinType::Float128) {
+  Lo = SSE;
+  Hi = SSEUp;
 } else if (k == BuiltinType::LongDouble) {
   const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
   if (LDF == &llvm::APFloat::IEEEquad()) {
diff --git a/clang/test/CodeGen/X86/fp128-abi.c 
b/clang/test/CodeGen/X86/fp128-abi.c
index 1c5d7cf1166ee1..2a0ae5009338a4 100644
--- a/clang/test/CodeGen/X86/fp128-abi.c
+++ b/clang/test/CodeGen/X86/fp128-abi.c
@@ -1,4 +1,5 @@
 // RUN: %clang_cc1 -triple x86_64-linux -emit-llvm  -target-feature +sse2 < %s 
| FileCheck %s --check-prefixes=CHECK
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm  -target-feature -sse2 < %s 
| FileCheck %s --check-prefixes=CHECK
 
 struct st1 {
   __float128 a;

>From 30db4d0a6d74fdc0642801998c8a734c6c82726d Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Fri, 5 Jan 2024 11:13:46 +0800
Subject: [PATCH 3/4] Added release note

---
 clang/docs/ReleaseNotes.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index b62293a33bb9ff..902f64bc9aa144 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -906,6 +906,7 @@ X86 Support
   * Support intrinsic of ``_uwrmsr``.
 - Support ISA of ``AVX10.1``.
 - ``-march=pantherlake`` and ``-march=clearwaterforest`` are now supported.
+- Added ABI handling for ``fp128``.
 
 Arm and AArch64 Support
 ^^^

>From af71a05c89240b866154da79cced93eae17821db Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Fri, 5 Jan 2024 11:14:52 +0800
Subject: [PATCH 4/4] Fix typo

---
 clang/docs/ReleaseNotes.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rs

[clang] [X86] Add ABI handling for __float128 (PR #75156)

[Phoebe Wang via cfe-commits]

phoebewang wrote:

> Add a Release notes entry? I always forget exactly what we need to do for ABI 
> fixes/tweaks

Goot point! Done.

https://github.com/llvm/llvm-project/pull/75156
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[clang-tools-extra] [llvm] [clang] DAG: Implement promotion for strict_fp_round (PR #74332)

[Phoebe Wang via cfe-commits]

@@ -1097,7 +1097,7 @@ def : Pat <
 multiclass f16_fp_Pats {
   // f16_to_fp patterns
   def : GCNPat <
-(f32 (f16_to_fp i32:$src0)),
+(f32 (any_f16_to_fp i32:$src0)),

phoebewang wrote:

Should we replace more `f16_to_fp` to `any_f16_to_fp` in this file and other 
target files?

https://github.com/llvm/llvm-project/pull/74332
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[clang-tools-extra] [llvm] [clang] DAG: Implement promotion for strict_fp_round (PR #74332)

[Phoebe Wang via cfe-commits]

@@ -2621,6 +2642,29 @@ SDValue 
DAGTypeLegalizer::PromoteFloatRes_FP_ROUND(SDNode *N) {
   return DAG.getNode(GetPromotionOpcode(VT, NVT), DL, NVT, Round);
 }
 
+// Explicit operation to reduce precision.  Reduce the value to half precision
+// and promote it back to the legal type.
+SDValue DAGTypeLegalizer::PromoteFloatRes_STRICT_FP_ROUND(SDNode *N) {

phoebewang wrote:

Why we need this given we have a handler here 
https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp#L2996-L3003

https://github.com/llvm/llvm-project/pull/74332
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[flang] [libc] [lldb] [compiler-rt] [clang-tools-extra] [llvm] [libcxx] [clang] [X86][BF16] Try to use `f16` for lowering (PR #76901)

[Phoebe Wang via cfe-commits]

@@ -22,10 +22,7 @@ define void @add(ptr %pa, ptr %pb, ptr %pc) nounwind {
 ; X86-NEXT:vaddss %xmm0, %xmm1, %xmm0
 ; X86-NEXT:vmovss %xmm0, (%esp)
 ; X86-NEXT:calll __truncsfbf2
-; X86-NEXT:fstps {{[0-9]+}}(%esp)
-; X86-NEXT:vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86-NEXT:vmovd %xmm0, %eax
-; X86-NEXT:movw %ax, (%esi)
+; X86-NEXT:vmovsh %xmm0, (%esi)

phoebewang wrote:

What's the mean by truncate?

https://github.com/llvm/llvm-project/pull/76901
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[clang] [flang] [compiler-rt] [clang-tools-extra] [libc] [libcxx] [lldb] [llvm] [X86][BF16] Try to use `f16` for lowering (PR #76901)

[Phoebe Wang via cfe-commits]

@@ -22,10 +22,7 @@ define void @add(ptr %pa, ptr %pb, ptr %pc) nounwind {
 ; X86-NEXT:vaddss %xmm0, %xmm1, %xmm0
 ; X86-NEXT:vmovss %xmm0, (%esp)
 ; X86-NEXT:calll __truncsfbf2
-; X86-NEXT:fstps {{[0-9]+}}(%esp)
-; X86-NEXT:vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86-NEXT:vmovd %xmm0, %eax
-; X86-NEXT:movw %ax, (%esi)
+; X86-NEXT:vmovsh %xmm0, (%esi)

phoebewang wrote:

`vmovsh` can store the low 16-bit to memory directly.
The original codes has ABI mistake, which store `bf16` without `f32`. Since 
`f32` uses X87 registers on 32-bit target, it need to store to another memory 
first, reload to store again.
The patch makes the result in XMM0, so one `vmovsh` is enough.

https://github.com/llvm/llvm-project/pull/76901
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[clang] [flang] [compiler-rt] [clang-tools-extra] [libc] [libcxx] [lldb] [llvm] [X86][BF16] Try to use `f16` for lowering (PR #76901)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang edited 
https://github.com/llvm/llvm-project/pull/76901
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[clang] [flang] [compiler-rt] [clang-tools-extra] [libc] [libcxx] [lldb] [llvm] [X86][BF16] Try to use `f16` for lowering (PR #76901)

[Phoebe Wang via cfe-commits]

phoebewang wrote:

Thanks @FreddyLeaf !

https://github.com/llvm/llvm-project/pull/76901
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[clang] [flang] [compiler-rt] [clang-tools-extra] [libc] [libcxx] [lldb] [llvm] [X86][BF16] Try to use `f16` for lowering (PR #76901)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang closed 
https://github.com/llvm/llvm-project/pull/76901
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[libcxx] [lldb] [openmp] [llvm] [mlir] [clang] [clang-tools-extra] [SEH] Fix register liveness verification for EHa (PR #76933)

[Phoebe Wang via cfe-commits]

@@ -3347,10 +3348,37 @@ void MachineVerifier::verifyLiveRangeSegment(const 
LiveRange &LR,
 OwnerLI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
   }
 
+  bool IsEHa = MF->getMMI().getModule()->getModuleFlag("eh-asynch");
   while (true) {
 assert(LiveInts->isLiveInToMBB(LR, &*MFI));
-// We don't know how to track physregs into a landing pad.
-if (!Reg.isVirtual() && MFI->isEHPad()) {
+auto IsSEHHandler = [](const MachineBasicBlock &Handler) -> bool {
+  if (!Handler.isMachineBlockAddressTaken())
+return false;
+
+  for (const User *U : Handler.getBasicBlock()->users()) {
+if (!isa(U))
+  continue;
+const Function *Fn = cast(U)->getCalledFunction();
+if (!Fn || !Fn->isIntrinsic())
+  continue;
+
+switch (Fn->getIntrinsicID()) {
+default:
+  continue;
+case Intrinsic::seh_scope_begin:
+case Intrinsic::seh_scope_end:
+case Intrinsic::seh_try_begin:
+case Intrinsic::seh_try_end:
+  return true;
+}
+  }
+  return false;
+};
+
+// TODO: we don't know how to track physregs into a landing pad. For async
+// EH, the virtual reg lives before scope begin, but we don't know seh 
scope

phoebewang wrote:

Can we get the scope through `seh_scope_begin/seh_scope_end` etc.?

https://github.com/llvm/llvm-project/pull/76933
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[clang] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)

[Phoebe Wang via cfe-commits]

@@ -69,7 +69,10 @@
 // RUN: %clang_cl -m32 -arch:avx2 --target=i386-pc-windows -### -- 2>&1 %s | 
FileCheck -check-prefix=avx2 %s
 // avx2: invalid /arch: argument
 
-// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj 
-Xclang -verify -DTEST_32_ARCH_AVX512F -- %s
+// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj 
-Xclang -verify=KNL1 -DTEST_32_ARCH_AVX512F -- %s

phoebewang wrote:

Why we emit warnings given no KNL/KNM feature specified?

https://github.com/llvm/llvm-project/pull/75580
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[clang] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)

[Phoebe Wang via cfe-commits]

@@ -18,7 +18,7 @@ This test serves two purposes:
 
 The list of warnings below should NEVER grow.  It should gradually shrink to 0.
 
-CHECK: Warnings without flags (65):

phoebewang wrote:

The comment says we should not increase it.

https://github.com/llvm/llvm-project/pull/75580
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[lldb] [clang] [llvm] [libcxx] [clang-tools-extra] [mlir] [openmp] [SEH] Fix register liveness verification for EHa (PR #76933)

[Phoebe Wang via cfe-commits]

@@ -3347,10 +3348,37 @@ void MachineVerifier::verifyLiveRangeSegment(const 
LiveRange &LR,
 OwnerLI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
   }
 
+  bool IsEHa = MF->getMMI().getModule()->getModuleFlag("eh-asynch");
   while (true) {
 assert(LiveInts->isLiveInToMBB(LR, &*MFI));
-// We don't know how to track physregs into a landing pad.
-if (!Reg.isVirtual() && MFI->isEHPad()) {
+auto IsSEHHandler = [](const MachineBasicBlock &Handler) -> bool {
+  if (!Handler.isMachineBlockAddressTaken())
+return false;
+
+  for (const User *U : Handler.getBasicBlock()->users()) {
+if (!isa(U))
+  continue;
+const Function *Fn = cast(U)->getCalledFunction();
+if (!Fn || !Fn->isIntrinsic())
+  continue;
+
+switch (Fn->getIntrinsicID()) {
+default:
+  continue;
+case Intrinsic::seh_scope_begin:
+case Intrinsic::seh_scope_end:
+case Intrinsic::seh_try_begin:
+case Intrinsic::seh_try_end:
+  return true;
+}
+  }
+  return false;
+};
+
+// TODO: we don't know how to track physregs into a landing pad. For async
+// EH, the virtual reg lives before scope begin, but we don't know seh 
scope

phoebewang wrote:

I once had an idea to lower them into pseudo instructions. But maybe need more 
work to do.

https://github.com/llvm/llvm-project/pull/76933
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[clang] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)

[Phoebe Wang via cfe-commits]

@@ -18,7 +18,7 @@ This test serves two purposes:
 
 The list of warnings below should NEVER grow.  It should gradually shrink to 0.
 
-CHECK: Warnings without flags (65):

phoebewang wrote:

Maybe it's not a good example. The test is to prevent adding warnings without 
-W flags. I think we also need the flag here for user to mask the warning.

https://github.com/llvm/llvm-project/pull/75580
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[clang] [X86] Add ABI handling for __float128 (PR #75156)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang updated 
https://github.com/llvm/llvm-project/pull/75156

>From 9860e5454bdf3ee3a4283ab7102a8d70c3ebcbbc Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Tue, 12 Dec 2023 17:27:33 +0800
Subject: [PATCH 1/5] [X86] Add ABI handling for fp128

Fixes #74601
---
 clang/lib/CodeGen/Targets/X86.cpp  |  3 ++-
 clang/test/CodeGen/X86/fp128-abi.c | 35 ++
 2 files changed, 37 insertions(+), 1 deletion(-)
 create mode 100644 clang/test/CodeGen/X86/fp128-abi.c

diff --git a/clang/lib/CodeGen/Targets/X86.cpp 
b/clang/lib/CodeGen/Targets/X86.cpp
index 2af24035043884..c4bf38056a673f 100644
--- a/clang/lib/CodeGen/Targets/X86.cpp
+++ b/clang/lib/CodeGen/Targets/X86.cpp
@@ -1795,7 +1795,8 @@ void X86_64ABIInfo::classify(QualType Ty, uint64_t 
OffsetBase, Class &Lo,
 } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
   Current = Integer;
 } else if (k == BuiltinType::Float || k == BuiltinType::Double ||
-   k == BuiltinType::Float16 || k == BuiltinType::BFloat16) {
+   k == BuiltinType::Float16 || k == BuiltinType::BFloat16 ||
+   k == BuiltinType::Float128) {
   Current = SSE;
 } else if (k == BuiltinType::LongDouble) {
   const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
diff --git a/clang/test/CodeGen/X86/fp128-abi.c 
b/clang/test/CodeGen/X86/fp128-abi.c
new file mode 100644
index 00..1c5d7cf1166ee1
--- /dev/null
+++ b/clang/test/CodeGen/X86/fp128-abi.c
@@ -0,0 +1,35 @@
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm  -target-feature +sse2 < %s 
| FileCheck %s --check-prefixes=CHECK
+
+struct st1 {
+  __float128 a;
+};
+
+struct st1 h1(__float128 a) {
+  // CHECK: define{{.*}}fp128 @h1(fp128
+  struct st1 x;
+  x.a = a;
+  return x;
+}
+
+__float128 h2(struct st1 x) {
+  // CHECK: define{{.*}}fp128 @h2(fp128
+  return x.a;
+}
+
+struct st2 {
+  __float128 a;
+  int b;
+};
+
+struct st2 h3(__float128 a, int b) {
+  // CHECK: define{{.*}}void @h3(ptr {{.*}}sret(%struct.st2)
+  struct st2 x;
+  x.a = a;
+  x.b = b;
+  return x;
+}
+
+__float128 h4(struct st2 x) {
+  // CHECK: define{{.*}}fp128 @h4(ptr {{.*}}byval(%struct.st2)
+  return x.a;
+}

>From 2619d6840965fb7447182f2026d5e48eca7b064b Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Thu, 21 Dec 2023 15:33:52 +0800
Subject: [PATCH 2/5] Add non-SSE RUN

---
 clang/lib/CodeGen/Targets/X86.cpp  | 6 --
 clang/test/CodeGen/X86/fp128-abi.c | 1 +
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/clang/lib/CodeGen/Targets/X86.cpp 
b/clang/lib/CodeGen/Targets/X86.cpp
index c4bf38056a673f..d053f41ab168f5 100644
--- a/clang/lib/CodeGen/Targets/X86.cpp
+++ b/clang/lib/CodeGen/Targets/X86.cpp
@@ -1795,9 +1795,11 @@ void X86_64ABIInfo::classify(QualType Ty, uint64_t 
OffsetBase, Class &Lo,
 } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
   Current = Integer;
 } else if (k == BuiltinType::Float || k == BuiltinType::Double ||
-   k == BuiltinType::Float16 || k == BuiltinType::BFloat16 ||
-   k == BuiltinType::Float128) {
+   k == BuiltinType::Float16 || k == BuiltinType::BFloat16) {
   Current = SSE;
+} else if (k == BuiltinType::Float128) {
+  Lo = SSE;
+  Hi = SSEUp;
 } else if (k == BuiltinType::LongDouble) {
   const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
   if (LDF == &llvm::APFloat::IEEEquad()) {
diff --git a/clang/test/CodeGen/X86/fp128-abi.c 
b/clang/test/CodeGen/X86/fp128-abi.c
index 1c5d7cf1166ee1..2a0ae5009338a4 100644
--- a/clang/test/CodeGen/X86/fp128-abi.c
+++ b/clang/test/CodeGen/X86/fp128-abi.c
@@ -1,4 +1,5 @@
 // RUN: %clang_cc1 -triple x86_64-linux -emit-llvm  -target-feature +sse2 < %s 
| FileCheck %s --check-prefixes=CHECK
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm  -target-feature -sse2 < %s 
| FileCheck %s --check-prefixes=CHECK
 
 struct st1 {
   __float128 a;

>From 30db4d0a6d74fdc0642801998c8a734c6c82726d Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Fri, 5 Jan 2024 11:13:46 +0800
Subject: [PATCH 3/5] Added release note

---
 clang/docs/ReleaseNotes.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index b62293a33bb9ff..902f64bc9aa144 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -906,6 +906,7 @@ X86 Support
   * Support intrinsic of ``_uwrmsr``.
 - Support ISA of ``AVX10.1``.
 - ``-march=pantherlake`` and ``-march=clearwaterforest`` are now supported.
+- Added ABI handling for ``fp128``.
 
 Arm and AArch64 Support
 ^^^

>From af71a05c89240b866154da79cced93eae17821db Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Fri, 5 Jan 2024 11:14:52 +0800
Subject: [PATCH 4/5] Fix typo

---
 clang/docs/ReleaseNotes.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rs

[clang] [X86] Add ABI handling for __float128 to match with GCC (PR #75156)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang edited 
https://github.com/llvm/llvm-project/pull/75156
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[clang] [X86] Add ABI handling for __float128 to match with GCC (PR #75156)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang closed 
https://github.com/llvm/llvm-project/pull/75156
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[clang-tools-extra] [clang] [llvm] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)

[Phoebe Wang via cfe-commits]

@@ -69,7 +69,10 @@
 // RUN: %clang_cl -m32 -arch:avx2 --target=i386-pc-windows -### -- 2>&1 %s | 
FileCheck -check-prefix=avx2 %s
 // avx2: invalid /arch: argument
 
-// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj 
-Xclang -verify -DTEST_32_ARCH_AVX512F -- %s
+// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj 
-Xclang -verify=KNL1 -DTEST_32_ARCH_AVX512F -- %s

phoebewang wrote:

Do you mean AVX512PF? By clang-cl?

https://github.com/llvm/llvm-project/pull/75580
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[clang-tools-extra] [clang] [llvm] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)

[Phoebe Wang via cfe-commits]

@@ -933,6 +933,14 @@ X86 Support
 - Support ISA of ``AVX10.1``.
 - ``-march=pantherlake`` and ``-march=clearwaterforest`` are now supported.
 - Added ABI handling for ``__float128`` to match with GCC.
+- Emit warnings for options to enable knl/knm specific ISAs: AVX512PF, AVX512ER
+  and PREFETCHWT1. From next version (LLVM 19), these ISAs' intrinsic supports
+  will be deprecated:
+  * intrinsic series of *_exp2a23_*
+  * intrinsic series of *_rsqrt28_*
+  * intrinsic series of *_rcp28_*
+  * intrinsic series of *_prefetch_i[3|6][2|4]gather_*
+  * intrinsic series of *_prefetch_i[3|6][2|4]scatter_*

phoebewang wrote:

And `_m_prefetchw`

https://github.com/llvm/llvm-project/pull/75580
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[clang-tools-extra] [clang] [llvm] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)

[Phoebe Wang via cfe-commits]

@@ -933,6 +933,14 @@ X86 Support
 - Support ISA of ``AVX10.1``.
 - ``-march=pantherlake`` and ``-march=clearwaterforest`` are now supported.
 - Added ABI handling for ``__float128`` to match with GCC.
+- Emit warnings for options to enable knl/knm specific ISAs: AVX512PF, AVX512ER
+  and PREFETCHWT1. From next version (LLVM 19), these ISAs' intrinsic supports
+  will be deprecated:
+  * intrinsic series of *_exp2a23_*
+  * intrinsic series of *_rsqrt28_*
+  * intrinsic series of *_rcp28_*
+  * intrinsic series of *_prefetch_i[3|6][2|4]gather_*
+  * intrinsic series of *_prefetch_i[3|6][2|4]scatter_*

phoebewang wrote:

Thanks @topperc ! You are correct, I forgot that.
KNL has a seperate feature called `prefetchwt1`, but the intrinsic/mnemonic is 
the same.

https://github.com/llvm/llvm-project/pull/75580
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[llvm] [clang] [clang-tools-extra] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/75580
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[clang] [Headers][X86] Reformat ia32intrin.h doc to match the other headers (PR #77525)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/77525
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[libunwind] [openmp] [lld] [clang] [mlir] [clang-tools-extra] [flang] [compiler-rt] [lldb] [llvm] [BranchFolding] Fix missing predecessors of landing-pad (PR #77608)

[Phoebe Wang via cfe-commits]

@@ -1363,6 +1363,14 @@ bool BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) 
{
 MachineBasicBlock *Pred = *(MBB->pred_end()-1);
 Pred->ReplaceUsesOfBlockWith(MBB, &*FallThrough);
   }
+  // Add rest successors of MBB to successors of FallThrough. Those
+  // successors are not directly reachable via MBB, so it should be
+  // landing-pad.
+  for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI)
+if (*SI != &*FallThrough && !FallThrough->isSuccessor(*SI)) {
+  assert((*SI)->isEHPad() && "Bad CFG");
+  FallThrough->copySuccessor(MBB, SI);
+}

phoebewang wrote:

It's checked by `isSuccessor`, so multi call is not a problem.
One problem, no matter add here or in `ReplaceUsesOfBlockWith`, is whether 
these successors be removed latter? I think adding an edge to a died BB may 
also problematic.

https://github.com/llvm/llvm-project/pull/77608
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[libunwind] [openmp] [lld] [clang] [mlir] [clang-tools-extra] [flang] [compiler-rt] [lldb] [llvm] [BranchFolding] Fix missing predecessors of landing-pad (PR #77608)

[Phoebe Wang via cfe-commits]

phoebewang wrote:

> > > This keeps CFG as only have one entry which is required by LiveDebugValues
> > 
> > 
> > If we just want to make LiveDebugValues happy, should it better to remove 
> > these died BB instead?
> 
> This died BB was already removed by BranchFolder. See rebased test diff. We 
> just want to salvage its successors info.

I see. I thought the successors are removed too.

https://github.com/llvm/llvm-project/pull/77608
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[libunwind] [openmp] [lld] [clang] [mlir] [clang-tools-extra] [flang] [compiler-rt] [lldb] [llvm] [BranchFolding] Fix missing predecessors of landing-pad (PR #77608)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang edited 
https://github.com/llvm/llvm-project/pull/77608
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[libunwind] [openmp] [lld] [clang] [mlir] [clang-tools-extra] [flang] [compiler-rt] [lldb] [llvm] [BranchFolding] Fix missing predecessors of landing-pad (PR #77608)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang edited 
https://github.com/llvm/llvm-project/pull/77608
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[clang] [Headers][X86] Add more descriptions to ia32intrin.h and immintrin.h (PR #77686)

[Phoebe Wang via cfe-commits]

@@ -173,25 +183,59 @@ __popcntq(unsigned long long __A)
 #endif /* __x86_64__ */
 
 #ifdef __x86_64__
+/// Returns the program status and control \c RFLAGS register with the \c VM
+///and \c RF flags cleared.
+///
+/// \headerfile 
+///
+/// This intrinsic corresponds to the \c PUSHFQ + \c POPQ instruction sequence.

phoebewang wrote:

Also `POP` instead `POPQ`. The same below.

https://github.com/llvm/llvm-project/pull/77686
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[llvm] [clang] [X86][WIP] Use vXi1 for `k` constraint in inline asm (PR #77733)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang created 
https://github.com/llvm/llvm-project/pull/77733

Fixes #77172

>From 72fa88d9e2277a8df60cf39d8cc96aad984dc2e9 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Thu, 11 Jan 2024 14:59:51 +0800
Subject: [PATCH] [X86][WIP] Use vXi1 for `k` constraint in inline asm

Fixes #77172
---
 clang/lib/CodeGen/CGStmt.cpp  |  4 +--
 clang/lib/CodeGen/Targets/X86.cpp |  5 
 .../X86/avx512-kconstraints-att_inline_asm.c  |  8 ++---
 llvm/lib/Target/X86/X86ISelLowering.cpp   | 30 +--
 4 files changed, 26 insertions(+), 21 deletions(-)

diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
index b89017de0bcf14..beff0ad9da2709 100644
--- a/clang/lib/CodeGen/CGStmt.cpp
+++ b/clang/lib/CodeGen/CGStmt.cpp
@@ -2399,9 +2399,9 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
 Tmp = Builder.CreatePtrToInt(
 Tmp, llvm::IntegerType::get(CTX, (unsigned)TmpSize));
 Tmp = Builder.CreateTrunc(Tmp, TruncTy);
-  } else if (TruncTy->isIntegerTy()) {
+  } else if (Tmp->getType()->isIntegerTy() && TruncTy->isIntegerTy()) {
 Tmp = Builder.CreateZExtOrTrunc(Tmp, TruncTy);
-  } else if (TruncTy->isVectorTy()) {
+  } else if (Tmp->getType()->isVectorTy() || TruncTy->isVectorTy()) {
 Tmp = Builder.CreateBitCast(Tmp, TruncTy);
   }
 }
diff --git a/clang/lib/CodeGen/Targets/X86.cpp 
b/clang/lib/CodeGen/Targets/X86.cpp
index d053f41ab168f5..542377ec08e964 100644
--- a/clang/lib/CodeGen/Targets/X86.cpp
+++ b/clang/lib/CodeGen/Targets/X86.cpp
@@ -40,6 +40,11 @@ static llvm::Type* 
X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
 return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
   }
 
+  if (Constraint == "k") {
+llvm::Type* Int1Ty = llvm::Type::getInt1Ty(CGF.getLLVMContext());
+return llvm::FixedVectorType::get(Int1Ty, Ty->getScalarSizeInBits());
+  }
+
   // No operation needed
   return Ty;
 }
diff --git a/clang/test/CodeGen/X86/avx512-kconstraints-att_inline_asm.c 
b/clang/test/CodeGen/X86/avx512-kconstraints-att_inline_asm.c
index b4939bfc2ca831..74b6719bf9cfdd 100644
--- a/clang/test/CodeGen/X86/avx512-kconstraints-att_inline_asm.c
+++ b/clang/test/CodeGen/X86/avx512-kconstraints-att_inline_asm.c
@@ -41,7 +41,7 @@ __m512i mask_Yk_i64(long long msk, __m512i x, __m512i y){
 }
 
 char k_wise_op_i8(char msk_src1,char msk_src2){
-//CHECK: i8 asm "kandb\09$2, $1, $0", "=k,k,k,~{dirflag},~{fpsr},~{flags}"(i8 
%{{.*}}, i8 %{{.*}})
+//CHECK: <8 x i1> asm "kandb\09$2, $1, $0", 
"=k,k,k,~{dirflag},~{fpsr},~{flags}"(<8 x i1> %{{.*}}, <8 x i1> %{{.*}})
   char msk_dst;
   asm ("kandb\t%2, %1, %0"
: "=k" (msk_dst)
@@ -50,7 +50,7 @@ char k_wise_op_i8(char msk_src1,char msk_src2){
 }
 
 short k_wise_op_i16(short msk_src1, short msk_src2){
-//CHECK: i16 asm "kandw\09$2, $1, $0", 
"=k,k,k,~{dirflag},~{fpsr},~{flags}"(i16 %{{.*}}, i16 %{{.*}})
+//CHECK: <16 x i1> asm "kandw\09$2, $1, $0", 
"=k,k,k,~{dirflag},~{fpsr},~{flags}"(<16 x i1> %{{.*}}, <16 x i1> %{{.*}})
   short msk_dst;
   asm ("kandw\t%2, %1, %0"
: "=k" (msk_dst)
@@ -59,7 +59,7 @@ short k_wise_op_i16(short msk_src1, short msk_src2){
 }
 
 int k_wise_op_i32(int msk_src1, int msk_src2){
-//CHECK: i32 asm "kandd\09$2, $1, $0", 
"=k,k,k,~{dirflag},~{fpsr},~{flags}"(i32 %{{.*}}, i32 %{{.*}})
+//CHECK: <32 x i1> asm "kandd\09$2, $1, $0", 
"=k,k,k,~{dirflag},~{fpsr},~{flags}"(<32 x i1> %{{.*}}, <32 x i1> %{{.*}})
   int msk_dst;
   asm ("kandd\t%2, %1, %0"
: "=k" (msk_dst)
@@ -68,7 +68,7 @@ int k_wise_op_i32(int msk_src1, int msk_src2){
 }
 
 long long k_wise_op_i64(long long msk_src1, long long msk_src2){
-//CHECK: i64 asm "kandq\09$2, $1, $0", 
"=k,k,k,~{dirflag},~{fpsr},~{flags}"(i64 %{{.*}}, i64 %{{.*}})
+//CHECK: <64 x i1> asm "kandq\09$2, $1, $0", 
"=k,k,k,~{dirflag},~{fpsr},~{flags}"(<64 x i1> %{{.*}}, <64 x i1> %{{.*}})
   long long msk_dst;
   asm ("kandq\t%2, %1, %0"
: "=k" (msk_dst)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp 
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 8c4f091c793dcb..fd05b167361bfd 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -57046,17 +57046,17 @@ X86TargetLowering::getRegForInlineAsmConstraint(const 
TargetRegisterInfo *TRI,
   // in the normal allocation?
 case 'k':
   if (Subtarget.hasAVX512()) {
-if (VT == MVT::i1)
+if (VT == MVT::v1i1)
   return std::make_pair(0U, &X86::VK1RegClass);
-if (VT == MVT::i8)
+if (VT == MVT::v8i1)
   return std::make_pair(0U, &X86::VK8RegClass);
-if (VT == MVT::i16)
+if (VT == MVT::v16i1)
   return std::make_pair(0U, &X86::VK16RegClass);
   }
   if (Subtarget.hasBWI()) {
-if (VT == MVT::i32)
+if (VT == MVT::v32i1)
   return std::make_pair(0U, &X86::VK32RegClass);
-if (VT == MVT::i64)
+if (VT == MVT::v64i1)
  

[llvm] [clang] [X86][WIP] Use vXi1 for `k` constraint in inline asm (PR #77733)

[Phoebe Wang via cfe-commits]

https://github.com/phoebewang updated 
https://github.com/llvm/llvm-project/pull/77733

>From 72fa88d9e2277a8df60cf39d8cc96aad984dc2e9 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Thu, 11 Jan 2024 14:59:51 +0800
Subject: [PATCH 1/2] [X86][WIP] Use vXi1 for `k` constraint in inline asm

Fixes #77172
---
 clang/lib/CodeGen/CGStmt.cpp  |  4 +--
 clang/lib/CodeGen/Targets/X86.cpp |  5 
 .../X86/avx512-kconstraints-att_inline_asm.c  |  8 ++---
 llvm/lib/Target/X86/X86ISelLowering.cpp   | 30 +--
 4 files changed, 26 insertions(+), 21 deletions(-)

diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
index b89017de0bcf14..beff0ad9da2709 100644
--- a/clang/lib/CodeGen/CGStmt.cpp
+++ b/clang/lib/CodeGen/CGStmt.cpp
@@ -2399,9 +2399,9 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
 Tmp = Builder.CreatePtrToInt(
 Tmp, llvm::IntegerType::get(CTX, (unsigned)TmpSize));
 Tmp = Builder.CreateTrunc(Tmp, TruncTy);
-  } else if (TruncTy->isIntegerTy()) {
+  } else if (Tmp->getType()->isIntegerTy() && TruncTy->isIntegerTy()) {
 Tmp = Builder.CreateZExtOrTrunc(Tmp, TruncTy);
-  } else if (TruncTy->isVectorTy()) {
+  } else if (Tmp->getType()->isVectorTy() || TruncTy->isVectorTy()) {
 Tmp = Builder.CreateBitCast(Tmp, TruncTy);
   }
 }
diff --git a/clang/lib/CodeGen/Targets/X86.cpp 
b/clang/lib/CodeGen/Targets/X86.cpp
index d053f41ab168f5..542377ec08e964 100644
--- a/clang/lib/CodeGen/Targets/X86.cpp
+++ b/clang/lib/CodeGen/Targets/X86.cpp
@@ -40,6 +40,11 @@ static llvm::Type* 
X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
 return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
   }
 
+  if (Constraint == "k") {
+llvm::Type* Int1Ty = llvm::Type::getInt1Ty(CGF.getLLVMContext());
+return llvm::FixedVectorType::get(Int1Ty, Ty->getScalarSizeInBits());
+  }
+
   // No operation needed
   return Ty;
 }
diff --git a/clang/test/CodeGen/X86/avx512-kconstraints-att_inline_asm.c 
b/clang/test/CodeGen/X86/avx512-kconstraints-att_inline_asm.c
index b4939bfc2ca831..74b6719bf9cfdd 100644
--- a/clang/test/CodeGen/X86/avx512-kconstraints-att_inline_asm.c
+++ b/clang/test/CodeGen/X86/avx512-kconstraints-att_inline_asm.c
@@ -41,7 +41,7 @@ __m512i mask_Yk_i64(long long msk, __m512i x, __m512i y){
 }
 
 char k_wise_op_i8(char msk_src1,char msk_src2){
-//CHECK: i8 asm "kandb\09$2, $1, $0", "=k,k,k,~{dirflag},~{fpsr},~{flags}"(i8 
%{{.*}}, i8 %{{.*}})
+//CHECK: <8 x i1> asm "kandb\09$2, $1, $0", 
"=k,k,k,~{dirflag},~{fpsr},~{flags}"(<8 x i1> %{{.*}}, <8 x i1> %{{.*}})
   char msk_dst;
   asm ("kandb\t%2, %1, %0"
: "=k" (msk_dst)
@@ -50,7 +50,7 @@ char k_wise_op_i8(char msk_src1,char msk_src2){
 }
 
 short k_wise_op_i16(short msk_src1, short msk_src2){
-//CHECK: i16 asm "kandw\09$2, $1, $0", 
"=k,k,k,~{dirflag},~{fpsr},~{flags}"(i16 %{{.*}}, i16 %{{.*}})
+//CHECK: <16 x i1> asm "kandw\09$2, $1, $0", 
"=k,k,k,~{dirflag},~{fpsr},~{flags}"(<16 x i1> %{{.*}}, <16 x i1> %{{.*}})
   short msk_dst;
   asm ("kandw\t%2, %1, %0"
: "=k" (msk_dst)
@@ -59,7 +59,7 @@ short k_wise_op_i16(short msk_src1, short msk_src2){
 }
 
 int k_wise_op_i32(int msk_src1, int msk_src2){
-//CHECK: i32 asm "kandd\09$2, $1, $0", 
"=k,k,k,~{dirflag},~{fpsr},~{flags}"(i32 %{{.*}}, i32 %{{.*}})
+//CHECK: <32 x i1> asm "kandd\09$2, $1, $0", 
"=k,k,k,~{dirflag},~{fpsr},~{flags}"(<32 x i1> %{{.*}}, <32 x i1> %{{.*}})
   int msk_dst;
   asm ("kandd\t%2, %1, %0"
: "=k" (msk_dst)
@@ -68,7 +68,7 @@ int k_wise_op_i32(int msk_src1, int msk_src2){
 }
 
 long long k_wise_op_i64(long long msk_src1, long long msk_src2){
-//CHECK: i64 asm "kandq\09$2, $1, $0", 
"=k,k,k,~{dirflag},~{fpsr},~{flags}"(i64 %{{.*}}, i64 %{{.*}})
+//CHECK: <64 x i1> asm "kandq\09$2, $1, $0", 
"=k,k,k,~{dirflag},~{fpsr},~{flags}"(<64 x i1> %{{.*}}, <64 x i1> %{{.*}})
   long long msk_dst;
   asm ("kandq\t%2, %1, %0"
: "=k" (msk_dst)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp 
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 8c4f091c793dcb..fd05b167361bfd 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -57046,17 +57046,17 @@ X86TargetLowering::getRegForInlineAsmConstraint(const 
TargetRegisterInfo *TRI,
   // in the normal allocation?
 case 'k':
   if (Subtarget.hasAVX512()) {
-if (VT == MVT::i1)
+if (VT == MVT::v1i1)
   return std::make_pair(0U, &X86::VK1RegClass);
-if (VT == MVT::i8)
+if (VT == MVT::v8i1)
   return std::make_pair(0U, &X86::VK8RegClass);
-if (VT == MVT::i16)
+if (VT == MVT::v16i1)
   return std::make_pair(0U, &X86::VK16RegClass);
   }
   if (Subtarget.hasBWI()) {
-if (VT == MVT::i32)
+if (VT == MVT::v32i1)
   return std::make_pair(0U, &X86::VK32RegClass);
-if (VT == MVT::i64)
+if (VT == MVT::v64i1)
   retur