[PATCH] D117112: [AArch64] Support for Ampere1 core

2022-04-27 Thread Philipp Tomsich via Phabricator via cfe-commits 
philipp.tomsich updated this revision to Diff 425609.
philipp.tomsich added a comment.
Herald added a project: All.

Update to reflect review results.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117112/new/

https://reviews.llvm.org/D117112

Files:
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
  llvm/lib/Target/AArch64/AArch64SchedPredAmpere.td
  llvm/lib/Target/AArch64/AArch64SchedPredicates.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/neon-dot-product.ll
  llvm/test/CodeGen/AArch64/remat.ll
  llvm/test/MC/AArch64/armv8.2a-dotprod.s
  llvm/test/MC/AArch64/armv8.3a-rcpc.s
  llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -1192,6 +1192,16 @@
  AArch64::AEK_SVE2 | AArch64::AEK_SVE2BITPERM |
  AArch64::AEK_BF16 | AArch64::AEK_I8MM,
  "8.5-A"),
+ARMCPUTestParams("ampere1", "armv8.6-a", "crypto-neon-fp-armv8",
+ AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+ AArch64::AEK_FP | AArch64::AEK_SIMD |
+ AArch64::AEK_FP16 | AArch64::AEK_RAS |
+ AArch64::AEK_LSE |
+ AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
+ AArch64::AEK_RDM | AArch64::AEK_MTE |
+ AArch64::AEK_SSBS | AArch64::AEK_SB |
+ AArch64::AEK_BF16 | AArch64::AEK_I8MM,
+ "8.6-A"),
 ARMCPUTestParams(
 "neoverse-512tvb", "armv8.4-a", "crypto-neon-fp-armv8",
 AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
Index: llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
===
--- llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
+++ llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
@@ -12,6 +12,7 @@
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-e1 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n1 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n2 --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1 --disassemble < %s | FileCheck %s
 
 # CHECK: ldaprb w0, [x0]
 # CHECK: ldaprh w0, [x0]
Index: llvm/test/MC/AArch64/armv8.3a-rcpc.s
===
--- llvm/test/MC/AArch64/armv8.3a-rcpc.s
+++ llvm/test/MC/AArch64/armv8.3a-rcpc.s
@@ -6,6 +6,7 @@
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-e1 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n1 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n2 < %s 2>&1 | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=ampere1 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a -mattr=+rcpc < %s 2>&1 | FileCheck %s
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
Index: llvm/test/MC/AArch64/armv8.2a-dotprod.s
===
--- llvm/test/MC/AArch64/armv8.2a-dotprod.s
+++ llvm/test/MC/AArch64/armv8.2a-dotprod.s
@@ -13,6 +13,7 @@
 // RUN: llvm-mc -triple aarch64 -mcpu=tsv110 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch64 -mcpu=cortex-r82 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch64 -mattr=+v8r -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
+// RUN: llvm-mc -triple aarch64 -mcpu=ampere1 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
 
 // RUN: not llvm-mc -triple aarch64 -mattr=+v8.2a -show-encoding < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
@@ -36,6 +37,8 @@
 // RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
 // RUN: not llvm-mc -triple aarch64 -mcpu=neoverse-n2 -mattr=-dotprod -show-encoding < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
+// RUN: not llvm-mc -triple aarch64 -mcpu=ampere1 -mattr=-dotprod -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
 
 udot v0.2s, v1.8b, v2.

[PATCH] D117112: [AArch64] Support for Ampere1 core

2022-04-28 Thread Philipp Tomsich via Phabricator via cfe-commits 
philipp.tomsich updated this revision to Diff 425726.
philipp.tomsich added a comment.

- additional tab -> space conversion (hopefully, I have emacs configured 
correctly now)
- added SBSS and MTE to the SubtargetFeatures
- inserted AMpere1 in the subtarget enum in alphabetical order


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117112/new/

https://reviews.llvm.org/D117112

Files:
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
  llvm/lib/Target/AArch64/AArch64SchedPredAmpere.td
  llvm/lib/Target/AArch64/AArch64SchedPredicates.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/neon-dot-product.ll
  llvm/test/CodeGen/AArch64/remat.ll
  llvm/test/MC/AArch64/armv8.2a-dotprod.s
  llvm/test/MC/AArch64/armv8.3a-rcpc.s
  llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -1192,6 +1192,16 @@
  AArch64::AEK_SVE2 | AArch64::AEK_SVE2BITPERM |
  AArch64::AEK_BF16 | AArch64::AEK_I8MM,
  "8.5-A"),
+ARMCPUTestParams("ampere1", "armv8.6-a", "crypto-neon-fp-armv8",
+ AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+ AArch64::AEK_FP | AArch64::AEK_SIMD |
+ AArch64::AEK_FP16 | AArch64::AEK_RAS |
+ AArch64::AEK_LSE |
+ AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
+ AArch64::AEK_RDM | AArch64::AEK_MTE |
+ AArch64::AEK_SSBS | AArch64::AEK_SB |
+ AArch64::AEK_BF16 | AArch64::AEK_I8MM,
+ "8.6-A"),
 ARMCPUTestParams(
 "neoverse-512tvb", "armv8.4-a", "crypto-neon-fp-armv8",
 AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
Index: llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
===
--- llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
+++ llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
@@ -12,6 +12,7 @@
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-e1 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n1 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n2 --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1 --disassemble < %s | FileCheck %s
 
 # CHECK: ldaprb w0, [x0]
 # CHECK: ldaprh w0, [x0]
Index: llvm/test/MC/AArch64/armv8.3a-rcpc.s
===
--- llvm/test/MC/AArch64/armv8.3a-rcpc.s
+++ llvm/test/MC/AArch64/armv8.3a-rcpc.s
@@ -6,6 +6,7 @@
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-e1 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n1 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n2 < %s 2>&1 | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=ampere1 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a -mattr=+rcpc < %s 2>&1 | FileCheck %s
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
Index: llvm/test/MC/AArch64/armv8.2a-dotprod.s
===
--- llvm/test/MC/AArch64/armv8.2a-dotprod.s
+++ llvm/test/MC/AArch64/armv8.2a-dotprod.s
@@ -13,6 +13,7 @@
 // RUN: llvm-mc -triple aarch64 -mcpu=tsv110 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch64 -mcpu=cortex-r82 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch64 -mattr=+v8r -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
+// RUN: llvm-mc -triple aarch64 -mcpu=ampere1 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
 
 // RUN: not llvm-mc -triple aarch64 -mattr=+v8.2a -show-encoding < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
@@ -36,6 +37,8 @@
 // RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
 // RUN: not llvm-mc -triple aarch64 -mcpu=neoverse-n2 -mattr=-dotprod -show-encoding < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
+// RUN: not llvm-mc -triple aarch64 -mcpu

[PATCH] D117112: [AArch64] Support for Ampere1 core

2022-05-02 Thread Philipp Tomsich via Phabricator via cfe-commits 
philipp.tomsich updated this revision to Diff 426541.
philipp.tomsich added a comment.

Adds two fixes for issues uncovered by the CI:

- The update of NumAArch64CPUArchs had been lost in a "rebase gone wrong" 
(i.e., another target was added and the previously increased-by-1 value now was 
the already present upstream).  This adjusts the value of NumAArch64CPUArchs to 
again account for the addition of an extra target.
- Adjusts the ARMCPUTestParams for ampere1 to reflect that ARMv8.6 encodes the 
crypto extensions differently than lower architecture levels.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117112/new/

https://reviews.llvm.org/D117112

Files:
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
  llvm/lib/Target/AArch64/AArch64SchedPredAmpere.td
  llvm/lib/Target/AArch64/AArch64SchedPredicates.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/neon-dot-product.ll
  llvm/test/CodeGen/AArch64/remat.ll
  llvm/test/MC/AArch64/armv8.2a-dotprod.s
  llvm/test/MC/AArch64/armv8.3a-rcpc.s
  llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -1192,6 +1192,14 @@
  AArch64::AEK_SVE2 | AArch64::AEK_SVE2BITPERM |
  AArch64::AEK_BF16 | AArch64::AEK_I8MM,
  "8.5-A"),
+ARMCPUTestParams("ampere1", "armv8.6-a", "crypto-neon-fp-armv8",
+ AArch64::AEK_CRC  | AArch64::AEK_FP   | AArch64::AEK_FP16   |
+ AArch64::AEK_SIMD | AArch64::AEK_RAS  | AArch64::AEK_LSE |
+ AArch64::AEK_RDM  | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+ AArch64::AEK_SM4  | AArch64::AEK_SHA3 | AArch64::AEK_BF16|
+ AArch64::AEK_SHA2 | AArch64::AEK_AES  | AArch64::AEK_I8MM|
+ AArch64::AEK_MTE  | AArch64::AEK_SSBS | AArch64::AEK_SB,
+ "8.6-A"),
 ARMCPUTestParams(
 "neoverse-512tvb", "armv8.4-a", "crypto-neon-fp-armv8",
 AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
@@ -1253,7 +1261,7 @@
  AArch64::AEK_LSE | AArch64::AEK_RDM,
  "8.2-A")));
 
-static constexpr unsigned NumAArch64CPUArchs = 53;
+static constexpr unsigned NumAArch64CPUArchs = 54;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
===
--- llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
+++ llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
@@ -12,6 +12,7 @@
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-e1 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n1 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n2 --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1 --disassemble < %s | FileCheck %s
 
 # CHECK: ldaprb w0, [x0]
 # CHECK: ldaprh w0, [x0]
Index: llvm/test/MC/AArch64/armv8.3a-rcpc.s
===
--- llvm/test/MC/AArch64/armv8.3a-rcpc.s
+++ llvm/test/MC/AArch64/armv8.3a-rcpc.s
@@ -6,6 +6,7 @@
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-e1 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n1 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n2 < %s 2>&1 | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=ampere1 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a -mattr=+rcpc < %s 2>&1 | FileCheck %s
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
Index: llvm/test/MC/AArch64/armv8.2a-dotprod.s
===
--- llvm/test/MC/AArch64/armv8.2a-dotprod.s
+++ llvm/test/MC/AArch64/armv8.2a-dotprod.s
@@ -13,6 +13,7 @@
 // RUN: llvm-mc -triple aarch64 -mcpu=tsv110 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch64 -mcpu=cortex-r82 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch6

[PATCH] D117112: [AArch64] Support for Ampere1 core

2022-05-03 Thread Philipp Tomsich via Phabricator via cfe-commits 
philipp.tomsich updated this revision to Diff 426622.
philipp.tomsich marked 4 inline comments as done.
philipp.tomsich added a comment.

Rebased to main.
The earlier base-regression was a precommitted test-case that caused 
SimpleLoopUnswitch tests (not related to these changes) to fail.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117112/new/

https://reviews.llvm.org/D117112

Files:
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
  llvm/lib/Target/AArch64/AArch64SchedPredAmpere.td
  llvm/lib/Target/AArch64/AArch64SchedPredicates.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/neon-dot-product.ll
  llvm/test/CodeGen/AArch64/remat.ll
  llvm/test/MC/AArch64/armv8.2a-dotprod.s
  llvm/test/MC/AArch64/armv8.3a-rcpc.s
  llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -1195,6 +1195,14 @@
  AArch64::AEK_SVE2 | AArch64::AEK_SVE2BITPERM |
  AArch64::AEK_BF16 | AArch64::AEK_I8MM,
  "8.5-A"),
+ARMCPUTestParams("ampere1", "armv8.6-a", "crypto-neon-fp-armv8",
+ AArch64::AEK_CRC  | AArch64::AEK_FP   | AArch64::AEK_FP16   |
+ AArch64::AEK_SIMD | AArch64::AEK_RAS  | AArch64::AEK_LSE |
+ AArch64::AEK_RDM  | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+ AArch64::AEK_SM4  | AArch64::AEK_SHA3 | AArch64::AEK_BF16|
+ AArch64::AEK_SHA2 | AArch64::AEK_AES  | AArch64::AEK_I8MM|
+ AArch64::AEK_MTE  | AArch64::AEK_SSBS | AArch64::AEK_SB,
+ "8.6-A"),
 ARMCPUTestParams(
 "neoverse-512tvb", "armv8.4-a", "crypto-neon-fp-armv8",
 AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
@@ -1256,7 +1264,7 @@
  AArch64::AEK_LSE | AArch64::AEK_RDM,
  "8.2-A")));
 
-static constexpr unsigned NumAArch64CPUArchs = 53;
+static constexpr unsigned NumAArch64CPUArchs = 54;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
===
--- llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
+++ llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
@@ -12,6 +12,7 @@
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-e1 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n1 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n2 --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1 --disassemble < %s | FileCheck %s
 
 # CHECK: ldaprb w0, [x0]
 # CHECK: ldaprh w0, [x0]
Index: llvm/test/MC/AArch64/armv8.3a-rcpc.s
===
--- llvm/test/MC/AArch64/armv8.3a-rcpc.s
+++ llvm/test/MC/AArch64/armv8.3a-rcpc.s
@@ -6,6 +6,7 @@
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-e1 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n1 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n2 < %s 2>&1 | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=ampere1 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a -mattr=+rcpc < %s 2>&1 | FileCheck %s
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
Index: llvm/test/MC/AArch64/armv8.2a-dotprod.s
===
--- llvm/test/MC/AArch64/armv8.2a-dotprod.s
+++ llvm/test/MC/AArch64/armv8.2a-dotprod.s
@@ -13,6 +13,7 @@
 // RUN: llvm-mc -triple aarch64 -mcpu=tsv110 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch64 -mcpu=cortex-r82 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch64 -mattr=+v8r -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
+// RUN: llvm-mc -triple aarch64 -mcpu=ampere1 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
 
 // RUN: not llvm-mc -triple aarch64 -mattr=+v8.2a -show-encoding < %s 2> %t
 // RUN:

[PATCH] D142439: Fix C++11 warnings in RangeSetTest.cpp

2023-01-24 Thread Philipp Tomsich via Phabricator via cfe-commits 
philipp.tomsich created this revision.
Herald added a subscriber: steakhal.
Herald added a project: All.
philipp.tomsich requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

This change fixes the following warnings:

 llvm/clang/unittests/StaticAnalyzer/RangeSetTest.cpp:727:55: warning: ISO 
C++11 requires at least one argument for the "..." in a variadic macro
   727 | TYPED_TEST_SUITE(RangeSetCastToNoopTest, NoopCastTypes);
 |   ^
 llvm/clang/unittests/StaticAnalyzer/RangeSetTest.cpp:728:65: warning: ISO 
C++11 requires at least one argument for the "..." in a variadic macro
   728 | TYPED_TEST_SUITE(RangeSetCastToPromotionTest, PromotionCastTypes);
 | ^
 llvm/clang/unittests/StaticAnalyzer/RangeSetTest.cpp:729:67: warning: ISO 
C++11 requires at least one argument for the "..." in a variadic macro
   729 | TYPED_TEST_SUITE(RangeSetCastToTruncationTest, 
TruncationCastTypes);
 |   ^
 llvm/clang/unittests/StaticAnalyzer/RangeSetTest.cpp:730:67: warning: ISO 
C++11 requires at least one argument for the "..." in a variadic macro
   730 | TYPED_TEST_SUITE(RangeSetCastToConversionTest, 
ConversionCastTypes);
 |   ^
 llvm/clang/unittests/StaticAnalyzer/RangeSetTest.cpp:732:46: warning: ISO 
C++11 requires at least one argument for the "..." in a variadic macro
   732 |  PromotionConversionCastTypes);
 |  ^
 llvm/clang/unittests/StaticAnalyzer/RangeSetTest.cpp:734:47: warning: ISO 
C++11 requires at least one argument for the "..." in a variadic macro
   734 |  TruncationConversionCastTypes);
 |   ^


Repository:
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https://reviews.llvm.org/D142439

Files:
  clang/unittests/StaticAnalyzer/RangeSetTest.cpp


Index: clang/unittests/StaticAnalyzer/RangeSetTest.cpp
===
--- clang/unittests/StaticAnalyzer/RangeSetTest.cpp
+++ clang/unittests/StaticAnalyzer/RangeSetTest.cpp
@@ -724,14 +724,14 @@
  CastType, CastType,
  CastType, CastType>;
 
-TYPED_TEST_SUITE(RangeSetCastToNoopTest, NoopCastTypes);
-TYPED_TEST_SUITE(RangeSetCastToPromotionTest, PromotionCastTypes);
-TYPED_TEST_SUITE(RangeSetCastToTruncationTest, TruncationCastTypes);
-TYPED_TEST_SUITE(RangeSetCastToConversionTest, ConversionCastTypes);
+TYPED_TEST_SUITE(RangeSetCastToNoopTest, NoopCastTypes, );
+TYPED_TEST_SUITE(RangeSetCastToPromotionTest, PromotionCastTypes, );
+TYPED_TEST_SUITE(RangeSetCastToTruncationTest, TruncationCastTypes, );
+TYPED_TEST_SUITE(RangeSetCastToConversionTest, ConversionCastTypes, );
 TYPED_TEST_SUITE(RangeSetCastToPromotionConversionTest,
- PromotionConversionCastTypes);
+ PromotionConversionCastTypes, );
 TYPED_TEST_SUITE(RangeSetCastToTruncationConversionTest,
- TruncationConversionCastTypes);
+ TruncationConversionCastTypes, );
 
 TYPED_TEST(RangeSetCastToNoopTest, RangeSetCastToNoopTest) {
   // Just to reduce the verbosity.


Index: clang/unittests/StaticAnalyzer/RangeSetTest.cpp
===
--- clang/unittests/StaticAnalyzer/RangeSetTest.cpp
+++ clang/unittests/StaticAnalyzer/RangeSetTest.cpp
@@ -724,14 +724,14 @@
  CastType, CastType,
  CastType, CastType>;
 
-TYPED_TEST_SUITE(RangeSetCastToNoopTest, NoopCastTypes);
-TYPED_TEST_SUITE(RangeSetCastToPromotionTest, PromotionCastTypes);
-TYPED_TEST_SUITE(RangeSetCastToTruncationTest, TruncationCastTypes);
-TYPED_TEST_SUITE(RangeSetCastToConversionTest, ConversionCastTypes);
+TYPED_TEST_SUITE(RangeSetCastToNoopTest, NoopCastTypes, );
+TYPED_TEST_SUITE(RangeSetCastToPromotionTest, PromotionCastTypes, );
+TYPED_TEST_SUITE(RangeSetCastToTruncationTest, TruncationCastTypes, );
+TYPED_TEST_SUITE(RangeSetCastToConversionTest, ConversionCastTypes, );
 TYPED_TEST_SUITE(RangeSetCastToPromotionConversionTest,
- PromotionConversionCastTypes);
+ PromotionConversionCastTypes, );
 TYPED_TEST_SUITE(RangeSetCastToTruncationConversionTest,
- TruncationConversionCastTypes);
+ TruncationConversionCastTypes, );
 
 TYPED_TEST(RangeSetCastToNoopTest, RangeSetCastToNoopTest) {
   // Just to reduce the verbosity.
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[PATCH] D142410: [AArch64] ARMv8.5-A implies both FEAT_SB and FEAT_SSBS

2023-01-24 Thread Philipp Tomsich via Phabricator via cfe-commits 
philipp.tomsich added a comment.

When looking at "ARM DDI 0487G.a", on page A2-68 under the heading "Additional 
functionality added to Armv8.0 in later releases" in the definition-list item 
"FEAT_SSBS, Speculative Store Bypass Safe":

> This feature is OPTIONAL in Armv8.0 implementations and mandatory in Armv8.5 
> implementations.

There is a to FEAT_SBSS in the backlink in "A2.8 The Armv8.5 architecture 
extension", under the subsection "A2.8.3 Features added to earlier extensions", 
in the bullet-list labeled "The features that have been added to earlier 
architectural extensions are:"


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[PATCH] D142396: [AArch64] Add the Ampere1A core

2023-01-24 Thread Philipp Tomsich via Phabricator via cfe-commits 
philipp.tomsich updated this revision to Diff 491738.
philipp.tomsich added a comment.

- Split off new (Ampere1A-specific) fusion case
- Updated the Ampere1A SubtargetFeature list to include (hopefully) all features


Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/TargetParser/AArch64TargetParser.h
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/TargetParser/Host.cpp
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/neon-dot-product.ll
  llvm/test/CodeGen/AArch64/remat.ll
  llvm/test/MC/AArch64/armv8.2a-dotprod.s
  llvm/test/MC/AArch64/armv8.3a-rcpc.s
  llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
  llvm/unittests/TargetParser/Host.cpp
  llvm/unittests/TargetParser/TargetParserTest.cpp

Index: llvm/unittests/TargetParser/TargetParserTest.cpp
===
--- llvm/unittests/TargetParser/TargetParserTest.cpp
+++ llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1341,6 +1341,15 @@
  AArch64::AEK_AES  | AArch64::AEK_I8MM | AArch64::AEK_SSBS |
  AArch64::AEK_SB   | AArch64::AEK_RAND,
  "8.6-A"),
+ARMCPUTestParams("ampere1a", "armv8.6-a", "crypto-neon-fp-armv8",
+ AArch64::AEK_CRC  | AArch64::AEK_FP   | AArch64::AEK_FP16   |
+ AArch64::AEK_SIMD | AArch64::AEK_RAS  | AArch64::AEK_LSE |
+ AArch64::AEK_RDM  | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+ AArch64::AEK_SM4  | AArch64::AEK_SHA3 | AArch64::AEK_BF16|
+ AArch64::AEK_SHA2 | AArch64::AEK_AES  | AArch64::AEK_I8MM|
+ AArch64::AEK_SSBS | AArch64::AEK_SB   | AArch64::AEK_RAND|
+ AArch64::AEK_MTE,
+ "8.6-A"),
 ARMCPUTestParams(
 "neoverse-512tvb", "armv8.4-a", "crypto-neon-fp-armv8",
 AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
@@ -1403,7 +1412,7 @@
  "8.2-A")));
 
 // Note: number of CPUs includes aliases.
-static constexpr unsigned NumAArch64CPUArchs = 61;
+static constexpr unsigned NumAArch64CPUArchs = 62;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/unittests/TargetParser/Host.cpp
===
--- llvm/unittests/TargetParser/Host.cpp
+++ llvm/unittests/TargetParser/Host.cpp
@@ -117,6 +117,9 @@
   EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
   "CPU part: 0xac3"),
 "ampere1");
+  EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
+  "CPU part: 0xac4"),
+"ampere1a");
 
   // MSM8992/4 weirdness
   StringRef MSM8992ProcCpuInfo = R"(
Index: llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
===
--- llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
+++ llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
@@ -13,6 +13,7 @@
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n1 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n2 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1 --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1a --disassemble < %s | FileCheck %s
 
 # CHECK: ldaprb w0, [x0]
 # CHECK: ldaprh w0, [x0]
Index: llvm/test/MC/AArch64/armv8.3a-rcpc.s
===
--- llvm/test/MC/AArch64/armv8.3a-rcpc.s
+++ llvm/test/MC/AArch64/armv8.3a-rcpc.s
@@ -7,6 +7,7 @@
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n1 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n2 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=ampere1 < %s 2>&1 | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=ampere1a < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a -mattr=+rcpc < %s 2>&1 | FileCheck %s
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
Index: llvm/test/MC/AArch64/armv8.2a-dotprod.s
===
--- llvm/test/MC/AArch64/armv8.2a-dotprod.s
+++ llvm/test/MC/AArch64/armv8.2a-dotprod.s
@@ -14,6 +14,

[PATCH] D142396: [AArch64] Add the Ampere1A core

2023-01-24 Thread Philipp Tomsich via Phabricator via cfe-commits 
philipp.tomsich added inline comments.



Comment at: llvm/include/llvm/TargetParser/AArch64TargetParser.h:492
+{"ampere1a", ARMV8_6A,
+ (AArch64::AEK_FP16 | AArch64::AEK_RAND | AArch64::AEK_SM4 |
+  AArch64::AEK_SHA3 | AArch64::AEK_SHA2 | AArch64::AEK_AES |

dmgreen wrote:
> Just to check, you didn't mention SM4 in the commit message or the gcc patch 
> from https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605942.html. 
> Should that be included here?
I'll have to review GCC I guess.
Small omissions are still possible, as we didn't get a /proc/cpuinfo to test 
-mcpu=native against -mcpu=ampere1a yet...

The manual states "The second-generation core adds support for the Memory 
Tagging Extension and SM3/SM4 cryptography instructions."  So yes, it should be 
included.


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[PATCH] D142396: [AArch64] Add the Ampere1A core

2023-01-24 Thread Philipp Tomsich via Phabricator via cfe-commits 
philipp.tomsich updated this revision to Diff 491840.
philipp.tomsich added a comment.

- untabify on some tabs that slipped in


Repository:
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Files:
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/TargetParser/AArch64TargetParser.h
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/TargetParser/Host.cpp
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/neon-dot-product.ll
  llvm/test/CodeGen/AArch64/remat.ll
  llvm/test/MC/AArch64/armv8.2a-dotprod.s
  llvm/test/MC/AArch64/armv8.3a-rcpc.s
  llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
  llvm/unittests/TargetParser/Host.cpp
  llvm/unittests/TargetParser/TargetParserTest.cpp

Index: llvm/unittests/TargetParser/TargetParserTest.cpp
===
--- llvm/unittests/TargetParser/TargetParserTest.cpp
+++ llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1341,6 +1341,15 @@
  AArch64::AEK_AES  | AArch64::AEK_I8MM | AArch64::AEK_SSBS |
  AArch64::AEK_SB   | AArch64::AEK_RAND,
  "8.6-A"),
+ARMCPUTestParams("ampere1a", "armv8.6-a", "crypto-neon-fp-armv8",
+ AArch64::AEK_CRC  | AArch64::AEK_FP   | AArch64::AEK_FP16   |
+ AArch64::AEK_SIMD | AArch64::AEK_RAS  | AArch64::AEK_LSE |
+ AArch64::AEK_RDM  | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+ AArch64::AEK_SM4  | AArch64::AEK_SHA3 | AArch64::AEK_BF16|
+ AArch64::AEK_SHA2 | AArch64::AEK_AES  | AArch64::AEK_I8MM|
+ AArch64::AEK_SSBS | AArch64::AEK_SB   | AArch64::AEK_RAND|
+ AArch64::AEK_MTE,
+ "8.6-A"),
 ARMCPUTestParams(
 "neoverse-512tvb", "armv8.4-a", "crypto-neon-fp-armv8",
 AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
@@ -1403,7 +1412,7 @@
  "8.2-A")));
 
 // Note: number of CPUs includes aliases.
-static constexpr unsigned NumAArch64CPUArchs = 61;
+static constexpr unsigned NumAArch64CPUArchs = 62;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/unittests/TargetParser/Host.cpp
===
--- llvm/unittests/TargetParser/Host.cpp
+++ llvm/unittests/TargetParser/Host.cpp
@@ -117,6 +117,9 @@
   EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
   "CPU part: 0xac3"),
 "ampere1");
+  EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
+  "CPU part: 0xac4"),
+"ampere1a");
 
   // MSM8992/4 weirdness
   StringRef MSM8992ProcCpuInfo = R"(
Index: llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
===
--- llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
+++ llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
@@ -13,6 +13,7 @@
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n1 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n2 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1 --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1a --disassemble < %s | FileCheck %s
 
 # CHECK: ldaprb w0, [x0]
 # CHECK: ldaprh w0, [x0]
Index: llvm/test/MC/AArch64/armv8.3a-rcpc.s
===
--- llvm/test/MC/AArch64/armv8.3a-rcpc.s
+++ llvm/test/MC/AArch64/armv8.3a-rcpc.s
@@ -7,6 +7,7 @@
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n1 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n2 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=ampere1 < %s 2>&1 | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=ampere1a < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a -mattr=+rcpc < %s 2>&1 | FileCheck %s
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
Index: llvm/test/MC/AArch64/armv8.2a-dotprod.s
===
--- llvm/test/MC/AArch64/armv8.2a-dotprod.s
+++ llvm/test/MC/AArch64/armv8.2a-dotprod.s
@@ -14,6 +14,7 @@
 // RUN: llvm-mc -triple aarch64 -mcpu=cortex-r82 -show-encoding < %s | FileCheck %s

[PATCH] D142439: Fix C++11 warnings in RangeSetTest.cpp

2023-01-24 Thread Philipp Tomsich via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG25b03ae78ff3: Fix C++11 warnings in RangeSetTest.cpp 
(authored by philipp.tomsich).

Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D142439

Files:
  clang/unittests/StaticAnalyzer/RangeSetTest.cpp


Index: clang/unittests/StaticAnalyzer/RangeSetTest.cpp
===
--- clang/unittests/StaticAnalyzer/RangeSetTest.cpp
+++ clang/unittests/StaticAnalyzer/RangeSetTest.cpp
@@ -724,14 +724,14 @@
  CastType, CastType,
  CastType, CastType>;
 
-TYPED_TEST_SUITE(RangeSetCastToNoopTest, NoopCastTypes);
-TYPED_TEST_SUITE(RangeSetCastToPromotionTest, PromotionCastTypes);
-TYPED_TEST_SUITE(RangeSetCastToTruncationTest, TruncationCastTypes);
-TYPED_TEST_SUITE(RangeSetCastToConversionTest, ConversionCastTypes);
+TYPED_TEST_SUITE(RangeSetCastToNoopTest, NoopCastTypes, );
+TYPED_TEST_SUITE(RangeSetCastToPromotionTest, PromotionCastTypes, );
+TYPED_TEST_SUITE(RangeSetCastToTruncationTest, TruncationCastTypes, );
+TYPED_TEST_SUITE(RangeSetCastToConversionTest, ConversionCastTypes, );
 TYPED_TEST_SUITE(RangeSetCastToPromotionConversionTest,
- PromotionConversionCastTypes);
+ PromotionConversionCastTypes, );
 TYPED_TEST_SUITE(RangeSetCastToTruncationConversionTest,
- TruncationConversionCastTypes);
+ TruncationConversionCastTypes, );
 
 TYPED_TEST(RangeSetCastToNoopTest, RangeSetCastToNoopTest) {
   // Just to reduce the verbosity.


Index: clang/unittests/StaticAnalyzer/RangeSetTest.cpp
===
--- clang/unittests/StaticAnalyzer/RangeSetTest.cpp
+++ clang/unittests/StaticAnalyzer/RangeSetTest.cpp
@@ -724,14 +724,14 @@
  CastType, CastType,
  CastType, CastType>;
 
-TYPED_TEST_SUITE(RangeSetCastToNoopTest, NoopCastTypes);
-TYPED_TEST_SUITE(RangeSetCastToPromotionTest, PromotionCastTypes);
-TYPED_TEST_SUITE(RangeSetCastToTruncationTest, TruncationCastTypes);
-TYPED_TEST_SUITE(RangeSetCastToConversionTest, ConversionCastTypes);
+TYPED_TEST_SUITE(RangeSetCastToNoopTest, NoopCastTypes, );
+TYPED_TEST_SUITE(RangeSetCastToPromotionTest, PromotionCastTypes, );
+TYPED_TEST_SUITE(RangeSetCastToTruncationTest, TruncationCastTypes, );
+TYPED_TEST_SUITE(RangeSetCastToConversionTest, ConversionCastTypes, );
 TYPED_TEST_SUITE(RangeSetCastToPromotionConversionTest,
- PromotionConversionCastTypes);
+ PromotionConversionCastTypes, );
 TYPED_TEST_SUITE(RangeSetCastToTruncationConversionTest,
- TruncationConversionCastTypes);
+ TruncationConversionCastTypes, );
 
 TYPED_TEST(RangeSetCastToNoopTest, RangeSetCastToNoopTest) {
   // Just to reduce the verbosity.
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[PATCH] D142396: [AArch64] Add the Ampere1A core

2023-01-24 Thread Philipp Tomsich via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGfb0af89193a9: [AArch64] Add the Ampere1A core (authored by 
philipp.tomsich).

Changed prior to commit:
  https://reviews.llvm.org/D142396?vs=491840&id=491900#toc

Repository:
  rG LLVM Github Monorepo

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Files:
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/TargetParser/AArch64TargetParser.h
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/TargetParser/Host.cpp
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/neon-dot-product.ll
  llvm/test/CodeGen/AArch64/remat.ll
  llvm/test/MC/AArch64/armv8.2a-dotprod.s
  llvm/test/MC/AArch64/armv8.3a-rcpc.s
  llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
  llvm/unittests/TargetParser/Host.cpp
  llvm/unittests/TargetParser/TargetParserTest.cpp

Index: llvm/unittests/TargetParser/TargetParserTest.cpp
===
--- llvm/unittests/TargetParser/TargetParserTest.cpp
+++ llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1339,6 +1339,16 @@
 AArch64::AEK_AES | AArch64::AEK_I8MM | AArch64::AEK_SSBS |
 AArch64::AEK_SB | AArch64::AEK_RAND,
 "8.6-A"),
+ARMCPUTestParams(
+"ampere1a", "armv8.6-a", "crypto-neon-fp-armv8",
+AArch64::AEK_CRC | AArch64::AEK_FP | AArch64::AEK_FP16 |
+AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
+AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 |
+AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM |
+AArch64::AEK_SSBS | AArch64::AEK_SB | AArch64::AEK_RAND |
+AArch64::AEK_MTE,
+"8.6-A"),
 ARMCPUTestParams(
 "neoverse-512tvb", "armv8.4-a", "crypto-neon-fp-armv8",
 AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
@@ -1399,7 +1409,7 @@
  "8.2-A")));
 
 // Note: number of CPUs includes aliases.
-static constexpr unsigned NumAArch64CPUArchs = 61;
+static constexpr unsigned NumAArch64CPUArchs = 62;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/unittests/TargetParser/Host.cpp
===
--- llvm/unittests/TargetParser/Host.cpp
+++ llvm/unittests/TargetParser/Host.cpp
@@ -117,6 +117,9 @@
   EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
   "CPU part: 0xac3"),
 "ampere1");
+  EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
+  "CPU part: 0xac4"),
+"ampere1a");
 
   // MSM8992/4 weirdness
   StringRef MSM8992ProcCpuInfo = R"(
Index: llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
===
--- llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
+++ llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
@@ -13,6 +13,7 @@
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n1 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n2 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1 --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1a --disassemble < %s | FileCheck %s
 
 # CHECK: ldaprb w0, [x0]
 # CHECK: ldaprh w0, [x0]
Index: llvm/test/MC/AArch64/armv8.3a-rcpc.s
===
--- llvm/test/MC/AArch64/armv8.3a-rcpc.s
+++ llvm/test/MC/AArch64/armv8.3a-rcpc.s
@@ -7,6 +7,7 @@
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n1 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n2 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=ampere1 < %s 2>&1 | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=ampere1a < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a -mattr=+rcpc < %s 2>&1 | FileCheck %s
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
Index: llvm/test/MC/AArch64/armv8.2a-dotprod.s
===
--- llvm/test/MC/AArch64/armv8.2a-dotprod.s
+++ llvm/test/MC/AArch64/armv8.2a-dotprod.s
@@ -14,6 +14,7 @@
 // RUN: llvm-mc -triple aarch64 -mcpu=cortex-r82 -show-e

[PATCH] D142396: [AArch64] Add the Ampere1A core

2023-01-23 Thread Philipp Tomsich via Phabricator via cfe-commits 
philipp.tomsich created this revision.
philipp.tomsich added a reviewer: dmgreen.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
philipp.tomsich requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

The Ampere1A core improves on the Ampere1 with key differences being:

- FEAT_MTE is now supported
- adds a new fusion pair for (A+B+1 and A-B-1)

Depends on D142395 


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D142396

Files:
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/TargetParser/AArch64TargetParser.h
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/TargetParser/Host.cpp
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/neon-dot-product.ll
  llvm/test/CodeGen/AArch64/remat.ll
  llvm/test/MC/AArch64/armv8.2a-dotprod.s
  llvm/test/MC/AArch64/armv8.3a-rcpc.s
  llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
  llvm/unittests/TargetParser/Host.cpp
  llvm/unittests/TargetParser/TargetParserTest.cpp

Index: llvm/unittests/TargetParser/TargetParserTest.cpp
===
--- llvm/unittests/TargetParser/TargetParserTest.cpp
+++ llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1341,6 +1341,15 @@
  AArch64::AEK_SHA2 | AArch64::AEK_AES  | AArch64::AEK_I8MM|
  AArch64::AEK_SSBS | AArch64::AEK_SB   | AArch64::AEK_RAND,
  "8.6-A"),
+ARMCPUTestParams("ampere1a", "armv8.6-a", "crypto-neon-fp-armv8",
+ AArch64::AEK_CRC  | AArch64::AEK_FP   | AArch64::AEK_FP16   |
+ AArch64::AEK_SIMD | AArch64::AEK_RAS  | AArch64::AEK_LSE |
+ AArch64::AEK_RDM  | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+ AArch64::AEK_SM4  | AArch64::AEK_SHA3 | AArch64::AEK_BF16|
+ AArch64::AEK_SHA2 | AArch64::AEK_AES  | AArch64::AEK_I8MM|
+ AArch64::AEK_SSBS | AArch64::AEK_SB   | AArch64::AEK_RAND|
+ AArch64::AEK_MTE,
+ "8.6-A"),
 ARMCPUTestParams(
 "neoverse-512tvb", "armv8.4-a", "crypto-neon-fp-armv8",
 AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
@@ -1403,7 +1412,7 @@
  "8.2-A")));
 
 // Note: number of CPUs includes aliases.
-static constexpr unsigned NumAArch64CPUArchs = 61;
+static constexpr unsigned NumAArch64CPUArchs = 62;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/unittests/TargetParser/Host.cpp
===
--- llvm/unittests/TargetParser/Host.cpp
+++ llvm/unittests/TargetParser/Host.cpp
@@ -117,6 +117,9 @@
   EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
   "CPU part: 0xac3"),
 "ampere1");
+  EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
+  "CPU part: 0xac4"),
+"ampere1a");
 
   // MSM8992/4 weirdness
   StringRef MSM8992ProcCpuInfo = R"(
Index: llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
===
--- llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
+++ llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
@@ -13,6 +13,7 @@
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n1 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n2 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1 --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1a --disassemble < %s | FileCheck %s
 
 # CHECK: ldaprb w0, [x0]
 # CHECK: ldaprh w0, [x0]
Index: llvm/test/MC/AArch64/armv8.3a-rcpc.s
===
--- llvm/test/MC/AArch64/armv8.3a-rcpc.s
+++ llvm/test/MC/AArch64/armv8.3a-rcpc.s
@@ -7,6 +7,7 @@
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n1 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n2 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=ampere1 < %s 2>&1 | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=ampere1a < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a -mattr=+rcpc < %s 2>&1 | FileCheck %s
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu

[PATCH] D142396: [AArch64] Add the Ampere1A core

2023-01-23 Thread Philipp Tomsich via Phabricator via cfe-commits 
philipp.tomsich updated this revision to Diff 491499.
philipp.tomsich added a comment.

v2 changes:

- fixes a whitespace issue
- fixes a rebase artifact on Ampere1


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D142396/new/

https://reviews.llvm.org/D142396

Files:
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/TargetParser/AArch64TargetParser.h
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/TargetParser/Host.cpp
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/neon-dot-product.ll
  llvm/test/CodeGen/AArch64/remat.ll
  llvm/test/MC/AArch64/armv8.2a-dotprod.s
  llvm/test/MC/AArch64/armv8.3a-rcpc.s
  llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
  llvm/unittests/TargetParser/Host.cpp
  llvm/unittests/TargetParser/TargetParserTest.cpp

Index: llvm/unittests/TargetParser/TargetParserTest.cpp
===
--- llvm/unittests/TargetParser/TargetParserTest.cpp
+++ llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1341,6 +1341,15 @@
  AArch64::AEK_SHA2 | AArch64::AEK_AES  | AArch64::AEK_I8MM|
  AArch64::AEK_SSBS | AArch64::AEK_SB   | AArch64::AEK_RAND,
  "8.6-A"),
+ARMCPUTestParams("ampere1a", "armv8.6-a", "crypto-neon-fp-armv8",
+ AArch64::AEK_CRC  | AArch64::AEK_FP   | AArch64::AEK_FP16   |
+ AArch64::AEK_SIMD | AArch64::AEK_RAS  | AArch64::AEK_LSE |
+ AArch64::AEK_RDM  | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+ AArch64::AEK_SM4  | AArch64::AEK_SHA3 | AArch64::AEK_BF16|
+ AArch64::AEK_SHA2 | AArch64::AEK_AES  | AArch64::AEK_I8MM|
+ AArch64::AEK_SSBS | AArch64::AEK_SB   | AArch64::AEK_RAND|
+ AArch64::AEK_MTE,
+ "8.6-A"),
 ARMCPUTestParams(
 "neoverse-512tvb", "armv8.4-a", "crypto-neon-fp-armv8",
 AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
@@ -1403,7 +1412,7 @@
  "8.2-A")));
 
 // Note: number of CPUs includes aliases.
-static constexpr unsigned NumAArch64CPUArchs = 61;
+static constexpr unsigned NumAArch64CPUArchs = 62;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/unittests/TargetParser/Host.cpp
===
--- llvm/unittests/TargetParser/Host.cpp
+++ llvm/unittests/TargetParser/Host.cpp
@@ -117,6 +117,9 @@
   EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
   "CPU part: 0xac3"),
 "ampere1");
+  EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
+  "CPU part: 0xac4"),
+"ampere1a");
 
   // MSM8992/4 weirdness
   StringRef MSM8992ProcCpuInfo = R"(
Index: llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
===
--- llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
+++ llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
@@ -13,6 +13,7 @@
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n1 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n2 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1 --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1a --disassemble < %s | FileCheck %s
 
 # CHECK: ldaprb w0, [x0]
 # CHECK: ldaprh w0, [x0]
Index: llvm/test/MC/AArch64/armv8.3a-rcpc.s
===
--- llvm/test/MC/AArch64/armv8.3a-rcpc.s
+++ llvm/test/MC/AArch64/armv8.3a-rcpc.s
@@ -7,6 +7,7 @@
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n1 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n2 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=ampere1 < %s 2>&1 | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=ampere1a < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a -mattr=+rcpc < %s 2>&1 | FileCheck %s
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
Index: llvm/test/MC/AArch64/armv8.2a-dotprod.s
===
--- llvm/test/MC/AArch64/armv8.2a-dotprod.s
+++ llvm/test/MC/AArch64/armv8.2a-dot

[PATCH] D142410: [AArch64] ARMv8.5-A implies both FEAT_SB and FEAT_SSBS

2023-01-23 Thread Philipp Tomsich via Phabricator via cfe-commits 
philipp.tomsich created this revision.
philipp.tomsich added a reviewer: dmgreen.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
philipp.tomsich requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

ARMv8.5-A implies SB and SSBS.  This requires some adjustments to the
testcases where ARMv8.5 cores (which must implement these) have tests
that don't expect SB or (usually) SBSS to be set.

Depends on D142396 


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D142410

Files:
  clang/test/CodeGen/aarch64-targetattr.c
  clang/test/Preprocessor/aarch64-target-features.c
  llvm/include/llvm/TargetParser/AArch64TargetParser.h
  llvm/lib/Target/AArch64/AArch64.td
  llvm/unittests/TargetParser/TargetParserTest.cpp

Index: llvm/unittests/TargetParser/TargetParserTest.cpp
===
--- llvm/unittests/TargetParser/TargetParserTest.cpp
+++ llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1094,7 +1094,7 @@
 AArch64::AEK_FP16 | AArch64::AEK_FP16FML | AArch64::AEK_SVE |
 AArch64::AEK_SVE2 | AArch64::AEK_SVE2BITPERM |
 AArch64::AEK_PAUTH | AArch64::AEK_FLAGM | AArch64::AEK_SB |
-AArch64::AEK_I8MM | AArch64::AEK_BF16,
+AArch64::AEK_I8MM | AArch64::AEK_BF16 | AArch64::AEK_SSBS,
 "9-A"),
 ARMCPUTestParams("cortex-a715", "armv9-a", "neon-fp-armv8",
  AArch64::AEK_CRC | AArch64::AEK_FP | AArch64::AEK_BF16 |
@@ -1107,7 +1107,8 @@
  AArch64::AEK_SB | AArch64::AEK_I8MM |
  AArch64::AEK_PERFMON | AArch64::AEK_PREDRES |
  AArch64::AEK_PROFILE | AArch64::AEK_FP16FML |
- AArch64::AEK_FP16 | AArch64::AEK_FLAGM,
+ AArch64::AEK_FP16 | AArch64::AEK_FLAGM |
+ AArch64::AEK_SSBS,
  "9-A"),
 ARMCPUTestParams(
 "neoverse-v1", "armv8.4-a", "crypto-neon-fp-armv8",
@@ -1128,7 +1129,7 @@
 AArch64::AEK_FP16 | AArch64::AEK_BF16 | AArch64::AEK_SVE2 |
 AArch64::AEK_PROFILE | AArch64::AEK_FP16FML |
 AArch64::AEK_I8MM | AArch64::AEK_SVE2BITPERM |
-AArch64::AEK_RAND,
+AArch64::AEK_RAND | AArch64::AEK_SB | AArch64::AEK_SSBS,
 "9-A"),
 ARMCPUTestParams("cortex-r82", "armv8-r", "crypto-neon-fp-armv8",
  AArch64::AEK_CRC | AArch64::AEK_RDM |
@@ -1228,7 +1229,8 @@
  AArch64::AEK_LSE | AArch64::AEK_RAS |
  AArch64::AEK_RDM | AArch64::AEK_RCPC |
  AArch64::AEK_DOTPROD | AArch64::AEK_FP16 |
- AArch64::AEK_FP16FML | AArch64::AEK_SHA3,
+ AArch64::AEK_FP16FML | AArch64::AEK_SHA3 |
+ AArch64::AEK_SB | AArch64::AEK_SSBS,
  "8.5-A"),
 ARMCPUTestParams("apple-a15", "armv8.5-a", "crypto-neon-fp-armv8",
  AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
@@ -1237,7 +1239,8 @@
  AArch64::AEK_RDM | AArch64::AEK_RCPC |
  AArch64::AEK_DOTPROD | AArch64::AEK_FP16 |
  AArch64::AEK_FP16FML | AArch64::AEK_SHA3 |
- AArch64::AEK_BF16 | AArch64::AEK_I8MM,
+ AArch64::AEK_BF16 | AArch64::AEK_I8MM |
+ AArch64::AEK_SB | AArch64::AEK_SSBS,
  "8.5-A"),
 ARMCPUTestParams("apple-a16", "armv8.5-a", "crypto-neon-fp-armv8",
  AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
@@ -1246,7 +1249,8 @@
  AArch64::AEK_RDM | AArch64::AEK_RCPC |
  AArch64::AEK_DOTPROD | AArch64::AEK_FP16 |
  AArch64::AEK_FP16FML | AArch64::AEK_SHA3 |
- AArch64::AEK_BF16 | AArch64::AEK_I8MM,
+ AArch64::AEK_BF16 | AArch64::AEK_I8MM |
+ AArch64::AEK_SB | AArch64::AEK_SSBS,
  "8.5-A"),
 ARMCPUTestParams("apple-m1", "armv8.5-a", "crypto-neon-fp-armv8",
  AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
@@ -1254,7 +1258,8 @@
  AArch64::AEK_LSE | AArch64::AEK_RAS |
  AArch64::AEK_RDM | AArch64::AEK_RCPC |
  AArch64::AEK_DOTPROD | AArch64::AEK_FP16 |
- AArch64::AEK_FP16FML | AArch64::AEK_SHA3,
+ AArch64::AEK_FP16FML | AArch64::AEK_SHA3 |
+ AArch64::AEK_SB | AArch64:

[PATCH] D159480: [Clang][AArch64] Fine-grained ldp and stp policies.

2023-09-08 Thread Philipp Tomsich via Phabricator via cfe-commits 
philipp.tomsich added a comment.

Should we move this to a GitHub PR instead?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159480/new/

https://reviews.llvm.org/D159480

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[PATCH] D142410: [AArch64] ARMv8.5-A implies both FEAT_SB and FEAT_SSBS

2023-04-13 Thread Philipp Tomsich via Phabricator via cfe-commits 
philipp.tomsich abandoned this revision.
philipp.tomsich added a comment.

I just saw that the last response was "unsubmitted".

Submitting and abandoning this revision (based on the discussion and the 
previously unsubmitted comment from my end).




Comment at: llvm/include/llvm/TargetParser/AArch64TargetParser.h:311
 inline constexpr ArchInfo ARMV8_4A  = { VersionTuple{8, 4}, AProfile, 
"armv8.4-a", "+v8.4a", (ARMV8_3A.DefaultExts | AArch64::AEK_DOTPROD)};
-inline constexpr ArchInfo ARMV8_5A  = { VersionTuple{8, 5}, AProfile, 
"armv8.5-a", "+v8.5a", (ARMV8_4A.DefaultExts)};
+inline constexpr ArchInfo ARMV8_5A  = { VersionTuple{8, 5}, AProfile, 
"armv8.5-a", "+v8.5a", (ARMV8_4A.DefaultExts | AArch64::AEK_SB | 
AArch64::AEK_SSBS )};
 constexpr unsigned BaseNoCrypto = ARMV8_5A.DefaultExts ^ AArch64::AEK_CRYPTO; 
// 8.6 onwards has no AEK_CRYPTO

lenary wrote:
> According to the A-profile Arm ARM (version I.a):
> - FEAT_SB is mandatory from v8.5 onwards, so thank you for correcting this 
> oversight.
> - There is no language about the same for FEAT_SSBS/FEAT_SSBS2. It was added 
> to v8.0a by v8.5a, but it doesn't seem to have been made mandatory in v8.5a, 
> as far as I can see. There is no language in section A2 (Architectural 
> Extensions), or in the description of the `ID_AA64PFR1_EL1.SSBS` register 
> about being mandatory from certain versions (other fields in this register do 
> have this language).
I have now picked up I.a after I had previously referenced G.a.

Features added to earlier extensions (For ARMv8.5) lists FEAT_SBSS.
However, the Text under FEAT_SBSS/FEAT_SSBS2 no longer has the "This feature is 
OPTIONAL in Armv8.0 implementations and mandatory in Armv8.5 implementations." 
that was present in version G.a of the spec.

So it looks as if this was made optional again somewhere between G.a and I.a?





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[PATCH] D143439: [RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension

2023-02-06 Thread Philipp Tomsich via Phabricator via cfe-commits 
philipp.tomsich added a comment.

Thanks for spotting this.
Fixed in our local git-tree as well, so it doesn't sneak back in during the 
merge.

I am blind to the difference between Ba, Bb, and Bs by now -- with Ba and Bs 
being too close to each other on the keyboard for comfort!.


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[PATCH] D143439: [RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension

2023-02-07 Thread Philipp Tomsich via Phabricator via cfe-commits 
philipp.tomsich added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:318
+if (Subtarget.is64Bit())
+  setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i32, Custom);
+  }

craig.topper wrote:
> without these two lines to promote i32, I suppose we would get zext i32 to 
> i64, ff1, addi? Is the sequence used for ctlzw better than that?
The sequences will have an identical critical-path (and require the same number 
of temporaries).
I read your comment as a recommendation to simplify the overall implementation 
(by removing the special case here and in the pattern-matching).


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[PATCH] D143439: [RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension

2023-02-07 Thread Philipp Tomsich via Phabricator via cfe-commits 
philipp.tomsich reopened this revision.
philipp.tomsich added a comment.

Reopening as this was accidentially pushed and reverted when doing 'arc patch 
on D143534 '.


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[PATCH] D143439: [RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension

2023-02-13 Thread Philipp Tomsich via Phabricator via cfe-commits 
philipp.tomsich marked 4 inline comments as done.
philipp.tomsich added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:315
+  if (Subtarget.hasVendorXTHeadBb()) {
+setOperationAction({ISD::CTLZ}, XLenVT, Legal);
+

inclyc wrote:
> It looks like this line of code will cause compilation warning.
> 
> ```
> [1677/1717] Building CXX object 
> lib/Target/RISCV/CMakeFiles/LLVMRISCVCodeGen.dir/RISCVISelLowering.cpp.o
> /tmp/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.cpp:315:24: 
> warning: braces around scalar initializer [-Wbraced-scalar-init]
> setOperationAction({ISD::CTLZ}, XLenVT, Legal);
>^~~
> 1 warning generated.
> [1717/1717] Creating library symlink lib/libclang-cpp.so
> [1542/1716] Building CXX object 
> lib/Target/RISCV/CMakeFiles/LLVMRISCVCodeGen.dir/RISCVISelLowering.cpp.o
> /tmp/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.cpp:315:24: 
> warning: braces around scalar initializer [-Wbraced-scalar-init]
> setOperationAction({ISD::CTLZ}, XLenVT, Legal);
>^~~
> 1 warning generated.
> [1716/1716] Linking C executable bin/mlir-capi-execution-engine-test
> ```
Thanks. I'll push a NFC commit to fix this, as soon as my testrun completes.
Interesting that I don't see this warning on my build ... will dig to make sure 
that we are not missing anything in the future.


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[PATCH] D117112: [AArch64] Support for Ampere1 core

2022-01-12 Thread Philipp Tomsich via Phabricator via cfe-commits 
philipp.tomsich created this revision.
philipp.tomsich added reviewers: kristof.beyls, jgreenhalgh.
Herald added a subscriber: hiraditya.
philipp.tomsich requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Add support for the Ampere Computing Ampere1 core.
Ampere1 implements the AArch64 state and is compatible with ARMv8.6-A.


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Files:
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
  llvm/lib/Target/AArch64/AArch64SchedPredAmpere.td
  llvm/lib/Target/AArch64/AArch64SchedPredicates.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/neon-dot-product.ll
  llvm/test/CodeGen/AArch64/remat.ll
  llvm/test/MC/AArch64/armv8.2a-dotprod.s
  llvm/test/MC/AArch64/armv8.3a-rcpc.s
  llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -1169,6 +1169,16 @@
  AArch64::AEK_SVE2 | AArch64::AEK_SVE2BITPERM |
  AArch64::AEK_BF16 | AArch64::AEK_I8MM,
  "8.5-A"),
+ARMCPUTestParams("ampere1", "armv8.6-a", "crypto-neon-fp-armv8",
+ AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+ AArch64::AEK_FP | AArch64::AEK_SIMD |
+ AArch64::AEK_FP16 | AArch64::AEK_RAS |
+ AArch64::AEK_LSE | 
+ AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
+ AArch64::AEK_RDM | AArch64::AEK_MTE |
+ AArch64::AEK_SSBS | AArch64::AEK_SB |
+ AArch64::AEK_BF16 | AArch64::AEK_I8MM,
+ "8.6-A"),
 ARMCPUTestParams(
 "neoverse-512tvb", "armv8.4-a", "crypto-neon-fp-armv8",
 AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
@@ -1232,7 +1242,7 @@
  AArch64::AEK_LSE | AArch64::AEK_RDM,
  "8.2-A")));
 
-static constexpr unsigned NumAArch64CPUArchs = 52;
+static constexpr unsigned NumAArch64CPUArchs = 53;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
===
--- llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
+++ llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
@@ -12,6 +12,7 @@
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-e1 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n1 --disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n2 --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1 --disassemble < %s | FileCheck %s
 
 # CHECK: ldaprb w0, [x0]
 # CHECK: ldaprh w0, [x0]
Index: llvm/test/MC/AArch64/armv8.3a-rcpc.s
===
--- llvm/test/MC/AArch64/armv8.3a-rcpc.s
+++ llvm/test/MC/AArch64/armv8.3a-rcpc.s
@@ -6,6 +6,7 @@
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-e1 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n1 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n2 < %s 2>&1 | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=ampere1 < %s 2>&1 | FileCheck %s
 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a -mattr=+rcpc < %s 2>&1 | FileCheck %s
 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
Index: llvm/test/MC/AArch64/armv8.2a-dotprod.s
===
--- llvm/test/MC/AArch64/armv8.2a-dotprod.s
+++ llvm/test/MC/AArch64/armv8.2a-dotprod.s
@@ -13,6 +13,7 @@
 // RUN: llvm-mc -triple aarch64 -mcpu=tsv110 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch64 -mcpu=cortex-r82 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
 // RUN: llvm-mc -triple aarch64 -mattr=+v8r -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
+// RUN: llvm-mc -triple aarch64 -mcpu=ampere1 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
 
 // RUN: not llvm-mc -triple aarch64 -mattr=+v8.2a -show