[PATCH] D33401: [mips] Add runtime options to enable/disable generation of madd.fmt, msub.fmt

[Petar Jovanovic via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL304929: [mips] Add runtime options to enable/disable 
madd.fmt and msub.fmt (authored by petarj).

Changed prior to commit:
  https://reviews.llvm.org/D33401?vs=101562&id=101767#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D33401

Files:
  cfe/trunk/include/clang/Driver/Options.td
  cfe/trunk/lib/Basic/Targets.cpp
  cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
  cfe/trunk/test/CodeGen/mips-madd4.c
  cfe/trunk/test/Preprocessor/init.c

Index: cfe/trunk/include/clang/Driver/Options.td
===
--- cfe/trunk/include/clang/Driver/Options.td
+++ cfe/trunk/include/clang/Driver/Options.td
@@ -2001,6 +2001,10 @@
 def mno_dspr2 : Flag<["-"], "mno-dspr2">, Group;
 def msingle_float : Flag<["-"], "msingle-float">, Group;
 def mdouble_float : Flag<["-"], "mdouble-float">, Group;
+def mmadd4 : Flag<["-"], "mmadd4">, Group,
+  HelpText<"Enable the generation of 4-operand madd.s, madd.d and related instructions.">;
+def mno_madd4 : Flag<["-"], "mno-madd4">, Group,
+  HelpText<"Disable the generation of 4-operand madd.s, madd.d and related instructions.">;
 def mmsa : Flag<["-"], "mmsa">, Group,
   HelpText<"Enable MSA ASE (MIPS only)">;
 def mno_msa : Flag<["-"], "mno-msa">, Group,
Index: cfe/trunk/test/Preprocessor/init.c
===
--- cfe/trunk/test/Preprocessor/init.c
+++ cfe/trunk/test/Preprocessor/init.c
@@ -4664,6 +4664,16 @@
 // RUN:   | FileCheck -match-full-lines -check-prefix MIPS-MSA %s
 // MIPS-MSA:#define __mips_msa 1
 //
+// RUN: %clang_cc1 -target-feature +nomadd4 \
+// RUN:   -E -dM -triple=mips-none-none < /dev/null \
+// RUN:   | FileCheck -match-full-lines -check-prefix MIPS-NOMADD4 %s
+// MIPS-NOMADD4:#define __mips_no_madd4 1
+//
+// RUN: %clang_cc1 \
+// RUN:   -E -dM -triple=mips-none-none < /dev/null \
+// RUN:   | FileCheck -match-full-lines -check-prefix MIPS-MADD4 %s
+// MIPS-MADD4-NOT:#define __mips_no_madd4 1
+//
 // RUN: %clang_cc1 -target-cpu mips32r3 -target-feature +nan2008 \
 // RUN:   -E -dM -triple=mips-none-none < /dev/null \
 // RUN:   | FileCheck -match-full-lines -check-prefix MIPS-NAN2008 %s
Index: cfe/trunk/test/CodeGen/mips-madd4.c
===
--- cfe/trunk/test/CodeGen/mips-madd4.c
+++ cfe/trunk/test/CodeGen/mips-madd4.c
@@ -0,0 +1,86 @@
+// RUN: %clang --target=mips64-unknown-linux -S -mmadd4%s -o -| FileCheck %s -check-prefix=MADD4
+// RUN: %clang --target=mips64-unknown-linux -S -mno-madd4 %s -o -| FileCheck %s -check-prefix=NOMADD4
+// RUN: %clang --target=mips64-unknown-linux -S -mmadd4-fno-honor-nans %s -o -| FileCheck %s -check-prefix=MADD4-NONAN
+// RUN: %clang --target=mips64-unknown-linux -S -mno-madd4 -fno-honor-nans %s -o -| FileCheck %s -check-prefix=NOMADD4-NONAN
+ 
+float madd_s (float f, float g, float h)
+{
+  return (f * g) + h;
+}
+// MADD4:   madd.s
+// NOMADD4: mul.s
+// NOMADD4: add.s
+
+float msub_s (float f, float g, float h)
+{
+  return (f * g) - h;
+}
+// MADD4:   msub.s
+// NOMADD4: mul.s
+// NOMADD4: sub.s
+
+double madd_d (double f, double g, double h)
+{
+  return (f * g) + h;
+}
+// MADD4:   madd.d
+// NOMADD4: mul.d
+// NOMADD4: add.d
+
+double msub_d (double f, double g, double h)
+{
+  return (f * g) - h;
+}
+// MADD4:   msub.d
+// NOMADD4: mul.d
+// NOMADD4: sub.d
+
+
+float nmadd_s (float f, float g, float h)
+{
+  // FIXME: Zero has been explicitly placed to force generation of a positive
+  // zero in IR until pattern used to match this instruction is changed to
+  // comply with negative zero as well.
+  return 0-((f * g) + h);
+}
+// MADD4-NONAN:   nmadd.s
+// NOMADD4-NONAN: mul.s
+// NOMADD4-NONAN: add.s
+// NOMADD4-NONAN: sub.s
+
+float nmsub_s (float f, float g, float h)
+{
+  // FIXME: Zero has been explicitly placed to force generation of a positive
+  // zero in IR until pattern used to match this instruction is changed to
+  // comply with negative zero as well.
+  return 0-((f * g) - h);
+}
+// MADD4-NONAN:   nmsub.s
+// NOMADD4-NONAN: mul.s
+// NOMADD4-NONAN: sub.s
+// NOMADD4-NONAN: sub.s
+
+double nmadd_d (double f, double g, double h)
+{
+  // FIXME: Zero has been explicitly placed to force generation of a positive
+  // zero in IR until pattern used to match this instruction is changed to
+  // comply with negative zero as well.
+  return 0-((f * g) + h);
+}
+// MADD4-NONAN:   nmadd.d
+// NOMADD4-NONAN: mul.d
+// NOMADD4-NONAN: add.d
+// NOMADD4-NONAN: sub.d
+
+double nmsub_d (double f, double g, double h)
+{
+  // FIXME: Zero has been explicitly placed to force generation of a positive
+  // zero in IR until pattern used to match this instruction is changed to
+  // comply with negative zero as well.
+  return 0-((f * g) - h);
+}
+// MADD4-NONAN:   nmsub.d
+// NOMADD4-NONAN: mul.d
+// NOMADD4-NONAN: sub.d
+// NOMADD4-NONAN: sub.d
+
Index: cfe/tru

[PATCH] D34514: [mips] Enable IAS by default for Android 64-bit MIPS target (N64)

[Petar Jovanovic via Phabricator via cfe-commits]

petarj created this revision.
Herald added subscribers: arichardson, srhines.

IAS is already used for MIPS64 in majority of Android projects.
Android MIPS64 uses N64 ABI. Set IAS as a default now.


Repository:
  rL LLVM

https://reviews.llvm.org/D34514

Files:
  lib/Driver/ToolChains/Gnu.cpp


Index: lib/Driver/ToolChains/Gnu.cpp
===
--- lib/Driver/ToolChains/Gnu.cpp
+++ lib/Driver/ToolChains/Gnu.cpp
@@ -2319,9 +2319,10 @@
 return true;
   case llvm::Triple::mips64:
   case llvm::Triple::mips64el:
-// Enabled for Debian mips64/mips64el only. Other targets are unable to
-// distinguish N32 from N64.
-if (getTriple().getEnvironment() == llvm::Triple::GNUABI64)
+// Enabled for Debian mips64/mips64el and Android (uses N64 ABI).
+// Other targets are unable to distinguish N32 from N64.
+if (getTriple().getEnvironment() == llvm::Triple::GNUABI64 ||
+getTriple().isAndroid())
   return true;
 return false;
   default:


Index: lib/Driver/ToolChains/Gnu.cpp
===
--- lib/Driver/ToolChains/Gnu.cpp
+++ lib/Driver/ToolChains/Gnu.cpp
@@ -2319,9 +2319,10 @@
 return true;
   case llvm::Triple::mips64:
   case llvm::Triple::mips64el:
-// Enabled for Debian mips64/mips64el only. Other targets are unable to
-// distinguish N32 from N64.
-if (getTriple().getEnvironment() == llvm::Triple::GNUABI64)
+// Enabled for Debian mips64/mips64el and Android (uses N64 ABI).
+// Other targets are unable to distinguish N32 from N64.
+if (getTriple().getEnvironment() == llvm::Triple::GNUABI64 ||
+getTriple().isAndroid())
   return true;
 return false;
   default:
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[PATCH] D34514: [mips] Enable IAS by default for Android 64-bit MIPS target (N64)

[Petar Jovanovic via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL306280: [mips] Enable IAS by default for Android 64-bit MIPS 
target (N64) (authored by petarj).

Changed prior to commit:
  https://reviews.llvm.org/D34514?vs=103574&id=103912#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D34514

Files:
  cfe/trunk/lib/Driver/ToolChains/Gnu.cpp


Index: cfe/trunk/lib/Driver/ToolChains/Gnu.cpp
===
--- cfe/trunk/lib/Driver/ToolChains/Gnu.cpp
+++ cfe/trunk/lib/Driver/ToolChains/Gnu.cpp
@@ -2338,9 +2338,11 @@
 return true;
   case llvm::Triple::mips64:
   case llvm::Triple::mips64el:
-// Enabled for Debian mips64/mips64el only. Other targets are unable to
-// distinguish N32 from N64.
-if (getTriple().getEnvironment() == llvm::Triple::GNUABI64)
+// Enabled for Debian and Android mips64/mipsel, as they can precisely
+// identify the ABI in use (Debian) or only use N64 for MIPS64 (Android).
+// Other targets are unable to distinguish N32 from N64.
+if (getTriple().getEnvironment() == llvm::Triple::GNUABI64 ||
+getTriple().isAndroid())
   return true;
 return false;
   default:


Index: cfe/trunk/lib/Driver/ToolChains/Gnu.cpp
===
--- cfe/trunk/lib/Driver/ToolChains/Gnu.cpp
+++ cfe/trunk/lib/Driver/ToolChains/Gnu.cpp
@@ -2338,9 +2338,11 @@
 return true;
   case llvm::Triple::mips64:
   case llvm::Triple::mips64el:
-// Enabled for Debian mips64/mips64el only. Other targets are unable to
-// distinguish N32 from N64.
-if (getTriple().getEnvironment() == llvm::Triple::GNUABI64)
+// Enabled for Debian and Android mips64/mipsel, as they can precisely
+// identify the ABI in use (Debian) or only use N64 for MIPS64 (Android).
+// Other targets are unable to distinguish N32 from N64.
+if (getTriple().getEnvironment() == llvm::Triple::GNUABI64 ||
+getTriple().isAndroid())
   return true;
 return false;
   default:
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[PATCH] D39053: [Bitfield] Add more cases to making the bitfield a separate location

[Petar Jovanovic via Phabricator via cfe-commits]

petarj added a comment.

Is everyone OK with the patch now?


https://reviews.llvm.org/D39053



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[PATCH] D58894: [analyzer] Handle modification of vars inside an expr with comma operator

[Petar Jovanovic via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL355605: [analyzer] handle modification of vars inside an 
expr with comma operator (authored by petarj, committed by ).
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D58894?vs=189661&id=189719#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D58894/new/

https://reviews.llvm.org/D58894

Files:
  cfe/trunk/include/clang/AST/Expr.h
  cfe/trunk/lib/Analysis/ExprMutationAnalyzer.cpp
  cfe/trunk/unittests/Analysis/ExprMutationAnalyzerTest.cpp

Index: cfe/trunk/lib/Analysis/ExprMutationAnalyzer.cpp
===
--- cfe/trunk/lib/Analysis/ExprMutationAnalyzer.cpp
+++ cfe/trunk/lib/Analysis/ExprMutationAnalyzer.cpp
@@ -24,6 +24,18 @@
   return InnerMatcher.matches(*Range, Finder, Builder);
 }
 
+AST_MATCHER_P(Expr, maybeEvalCommaExpr,
+ ast_matchers::internal::Matcher, InnerMatcher) {
+  const Expr* Result = &Node;
+  while (const auto *BOComma =
+   dyn_cast_or_null(Result->IgnoreParens())) {
+if (!BOComma->isCommaOp())
+  break;
+Result = BOComma->getRHS();
+  }
+  return InnerMatcher.matches(*Result, Finder, Builder);
+}
+
 const ast_matchers::internal::VariadicDynCastAllOfMatcher
 cxxTypeidExpr;
 
@@ -193,24 +205,28 @@
 const Stmt *ExprMutationAnalyzer::findDirectMutation(const Expr *Exp) {
   // LHS of any assignment operators.
   const auto AsAssignmentLhs =
-  binaryOperator(isAssignmentOperator(), hasLHS(equalsNode(Exp)));
+  binaryOperator(isAssignmentOperator(),
+ hasLHS(maybeEvalCommaExpr(equalsNode(Exp;
 
   // Operand of increment/decrement operators.
   const auto AsIncDecOperand =
   unaryOperator(anyOf(hasOperatorName("++"), hasOperatorName("--")),
-hasUnaryOperand(equalsNode(Exp)));
+hasUnaryOperand(maybeEvalCommaExpr(equalsNode(Exp;
 
   // Invoking non-const member function.
   // A member function is assumed to be non-const when it is unresolved.
   const auto NonConstMethod = cxxMethodDecl(unless(isConst()));
   const auto AsNonConstThis =
-  expr(anyOf(cxxMemberCallExpr(callee(NonConstMethod), on(equalsNode(Exp))),
+  expr(anyOf(cxxMemberCallExpr(callee(NonConstMethod),
+   on(maybeEvalCommaExpr(equalsNode(Exp,
  cxxOperatorCallExpr(callee(NonConstMethod),
- hasArgument(0, equalsNode(Exp))),
+ hasArgument(0,
+ maybeEvalCommaExpr(equalsNode(Exp,
  callExpr(callee(expr(anyOf(
- unresolvedMemberExpr(hasObjectExpression(equalsNode(Exp))),
+ unresolvedMemberExpr(
+   hasObjectExpression(maybeEvalCommaExpr(equalsNode(Exp,
  cxxDependentScopeMemberExpr(
- hasObjectExpression(equalsNode(Exp);
+ hasObjectExpression(maybeEvalCommaExpr(equalsNode(Exp));
 
   // Taking address of 'Exp'.
   // We're assuming 'Exp' is mutated as soon as its address is taken, though in
@@ -220,10 +236,11 @@
   unaryOperator(hasOperatorName("&"),
 // A NoOp implicit cast is adding const.
 unless(hasParent(implicitCastExpr(hasCastKind(CK_NoOp,
-hasUnaryOperand(equalsNode(Exp)));
+hasUnaryOperand(maybeEvalCommaExpr(equalsNode(Exp;
   const auto AsPointerFromArrayDecay =
   castExpr(hasCastKind(CK_ArrayToPointerDecay),
-   unless(hasParent(arraySubscriptExpr())), has(equalsNode(Exp)));
+   unless(hasParent(arraySubscriptExpr())),
+   has(maybeEvalCommaExpr(equalsNode(Exp;
   // Treat calling `operator->()` of move-only classes as taking address.
   // These are typically smart pointers with unique ownership so we treat
   // mutation of pointee as mutation of the smart pointer itself.
@@ -231,7 +248,8 @@
   cxxOperatorCallExpr(hasOverloadedOperatorName("->"),
   callee(cxxMethodDecl(ofClass(isMoveOnly()),
returns(nonConstPointerType(,
-  argumentCountIs(1), hasArgument(0, equalsNode(Exp)));
+  argumentCountIs(1),
+  hasArgument(0, maybeEvalCommaExpr(equalsNode(Exp;
 
   // Used as non-const-ref argument when calling a function.
   // An argument is assumed to be non-const-ref when the function is unresolved.
@@ -239,7 +257,8 @@
   // findFunctionArgMutation which has additional smarts for handling forwarding
   // references.
   const auto NonConstRefParam = forEachArgumentWithParam(
-  equalsNode(Exp), parmVarDecl(hasType(no

[PATCH] D36824: [mips] Rename getSupportedNanEncoding() to getIEEE754Standard() (NFC)

[Petar Jovanovic via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL311454: [mips] Rename getSupportedNanEncoding() to 
getIEEE754Standard() (authored by petarj).

Changed prior to commit:
  https://reviews.llvm.org/D36824?vs=112150&id=112166#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D36824

Files:
  cfe/trunk/lib/Basic/Targets/Mips.h
  cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
  cfe/trunk/lib/Driver/ToolChains/Arch/Mips.h

Index: cfe/trunk/lib/Basic/Targets/Mips.h
===
--- cfe/trunk/lib/Basic/Targets/Mips.h
+++ cfe/trunk/lib/Basic/Targets/Mips.h
@@ -77,7 +77,7 @@
 Triple.getOS() == llvm::Triple::OpenBSD;
   }
 
-  bool isNaN2008Default() const {
+  bool isIEEE754_2008Default() const {
 return CPU == "mips32r6" || CPU == "mips64r6";
   }
 
@@ -299,7 +299,7 @@
 DiagnosticsEngine &Diags) override {
 IsMips16 = false;
 IsMicromips = false;
-IsNan2008 = isNaN2008Default();
+IsNan2008 = isIEEE754_2008Default();
 IsSingleFloat = false;
 FloatABI = HardFloat;
 DspRev = NoDSP;
Index: cfe/trunk/lib/Driver/ToolChains/Arch/Mips.h
===
--- cfe/trunk/lib/Driver/ToolChains/Arch/Mips.h
+++ cfe/trunk/lib/Driver/ToolChains/Arch/Mips.h
@@ -24,15 +24,15 @@
 bool isMipsArch(llvm::Triple::ArchType Arch);
 
 namespace mips {
-typedef enum { NanLegacy = 1, Nan2008 = 2 } NanEncoding;
+typedef enum { Legacy = 1, Std2008 = 2 } IEEE754Standard;
 
 enum class FloatABI {
   Invalid,
   Soft,
   Hard,
 };
 
-NanEncoding getSupportedNanEncoding(StringRef &CPU);
+IEEE754Standard getIEEE754Standard(StringRef &CPU);
 bool hasCompactBranches(StringRef &CPU);
 void getMipsCPUAndABI(const llvm::opt::ArgList &Args,
   const llvm::Triple &Triple, StringRef &CPUName,
Index: cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
===
--- cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
+++ cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -265,14 +265,14 @@
   if (Arg *A = Args.getLastArg(options::OPT_mnan_EQ)) {
 StringRef Val = StringRef(A->getValue());
 if (Val == "2008") {
-  if (mips::getSupportedNanEncoding(CPUName) & mips::Nan2008)
+  if (mips::getIEEE754Standard(CPUName) & mips::Std2008)
 Features.push_back("+nan2008");
   else {
 Features.push_back("-nan2008");
 D.Diag(diag::warn_target_unsupported_nan2008) << CPUName;
   }
 } else if (Val == "legacy") {
-  if (mips::getSupportedNanEncoding(CPUName) & mips::NanLegacy)
+  if (mips::getIEEE754Standard(CPUName) & mips::Legacy)
 Features.push_back("-nan2008");
   else {
 Features.push_back("+nan2008");
@@ -323,27 +323,28 @@
   AddTargetFeature(Args, Features, options::OPT_mmt, options::OPT_mno_mt, "mt");
 }
 
-mips::NanEncoding mips::getSupportedNanEncoding(StringRef &CPU) {
-  // Strictly speaking, mips32r2 and mips64r2 are NanLegacy-only since Nan2008
-  // was first introduced in Release 3. However, other compilers have
-  // traditionally allowed it for Release 2 so we should do the same.
-  return (NanEncoding)llvm::StringSwitch(CPU)
-  .Case("mips1", NanLegacy)
-  .Case("mips2", NanLegacy)
-  .Case("mips3", NanLegacy)
-  .Case("mips4", NanLegacy)
-  .Case("mips5", NanLegacy)
-  .Case("mips32", NanLegacy)
-  .Case("mips32r2", NanLegacy | Nan2008)
-  .Case("mips32r3", NanLegacy | Nan2008)
-  .Case("mips32r5", NanLegacy | Nan2008)
-  .Case("mips32r6", Nan2008)
-  .Case("mips64", NanLegacy)
-  .Case("mips64r2", NanLegacy | Nan2008)
-  .Case("mips64r3", NanLegacy | Nan2008)
-  .Case("mips64r5", NanLegacy | Nan2008)
-  .Case("mips64r6", Nan2008)
-  .Default(NanLegacy);
+mips::IEEE754Standard mips::getIEEE754Standard(StringRef &CPU) {
+  // Strictly speaking, mips32r2 and mips64r2 do not conform to the
+  // IEEE754-2008 standard. Support for this standard was first introduced
+  // in Release 3. However, other compilers have traditionally allowed it
+  // for Release 2 so we should do the same.
+  return (IEEE754Standard)llvm::StringSwitch(CPU)
+  .Case("mips1", Legacy)
+  .Case("mips2", Legacy)
+  .Case("mips3", Legacy)
+  .Case("mips4", Legacy)
+  .Case("mips5", Legacy)
+  .Case("mips32", Legacy)
+  .Case("mips32r2", Legacy | Std2008)
+  .Case("mips32r3", Legacy | Std2008)
+  .Case("mips32r5", Legacy | Std2008)
+  .Case("mips32r6", Std2008)
+  .Case("mips64", Legacy)
+  .Case("mips64r2", Legacy | Std2008)
+  .Case("mips64r3", Legacy | Std2008)
+  .Case("mips64r5", Legacy | Std2008)
+  .Case("mips64r6", Std2008)
+  .Default(Std2008);
 }
 
 bool mips::hasCompactBranches(StringRef &CPU) {
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[PATCH] D35982: [mips] Introducing option -mabs=[legacy/2008]

[Petar Jovanovic via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL311669: [mips] Introducing option -mabs=[legacy/2008] 
(authored by petarj).

Changed prior to commit:
  https://reviews.llvm.org/D35982?vs=112534&id=112571#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D35982

Files:
  cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
  cfe/trunk/include/clang/Basic/DiagnosticGroups.td
  cfe/trunk/include/clang/Driver/Options.td
  cfe/trunk/lib/Basic/Targets/Mips.cpp
  cfe/trunk/lib/Basic/Targets/Mips.h
  cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
  cfe/trunk/test/Driver/mips-features.c
  cfe/trunk/test/Driver/mips-mabs-warning.c
  cfe/trunk/test/Preprocessor/init.c

Index: cfe/trunk/lib/Basic/Targets/Mips.cpp
===
--- cfe/trunk/lib/Basic/Targets/Mips.cpp
+++ cfe/trunk/lib/Basic/Targets/Mips.cpp
@@ -149,6 +149,9 @@
   if (IsNan2008)
 Builder.defineMacro("__mips_nan2008", Twine(1));
 
+  if (IsAbs2008)
+Builder.defineMacro("__mips_abs2008", Twine(1));
+
   switch (DspRev) {
   default:
 break;
Index: cfe/trunk/lib/Basic/Targets/Mips.h
===
--- cfe/trunk/lib/Basic/Targets/Mips.h
+++ cfe/trunk/lib/Basic/Targets/Mips.h
@@ -46,6 +46,7 @@
   bool IsMips16;
   bool IsMicromips;
   bool IsNan2008;
+  bool IsAbs2008;
   bool IsSingleFloat;
   bool IsNoABICalls;
   bool CanUseBSDABICalls;
@@ -61,9 +62,9 @@
 public:
   MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
   : TargetInfo(Triple), IsMips16(false), IsMicromips(false),
-IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false),
-CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP),
-HasMSA(false), DisableMadd4(false), HasFP64(false) {
+IsNan2008(false), IsAbs2008(false), IsSingleFloat(false),
+IsNoABICalls(false), CanUseBSDABICalls(false), FloatABI(HardFloat),
+DspRev(NoDSP), HasMSA(false), DisableMadd4(false), HasFP64(false) {
 TheCXXABI.set(TargetCXXABI::GenericMIPS);
 
 setABI((getTriple().getArch() == llvm::Triple::mips ||
@@ -300,6 +301,7 @@
 IsMips16 = false;
 IsMicromips = false;
 IsNan2008 = isIEEE754_2008Default();
+IsAbs2008 = isIEEE754_2008Default();
 IsSingleFloat = false;
 FloatABI = HardFloat;
 DspRev = NoDSP;
@@ -330,6 +332,10 @@
 IsNan2008 = true;
   else if (Feature == "-nan2008")
 IsNan2008 = false;
+  else if (Feature == "+abs2008")
+IsAbs2008 = true;
+  else if (Feature == "-abs2008")
+IsAbs2008 = false;
   else if (Feature == "+noabicalls")
 IsNoABICalls = true;
 }
Index: cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
===
--- cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
+++ cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -283,6 +283,28 @@
   << A->getOption().getName() << Val;
   }
 
+  if (Arg *A = Args.getLastArg(options::OPT_mabs_EQ)) {
+StringRef Val = StringRef(A->getValue());
+if (Val == "2008") {
+  if (mips::getIEEE754Standard(CPUName) & mips::Std2008) {
+Features.push_back("+abs2008");
+  } else {
+Features.push_back("-abs2008");
+D.Diag(diag::warn_target_unsupported_abs2008) << CPUName;
+  }
+} else if (Val == "legacy") {
+  if (mips::getIEEE754Standard(CPUName) & mips::Legacy) {
+Features.push_back("-abs2008");
+  } else {
+Features.push_back("+abs2008");
+D.Diag(diag::warn_target_unsupported_abslegacy) << CPUName;
+  }
+} else {
+  D.Diag(diag::err_drv_unsupported_option_argument)
+  << A->getOption().getName() << Val;
+}
+  }
+
   AddTargetFeature(Args, Features, options::OPT_msingle_float,
options::OPT_mdouble_float, "single-float");
   AddTargetFeature(Args, Features, options::OPT_mips16, options::OPT_mno_mips16,
Index: cfe/trunk/include/clang/Driver/Options.td
===
--- cfe/trunk/include/clang/Driver/Options.td
+++ cfe/trunk/include/clang/Driver/Options.td
@@ -2066,6 +2066,7 @@
   HelpText<"Do not place constants in the .rodata section instead of the "
".sdata if they meet the -G  threshold (MIPS)">;
 def mnan_EQ : Joined<["-"], "mnan=">, Group;
+def mabs_EQ : Joined<["-"], "mabs=">, Group;
 def mabicalls : Flag<["-"], "mabicalls">, Group,
   HelpText<"Enable SVR4-style position-independent code (Mips only)">;
 def mno_abicalls : Flag<["-"], "mno-abicalls">, Group,
Index: cfe/trunk/include/clang/Basic/DiagnosticGroups.td
===
--- cfe/trunk/include/clang/Basic/DiagnosticGroups.td
+++ cfe/trunk/include/clang/Basic/DiagnosticGroups.td
@@ -61,6 +61,7 @@
 def DoublePromotion : DiagGroup<"double-promotion">;
 def EnumTooLarge : DiagGroup<"enum-too-large

[PATCH] D31082: [mips][msa] Range adjustment for ldi_b builtin function operand

[Petar Jovanovic via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL299229: [mips][msa] Range adjustment for ldi_b builtin 
function operand (authored by petarj).

Changed prior to commit:
  https://reviews.llvm.org/D31082?vs=92439&id=93669#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D31082

Files:
  cfe/trunk/lib/Sema/SemaChecking.cpp
  cfe/trunk/test/CodeGen/builtins-mips-msa-error.c
  cfe/trunk/test/CodeGen/builtins-mips-msa.c


Index: cfe/trunk/lib/Sema/SemaChecking.cpp
===
--- cfe/trunk/lib/Sema/SemaChecking.cpp
+++ cfe/trunk/lib/Sema/SemaChecking.cpp
@@ -1640,7 +1640,7 @@
   case Mips::BI__builtin_msa_sldi_d: i = 2; l = 0; u = 1; break;
   // Memory offsets and immediate loads.
   // These intrinsics take a signed 10 bit immediate.
-  case Mips::BI__builtin_msa_ldi_b: i = 0; l = -128; u = 127; break;
+  case Mips::BI__builtin_msa_ldi_b: i = 0; l = -128; u = 255; break;
   case Mips::BI__builtin_msa_ldi_h:
   case Mips::BI__builtin_msa_ldi_w:
   case Mips::BI__builtin_msa_ldi_d: i = 0; l = -512; u = 511; break;
Index: cfe/trunk/test/CodeGen/builtins-mips-msa-error.c
===
--- cfe/trunk/test/CodeGen/builtins-mips-msa-error.c
+++ cfe/trunk/test/CodeGen/builtins-mips-msa-error.c
@@ -119,7 +119,7 @@
   v4i32_r = __msa_ld_w(&v4i32_a, 512);   // expected-error 
{{argument should be a value from -512 to 511}}
   v2i64_r = __msa_ld_d(&v2i64_a, 512);   // expected-error 
{{argument should be a value from -512 to 511}}
 
-  v16i8_r = __msa_ldi_b(512);// expected-error 
{{argument should be a value from -512 to 511}}
+  v16i8_r = __msa_ldi_b(256);// expected-error 
{{argument should be a value from -128 to 255}}
   v8i16_r = __msa_ldi_h(512);// expected-error 
{{argument should be a value from -512 to 511}}
   v4i32_r = __msa_ldi_w(512);// expected-error 
{{argument should be a value from -512 to 511}}
   v2i64_r = __msa_ldi_d(512);// expected-error 
{{argument should be a value from -512 to 511}}
@@ -310,7 +310,7 @@
   v4i32_r = __msa_ld_w(&v4i32_a, -513);  // expected-error 
{{argument should be a value from -512 to 511}}
   v2i64_r = __msa_ld_d(&v2i64_a, -513);  // expected-error 
{{argument should be a value from -512 to 511}}
 
-  v16i8_r = __msa_ldi_b(-513);   // expected-error 
{{argument should be a value from -512 to 511}}
+  v16i8_r = __msa_ldi_b(-129);   // expected-error 
{{argument should be a value from -128 to 255}}
   v8i16_r = __msa_ldi_h(-513);   // expected-error 
{{argument should be a value from -512 to 511}}
   v4i32_r = __msa_ldi_w(-513);   // expected-error 
{{argument should be a value from -512 to 511}}
   v2i64_r = __msa_ldi_d(-513);   // expected-error 
{{argument should be a value from -512 to 511}}
Index: cfe/trunk/test/CodeGen/builtins-mips-msa.c
===
--- cfe/trunk/test/CodeGen/builtins-mips-msa.c
+++ cfe/trunk/test/CodeGen/builtins-mips-msa.c
@@ -526,6 +526,8 @@
   v2i64_r = __msa_ld_d(&v2i64_a, 96); // CHECK: call <2  x i64> 
@llvm.mips.ld.d(
 
   v16i8_r = __msa_ldi_b(3); // CHECK: call <16 x i8>  @llvm.mips.ldi.b(
+  v16i8_r = __msa_ldi_b(-128); // CHECK: call <16 x i8>  @llvm.mips.ldi.b(
+  v16i8_r = __msa_ldi_b(255); // CHECK: call <16 x i8>  @llvm.mips.ldi.b(
   v8i16_r = __msa_ldi_h(3); // CHECK: call <8  x i16> @llvm.mips.ldi.h(
   v4i32_r = __msa_ldi_w(3); // CHECK: call <4  x i32> @llvm.mips.ldi.w(
   v2i64_r = __msa_ldi_d(3); // CHECK: call <2  x i64> @llvm.mips.ldi.d(


Index: cfe/trunk/lib/Sema/SemaChecking.cpp
===
--- cfe/trunk/lib/Sema/SemaChecking.cpp
+++ cfe/trunk/lib/Sema/SemaChecking.cpp
@@ -1640,7 +1640,7 @@
   case Mips::BI__builtin_msa_sldi_d: i = 2; l = 0; u = 1; break;
   // Memory offsets and immediate loads.
   // These intrinsics take a signed 10 bit immediate.
-  case Mips::BI__builtin_msa_ldi_b: i = 0; l = -128; u = 127; break;
+  case Mips::BI__builtin_msa_ldi_b: i = 0; l = -128; u = 255; break;
   case Mips::BI__builtin_msa_ldi_h:
   case Mips::BI__builtin_msa_ldi_w:
   case Mips::BI__builtin_msa_ldi_d: i = 0; l = -512; u = 511; break;
Index: cfe/trunk/test/CodeGen/builtins-mips-msa-error.c
===
--- cfe/trunk/test/CodeGen/builtins-mips-msa-error.c
+++ cfe/trunk/test/CodeGen/builtins-mips-msa-error.c
@@ -119,7 +119,7 @@
   v4i32_r = __msa_ld_w(&v4i32_a, 512);   // expected-error {{argument should be a value from -512 to 511}}
   v2i64_r = __msa_ld_d(&v2i64_a, 512);   // expected-error {{argument should be a value from -51

[PATCH] D35406: [clangd] Replace ASTUnit with manual AST management.

[Petar Jovanovic via Phabricator via cfe-commits]

petarj added a comment.

Can you check if this change introduced clang-x86-windows-msvc2015 buildbot 
failure 
?


Repository:
  rL LLVM

https://reviews.llvm.org/D35406



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[PATCH] D39053: [Bitfield] Add more cases to making the bitfield a separate location

[Petar Jovanovic via Phabricator via cfe-commits]

petarj added a comment.

This sounds as a valid improvement. Can we have this code committed?


https://reviews.llvm.org/D39053



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[PATCH] D30693: [mips][msa] Remove range checks for non-immediate sld.[bhwd] instructions

[Petar Jovanovic via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL297485: [mips][msa] Remove range checks for non-immediate 
sld.[bhwd] instructions (authored by petarj).

Changed prior to commit:
  https://reviews.llvm.org/D30693?vs=91158&id=91372#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D30693

Files:
  cfe/trunk/lib/Sema/SemaChecking.cpp
  cfe/trunk/test/CodeGen/builtins-mips-msa-error.c
  cfe/trunk/test/CodeGen/builtins-mips-msa.c


Index: cfe/trunk/lib/Sema/SemaChecking.cpp
===
--- cfe/trunk/lib/Sema/SemaChecking.cpp
+++ cfe/trunk/lib/Sema/SemaChecking.cpp
@@ -1619,28 +1619,24 @@
   case Mips::BI__builtin_msa_copy_u_b:
   case Mips::BI__builtin_msa_insve_b:
   case Mips::BI__builtin_msa_splati_b: i = 1; l = 0; u = 15; break;
-  case Mips::BI__builtin_msa_sld_b:
   case Mips::BI__builtin_msa_sldi_b: i = 2; l = 0; u = 15; break;
   // These intrinsics take an unsigned 3 bit immediate.
   case Mips::BI__builtin_msa_copy_s_h:
   case Mips::BI__builtin_msa_copy_u_h:
   case Mips::BI__builtin_msa_insve_h:
   case Mips::BI__builtin_msa_splati_h: i = 1; l = 0; u = 7; break;
-  case Mips::BI__builtin_msa_sld_h:
   case Mips::BI__builtin_msa_sldi_h: i = 2; l = 0; u = 7; break;
   // These intrinsics take an unsigned 2 bit immediate.
   case Mips::BI__builtin_msa_copy_s_w:
   case Mips::BI__builtin_msa_copy_u_w:
   case Mips::BI__builtin_msa_insve_w:
   case Mips::BI__builtin_msa_splati_w: i = 1; l = 0; u = 3; break;
-  case Mips::BI__builtin_msa_sld_w:
   case Mips::BI__builtin_msa_sldi_w: i = 2; l = 0; u = 3; break;
   // These intrinsics take an unsigned 1 bit immediate.
   case Mips::BI__builtin_msa_copy_s_d:
   case Mips::BI__builtin_msa_copy_u_d:
   case Mips::BI__builtin_msa_insve_d:
   case Mips::BI__builtin_msa_splati_d: i = 1; l = 0; u = 1; break;
-  case Mips::BI__builtin_msa_sld_d:
   case Mips::BI__builtin_msa_sldi_d: i = 2; l = 0; u = 1; break;
   // Memory offsets and immediate loads.
   // These intrinsics take a signed 10 bit immediate.
Index: cfe/trunk/test/CodeGen/builtins-mips-msa.c
===
--- cfe/trunk/test/CodeGen/builtins-mips-msa.c
+++ cfe/trunk/test/CodeGen/builtins-mips-msa.c
@@ -699,6 +699,11 @@
   v4i32_r = __msa_sld_w(v4i32_r, v4i32_a, 3); // CHECK: call <4  x i32> 
@llvm.mips.sld.w(
   v2i64_r = __msa_sld_d(v2i64_r, v2i64_a, 1); // CHECK: call <2  x i64> 
@llvm.mips.sld.d(
 
+  v16i8_r = __msa_sld_b(v16i8_r, v16i8_a, 16); // CHECK: call <16 x i8>  
@llvm.mips.sld.b(
+  v8i16_r = __msa_sld_h(v8i16_r, v8i16_a, 8); // CHECK: call <8  x i16> 
@llvm.mips.sld.h(
+  v4i32_r = __msa_sld_w(v4i32_r, v4i32_a, 4); // CHECK: call <4  x i32> 
@llvm.mips.sld.w(
+  v2i64_r = __msa_sld_d(v2i64_r, v2i64_a, 2); // CHECK: call <2  x i64> 
@llvm.mips.sld.d(
+
   v16i8_r = __msa_sldi_b(v16i8_r, v16i8_a, 7); // CHECK: call <16 x i8>  
@llvm.mips.sldi.b(
   v8i16_r = __msa_sldi_h(v8i16_r, v8i16_a, 3); // CHECK: call <8  x i16> 
@llvm.mips.sldi.h(
   v4i32_r = __msa_sldi_w(v4i32_r, v4i32_a, 2); // CHECK: call <4  x i32> 
@llvm.mips.sldi.w(
Index: cfe/trunk/test/CodeGen/builtins-mips-msa-error.c
===
--- cfe/trunk/test/CodeGen/builtins-mips-msa-error.c
+++ cfe/trunk/test/CodeGen/builtins-mips-msa-error.c
@@ -162,11 +162,6 @@
   v8i16_r = __msa_shf_h(v8i16_a, 256);   // CHECK: warning: 
argument should be a value from 0 to 255}}
   v4i32_r = __msa_shf_w(v4i32_a, 256);   // CHECK: warning: 
argument should be a value from 0 to 255}}
 
-  v16i8_r = __msa_sld_b(v16i8_r, v16i8_a, 16);  // expected-error 
{{argument should be a value from 0 to 15}}
-  v8i16_r = __msa_sld_h(v8i16_r, v8i16_a, 8);   // expected-error 
{{argument should be a value from 0 to 7}}
-  v4i32_r = __msa_sld_w(v4i32_r, v4i32_a, 4);   // expected-error 
{{argument should be a value from 0 to 3}}
-  v2i64_r = __msa_sld_d(v2i64_r, v2i64_a, 2);   // expected-error 
{{argument should be a value from 0 to 1}}
-
   v16i8_r = __msa_sldi_b(v16i8_r, v16i8_a, 16);  // expected-error 
{{argument should be a value from 0 to 15}}
   v8i16_r = __msa_sldi_h(v8i16_r, v8i16_a, 8);   // expected-error 
{{argument should be a value from 0 to 7}}
   v4i32_r = __msa_sldi_w(v4i32_r, v4i32_a, 4);   // expected-error 
{{argument should be a value from 0 to 3}}
@@ -358,11 +353,6 @@
   v8i16_r = __msa_shf_h(v8i16_a, -1);// CHECK: warning: 
argument should be a value from 0 to 255}}
   v4i32_r = __msa_shf_w(v4i32_a, -1);// CHECK: warning: 
argument should be a value from 0 to 255}}
 
-  v16i8_r = __msa_sld_b(v16i8_r, v16i8_a, -17);  // expected-error 
{{argument should be a value from 0 to 15}}
-  v8i16_r = __msa_sld_h(v8i16_r, v8i16_a, -8);   // expected-error 
{{argument should be a value from 0 to 7}}
-  v4i32_r = __msa_sld_w(v4i32_r, v4i32_a, -4);  

[PATCH] D32900: [mips] Impose a threshold for coercion of aggregates

[Petar Jovanovic via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL302547: [mips] Impose a threshold for coercion of aggregates 
(authored by petarj).

Changed prior to commit:
  https://reviews.llvm.org/D32900?vs=98269&id=98304#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D32900

Files:
  cfe/trunk/lib/CodeGen/TargetInfo.cpp
  cfe/trunk/test/CodeGen/mips-aggregate-arg.c


Index: cfe/trunk/test/CodeGen/mips-aggregate-arg.c
===
--- cfe/trunk/test/CodeGen/mips-aggregate-arg.c
+++ cfe/trunk/test/CodeGen/mips-aggregate-arg.c
@@ -0,0 +1,38 @@
+// RUN: %clang_cc1 -triple mipsel-unknown-linux-gnu -S -emit-llvm -o - %s | 
FileCheck -check-prefix=O32 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s  
-target-abi n32 | FileCheck -check-prefix=N32-N64 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s  
-target-abi n64 | FileCheck -check-prefix=N32-N64 %s
+
+struct t1 {
+  char t1[10];
+};
+
+struct t2 {
+  char t2[20];
+};
+
+struct t3 {
+  char t3[65];
+};
+
+extern struct t1 g1;
+extern struct t2 g2;
+extern struct t3 g3;
+extern void f1(struct t1);
+extern void f2(struct t2);
+extern void f3(struct t3);
+
+void f() {
+
+// O32:  call void @f1(i32 inreg %3, i32 inreg %5, i16 inreg %7)
+// O32:  call void @f2(%struct.t2* byval align 4 %tmp)
+// O32:  call void @f3(%struct.t3* byval align 4 %tmp1)
+
+// N32-N64:  call void @f1(i64 inreg %3, i16 inreg %5)
+// N32-N64:  call void @f2(i64 inreg %9, i64 inreg %11, i32 inreg %13)
+// N32-N64:  call void @f3(%struct.t3* byval align 8 %tmp)
+
+  f1(g1);
+  f2(g2);
+  f3(g3);
+}
+
Index: cfe/trunk/lib/CodeGen/TargetInfo.cpp
===
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp
@@ -6695,6 +6695,14 @@
   return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
 }
 
+// Use indirect if the aggregate cannot fit into registers for
+// passing arguments according to the ABI
+unsigned Threshold = IsO32 ? 16 : 64;
+
+if(getContext().getTypeSizeInChars(Ty) > 
CharUnits::fromQuantity(Threshold))
+  return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align), true,
+ getContext().getTypeAlign(Ty) / 8 > 
Align);
+
 // If we have reached here, aggregates are passed directly by coercing to
 // another structure type. Padding is inserted if the offset of the
 // aggregate is unaligned.


Index: cfe/trunk/test/CodeGen/mips-aggregate-arg.c
===
--- cfe/trunk/test/CodeGen/mips-aggregate-arg.c
+++ cfe/trunk/test/CodeGen/mips-aggregate-arg.c
@@ -0,0 +1,38 @@
+// RUN: %clang_cc1 -triple mipsel-unknown-linux-gnu -S -emit-llvm -o - %s | FileCheck -check-prefix=O32 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s  -target-abi n32 | FileCheck -check-prefix=N32-N64 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s  -target-abi n64 | FileCheck -check-prefix=N32-N64 %s
+
+struct t1 {
+  char t1[10];
+};
+
+struct t2 {
+  char t2[20];
+};
+
+struct t3 {
+  char t3[65];
+};
+
+extern struct t1 g1;
+extern struct t2 g2;
+extern struct t3 g3;
+extern void f1(struct t1);
+extern void f2(struct t2);
+extern void f3(struct t3);
+
+void f() {
+
+// O32:  call void @f1(i32 inreg %3, i32 inreg %5, i16 inreg %7)
+// O32:  call void @f2(%struct.t2* byval align 4 %tmp)
+// O32:  call void @f3(%struct.t3* byval align 4 %tmp1)
+
+// N32-N64:  call void @f1(i64 inreg %3, i16 inreg %5)
+// N32-N64:  call void @f2(i64 inreg %9, i64 inreg %11, i32 inreg %13)
+// N32-N64:  call void @f3(%struct.t3* byval align 8 %tmp)
+
+  f1(g1);
+  f2(g2);
+  f3(g3);
+}
+
Index: cfe/trunk/lib/CodeGen/TargetInfo.cpp
===
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp
@@ -6695,6 +6695,14 @@
   return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
 }
 
+// Use indirect if the aggregate cannot fit into registers for
+// passing arguments according to the ABI
+unsigned Threshold = IsO32 ? 16 : 64;
+
+if(getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(Threshold))
+  return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align), true,
+ getContext().getTypeAlign(Ty) / 8 > Align);
+
 // If we have reached here, aggregates are passed directly by coercing to
 // another structure type. Padding is inserted if the offset of the
 // aggregate is unaligned.
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