[clang] be881e2 - [AArch64] FMLA/FMLS patterns improvement.
Author: Pavel Iliin
Date: 2020-04-21T18:23:21+01:00
New Revision: be881e2831735d6879ee43710f5a4d1c8d50c615
URL:
https://github.com/llvm/llvm-project/commit/be881e2831735d6879ee43710f5a4d1c8d50c615
DIFF:
https://github.com/llvm/llvm-project/commit/be881e2831735d6879ee43710f5a4d1c8d50c615.diff
LOG: [AArch64] FMLA/FMLS patterns improvement.
FMLA/FMLS f16 indexed patterns added.
Fixes https://bugs.llvm.org/show_bug.cgi?id=45467
Removed redundant v2f32 vector_extract indexed pattern since
Instruction Selection is able to match v4f32 instead.
Added:
Modified:
clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-constrained.c
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll
Removed:
diff --git a/clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-constrained.c
b/clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-constrained.c
index d7830f71e2de..b72bd3f977dd 100644
--- a/clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-constrained.c
+++ b/clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-constrained.c
@@ -89,7 +89,7 @@ float16x8_t test_vfmsq_f16(float16x8_t a, float16x8_t b,
float16x8_t c) {
// COMMONIR: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
// UNCONSTRAINED: [[FMLA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half>
[[TMP4]], <4 x half> [[LANE]], <4 x half> [[TMP5]])
// CONSTRAINED: [[FMLA:%.*]] = call <4 x half>
@llvm.experimental.constrained.fma.v4f16(<4 x half> [[TMP4]], <4 x half>
[[LANE]], <4 x half> [[TMP5]], metadata !"round.tonearest", metadata
!"fpexcept.strict")
-// CHECK-ASM: fmla v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
+// CHECK-ASM: fmla v{{[0-9]+}}.4h, v{{[0-9]+}}.4h,
v{{[0-9]+}}.h[{{[0-9]+}}]
// COMMONIR: ret <4 x half> [[FMLA]]
float16x4_t test_vfma_lane_f16(float16x4_t a, float16x4_t b, float16x4_t c) {
return vfma_lane_f16(a, b, c, 3);
@@ -105,7 +105,7 @@ float16x4_t test_vfma_lane_f16(float16x4_t a, float16x4_t
b, float16x4_t c) {
// COMMONIR: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
// UNCONSTRAINED: [[FMLA:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half>
[[TMP4]], <8 x half> [[LANE]], <8 x half> [[TMP5]])
// CONSTRAINED: [[FMLA:%.*]] = call <8 x half>
@llvm.experimental.constrained.fma.v8f16(<8 x half> [[TMP4]], <8 x half>
[[LANE]], <8 x half> [[TMP5]], metadata !"round.tonearest", metadata
!"fpexcept.strict")
-// CHECK-ASM: fmla v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
+// CHECK-ASM: fmla v{{[0-9]+}}.8h, v{{[0-9]+}}.8h,
v{{[0-9]+}}.h[{{[0-9]+}}]
// COMMONIR: ret <8 x half> [[FMLA]]
float16x8_t test_vfmaq_lane_f16(float16x8_t a, float16x8_t b, float16x4_t c) {
return vfmaq_lane_f16(a, b, c, 3);
@@ -137,7 +137,7 @@ float16x4_t test_vfma_laneq_f16(float16x4_t a, float16x4_t
b, float16x8_t c) {
// COMMONIR: [[LANE:%.*]] = shufflevector <8 x half> [[TMP5]], <8 x half>
[[TMP5]], <8 x i32>
// UNCONSTRAINED: [[FMLA:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half>
[[LANE]], <8 x half> [[TMP4]], <8 x half> [[TMP3]])
// CONSTRAINED: [[FMLA:%.*]] = call <8 x half>
@llvm.experimental.constrained.fma.v8f16(<8 x half> [[LANE]], <8 x half>
[[TMP4]], <8 x half> [[TMP3]], metadata !"round.tonearest", metadata
!"fpexcept.strict")
-// CHECK-ASM: fmla v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
+// CHECK-ASM: fmla v{{[0-9]+}}.8h, v{{[0-9]+}}.8h,
v{{[0-9]+}}.h[{{[0-9]+}}]
// COMMONIR: ret <8 x half> [[FMLA]]
float16x8_t test_vfmaq_laneq_f16(float16x8_t a, float16x8_t b, float16x8_t c) {
return vfmaq_laneq_f16(a, b, c, 7);
@@ -150,7 +150,7 @@ float16x8_t test_vfmaq_laneq_f16(float16x8_t a, float16x8_t
b, float16x8_t c) {
// COMMONIR: [[TMP3:%.*]] = insertelement <4 x half> [[TMP2]], half %c,
i32 3
// UNCONSTRAINED: [[FMA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half>
%b, <4 x half> [[TMP3]], <4 x half> %a)
// CONSTRAINED: [[FMA:%.*]] = call <4 x half>
@llvm.experimental.constrained.fma.v4f16(<4 x half> %b, <4 x half> [[TMP3]], <4
x half> %a, metadata !"round.tonearest", metadata !"fpexcept.strict")
-// CHECK-ASM: fmla v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
+// CHECK-ASM: fmla v{{[0-9]+}}.4h, v{{[0-9]+}}.4h,
v{{[0-9]+}}.h[{{[0-9]+}}]
// COMMONIR: ret <4 x half> [[FMA]]
float16x4_t test_vfma_n_f16(float16x4_t a, float16x4_t b, float16_t c) {
return vfma_n_f16(a, b, c);
@@ -167,7 +167,7 @@ float16x4_t test_vfma_n_f16(float16x4_t a, float16x4_t b,
float16_t c) {
// COMMONIR: [[TMP7:%.*]] = insertelement <8 x half> [[TMP6]], half %c,
i32 7
// UNCONSTRAINED: [[FMA:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half>
%b, <8 x half> [[TMP7]], <8 x half> %a)
// CONSTRAINED: [[FMA:%.*]] = call <8 x half>
@llvm.experimental.constrained.fma.v8f16(<8 x half> %b, <8 x half> [[TMP7]], <8
x half> %a, metadata !"round.tonearest", metadata !"fpexcept.strict")
-//
[clang] 4eca1c0 - [AArch64][FIX] f16 indexed patterns encoding restrictions.
Author: Pavel Iliin
Date: 2020-04-22T14:11:28+01:00
New Revision: 4eca1c06a4a9183fcf7bb230d894617caf3cf3be
URL:
https://github.com/llvm/llvm-project/commit/4eca1c06a4a9183fcf7bb230d894617caf3cf3be
DIFF:
https://github.com/llvm/llvm-project/commit/4eca1c06a4a9183fcf7bb230d894617caf3cf3be.diff
LOG: [AArch64][FIX] f16 indexed patterns encoding restrictions.
Added:
Modified:
clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-constrained.c
llvm/lib/Target/AArch64/AArch64InstrFormats.td
Removed:
diff --git a/clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-constrained.c
b/clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-constrained.c
index b72bd3f977dd..6058e6f92832 100644
--- a/clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-constrained.c
+++ b/clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-constrained.c
@@ -121,7 +121,7 @@ float16x8_t test_vfmaq_lane_f16(float16x8_t a, float16x8_t
b, float16x4_t c) {
// COMMONIR: [[LANE:%.*]] = shufflevector <8 x half> [[TMP5]], <8 x half>
[[TMP5]], <4 x i32>
// UNCONSTRAINED: [[FMLA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half>
[[LANE]], <4 x half> [[TMP4]], <4 x half> [[TMP3]])
// CONSTRAINED: [[FMLA:%.*]] = call <4 x half>
@llvm.experimental.constrained.fma.v4f16(<4 x half> [[LANE]], <4 x half>
[[TMP4]], <4 x half> [[TMP3]], metadata !"round.tonearest", metadata
!"fpexcept.strict")
-// CHECK-ASM: fmla v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
+// CHECK-ASM: fmla v{{[0-9]+}}.4h, v{{[0-9]+}}.4h,
v{{[0-9]+}}.h[{{[0-9]+}}]
// COMMONIR: ret <4 x half> [[FMLA]]
float16x4_t test_vfma_laneq_f16(float16x4_t a, float16x4_t b, float16x8_t c) {
return vfma_laneq_f16(a, b, c, 7);
@@ -239,7 +239,7 @@ float16x8_t test_vfmsq_lane_f16(float16x8_t a, float16x8_t
b, float16x4_t c) {
// COMMONIR: [[LANE:%.*]] = shufflevector <8 x half> [[TMP5]], <8 x half>
[[TMP5]], <4 x i32>
// UNCONSTRAINED: [[FMLA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half>
[[LANE]], <4 x half> [[TMP4]], <4 x half> [[TMP3]])
// CONSTRAINED: [[FMLA:%.*]] = call <4 x half>
@llvm.experimental.constrained.fma.v4f16(<4 x half> [[LANE]], <4 x half>
[[TMP4]], <4 x half> [[TMP3]], metadata !"round.tonearest", metadata
!"fpexcept.strict")
-// CHECK-ASM: fmls v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
+// CHECK-ASM: fmls v{{[0-9]+}}.4h, v{{[0-9]+}}.4h,
v{{[0-9]+}}.h[{{[0-9]+}}]
// COMMONIR: ret <4 x half> [[FMLA]]
float16x4_t test_vfms_laneq_f16(float16x4_t a, float16x4_t b, float16x8_t c) {
return vfms_laneq_f16(a, b, c, 7);
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 061e2a0ec619..29422fa650e6 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -8068,29 +8068,29 @@ multiclass SIMDFPIndexedTiedPatterns {
let Predicates = [HasNEON, HasFullFP16] in {
// Patterns for f16: DUPLANE, DUP scalar and vector_extract.
def : Pat<(v8f16 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn),
- (AArch64duplane16 (v8f16 V128:$Rm),
+ (AArch64duplane16 (v8f16 V128_lo:$Rm),
VectorIndexH:$idx))),
(!cast(INST # "v8i16_indexed")
-V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexH:$idx)>;
+V128:$Rd, V128:$Rn, V128_lo:$Rm, VectorIndexH:$idx)>;
def : Pat<(v8f16 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn),
(AArch64dup (f16 FPR16Op:$Rm,
(!cast(INST # "v8i16_indexed") V128:$Rd, V128:$Rn,
(SUBREG_TO_REG (i32 0), FPR16Op:$Rm, hsub), (i64 0))>;
def : Pat<(v4f16 (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn),
- (AArch64duplane16 (v8f16 V128:$Rm),
- VectorIndexS:$idx))),
+ (AArch64duplane16 (v8f16 V128_lo:$Rm),
+ VectorIndexH:$idx))),
(!cast(INST # "v4i16_indexed")
-V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
+V64:$Rd, V64:$Rn, V128_lo:$Rm, VectorIndexH:$idx)>;
def : Pat<(v4f16 (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn),
(AArch64dup (f16 FPR16Op:$Rm,
(!cast(INST # "v4i16_indexed") V64:$Rd, V64:$Rn,
(SUBREG_TO_REG (i32 0), FPR16Op:$Rm, hsub), (i64 0))>;
def : Pat<(f16 (OpNode (f16 FPR16:$Rd), (f16 FPR16:$Rn),
- (vector_extract (v8f16 V128:$Rm),
VectorIndexH:$idx))),
+ (vector_extract (v8f16 V128_lo:$Rm),
VectorIndexH:$idx))),
(!cast(INST # "v1i16_indexed") FPR16:$Rd, FPR16:$Rn,
-V128:$Rm, VectorIndexH:$idx)>;
+V128_lo:$Rm, VectorIndexH:$idx)>;
} // Predicates = [HasNEON, HasFullFP16]
/
[llvm] [compiler-rt] [clang] [AArch64][SME] Add support for sme-fa64 (PR #70809)
@@ -248,8 +250,9 @@ inline constexpr ExtensionInfo Extensions[] = {
{"simd", AArch64::AEK_SIMD, "+neon", "-neon", FEAT_SIMD,
"+fp-armv8,+neon", 100},
{"sm4", AArch64::AEK_SM4, "+sm4", "-sm4", FEAT_SM4,
"+sm4,+fp-armv8,+neon", 60},
{"sme-f16f16", AArch64::AEK_SMEF16F16, "+sme-f16f16", "-sme-f16f16",
FEAT_INIT, "", 0},
-{"sme-f64f64", AArch64::AEK_SMEF64F64, "+sme-f64f64", "-sme-f64f64",
FEAT_SME_F64, "+sme,+sme-f64f64,+bf16", 560},
-{"sme-i16i64", AArch64::AEK_SMEI16I64, "+sme-i16i64", "-sme-i16i64",
FEAT_SME_I64, "+sme,+sme-i16i64,+bf16", 570},
+{"sme-f64f64", AArch64::AEK_SMEF64F64, "+sme-f64f64", "-sme-f64f64",
FEAT_SME_F64, "+sme,+sme-f64f64,+bf16", 560},
+{"sme-i16i64", AArch64::AEK_SMEI16I64, "+sme-i16i64", "-sme-i16i64",
FEAT_SME_I64, "+sme,+sme-i16i64,+bf16", 570},
+{"sme-fa64", AArch64::AEK_SMEFA64, "+sme-fa64", "-sme-fa64",
FEAT_SME_FA64, "+sve2", 580},
ilinpv wrote:
sme-f16f16 is not supported by Function Multi Versioning. All features
supported by FMV with priorities should be specified in ACLE:
https://github.com/ARM-software/acle/blob/main/main/acle.md#function-multi-versioning
I am not sure if we need support for sme-fa64 in FMV, probably
@DanielKristofKiss can clarify.
https://github.com/llvm/llvm-project/pull/70809
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[compiler-rt] [llvm] [clang] [AArch64][SME] Add support for sme-fa64 (PR #70809)
@@ -293,6 +295,7 @@ inline constexpr ExtensionInfo Extensions[] = {
{"sme-lutv2", AArch64::AEK_SME_LUTv2, "+sme-lutv2", "-sme-lutv2",
FEAT_INIT, "", 0},
{"sme-f8f16", AArch64::AEK_SMEF8F16, "+sme-f8f16", "-sme-f8f16",
FEAT_INIT, "+sme2,+fp8", 0},
{"sme-f8f32", AArch64::AEK_SMEF8F32, "+sme-f8f32", "-sme-f8f32",
FEAT_INIT, "+sme2,+fp8", 0},
+{"sme-fa64", AArch64::AEK_SMEFA64, "+sme-fa64", "-sme-fa64",
FEAT_INIT, "+sme,+sve2,+simd", 0},
ilinpv wrote:
No need for "+sme,+sve2,+simd" mapping if feature is not in FMV list.
https://github.com/llvm/llvm-project/pull/70809
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[compiler-rt] [clang] [llvm] [AArch64][SME] Add support for sme-fa64 (PR #70809)
@@ -1363,6 +1367,8 @@ static void __init_cpu_features_constructor(unsigned long hwcap, setCPUFeature(FEAT_SME_I64); if (hwcap2 & HWCAP2_SME_F64F64) setCPUFeature(FEAT_SME_F64); + if (hwcap2 & HWCAP2_SME_FA64) +setCPUFeature(FEAT_SME_FA64); ilinpv wrote: We don't need FEAT_SME_FA64 in CPUFeatures enums if we are not supporting it in FMV. https://github.com/llvm/llvm-project/pull/70809 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [compiler-rt] [AArch64][SME] Add support for sme-fa64 (PR #70809)
@@ -1363,6 +1367,8 @@ static void __init_cpu_features_constructor(unsigned long hwcap, setCPUFeature(FEAT_SME_I64); if (hwcap2 & HWCAP2_SME_F64F64) setCPUFeature(FEAT_SME_F64); + if (hwcap2 & HWCAP2_SME_FA64) +setCPUFeature(FEAT_SME_FA64); ilinpv wrote: I think it is better to remove any code that become unused. https://github.com/llvm/llvm-project/pull/70809 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[compiler-rt] [clang] [llvm] [AArch64][SME] Add support for sme-fa64 (PR #70809)
@@ -1363,6 +1367,8 @@ static void __init_cpu_features_constructor(unsigned long hwcap, setCPUFeature(FEAT_SME_I64); if (hwcap2 & HWCAP2_SME_F64F64) setCPUFeature(FEAT_SME_F64); + if (hwcap2 & HWCAP2_SME_FA64) +setCPUFeature(FEAT_SME_FA64); ilinpv wrote: FEAT_SME_FA64 still left in CPUFeatures in `cpu_model.c` and in `AArch64TargetParser.h` Remove it please. https://github.com/llvm/llvm-project/pull/70809 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [compiler-rt] [clang] [AArch64][SME] Add support for sme-fa64 (PR #70809)
https://github.com/ilinpv edited https://github.com/llvm/llvm-project/pull/70809 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [compiler-rt] [clang] [AArch64][SME] Add support for sme-fa64 (PR #70809)
https://github.com/ilinpv approved this pull request. LGTM overall, thanks, just address one nit above. https://github.com/llvm/llvm-project/pull/70809 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [compiler-rt] [AArch64][SME] Add support for sme-fa64 (PR #70809)
@@ -293,6 +294,7 @@ inline constexpr ExtensionInfo Extensions[] = {
{"sme-lutv2", AArch64::AEK_SME_LUTv2, "+sme-lutv2", "-sme-lutv2",
FEAT_INIT, "", 0},
{"sme-f8f16", AArch64::AEK_SMEF8F16, "+sme-f8f16", "-sme-f8f16",
FEAT_INIT, "+sme2,+fp8", 0},
{"sme-f8f32", AArch64::AEK_SMEF8F32, "+sme-f8f32", "-sme-f8f32",
FEAT_INIT, "+sme2,+fp8", 0},
+{"sme-fa64", AArch64::AEK_SMEFA64, "+sme-fa64", "-sme-fa64",
FEAT_INIT, "", 0},
ilinpv wrote:
Small nit: remove extra space before FEAT_INIT here
https://github.com/llvm/llvm-project/pull/70809
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[clang] [lldb] [compiler-rt] [flang] [mlir] [libcxx] [lld] [llvm] [builtins] Refactor cpu_model support to reduce #if nesting. NFCI (PR #75635)
https://github.com/ilinpv commented: Thanks a lot for refactoring! It indeed becomes necessary and looks well-structured now, small nit - rename lse_atomics/fucsia.inc and fmv/fucsia.inc files as well. https://github.com/llvm/llvm-project/pull/75635 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [TargetParser] Define AEK_FCMA and AEK_JSCVT for tsv110 (PR #75516)
@@ -81,6 +81,15 @@ static bool DecodeAArch64Features(const Driver &D, StringRef text, else return false; +// +jsconv and +complxnum implies +neon and +fp-armv8 ilinpv wrote: I don't think we need these implications. Features dependencies are already set in llvm/lib/Target/AArch64/AArch64.td `def FeatureComplxNum : SubtargetFeature< "complxnum", "HasComplxNum", "true", "Enable v8.3-A Floating-point complex number support (FEAT_FCMA)", [FeatureNEON]>;` `def FeatureJS : SubtargetFeature< "jsconv", "HasJS", "true", "Enable v8.3-A JavaScript FP conversion instructions (FEAT_JSCVT)", [FeatureFPARMv8]>;` https://github.com/llvm/llvm-project/pull/75516 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [clang] [llvm] [mlir] [lldb] [compiler-rt] [lld] [flang] [libcxx] [builtins][arm64] Implement __init_cpu_features_resolver on Apple platforms (PR #75636)
@@ -0,0 +1,69 @@
+#include
+#if TARGET_OS_OSX || TARGET_OS_IPHONE
+#include
+#include
+
+static bool isKnownAndSupported(const char *name) {
+ int32_t val = 0;
+ size_t size = sizeof(val);
+ if (sysctlbyname(name, &val, &size, NULL, 0))
+return false;
+ return val;
+}
+
+void __init_cpu_features_resolver(void) {
+ // On Darwin platforms, this may be called concurrently by multiple threads
+ // because the resolvers that use it are called lazily at runtime (unlike on
+ // ELF platforms, where IFuncs are resolved serially at load time). This
+ // function's effect on __aarch64_cpu_features should be idempotent, but even
+ // so we need dispatch_once to resolve the race condition. Dispatch is
+ // available through libSystem, which we need anyway for the sysctl, so this
+ // does not add a new dependency.
+
+ static dispatch_once_t onceToken = 0;
+ dispatch_once(&onceToken, ^{
+//
https://developer.apple.com/documentation/kernel/1387446-sysctlbyname/determining_instruction_set_characteristics
+static struct {
+ const char *sysctl_name;
+ enum CPUFeatures feature;
+} features[] = {
ilinpv wrote:
> Any word on when FMV might come out of beta?
There's no specific deadline right now, possibly within a year or half - we
want to collect and address all feedback on FMV from partners and compilers
communities.
https://github.com/llvm/llvm-project/pull/75636
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[clang] [llvm] [CodeGen][AArch64][FMV] PAC the stub_helper's frame on arm64e (PR #84704)
@@ -0,0 +1,58 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --function-signature --check-attributes --check-globals
--include-generated-funcs
+// RUN: %clang_cc1 -triple arm64e-apple-ios -target-feature +ls64
-target-feature +fullfp16 -S -emit-llvm -o - %s | FileCheck %s
+
+int __attribute__((target_version("sha1"))) fmv(void) { return 1; }
+int __attribute__((target_version("default"))) fmv(void) { return 0; }
+int foo() {
+ return fmv();
+}
+
+//.
+// CHECK: @__aarch64_cpu_features = external dso_local global { i64 }
+// CHECK: @fmv.ifunc = weak_odr alias i32 (), ptr @fmv
+// CHECK: @fmv = weak_odr ifunc i32 (), ptr @fmv.resolver
+//.
+// CHECK: Function Attrs: noinline nounwind optnone
+// CHECK-LABEL: define {{[^@]+}}@fmv._Msha1
+// CHECK-SAME: () #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:ret i32 1
+//
+//
+// CHECK: Function Attrs: noinline nounwind optnone
+// CHECK-LABEL: define {{[^@]+}}@foo
+// CHECK-SAME: () #[[ATTR1:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[CALL:%.*]] = call i32 @fmv()
+// CHECK-NEXT:ret i32 [[CALL]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@fmv.resolver
+// CHECK-SAME: () #[[ATTR2:[0-9]+]] {
+// CHECK-NEXT: resolver_entry:
+// CHECK-NEXT:call void @__init_cpu_features_resolver()
+// CHECK-NEXT:[[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = and i64 [[TMP0]], 2048
+// CHECK-NEXT:[[TMP2:%.*]] = icmp eq i64 [[TMP1]], 2048
+// CHECK-NEXT:[[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-NEXT:br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label
[[RESOLVER_ELSE:%.*]]
+// CHECK: resolver_return:
+// CHECK-NEXT:ret ptr @fmv._Msha1
+// CHECK: resolver_else:
+// CHECK-NEXT:ret ptr @fmv.default
ilinpv wrote:
Looks useful for arm64 as well, could you reveal more details on the machinery
and approach to PAC resolver?
https://github.com/llvm/llvm-project/pull/84704
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[clang] [FMV] Allow target version definitions in any order. (PR #83887)
https://github.com/ilinpv approved this pull request. Thanks for tests! https://github.com/llvm/llvm-project/pull/83887 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [NFC][Docs] Documenting __builtin_cpu_supports. (PR #84098)
https://github.com/ilinpv created
https://github.com/llvm/llvm-project/pull/84098
None
>From 528af71d043d306a4aeb5c448a0780fa42644c15 Mon Sep 17 00:00:00 2001
From: Pavel Iliin
Date: Wed, 6 Mar 2024 00:23:36 +
Subject: [PATCH] [NFC][Docs] Documenting __builtin_cpu_supports.
---
clang/docs/LanguageExtensions.rst | 28
1 file changed, 28 insertions(+)
diff --git a/clang/docs/LanguageExtensions.rst
b/clang/docs/LanguageExtensions.rst
index bcd69198eafdbe..f939d1c765e91a 100644
--- a/clang/docs/LanguageExtensions.rst
+++ b/clang/docs/LanguageExtensions.rst
@@ -2799,6 +2799,34 @@ counter's true frequency will need to be provided by the
user.
Query for this feature with ``__has_builtin(__builtin_readsteadycounter)``.
+``__builtin_cpu_supports``
+--
+
+**Syntax**:
+
+.. code-block:: c++
+
+ int __builtin_cpu_supports(const char *features);
+
+**Example of Use:**:
+
+.. code-block:: c++
+
+ if (__builtin_cpu_supports("sve"))
+sve_code();
+
+**Description**:
+
+The ``__builtin_cpu_supports`` function detects at runtime if target CPU
+supports features specified in string argument. It returns positive integer
+if all features are supported and 0 otherwise. Names of features and format is
+target specific. For example on AArch64 features are combined using ``+`` like
+this ``__builtin_cpu_supports("flagm+sha3+lse+rcpc2+fcma+memtag+bti+sme2")``.
+If feature name is not supported or format is wrong, compiler will issue a
+warning and replace builtin by constant 0.
+
+Query for this feature with ``__has_builtin(__builtin_cpu_supports)``.
+
``__builtin_dump_struct``
-
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[clang] [compiler-rt] [AArch64] Implement __builtin_cpu_supports, compiler-rt tests. (PR #82378)
ilinpv wrote: Documentation update https://github.com/llvm/llvm-project/pull/84098 https://github.com/llvm/llvm-project/pull/82378 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [NFC][Docs] Documenting __builtin_cpu_supports. (PR #84098)
@@ -2799,6 +2799,34 @@ counter's true frequency will need to be provided by the
user.
Query for this feature with ``__has_builtin(__builtin_readsteadycounter)``.
+``__builtin_cpu_supports``
+--
+
+**Syntax**:
+
+.. code-block:: c++
+
+ int __builtin_cpu_supports(const char *features);
+
+**Example of Use:**:
+
+.. code-block:: c++
+
+ if (__builtin_cpu_supports("sve"))
+sve_code();
+
+**Description**:
+
+The ``__builtin_cpu_supports`` function detects at runtime if target CPU
+supports features specified in string argument. It returns positive integer
+if all features are supported and 0 otherwise. Names of features and format is
+target specific. For example on AArch64 features are combined using ``+`` like
+this ``__builtin_cpu_supports("flagm+sha3+lse+rcpc2+fcma+memtag+bti+sme2")``.
+If feature name is not supported or format is wrong, compiler will issue a
+warning and replace builtin by constant 0.
+
+Query for this feature with ``__has_builtin(__builtin_cpu_supports)``.
ilinpv wrote:
ah, articles 🤦 Thanks for grammar fix
https://github.com/llvm/llvm-project/pull/84098
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[clang] [NFC][Docs] Documenting __builtin_cpu_supports. (PR #84098)
https://github.com/ilinpv updated
https://github.com/llvm/llvm-project/pull/84098
>From 528af71d043d306a4aeb5c448a0780fa42644c15 Mon Sep 17 00:00:00 2001
From: Pavel Iliin
Date: Wed, 6 Mar 2024 00:23:36 +
Subject: [PATCH 1/2] [NFC][Docs] Documenting __builtin_cpu_supports.
---
clang/docs/LanguageExtensions.rst | 28
1 file changed, 28 insertions(+)
diff --git a/clang/docs/LanguageExtensions.rst
b/clang/docs/LanguageExtensions.rst
index bcd69198eafdbe..f939d1c765e91a 100644
--- a/clang/docs/LanguageExtensions.rst
+++ b/clang/docs/LanguageExtensions.rst
@@ -2799,6 +2799,34 @@ counter's true frequency will need to be provided by the
user.
Query for this feature with ``__has_builtin(__builtin_readsteadycounter)``.
+``__builtin_cpu_supports``
+--
+
+**Syntax**:
+
+.. code-block:: c++
+
+ int __builtin_cpu_supports(const char *features);
+
+**Example of Use:**:
+
+.. code-block:: c++
+
+ if (__builtin_cpu_supports("sve"))
+sve_code();
+
+**Description**:
+
+The ``__builtin_cpu_supports`` function detects at runtime if target CPU
+supports features specified in string argument. It returns positive integer
+if all features are supported and 0 otherwise. Names of features and format is
+target specific. For example on AArch64 features are combined using ``+`` like
+this ``__builtin_cpu_supports("flagm+sha3+lse+rcpc2+fcma+memtag+bti+sme2")``.
+If feature name is not supported or format is wrong, compiler will issue a
+warning and replace builtin by constant 0.
+
+Query for this feature with ``__has_builtin(__builtin_cpu_supports)``.
+
``__builtin_dump_struct``
-
>From 165d1f0a360f47c2419eef1c4ab1c54d826b609a Mon Sep 17 00:00:00 2001
From: Pavel Iliin
Date: Wed, 6 Mar 2024 11:19:20 +
Subject: [PATCH 2/2] Update clang/docs/LanguageExtensions.rst
Co-authored-by: Jon Roelofs
---
clang/docs/LanguageExtensions.rst | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/clang/docs/LanguageExtensions.rst
b/clang/docs/LanguageExtensions.rst
index f939d1c765e91a..96b76273c71166 100644
--- a/clang/docs/LanguageExtensions.rst
+++ b/clang/docs/LanguageExtensions.rst
@@ -2817,13 +2817,13 @@ Query for this feature with
``__has_builtin(__builtin_readsteadycounter)``.
**Description**:
-The ``__builtin_cpu_supports`` function detects at runtime if target CPU
-supports features specified in string argument. It returns positive integer
-if all features are supported and 0 otherwise. Names of features and format is
+The ``__builtin_cpu_supports`` function detects at runtime if the target CPU
+supports features specified in string argument. It returns a positive integer
+if all features are supported and 0 otherwise. Names of features and format are
target specific. For example on AArch64 features are combined using ``+`` like
this ``__builtin_cpu_supports("flagm+sha3+lse+rcpc2+fcma+memtag+bti+sme2")``.
-If feature name is not supported or format is wrong, compiler will issue a
-warning and replace builtin by constant 0.
+If a feature name is not supported or the format is wrong, the compiler will
issue a
+warning and replace builtin by the constant 0.
Query for this feature with ``__has_builtin(__builtin_cpu_supports)``.
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[clang] [NFC][Docs] Documenting __builtin_cpu_supports. (PR #84098)
https://github.com/ilinpv updated
https://github.com/llvm/llvm-project/pull/84098
>From 528af71d043d306a4aeb5c448a0780fa42644c15 Mon Sep 17 00:00:00 2001
From: Pavel Iliin
Date: Wed, 6 Mar 2024 00:23:36 +
Subject: [PATCH 1/3] [NFC][Docs] Documenting __builtin_cpu_supports.
---
clang/docs/LanguageExtensions.rst | 28
1 file changed, 28 insertions(+)
diff --git a/clang/docs/LanguageExtensions.rst
b/clang/docs/LanguageExtensions.rst
index bcd69198eafdbe..f939d1c765e91a 100644
--- a/clang/docs/LanguageExtensions.rst
+++ b/clang/docs/LanguageExtensions.rst
@@ -2799,6 +2799,34 @@ counter's true frequency will need to be provided by the
user.
Query for this feature with ``__has_builtin(__builtin_readsteadycounter)``.
+``__builtin_cpu_supports``
+--
+
+**Syntax**:
+
+.. code-block:: c++
+
+ int __builtin_cpu_supports(const char *features);
+
+**Example of Use:**:
+
+.. code-block:: c++
+
+ if (__builtin_cpu_supports("sve"))
+sve_code();
+
+**Description**:
+
+The ``__builtin_cpu_supports`` function detects at runtime if target CPU
+supports features specified in string argument. It returns positive integer
+if all features are supported and 0 otherwise. Names of features and format is
+target specific. For example on AArch64 features are combined using ``+`` like
+this ``__builtin_cpu_supports("flagm+sha3+lse+rcpc2+fcma+memtag+bti+sme2")``.
+If feature name is not supported or format is wrong, compiler will issue a
+warning and replace builtin by constant 0.
+
+Query for this feature with ``__has_builtin(__builtin_cpu_supports)``.
+
``__builtin_dump_struct``
-
>From 165d1f0a360f47c2419eef1c4ab1c54d826b609a Mon Sep 17 00:00:00 2001
From: Pavel Iliin
Date: Wed, 6 Mar 2024 11:19:20 +
Subject: [PATCH 2/3] Update clang/docs/LanguageExtensions.rst
Co-authored-by: Jon Roelofs
---
clang/docs/LanguageExtensions.rst | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/clang/docs/LanguageExtensions.rst
b/clang/docs/LanguageExtensions.rst
index f939d1c765e91a..96b76273c71166 100644
--- a/clang/docs/LanguageExtensions.rst
+++ b/clang/docs/LanguageExtensions.rst
@@ -2817,13 +2817,13 @@ Query for this feature with
``__has_builtin(__builtin_readsteadycounter)``.
**Description**:
-The ``__builtin_cpu_supports`` function detects at runtime if target CPU
-supports features specified in string argument. It returns positive integer
-if all features are supported and 0 otherwise. Names of features and format is
+The ``__builtin_cpu_supports`` function detects at runtime if the target CPU
+supports features specified in string argument. It returns a positive integer
+if all features are supported and 0 otherwise. Names of features and format are
target specific. For example on AArch64 features are combined using ``+`` like
this ``__builtin_cpu_supports("flagm+sha3+lse+rcpc2+fcma+memtag+bti+sme2")``.
-If feature name is not supported or format is wrong, compiler will issue a
-warning and replace builtin by constant 0.
+If a feature name is not supported or the format is wrong, the compiler will
issue a
+warning and replace builtin by the constant 0.
Query for this feature with ``__has_builtin(__builtin_cpu_supports)``.
>From 280583a3f8fabb544b549feffbd4e7bb27808bc3 Mon Sep 17 00:00:00 2001
From: Pavel Iliin
Date: Wed, 6 Mar 2024 15:48:58 +
Subject: [PATCH 3/3] Addressing comments to __builtin_cpu_supports
description.
---
clang/docs/LanguageExtensions.rst | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/clang/docs/LanguageExtensions.rst
b/clang/docs/LanguageExtensions.rst
index 96b76273c71166..2b54dffd058a35 100644
--- a/clang/docs/LanguageExtensions.rst
+++ b/clang/docs/LanguageExtensions.rst
@@ -2817,13 +2817,13 @@ Query for this feature with
``__has_builtin(__builtin_readsteadycounter)``.
**Description**:
-The ``__builtin_cpu_supports`` function detects at runtime if the target CPU
-supports features specified in string argument. It returns a positive integer
-if all features are supported and 0 otherwise. Names of features and format are
-target specific. For example on AArch64 features are combined using ``+`` like
-this ``__builtin_cpu_supports("flagm+sha3+lse+rcpc2+fcma+memtag+bti+sme2")``.
-If a feature name is not supported or the format is wrong, the compiler will
issue a
-warning and replace builtin by the constant 0.
+The ``__builtin_cpu_supports`` function detects if the run-time CPU supports
+features specified in string argument. It returns a positive integer if all
+features are supported and 0 otherwise. Feature names are target specific. On
+AArch64 features are combined using ``+`` like this
+``__builtin_cpu_supports("flagm+sha3+lse+rcpc2+fcma+memtag+bti+sme2")``.
+If a feature name is not supported, Clang will issue a warning and replace
+builtin by the constant 0.
Query for this feature with ``__has_builtin(__bu
[clang] [NFC][Docs] Documenting __builtin_cpu_supports. (PR #84098)
ilinpv wrote: Thanks @MaskRay for valuable comments, all addressed. https://github.com/llvm/llvm-project/pull/84098 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [NFC][Docs] Documenting __builtin_cpu_supports. (PR #84098)
https://github.com/ilinpv closed https://github.com/llvm/llvm-project/pull/84098 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [AArch64] Implement __builtin_cpu_supports, compiler-rt tests. (PR #82378)
ilinpv wrote: @alexfh thanks for example, clang doesn't compile that on x86 before patch as well. It looks like a bug in GCC that it happily compiles the builtin above on x86. https://github.com/llvm/llvm-project/pull/82378 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86][AArch64][PowerPC] __builtin_cpu_supports accepts unknown options. (PR #83515)
https://github.com/ilinpv created
https://github.com/llvm/llvm-project/pull/83515
The patch fixes https://github.com/llvm/llvm-project/issues/83407 modifing
__builtin_cpu_supports behaviour so that it returns false if unsupported
features names provided in parameter and issue a warning.
__builtin_cpu_supports is target independent, but currently supported by X86,
AArch64 and PowerPC only.
>From 6cd58223b59f7a78dc349c63e27d7771a20f0f1a Mon Sep 17 00:00:00 2001
From: Pavel Iliin
Date: Fri, 1 Mar 2024 01:46:53 +
Subject: [PATCH] [X86][AArch64][PowerPC] __builtin_cpu_supports accepts
unknown options.
The patch fixes https://github.com/llvm/llvm-project/issues/83407
modifing __builtin_cpu_supports behaviour so that it returns false if
unsupported features names provided in parameter and issue a warning.
__builtin_cpu_supports is target independent, but currently supported
by X86, AArch64 and PowerPC only.
---
clang/include/clang/Basic/DiagnosticSemaKinds.td | 2 +-
clang/lib/CodeGen/CGBuiltin.cpp | 7 ++-
clang/lib/Sema/SemaChecking.cpp | 8 +---
clang/test/CodeGen/aarch64-cpu-supports.c| 8
clang/test/Misc/warning-flags.c | 3 ++-
clang/test/Sema/aarch64-cpu-supports.c | 10 +-
clang/test/Sema/builtin-cpu-supports.c | 6 +++---
7 files changed, 30 insertions(+), 14 deletions(-)
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 4f8902e37bd3bb..938de5859513f8 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -765,7 +765,7 @@ def err_builtin_redeclare : Error<"cannot redeclare builtin
function %0">;
def err_arm_invalid_specialreg : Error<"invalid special register for builtin">;
def err_arm_invalid_coproc : Error<"coprocessor %0 must be configured as "
"%select{GCP|CDE}1">;
-def err_invalid_cpu_supports : Error<"invalid cpu feature string for builtin">;
+def warn_invalid_cpu_supports : Warning<"invalid cpu feature string for
builtin">;
def err_invalid_cpu_is : Error<"invalid cpu name for builtin">;
def err_invalid_cpu_specific_dispatch_value : Error<
"invalid option '%0' for %select{cpu_specific|cpu_dispatch}1">;
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 98684448f4ff5c..e90014261217bc 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -13952,6 +13952,8 @@ Value *CodeGenFunction::EmitX86CpuIs(StringRef CPUStr) {
Value *CodeGenFunction::EmitX86CpuSupports(const CallExpr *E) {
const Expr *FeatureExpr = E->getArg(0)->IgnoreParenCasts();
StringRef FeatureStr = cast(FeatureExpr)->getString();
+ if (!getContext().getTargetInfo().validateCpuSupports(FeatureStr))
+return Builder.getFalse();
return EmitX86CpuSupports(FeatureStr);
}
@@ -14041,6 +14043,8 @@ Value *CodeGenFunction::EmitAArch64CpuSupports(const
CallExpr *E) {
ArgStr.split(Features, "+");
for (auto &Feature : Features) {
Feature = Feature.trim();
+if (!llvm::AArch64::parseArchExtension(Feature))
+ return Builder.getFalse();
if (Feature != "default")
Features.push_back(Feature);
}
@@ -16639,7 +16643,8 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
.Case(Name, {FA_WORD, Bitmask})
#include "llvm/TargetParser/PPCTargetParser.def"
.Default({0, 0});
-assert(BitMask && "Invalid target feature string. Missed by
SemaChecking?");
+if (!BitMask)
+ return Builder.getFalse();
Value *Op0 = llvm::ConstantInt::get(Int32Ty, FeatureWord);
llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_fixed_addr_ld);
Value *TheCall = Builder.CreateCall(F, {Op0}, "cpu_supports");
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 690bdaa63d058b..7be2b31df2413f 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -2180,9 +2180,11 @@ static bool SemaBuiltinCpu(Sema &S, const TargetInfo
&TI, CallExpr *TheCall,
// Check the contents of the string.
StringRef Feature = cast(Arg)->getString();
- if (IsCPUSupports && !TheTI->validateCpuSupports(Feature))
-return S.Diag(TheCall->getBeginLoc(), diag::err_invalid_cpu_supports)
- << Arg->getSourceRange();
+ if (IsCPUSupports && !TheTI->validateCpuSupports(Feature)) {
+S.Diag(TheCall->getBeginLoc(), diag::warn_invalid_cpu_supports)
+<< Arg->getSourceRange();
+return false;
+ }
if (!IsCPUSupports && !TheTI->validateCpuIs(Feature))
return S.Diag(TheCall->getBeginLoc(), diag::err_invalid_cpu_is)
<< Arg->getSourceRange();
diff --git a/clang/test/CodeGen/aarch64-cpu-supports.c
b/clang/test/CodeGen/aarch64-cpu-supports.c
index 872fec6827ef11..c54b7475a3fd5f 100644
--- a/clang/test/CodeGen/aarch64-cpu-supports.c
+++ b/clang/test/CodeGen/aarch64-cpu-supports.c
@@ -34,6
[clang] [compiler-rt] [AArch64] Implement __builtin_cpu_supports, compiler-rt tests. (PR #82378)
ilinpv wrote: Fix on review https://github.com/llvm/llvm-project/pull/83515 The documentation is coming next. https://github.com/llvm/llvm-project/pull/82378 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86][AArch64][PowerPC] __builtin_cpu_supports accepts unknown options. (PR #83515)
https://github.com/ilinpv closed https://github.com/llvm/llvm-project/pull/83515 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [FMV] Allow target version definitions in any order. (PR #83887)
https://github.com/ilinpv edited https://github.com/llvm/llvm-project/pull/83887 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [FMV] Allow target version definitions in any order. (PR #83887)
https://github.com/ilinpv requested changes to this pull request. https://github.com/llvm/llvm-project/pull/83887 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [FMV] Allow target version definitions in any order. (PR #83887)
@@ -11429,6 +11429,16 @@ static bool CheckTargetCausesMultiVersioning(Sema &S,
FunctionDecl *OldFD,
bool &Redeclaration,
NamedDecl *&OldDecl,
LookupResult &Previous) {
+ assert(!OldFD->isMultiVersion() && "Unexpected MultiVersion");
+
+ // The definitions should be allowed in any order. If we have discovered
+ // a new target version and the preceeding was the default, then add the
+ // corresponding attribute to it.
+ if (OldFD->getMultiVersionKind() == MultiVersionKind::None &&
ilinpv wrote:
Should it work for case target_version("default") declared first? It would good
to add tests for various orders of function definition and target_version
attributes.
https://github.com/llvm/llvm-project/pull/83887
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[clang] [FMV] Allow target version definitions in any order. (PR #83887)
@@ -11455,9 +11465,8 @@ static bool CheckTargetCausesMultiVersioning(Sema &S,
FunctionDecl *OldFD,
}
// If this is 'default', permit the forward declaration.
- if (!OldFD->isMultiVersion() &&
- ((NewTA && NewTA->isDefaultVersion() && !OldTA) ||
- (NewTVA && NewTVA->isDefaultVersion() && !OldTVA))) {
+ if ((NewTA && NewTA->isDefaultVersion() && !OldTA) ||
ilinpv wrote:
Seems we are changing "target" attribute semantic here as well that we would
like to avoid, why are we sure that !OldFD->isMultiVersion() is always true ?
https://github.com/llvm/llvm-project/pull/83887
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[clang] [NFC][FMV] Add tests to demonstrate feature priorities. (PR #79455)
https://github.com/ilinpv approved this pull request. LGTM, thanks for additinal FMV tests! https://github.com/llvm/llvm-project/pull/79455 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [FMV] Add alias for FEAT_RDM and change priorities according to ACLE. (PR #79316)
@@ -114,6 +121,10 @@ const AArch64::ArchInfo *AArch64::parseArch(StringRef
Arch) {
}
std::optional AArch64::parseArchExtension(StringRef
ArchExt) {
+ // Resolve aliases first.
+ ArchExt = resolveExtAlias(ArchExt);
ilinpv wrote:
Seems resolving aliases here expands "rdma" alias beyond FMV.
https://github.com/llvm/llvm-project/pull/79316
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[clang] [llvm] [compiler-rt] [AArch64][FMV] Support feature MOPS in Function Multi Versioning. (PR #78788)
@@ -172,6 +172,11 @@ static void __init_cpu_features_constructor(unsigned long hwcap, // ID_AA64ISAR1_EL1.LS64 >= 0b0011 if (extractBits(ftr, 60, 4) >= 0x3) setCPUFeature(FEAT_LS64_ACCDATA); + ilinpv wrote: There is HWCAP2_MOPS support in ELF hwcaps https://docs.kernel.org/arch/arm64/elf_hwcaps.html which can be also used for mops detection if available https://github.com/llvm/llvm-project/pull/78788 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [AArch64][FMV] Support feature MOPS in Function Multi Versioning. (PR #78788)
https://github.com/ilinpv approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/78788 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [AArch64][Clang] Fix linker error for function multiversioning (PR #74358)
https://github.com/ilinpv approved this pull request. https://github.com/llvm/llvm-project/pull/74358 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [AArch64][Clang] Fix linker error for function multiversioning (PR #74358)
@@ -1752,8 +1754,10 @@ static void AppendTargetClonesMangling(const
CodeGenModule &CGM,
const TargetInfo &TI = CGM.getTarget();
if (TI.getTriple().isAArch64()) {
ilinpv wrote:
@jroelofs currently in [FMV
spec](https://github.com/ARM-software/acle/blob/main/main/acle.md#function-multi-versioning):
```
The following attributes trigger the multi version code generation:
__attribute__((target_version("name"))) and
__attribute__((target_clones("name",...))).
These attributes can't be mixed with each other.
```
https://github.com/llvm/llvm-project/pull/74358
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[clang] c5e7e64 - [AArch64][Clang][Linux] Enable out-of-line atomics by default.
Author: Pavel Iliin
Date: 2021-01-29T17:44:45Z
New Revision: c5e7e649d537067dec7111f3de1430d0fc8a4d11
URL:
https://github.com/llvm/llvm-project/commit/c5e7e649d537067dec7111f3de1430d0fc8a4d11
DIFF:
https://github.com/llvm/llvm-project/commit/c5e7e649d537067dec7111f3de1430d0fc8a4d11.diff
LOG: [AArch64][Clang][Linux] Enable out-of-line atomics by default.
Generate outline atomics if compiling for armv8-a non-LSE AArch64 Linux
(including Android) targets to use LSE instructions, if they are available,
at runtime. Library support is checked by clang driver which doesn't enable
outline atomics if no proper libraries (libgcc >= 9.3.1 or compiler-rt) found.
Differential Revision: https://reviews.llvm.org/D93585
Added:
clang/test/Driver/Inputs/aarch64-linux-gnu-tree/gcc-10/lib/gcc/aarch64-unknown-linux-gnu/10/crtbegin.o
clang/test/Driver/Inputs/aarch64-linux-gnu-tree/gcc-10/lib/gcc/aarch64-unknown-linux-gnu/10/libgcc.a
clang/test/Driver/Inputs/aarch64-linux-gnu-tree/gcc-7.5.0/lib/gcc/aarch64-unknown-linux-gnu/7.5.0/crtbegin.o
clang/test/Driver/Inputs/aarch64-linux-gnu-tree/gcc-7.5.0/lib/gcc/aarch64-unknown-linux-gnu/7.5.0/libgcc.a
clang/test/Driver/Inputs/aarch64-linux-gnu-tree/gcc-9.3.0/lib/gcc/aarch64-unknown-linux-gnu/9.3.0/crtbegin.o
clang/test/Driver/Inputs/aarch64-linux-gnu-tree/gcc-9.3.0/lib/gcc/aarch64-unknown-linux-gnu/9.3.0/libgcc.a
clang/test/Driver/Inputs/aarch64-linux-gnu-tree/gcc-9.3.1/lib/gcc/aarch64-unknown-linux-gnu/9.3.1/crtbegin.o
clang/test/Driver/Inputs/aarch64-linux-gnu-tree/gcc-9.3.1/lib/gcc/aarch64-unknown-linux-gnu/9.3.1/libgcc.a
Modified:
clang/include/clang/Driver/ToolChain.h
clang/lib/Driver/ToolChains/Clang.cpp
clang/lib/Driver/ToolChains/Linux.cpp
clang/lib/Driver/ToolChains/Linux.h
clang/test/Driver/aarch64-features.c
Removed:
diff --git a/clang/include/clang/Driver/ToolChain.h
b/clang/include/clang/Driver/ToolChain.h
index 28c37a44e1eb..59fdd2997fec 100644
--- a/clang/include/clang/Driver/ToolChain.h
+++ b/clang/include/clang/Driver/ToolChain.h
@@ -456,6 +456,12 @@ class ToolChain {
/// by default.
virtual bool IsUnwindTablesDefault(const llvm::opt::ArgList &Args) const;
+ /// Test whether this toolchain supports outline atomics by default.
+ virtual bool
+ IsAArch64OutlineAtomicsDefault(const llvm::opt::ArgList &Args) const {
+return false;
+ }
+
/// Test whether this toolchain defaults to PIC.
virtual bool isPICDefault() const = 0;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index 7bac2b1df17d..b0379aece75b 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -6500,6 +6500,10 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
CmdArgs.push_back("-target-feature");
CmdArgs.push_back("-outline-atomics");
}
+ } else if (Triple.isAArch64() &&
+ getToolChain().IsAArch64OutlineAtomicsDefault(Args)) {
+CmdArgs.push_back("-target-feature");
+CmdArgs.push_back("+outline-atomics");
}
if (Args.hasFlag(options::OPT_faddrsig, options::OPT_fno_addrsig,
diff --git a/clang/lib/Driver/ToolChains/Linux.cpp
b/clang/lib/Driver/ToolChains/Linux.cpp
index 9663a7390ada..5f0ce69fc5e6 100644
--- a/clang/lib/Driver/ToolChains/Linux.cpp
+++ b/clang/lib/Driver/ToolChains/Linux.cpp
@@ -836,6 +836,19 @@ bool Linux::isPIEDefault() const {
getTriple().isMusl() || getSanitizerArgs().requiresPIE();
}
+bool Linux::IsAArch64OutlineAtomicsDefault(const ArgList &Args) const {
+ // Outline atomics for AArch64 are supported by compiler-rt
+ // and libgcc since 9.3.1
+ assert(getTriple().isAArch64() && "expected AArch64 target!");
+ ToolChain::RuntimeLibType RtLib = GetRuntimeLibType(Args);
+ if (RtLib == ToolChain::RLT_CompilerRT)
+return true;
+ assert(RtLib == ToolChain::RLT_Libgcc && "unexpected runtime library type!");
+ if (GCCInstallation.getVersion().isOlderThan(9, 3, 1))
+return false;
+ return true;
+}
+
bool Linux::isNoExecStackDefault() const {
return getTriple().isAndroid();
}
diff --git a/clang/lib/Driver/ToolChains/Linux.h
b/clang/lib/Driver/ToolChains/Linux.h
index 6b16b0e64990..a45236bc10d3 100644
--- a/clang/lib/Driver/ToolChains/Linux.h
+++ b/clang/lib/Driver/ToolChains/Linux.h
@@ -36,6 +36,8 @@ class LLVM_LIBRARY_VISIBILITY Linux : public Generic_ELF {
void AddIAMCUIncludeArgs(const llvm::opt::ArgList &DriverArgs,
llvm::opt::ArgStringList &CC1Args) const override;
CXXStdlibType GetDefaultCXXStdlibType() const override;
+ bool
+ IsAArch64OutlineAtomicsDefault(const llvm::opt::ArgList &Args) const
override;
bool isPIEDefault() const override;
bool isNoExecStackDefault() const override;
bool IsMathErrnoDefault() const override;
diff --git
a/clang/test/Driver/Inputs/aarch64-lin
[clang] bf94eac - [AArch64][NFC] Fix aarch64 target features test.
Author: Pavel Iliin Date: 2022-12-20T22:29:16Z New Revision: bf94eac6a3f7c5cd8941956d44c15524fa3751bd URL: https://github.com/llvm/llvm-project/commit/bf94eac6a3f7c5cd8941956d44c15524fa3751bd DIFF: https://github.com/llvm/llvm-project/commit/bf94eac6a3f7c5cd8941956d44c15524fa3751bd.diff LOG: [AArch64][NFC] Fix aarch64 target features test. Added: Modified: clang/test/Driver/aarch64-features.c Removed: diff --git a/clang/test/Driver/aarch64-features.c b/clang/test/Driver/aarch64-features.c index 5c079b62768ae..b5ffc95f26d04 100644 --- a/clang/test/Driver/aarch64-features.c +++ b/clang/test/Driver/aarch64-features.c @@ -13,7 +13,7 @@ // RUN: %clang -target aarch64-linux-android -rtlib=compiler-rt -mno-fmv \ // RUN: -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-FMV-OFF %s -// RUN: %clang -target aarch64-linux-gnu \ +// RUN: %clang -target aarch64-linux-gnu -rtlib=libgcc \ // RUN: -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-FMV-OFF %s // RUN: %clang -target arm64-unknown-linux -rtlib=libgcc \ ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 2184fcf - [AArch64] Fix AArch64TargetParser.def includes for standalone builds.
Author: Pavel Iliin
Date: 2022-12-28T17:38:35Z
New Revision: 2184fcf17ee00a939b3bde98a28ef586c67d6b1a
URL:
https://github.com/llvm/llvm-project/commit/2184fcf17ee00a939b3bde98a28ef586c67d6b1a
DIFF:
https://github.com/llvm/llvm-project/commit/2184fcf17ee00a939b3bde98a28ef586c67d6b1a.diff
LOG: [AArch64] Fix AArch64TargetParser.def includes for standalone builds.
Added:
Modified:
clang/lib/Basic/Targets/AArch64.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index dfbff695b09ad..d3c56e3a3ea6e 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -647,7 +647,7 @@ unsigned
AArch64TargetInfo::multiVersionSortPriority(StringRef Name) const {
#define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE, FMV_ID,
\
DEP_FEATURES, FMV_PRIORITY)
\
.Case(NAME, FMV_PRIORITY)
-#include "../../../../llvm/include/llvm/TargetParser/AArch64TargetParser.def"
+#include "llvm/TargetParser/AArch64TargetParser.def"
;
assert((Name == "none" || Priority < multiVersionFeatureCost()) &&
"FMV priority is out of bounds!");
@@ -666,7 +666,7 @@ bool AArch64TargetInfo::getFeatureDepOptions(StringRef Name,
#define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE, FMV_ID,
\
DEP_FEATURES, FMV_PRIORITY)
\
.Case(NAME, DEP_FEATURES)
-#include "../../../../llvm/include/llvm/TargetParser/AArch64TargetParser.def"
+#include "llvm/TargetParser/AArch64TargetParser.def"
.Default("");
return FeatureVec != "";
}
@@ -676,7 +676,7 @@ bool AArch64TargetInfo::validateCpuSupports(StringRef
FeatureStr) const {
#define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE, FMV_ID,
\
DEP_FEATURES, FMV_PRIORITY)
\
.Case(NAME, llvm::AArch64::FEAT_##FMV_ID)
-#include "../../../../llvm/include/llvm/TargetParser/AArch64TargetParser.def"
+#include "llvm/TargetParser/AArch64TargetParser.def"
.Default(llvm::AArch64::FEAT_MAX);
return Feat != llvm::AArch64::FEAT_MAX;
}
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[clang] 5474d7d - [AArch64] Function multi-versioning release notes added. NFC.
Author: Pavel Iliin
Date: 2023-01-23T18:08:07Z
New Revision: 5474d7d932710c260f03ce6c6387ec9d82bd10e2
URL:
https://github.com/llvm/llvm-project/commit/5474d7d932710c260f03ce6c6387ec9d82bd10e2
DIFF:
https://github.com/llvm/llvm-project/commit/5474d7d932710c260f03ce6c6387ec9d82bd10e2.diff
LOG: [AArch64] Function multi-versioning release notes added. NFC.
Differential Revision: https://reviews.llvm.org/D141606
Added:
Modified:
clang/docs/ReleaseNotes.rst
llvm/docs/ReleaseNotes.rst
Removed:
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index e996858c6830b..080a400726057 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -614,6 +614,15 @@ Attribute Changes in Clang
memory placement. It emits a warning if something in the code provably
prevents
an instance from a read-only memory placement.
+- Introduced new attribute ``__attribute__((target_version("cpu_features")))``
+ and expanded the functionality of the existing attribute
+ ``__attribute__((target_clones("cpu_features1","cpu_features2",...)))`` to
+ support Function Multi Versioning on AArch64 target. It detects at runtime
+ which function versions are supported by CPU and calls the one with highest
+ priority. Refer to `clang attributes
+ `_ for
+ more details.
+
Windows Support
---
- For the MinGW driver, added the options ``-mguard=none``, ``-mguard=cf`` and
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index fbacfefe467cb..53c947dc7cef1 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -133,6 +133,10 @@ Changes to the AArch64 Backend
* Added support for the Neoverse V2 CPU.
* Added support for assembly for RME MEC (Memory Encryption Contexts).
* Added codegen support for the Armv8.3 Complex Number extension.
+* Implemented `Function Multi Versioning
+
`_
+ in accordance with Arm C Language Extensions specification. Currently in Beta
+ state.
Changes to the AMDGPU Backend
-
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[clang] 0b92f85 - Revert "[AArch64] Function multi-versioning release notes added. NFC."
Author: Pavel Iliin
Date: 2023-01-23T18:24:21Z
New Revision: 0b92f852708b64084c39ac98e55de2381a40de0c
URL:
https://github.com/llvm/llvm-project/commit/0b92f852708b64084c39ac98e55de2381a40de0c
DIFF:
https://github.com/llvm/llvm-project/commit/0b92f852708b64084c39ac98e55de2381a40de0c.diff
LOG: Revert "[AArch64] Function multi-versioning release notes added. NFC."
This reverts commit 5474d7d932710c260f03ce6c6387ec9d82bd10e2.
Wrong differential revision link was used.
Added:
Modified:
clang/docs/ReleaseNotes.rst
llvm/docs/ReleaseNotes.rst
Removed:
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 080a400726057..e996858c6830b 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -614,15 +614,6 @@ Attribute Changes in Clang
memory placement. It emits a warning if something in the code provably
prevents
an instance from a read-only memory placement.
-- Introduced new attribute ``__attribute__((target_version("cpu_features")))``
- and expanded the functionality of the existing attribute
- ``__attribute__((target_clones("cpu_features1","cpu_features2",...)))`` to
- support Function Multi Versioning on AArch64 target. It detects at runtime
- which function versions are supported by CPU and calls the one with highest
- priority. Refer to `clang attributes
- `_ for
- more details.
-
Windows Support
---
- For the MinGW driver, added the options ``-mguard=none``, ``-mguard=cf`` and
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 53c947dc7cef1..fbacfefe467cb 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -133,10 +133,6 @@ Changes to the AArch64 Backend
* Added support for the Neoverse V2 CPU.
* Added support for assembly for RME MEC (Memory Encryption Contexts).
* Added codegen support for the Armv8.3 Complex Number extension.
-* Implemented `Function Multi Versioning
-
`_
- in accordance with Arm C Language Extensions specification. Currently in Beta
- state.
Changes to the AMDGPU Backend
-
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[clang] c57eaf1 - [AArch64] Function multi-versioning release notes added. NFC.
Author: Pavel Iliin
Date: 2023-01-23T18:31:22Z
New Revision: c57eaf1c8ce37f52f19f47f61591dd7597a68226
URL:
https://github.com/llvm/llvm-project/commit/c57eaf1c8ce37f52f19f47f61591dd7597a68226
DIFF:
https://github.com/llvm/llvm-project/commit/c57eaf1c8ce37f52f19f47f61591dd7597a68226.diff
LOG: [AArch64] Function multi-versioning release notes added. NFC.
Differential Revision: https://reviews.llvm.org/D142265
Added:
Modified:
clang/docs/ReleaseNotes.rst
llvm/docs/ReleaseNotes.rst
Removed:
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index e996858c6830b..080a400726057 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -614,6 +614,15 @@ Attribute Changes in Clang
memory placement. It emits a warning if something in the code provably
prevents
an instance from a read-only memory placement.
+- Introduced new attribute ``__attribute__((target_version("cpu_features")))``
+ and expanded the functionality of the existing attribute
+ ``__attribute__((target_clones("cpu_features1","cpu_features2",...)))`` to
+ support Function Multi Versioning on AArch64 target. It detects at runtime
+ which function versions are supported by CPU and calls the one with highest
+ priority. Refer to `clang attributes
+ `_ for
+ more details.
+
Windows Support
---
- For the MinGW driver, added the options ``-mguard=none``, ``-mguard=cf`` and
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index fbacfefe467cb..53c947dc7cef1 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -133,6 +133,10 @@ Changes to the AArch64 Backend
* Added support for the Neoverse V2 CPU.
* Added support for assembly for RME MEC (Memory Encryption Contexts).
* Added codegen support for the Armv8.3 Complex Number extension.
+* Implemented `Function Multi Versioning
+
`_
+ in accordance with Arm C Language Extensions specification. Currently in Beta
+ state.
Changes to the AMDGPU Backend
-
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[clang] 6e070c3 - [NFC] Specifing clang namespace for builtins.
Author: Pavel Iliin
Date: 2022-06-18T10:44:25+01:00
New Revision: 6e070c3c9101ac7b7a3736021bff98e9a1f5a362
URL:
https://github.com/llvm/llvm-project/commit/6e070c3c9101ac7b7a3736021bff98e9a1f5a362
DIFF:
https://github.com/llvm/llvm-project/commit/6e070c3c9101ac7b7a3736021bff98e9a1f5a362.diff
LOG: [NFC] Specifing clang namespace for builtins.
Added:
Modified:
clang/lib/CodeGen/CGBuiltin.cpp
Removed:
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index ce4ecc5c3284..48207edfe576 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -1169,141 +1169,141 @@ translateArmToMsvcIntrin(unsigned BuiltinID) {
switch (BuiltinID) {
default:
return None;
- case ARM::BI_BitScanForward:
- case ARM::BI_BitScanForward64:
+ case clang::ARM::BI_BitScanForward:
+ case clang::ARM::BI_BitScanForward64:
return MSVCIntrin::_BitScanForward;
- case ARM::BI_BitScanReverse:
- case ARM::BI_BitScanReverse64:
+ case clang::ARM::BI_BitScanReverse:
+ case clang::ARM::BI_BitScanReverse64:
return MSVCIntrin::_BitScanReverse;
- case ARM::BI_InterlockedAnd64:
+ case clang::ARM::BI_InterlockedAnd64:
return MSVCIntrin::_InterlockedAnd;
- case ARM::BI_InterlockedExchange64:
+ case clang::ARM::BI_InterlockedExchange64:
return MSVCIntrin::_InterlockedExchange;
- case ARM::BI_InterlockedExchangeAdd64:
+ case clang::ARM::BI_InterlockedExchangeAdd64:
return MSVCIntrin::_InterlockedExchangeAdd;
- case ARM::BI_InterlockedExchangeSub64:
+ case clang::ARM::BI_InterlockedExchangeSub64:
return MSVCIntrin::_InterlockedExchangeSub;
- case ARM::BI_InterlockedOr64:
+ case clang::ARM::BI_InterlockedOr64:
return MSVCIntrin::_InterlockedOr;
- case ARM::BI_InterlockedXor64:
+ case clang::ARM::BI_InterlockedXor64:
return MSVCIntrin::_InterlockedXor;
- case ARM::BI_InterlockedDecrement64:
+ case clang::ARM::BI_InterlockedDecrement64:
return MSVCIntrin::_InterlockedDecrement;
- case ARM::BI_InterlockedIncrement64:
+ case clang::ARM::BI_InterlockedIncrement64:
return MSVCIntrin::_InterlockedIncrement;
- case ARM::BI_InterlockedExchangeAdd8_acq:
- case ARM::BI_InterlockedExchangeAdd16_acq:
- case ARM::BI_InterlockedExchangeAdd_acq:
- case ARM::BI_InterlockedExchangeAdd64_acq:
+ case clang::ARM::BI_InterlockedExchangeAdd8_acq:
+ case clang::ARM::BI_InterlockedExchangeAdd16_acq:
+ case clang::ARM::BI_InterlockedExchangeAdd_acq:
+ case clang::ARM::BI_InterlockedExchangeAdd64_acq:
return MSVCIntrin::_InterlockedExchangeAdd_acq;
- case ARM::BI_InterlockedExchangeAdd8_rel:
- case ARM::BI_InterlockedExchangeAdd16_rel:
- case ARM::BI_InterlockedExchangeAdd_rel:
- case ARM::BI_InterlockedExchangeAdd64_rel:
+ case clang::ARM::BI_InterlockedExchangeAdd8_rel:
+ case clang::ARM::BI_InterlockedExchangeAdd16_rel:
+ case clang::ARM::BI_InterlockedExchangeAdd_rel:
+ case clang::ARM::BI_InterlockedExchangeAdd64_rel:
return MSVCIntrin::_InterlockedExchangeAdd_rel;
- case ARM::BI_InterlockedExchangeAdd8_nf:
- case ARM::BI_InterlockedExchangeAdd16_nf:
- case ARM::BI_InterlockedExchangeAdd_nf:
- case ARM::BI_InterlockedExchangeAdd64_nf:
+ case clang::ARM::BI_InterlockedExchangeAdd8_nf:
+ case clang::ARM::BI_InterlockedExchangeAdd16_nf:
+ case clang::ARM::BI_InterlockedExchangeAdd_nf:
+ case clang::ARM::BI_InterlockedExchangeAdd64_nf:
return MSVCIntrin::_InterlockedExchangeAdd_nf;
- case ARM::BI_InterlockedExchange8_acq:
- case ARM::BI_InterlockedExchange16_acq:
- case ARM::BI_InterlockedExchange_acq:
- case ARM::BI_InterlockedExchange64_acq:
+ case clang::ARM::BI_InterlockedExchange8_acq:
+ case clang::ARM::BI_InterlockedExchange16_acq:
+ case clang::ARM::BI_InterlockedExchange_acq:
+ case clang::ARM::BI_InterlockedExchange64_acq:
return MSVCIntrin::_InterlockedExchange_acq;
- case ARM::BI_InterlockedExchange8_rel:
- case ARM::BI_InterlockedExchange16_rel:
- case ARM::BI_InterlockedExchange_rel:
- case ARM::BI_InterlockedExchange64_rel:
+ case clang::ARM::BI_InterlockedExchange8_rel:
+ case clang::ARM::BI_InterlockedExchange16_rel:
+ case clang::ARM::BI_InterlockedExchange_rel:
+ case clang::ARM::BI_InterlockedExchange64_rel:
return MSVCIntrin::_InterlockedExchange_rel;
- case ARM::BI_InterlockedExchange8_nf:
- case ARM::BI_InterlockedExchange16_nf:
- case ARM::BI_InterlockedExchange_nf:
- case ARM::BI_InterlockedExchange64_nf:
+ case clang::ARM::BI_InterlockedExchange8_nf:
+ case clang::ARM::BI_InterlockedExchange16_nf:
+ case clang::ARM::BI_InterlockedExchange_nf:
+ case clang::ARM::BI_InterlockedExchange64_nf:
return MSVCIntrin::_InterlockedExchange_nf;
- case ARM::BI_InterlockedCompareExchange8_acq:
- case ARM::BI_InterlockedCompareExchange16_acq:
- case ARM::BI_InterlockedCompareExchange_acq:
- case ARM::BI_InterlockedCompareExchange64_acq:
+ case clan
[clang] 8ec50d6 - [AArch64] Fix FMV ifunc resolver usage on old Android APIs. Rename internal compiler-rt FMV functions.
Author: Pavel Iliin
Date: 2023-09-29T17:10:48+01:00
New Revision: 8ec50d64464c7e6804827d5f4f298366be535001
URL:
https://github.com/llvm/llvm-project/commit/8ec50d64464c7e6804827d5f4f298366be535001
DIFF:
https://github.com/llvm/llvm-project/commit/8ec50d64464c7e6804827d5f4f298366be535001.diff
LOG: [AArch64] Fix FMV ifunc resolver usage on old Android APIs. Rename
internal compiler-rt FMV functions.
The patch fixes Function Multi Versioning features detection by ifunc
resolver on Android API levels < 30.
Ifunc hwcaps parameters are not supported on Android API levels 23-29,
so all CPU features are set unsupported if they were not initialized
before ifunc resolver call.
There is no support for ifunc on Android API levels < 23, so Function
Multi Versioning is disabled in this case.
Also use two underscore prefix for FMV runtime support functions to
avoid conflict with user program ones.
Differential Revision: https://reviews.llvm.org/D158641
Added:
Modified:
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Driver/ToolChains/Clang.cpp
clang/test/CodeGen/attr-target-clones-aarch64.c
clang/test/CodeGen/attr-target-version.c
clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp
clang/test/CodeGenCXX/attr-target-version.cpp
clang/test/Driver/aarch64-features.c
compiler-rt/lib/builtins/cpu_model.c
Removed:
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index b0fd38408806566..3f68aa2c953c74b 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -13524,7 +13524,7 @@
CodeGenFunction::EmitX86CpuSupports(std::array FeatureMask) {
Value *CodeGenFunction::EmitAArch64CpuInit() {
llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy, false);
llvm::FunctionCallee Func =
- CGM.CreateRuntimeFunction(FTy, "init_cpu_features_resolver");
+ CGM.CreateRuntimeFunction(FTy, "__init_cpu_features_resolver");
cast(Func.getCallee())->setDSOLocal(true);
cast(Func.getCallee())
->setDLLStorageClass(llvm::GlobalValue::DefaultStorageClass);
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index dda6aef641904aa..a694d00b569a590 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -7524,6 +7524,7 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
if (Triple.isAArch64() &&
(Args.hasArg(options::OPT_mno_fmv) ||
+ (Triple.isAndroid() && Triple.isAndroidVersionLT(23)) ||
getToolChain().GetRuntimeLibType(Args) != ToolChain::RLT_CompilerRT)) {
// Disable Function Multiversioning on AArch64 target.
CmdArgs.push_back("-target-feature");
diff --git a/clang/test/CodeGen/attr-target-clones-aarch64.c
b/clang/test/CodeGen/attr-target-clones-aarch64.c
index 4a5e47306c11b81..3f2f2fdd24e8aa7 100644
--- a/clang/test/CodeGen/attr-target-clones-aarch64.c
+++ b/clang/test/CodeGen/attr-target-clones-aarch64.c
@@ -45,7 +45,7 @@ inline int __attribute__((target_clones("fp16",
"sve2-bitperm+fcma", "default"))
// CHECK-NEXT:ret i32 0
// CHECK-LABEL: @ftc.resolver(
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT:call void @init_cpu_features_resolver()
+// CHECK-NEXT:call void @__init_cpu_features_resolver()
// CHECK-NEXT:[[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT:[[TMP1:%.*]] = and i64 [[TMP0]], 16512
// CHECK-NEXT:[[TMP2:%.*]] = icmp eq i64 [[TMP1]], 16512
@@ -77,7 +77,7 @@ inline int __attribute__((target_clones("fp16",
"sve2-bitperm+fcma", "default"))
// CHECK-NEXT:ret i32 1
// CHECK-LABEL: @ftc_def.resolver(
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT:call void @init_cpu_features_resolver()
+// CHECK-NEXT:call void @__init_cpu_features_resolver()
// CHECK-NEXT:[[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT:[[TMP1:%.*]] = and i64 [[TMP0]], 17592186048512
// CHECK-NEXT:[[TMP2:%.*]] = icmp eq i64 [[TMP1]], 17592186048512
@@ -105,7 +105,7 @@ inline int __attribute__((target_clones("fp16",
"sve2-bitperm+fcma", "default"))
// CHECK-NEXT:ret i32 2
// CHECK-LABEL: @ftc_dup1.resolver(
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT:call void @init_cpu_features_resolver()
+// CHECK-NEXT:call void @__init_cpu_features_resolver()
// CHECK-NEXT:[[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT:[[TMP1:%.*]] = and i64 [[TMP0]], 4096
// CHECK-NEXT:[[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4096
@@ -129,7 +129,7 @@ inline int __attribute__((target_clones("fp16",
"sve2-bitperm+fcma", "default"))
// CHECK-NEXT:ret i32 3
// CHECK-LABEL: @ftc_dup2.resolver(
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT:call void @init_cpu_features_resolver()
+// CHECK-NEXT:call void @__init_cpu_features_resolver()
// CHECK-NEXT:[[TMP0:%.*]] =
[clang] [AArch64][FMV] Add rcpc3 support, introduce bits for features extensi… (PR #68104)
https://github.com/ilinpv created
https://github.com/llvm/llvm-project/pull/68104
…on and initialization.
The patch implements FEAT_LRCPC3 support (Load-Acquire RCpc instructions
version 3) in Function Multi Versioning. To maintain compatibility while
features list grows extension bit FEAT_EXT and initialization bit FEAT_INIT are
reserved.
>From 38264c4bb4ca6ce408b3f362dcd5855f6166119c Mon Sep 17 00:00:00 2001
From: Pavel Iliin
Date: Tue, 3 Oct 2023 01:05:08 +0100
Subject: [PATCH] [AArch64][FMV] Add rcpc3 support, introduce bits for features
extension and initialization.
The patch implements FEAT_LRCPC3 support (Load-Acquire RCpc
instructions version 3) in Function Multi Versioning. To maintain
compatibility while features list grows extension bit FEAT_EXT and
initialization bit FEAT_INIT are reserved.
---
clang/test/CodeGen/attr-target-version.c | 54 +-
clang/test/Sema/attr-target-clones-aarch64.c | 2 +-
clang/test/SemaCXX/attr-target-version.cpp| 1 +
compiler-rt/lib/builtins/cpu_model.c | 11 +++-
.../llvm/TargetParser/AArch64TargetParser.h | 55 ++-
5 files changed, 67 insertions(+), 56 deletions(-)
diff --git a/clang/test/CodeGen/attr-target-version.c
b/clang/test/CodeGen/attr-target-version.c
index 8d4a4f137569ccd..a7cd6f7bf802c55 100644
--- a/clang/test/CodeGen/attr-target-version.c
+++ b/clang/test/CodeGen/attr-target-version.c
@@ -35,7 +35,7 @@ inline int __attribute__((target_version("sve+sve-bf16")))
fmv_inline(void) { re
inline int __attribute__((target_version("sve2-aes+sve2-sha3")))
fmv_inline(void) { return 5; }
inline int __attribute__((target_version("sve2+sve2-pmull128+sve2-bitperm")))
fmv_inline(void) { return 9; }
inline int __attribute__((target_version("sve2-sm4+memtag2")))
fmv_inline(void) { return 10; }
-inline int __attribute__((target_version("memtag3"))) fmv_inline(void) {
return 11; }
+inline int __attribute__((target_version("memtag3+rcpc3"))) fmv_inline(void) {
return 11; }
inline int __attribute__((target_version("default"))) fmv_inline(void) {
return 3; }
__attribute__((target_version("ls64"))) int fmv_e(void);
@@ -289,68 +289,68 @@ int hoo(void) {
// CHECK-NEXT:ret ptr @fmv_inline._Msha3Mi8mmMf32mm
// CHECK: resolver_else6:
// CHECK-NEXT:[[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align
8
-// CHECK-NEXT:[[TMP17:%.*]] = and i64 [[TMP16]], 19791209299968
-// CHECK-NEXT:[[TMP18:%.*]] = icmp eq i64 [[TMP17]], 19791209299968
+// CHECK-NEXT:[[TMP17:%.*]] = and i64 [[TMP16]], 288265560523800576
+// CHECK-NEXT:[[TMP18:%.*]] = icmp eq i64 [[TMP17]], 288265560523800576
// CHECK-NEXT:[[TMP19:%.*]] = and i1 true, [[TMP18]]
// CHECK-NEXT:br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label
[[RESOLVER_ELSE8:%.*]]
// CHECK: resolver_return7:
-// CHECK-NEXT:ret ptr @fmv_inline._Msve2-sm4Mmemtag2
+// CHECK-NEXT:ret ptr @fmv_inline._Mrcpc3Mmemtag3
// CHECK: resolver_else8:
// CHECK-NEXT:[[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align
8
-// CHECK-NEXT:[[TMP21:%.*]] = and i64 [[TMP20]], 1236950581248
-// CHECK-NEXT:[[TMP22:%.*]] = icmp eq i64 [[TMP21]], 1236950581248
+// CHECK-NEXT:[[TMP21:%.*]] = and i64 [[TMP20]], 19791209299968
+// CHECK-NEXT:[[TMP22:%.*]] = icmp eq i64 [[TMP21]], 19791209299968
// CHECK-NEXT:[[TMP23:%.*]] = and i1 true, [[TMP22]]
// CHECK-NEXT:br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label
[[RESOLVER_ELSE10:%.*]]
// CHECK: resolver_return9:
-// CHECK-NEXT:ret ptr @fmv_inline._Msve2-aesMsve2-sha3
+// CHECK-NEXT:ret ptr @fmv_inline._Msve2-sm4Mmemtag2
// CHECK: resolver_else10:
// CHECK-NEXT:[[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align
8
-// CHECK-NEXT:[[TMP25:%.*]] = and i64 [[TMP24]], 4295098368
-// CHECK-NEXT:[[TMP26:%.*]] = icmp eq i64 [[TMP25]], 4295098368
+// CHECK-NEXT:[[TMP25:%.*]] = and i64 [[TMP24]], 1236950581248
+// CHECK-NEXT:[[TMP26:%.*]] = icmp eq i64 [[TMP25]], 1236950581248
// CHECK-NEXT:[[TMP27:%.*]] = and i1 true, [[TMP26]]
// CHECK-NEXT:br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label
[[RESOLVER_ELSE12:%.*]]
// CHECK: resolver_return11:
-// CHECK-NEXT:ret ptr @fmv_inline._MditMsve-ebf16
+// CHECK-NEXT:ret ptr @fmv_inline._Msve2-aesMsve2-sha3
// CHECK: resolver_else12:
// CHECK-NEXT:[[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align
8
-// CHECK-NEXT:[[TMP29:%.*]] = and i64 [[TMP28]], 3221225472
-// CHECK-NEXT:[[TMP30:%.*]] = icmp eq i64 [[TMP29]], 3221225472
+// CHECK-NEXT:[[TMP29:%.*]] = and i64 [[TMP28]], 4295098368
+// CHECK-NEXT:[[TMP30:%.*]] = icmp eq i64 [[TMP29]], 4295098368
// CHECK-NEXT:[[TMP31:%.*]] = and i1 true, [[TMP30]]
// CHECK-NEXT:br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label
[[RESOLVER_ELSE14:%.*]]
// CHECK: resolver_return13:
-// CHECK-NEXT:ret ptr @fmv_inline._M
[clang] [AArch64][FMV] Add rcpc3 support, introduce bits for features extensi… (PR #68104)
https://github.com/ilinpv closed https://github.com/llvm/llvm-project/pull/68104 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
https://github.com/ilinpv commented: Except for the AuxTarget question, target independent part looks good to me. Thank you for the patch. https://github.com/llvm/llvm-project/pull/68919 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
https://github.com/ilinpv edited https://github.com/llvm/llvm-project/pull/68919 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema &S,
SourceLocation Loc,
return false;
}
+/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *).
+/// This checks that the target supports __builtin_cpu_supports and
+/// that the string argument is constant and valid.
+static bool SemaBuiltinCpuSupports(Sema &S, const TargetInfo &TI,
+ const TargetInfo *AuxTI, CallExpr *TheCall)
{
+ Expr *Arg = TheCall->getArg(0);
+
+ const TargetInfo *TheTI = nullptr;
+ if (TI.supportsCpuSupports())
+TheTI = &TI;
+ else if (AuxTI && AuxTI->supportsCpuSupports())
+TheTI = AuxTI;
ilinpv wrote:
If these builtins are needed for auxiliary target ( are they ? ) it would good
to have tests for that.
https://github.com/llvm/llvm-project/pull/68919
___
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[clang] [AArch64] Fix FMV crash on unspecified number of parameters function (PR #65671)
https://github.com/ilinpv created
https://github.com/llvm/llvm-project/pull/65671:
Fix Function Multi Versioning crash reported in
https://github.com/llvm/llvm-project/issues/65669
>From 209597f82942f857e6f83da85335d61a6274e278 Mon Sep 17 00:00:00 2001
From: Pavel Iliin
Date: Thu, 7 Sep 2023 21:09:20 +0100
Subject: [PATCH] [AArch64] Fix FMV crash on unspecified number of parameters
function
Fix Function Multi Versioning crash reported in
https://github.com/llvm/llvm-project/issues/65669
---
clang/lib/Sema/SemaDecl.cpp | 28 ++-
clang/test/Sema/attr-target-version.c | 5 +
2 files changed, 20 insertions(+), 13 deletions(-)
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index d94366dac102a2a..027c6c3e4222f07 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -11680,20 +11680,22 @@ static bool CheckMultiVersionFunction(Sema &S,
FunctionDecl *NewFD,
FunctionDecl *OldFD = OldDecl->getAsFunction();
if (!OldFD->isMultiVersion() && MVKind == MultiVersionKind::None) {
-// No target_version attributes mean default
-if (!NewTVA) {
- const auto *OldTVA = OldFD->getAttr();
- if (OldTVA) {
-NewFD->addAttr(TargetVersionAttr::CreateImplicit(
-S.Context, "default", NewFD->getSourceRange()));
-NewFD->setIsMultiVersion();
-OldFD->setIsMultiVersion();
-OldDecl = OldFD;
-Redeclaration = true;
-return true;
- }
+if (NewTVA || !OldFD->getAttr())
+ return false;
+if (!NewFD->getType()->getAs()) {
+ // Multiversion declaration doesn't have prototype.
+ S.Diag(NewFD->getLocation(), diag::err_multiversion_noproto);
+ NewFD->setInvalidDecl();
+} else {
+ // No "target_version" attribute is equivalent to "default" attribute.
+ NewFD->addAttr(TargetVersionAttr::CreateImplicit(
+ S.Context, "default", NewFD->getSourceRange()));
+ NewFD->setIsMultiVersion();
+ OldFD->setIsMultiVersion();
+ OldDecl = OldFD;
+ Redeclaration = true;
}
-return false;
+return true;
}
// Multiversioned redeclarations aren't allowed to omit the attribute, except
diff --git a/clang/test/Sema/attr-target-version.c
b/clang/test/Sema/attr-target-version.c
index 0cfec5ecb49ce7c..587c721de5e3226 100644
--- a/clang/test/Sema/attr-target-version.c
+++ b/clang/test/Sema/attr-target-version.c
@@ -89,3 +89,8 @@ float __attribute__((target_version("rdm"))) rtype(int);
int __attribute__((target_version("sha2"))) combine(void) { return 1; }
// expected-error@+1 {{multiversioned function declaration has a different
calling convention}}
int __attribute__((aarch64_vector_pcs, target_version("sha3"))) combine(void)
{ return 2; }
+
+int __attribute__((target_version("fp+aes+pmull+rcpc"))) unspec_args() {
return -1; }
+// expected-error@+1 {{multiversioned function must have a prototype}}
+int __attribute__((target_version("default"))) unspec_args() { return 0; }
+int cargs() { return unspec_args(); }
___
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[clang] [AArch64] Fix FMV crash on unspecified number of parameters function (PR #65671)
https://github.com/ilinpv review_requested https://github.com/llvm/llvm-project/pull/65671 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [AArch64] Fix FMV crash on unspecified number of parameters function (PR #65671)
https://github.com/ilinpv review_requested https://github.com/llvm/llvm-project/pull/65671 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [AArch64] Fix FMV crash on unspecified number of parameters function (PR #65671)
https://github.com/ilinpv closed https://github.com/llvm/llvm-project/pull/65671 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 124b46a - [NFC][AArch64] Document and improve FMV code.
Author: Pavel Iliin
Date: 2023-03-08T23:22:46Z
New Revision: 124b46a897a7044be3cb49b9e0097d8cca47ba6b
URL:
https://github.com/llvm/llvm-project/commit/124b46a897a7044be3cb49b9e0097d8cca47ba6b
DIFF:
https://github.com/llvm/llvm-project/commit/124b46a897a7044be3cb49b9e0097d8cca47ba6b.diff
LOG: [NFC][AArch64] Document and improve FMV code.
Differential Revision: https://reviews.llvm.org/D145538
Added:
Modified:
clang/include/clang/Basic/TargetInfo.h
clang/lib/AST/ASTContext.cpp
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/AArch64.h
clang/lib/Sema/SemaDeclAttr.cpp
llvm/include/llvm/TargetParser/AArch64TargetParser.h
Removed:
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 1bdee3f416a90..6de5d90b12634 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1333,12 +1333,16 @@ class TargetInfo : public virtual
TransferrableTargetInfo,
}
/// Returns true if feature has an impact on target code
- /// generation and get its dependent options in second argument.
- virtual bool getFeatureDepOptions(StringRef Feature,
-std::string &Options) const {
+ /// generation.
+ virtual bool doesFeatureAffectCodeGen(StringRef Feature) const {
return true;
}
+ /// For given feature return dependent ones.
+ virtual StringRef getFeatureDependencies(StringRef Feature) const {
+return StringRef();
+ }
+
struct BranchProtectionInfo {
LangOptions::SignReturnAddressScopeKind SignReturnAddr =
LangOptions::SignReturnAddressScopeKind::None;
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 1995030eec25f..90448c378458b 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -13456,6 +13456,7 @@ std::vector
ASTContext::filterFunctionTargetVersionAttrs(
TV->getFeatures(Feats);
for (auto &Feature : Feats)
if (Target->validateCpuSupports(Feature.str()))
+ // Use '?' to mark features that came from TargetVersion.
ResFeats.push_back("?" + Feature.str());
return ResFeats;
}
@@ -13525,6 +13526,7 @@ void
ASTContext::getFunctionFeatureMap(llvm::StringMap &FeatureMap,
VersionStr.split(VersionFeatures, "+");
for (auto &VFeature : VersionFeatures) {
VFeature = VFeature.trim();
+ // Use '?' to mark features that came from AArch64 TargetClones.
Features.push_back((StringRef{"?"} + VFeature).str());
}
}
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 9b67becff9e75..7f331004348f1 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -606,16 +606,18 @@ unsigned AArch64TargetInfo::multiVersionFeatureCost()
const {
return llvm::AArch64::ExtensionInfo::MaxFMVPriority;
}
-bool AArch64TargetInfo::getFeatureDepOptions(StringRef Name,
- std::string &FeatureVec) const {
- FeatureVec = "";
- for (const auto &E : llvm::AArch64::Extensions) {
-if (Name == E.Name) {
- FeatureVec = E.DependentFeatures;
- break;
-}
- }
- return FeatureVec != "";
+bool AArch64TargetInfo::doesFeatureAffectCodeGen(StringRef Name) const {
+ auto F = llvm::find_if(llvm::AArch64::Extensions, [&](const auto &E) {
+return Name == E.Name && !E.DependentFeatures.empty();
+ });
+ return F != std::end(llvm::AArch64::Extensions);
+}
+
+StringRef AArch64TargetInfo::getFeatureDependencies(StringRef Name) const {
+ auto F = llvm::find_if(llvm::AArch64::Extensions,
+ [&](const auto &E) { return Name == E.Name; });
+ return F != std::end(llvm::AArch64::Extensions) ? F->DependentFeatures
+ : StringRef();
}
bool AArch64TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
@@ -962,18 +964,18 @@ bool AArch64TargetInfo::initFeatureMap(
}
// Process target and dependent features. This is done in two loops
collecting
- // them into UpdatedFeaturesVec: first to add dependent '+'features,
- // second to add target '+/-'features that can later disable some of
- // features added on the first loop.
+ // them into UpdatedFeaturesVec: first to add dependent '+'features, second
to
+ // add target '+/-'features that can later disable some of features added on
+ // the first loop. Function Multi Versioning features begin with '?'.
for (const auto &Feature : FeaturesVec)
-if ((Feature[0] == '?' || Feature[0] == '+')) {
- std::string Options;
- if (AArch64TargetInfo::getFeatureDepOptions(Feature.substr(1), Options))
{
-SmallVector AttrFeatures;
-StringRef(Options).split(AttrFeatures, ",");
-for (auto F : AttrFeatures)
- UpdatedFeaturesVec.push
[clang] 30b0fdf - [AArch64][FMV] Fix name mangling.
Author: Pavel Iliin
Date: 2023-05-23T13:42:55+01:00
New Revision: 30b0fdfff1931c625babe45cbf9405003c48f8a0
URL:
https://github.com/llvm/llvm-project/commit/30b0fdfff1931c625babe45cbf9405003c48f8a0
DIFF:
https://github.com/llvm/llvm-project/commit/30b0fdfff1931c625babe45cbf9405003c48f8a0.diff
LOG: [AArch64][FMV] Fix name mangling.
Put features into function version name in increasing priority order.
Differential Revision: https://reviews.llvm.org/D150800
Added:
Modified:
clang/lib/CodeGen/CodeGenModule.cpp
clang/test/CodeGen/attr-target-clones-aarch64.c
clang/test/CodeGen/attr-target-version.c
clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp
clang/test/CodeGenCXX/attr-target-version.cpp
Removed:
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 5cd29d3657879..66c2abdb903aa 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -1362,8 +1362,13 @@ static void AppendTargetVersionMangling(const
CodeGenModule &CGM,
if (Attr->isDefaultVersion())
return;
Out << "._";
+ const TargetInfo &TI = CGM.getTarget();
llvm::SmallVector Feats;
Attr->getFeatures(Feats);
+ llvm::stable_sort(Feats, [&TI](const StringRef FeatL, const StringRef FeatR)
{
+return TI.multiVersionSortPriority(FeatL) <
+ TI.multiVersionSortPriority(FeatR);
+ });
for (const auto &Feat : Feats) {
Out << 'M';
Out << Feat;
@@ -1415,13 +1420,19 @@ static void AppendTargetClonesMangling(const
CodeGenModule &CGM,
const TargetClonesAttr *Attr,
unsigned VersionIndex,
raw_ostream &Out) {
- if (CGM.getTarget().getTriple().isAArch64()) {
+ const TargetInfo &TI = CGM.getTarget();
+ if (TI.getTriple().isAArch64()) {
StringRef FeatureStr = Attr->getFeatureStr(VersionIndex);
if (FeatureStr == "default")
return;
Out << "._";
SmallVector Features;
FeatureStr.split(Features, "+");
+llvm::stable_sort(Features,
+ [&TI](const StringRef FeatL, const StringRef FeatR) {
+return TI.multiVersionSortPriority(FeatL) <
+ TI.multiVersionSortPriority(FeatR);
+ });
for (auto &Feat : Features) {
Out << 'M';
Out << Feat;
diff --git a/clang/test/CodeGen/attr-target-clones-aarch64.c
b/clang/test/CodeGen/attr-target-clones-aarch64.c
index f61db5f15bf54..4a5e47306c11b 100644
--- a/clang/test/CodeGen/attr-target-clones-aarch64.c
+++ b/clang/test/CodeGen/attr-target-clones-aarch64.c
@@ -32,7 +32,7 @@ inline int __attribute__((target_clones("fp16",
"sve2-bitperm+fcma", "default"))
// CHECK: @ftc_inline3.ifunc = weak_odr ifunc i32 (), ptr @ftc_inline3.resolver
// CHECK: Function Attrs: noinline nounwind optnone
-// CHECK-LABEL: @ftc._MaesMlse(
+// CHECK-LABEL: @ftc._MlseMaes(
// CHECK-NEXT: entry:
// CHECK-NEXT:ret i32 0
// CHECK: Function Attrs: noinline nounwind optnone
@@ -52,7 +52,7 @@ inline int __attribute__((target_clones("fp16",
"sve2-bitperm+fcma", "default"))
// CHECK-NEXT:[[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT:br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label
[[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
-// CHECK-NEXT:ret ptr @ftc._MaesMlse
+// CHECK-NEXT:ret ptr @ftc._MlseMaes
// CHECK: resolver_else:
// CHECK-NEXT:[[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT:[[TMP5:%.*]] = and i64 [[TMP4]], 68719476736
@@ -68,7 +68,7 @@ inline int __attribute__((target_clones("fp16",
"sve2-bitperm+fcma", "default"))
// CHECK-NEXT: entry:
// CHECK-NEXT:ret i32 1
// CHECK: Function Attrs: noinline nounwind optnone
-// CHECK-LABEL: @ftc_def._Mmemtag2Msha2(
+// CHECK-LABEL: @ftc_def._Msha2Mmemtag2(
// CHECK-NEXT: entry:
// CHECK-NEXT:ret i32 1
// CHECK: Function Attrs: noinline nounwind optnone
@@ -84,7 +84,7 @@ inline int __attribute__((target_clones("fp16",
"sve2-bitperm+fcma", "default"))
// CHECK-NEXT:[[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT:br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label
[[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
-// CHECK-NEXT:ret ptr @ftc_def._Mmemtag2Msha2
+// CHECK-NEXT:ret ptr @ftc_def._Msha2Mmemtag2
// CHECK: resolver_else:
// CHECK-NEXT:[[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT:[[TMP5:%.*]] = and i64 [[TMP4]], 4096
@@ -120,7 +120,7 @@ inline int __attribute__((target_clones("fp16",
"sve2-bitperm+fcma", "default"))
// CHECK-NEXT: entry:
// CHECK-NEXT:ret i32 3
// CHECK: Function Attrs: noinline nounwind optnone
-// CHECK-LABEL: @ftc_dup2._McrcMdotprod(
+// CHECK-LABEL: @ftc_dup2._MdotprodMcrc(
// CHECK-NEXT: entr
[clang] b6db864 - [AArch64][FMV] Prevent target attribute using for multiversioning.
Author: Pavel Iliin
Date: 2023-05-23T17:29:55+01:00
New Revision: b6db864a2fdf2bcfac62b2c0b71b9ed1cc039c27
URL:
https://github.com/llvm/llvm-project/commit/b6db864a2fdf2bcfac62b2c0b71b9ed1cc039c27
DIFF:
https://github.com/llvm/llvm-project/commit/b6db864a2fdf2bcfac62b2c0b71b9ed1cc039c27.diff
LOG: [AArch64][FMV] Prevent target attribute using for multiversioning.
On AArch64 for function multiversioning target_version/target_clones
attributes should be used. The patch fixes the defect allowing target
attribute to cause multiversioning.
Differential Revision: https://reviews.llvm.org/D150867
Added:
Modified:
clang/lib/Sema/SemaDecl.cpp
clang/test/Sema/attr-target-version.c
Removed:
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index adebfe85be45..2f9c8c70e209 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -11540,6 +11540,10 @@ static bool CheckMultiVersionFunction(Sema &S,
FunctionDecl *NewFD,
return false;
}
+ // Target attribute on AArch64 is not used for multiversioning
+ if (NewTA && S.getASTContext().getTargetInfo().getTriple().isAArch64())
+return false;
+
if (!OldDecl || !OldDecl->getAsFunction() ||
OldDecl->getDeclContext()->getRedeclContext() !=
NewFD->getDeclContext()->getRedeclContext()) {
diff --git a/clang/test/Sema/attr-target-version.c
b/clang/test/Sema/attr-target-version.c
index c054b037ee84..0cfec5ecb49c 100644
--- a/clang/test/Sema/attr-target-version.c
+++ b/clang/test/Sema/attr-target-version.c
@@ -15,15 +15,22 @@ int __attribute__((target_version("aes"))) foo(void) {
return 1; }
//expected-note@+1 {{previous definition is here}}
int __attribute__((target_version("default"))) foo(void) { return 2; }
-//expected-note@+1 {{previous declaration is here}}
+//expected-note@+1 {{previous definition is here}}
int __attribute__((target_version("sha3 + pmull "))) foo(void) { return 1; }
+//expected-note@-1 {{previous definition is here}}
-//expected-error@+1 {{multiversioning attributes cannot be combined}}
+//expected-error@+1 {{redefinition of 'foo'}}
int __attribute__((target("dotprod"))) foo(void) { return -1; }
+//expected-warning@-1 {{attribute declaration must precede definition}}
//expected-error@+1 {{redefinition of 'foo'}}
int foo(void) { return 2; }
+//expected-note@+1 {{previous definition is here}}
+__attribute__ ((target("bf16,sve,sve2,dotprod"))) int func(void) { return 1; }
+//expected-error@+1 {{redefinition of 'func'}}
+__attribute__ ((target("default"))) int func(void) { return 0; }
+
//expected-note@+1 {{previous declaration is here}}
void __attribute__((target_version("bti+flagm2"))) one(void) {}
//expected-error@+1 {{multiversioned function redeclarations require identical
target attributes}}
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
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[clang] [compiler-rt] [AArch64] Implement __builtin_cpu_supports, compiler-rt tests. (PR #82378)
https://github.com/ilinpv created
https://github.com/llvm/llvm-project/pull/82378
The patch complements https://github.com/llvm/llvm-project/pull/68919 and adds
AArch64 support for builtin
`__builtin_cpu_supports("feature1+...+featureN")`
which return true if all specified CPU features in argument are detected. Also
compiler-rt aarch64 native run tests for features detection mechanism were
added and 'cpu_model' check was fixed after its refactor merged
https://github.com/llvm/llvm-project/pull/75635 Original RFC was
https://reviews.llvm.org/D153153
>From 7e4c00db7875b10173b3b265a78d5de6eff390a3 Mon Sep 17 00:00:00 2001
From: Pavel Iliin
Date: Tue, 20 Feb 2024 02:01:04 +
Subject: [PATCH] [AArch64] Implement __builtin_cpu_supports, compiler-rt
tests.
The patch complements https://github.com/llvm/llvm-project/pull/68919
and adds AArch64 support for builtin
__builtin_cpu_supports("feature1+...+featureN")
which return true if all specified CPU features in argument are
detected. Also compiler-rt aarch64 native run tests for features
detection mechanism were added and 'cpu_model' check was fixed after its
refactor merged https://github.com/llvm/llvm-project/pull/75635
Original RFC was https://reviews.llvm.org/D153153
---
clang/lib/Basic/Targets/AArch64.cpp | 8 ++-
clang/lib/Basic/Targets/AArch64.h | 2 +-
clang/lib/CodeGen/CGBuiltin.cpp | 16 ++
clang/lib/CodeGen/CodeGenFunction.h | 2 +-
.../CodeGen/aarch64-cpu-supports-target.c | 52 ++
clang/test/CodeGen/aarch64-cpu-supports.c | 54 +++
clang/test/Preprocessor/has_builtin_cpuid.c | 7 +--
clang/test/Sema/aarch64-cpu-supports.c| 26 +
clang/test/Sema/builtin-cpu-supports.c| 2 +-
.../builtins/Unit/aarch64_cpu_features_test.c | 17 ++
.../test/builtins/Unit/cpu_model_test.c | 2 +-
11 files changed, 177 insertions(+), 11 deletions(-)
create mode 100644 clang/test/CodeGen/aarch64-cpu-supports-target.c
create mode 100644 clang/test/CodeGen/aarch64-cpu-supports.c
create mode 100644 clang/test/Sema/aarch64-cpu-supports.c
create mode 100644 compiler-rt/test/builtins/Unit/aarch64_cpu_features_test.c
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 68032961451d90..5abb060073c517 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -667,7 +667,13 @@ StringRef
AArch64TargetInfo::getFeatureDependencies(StringRef Name) const {
}
bool AArch64TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
- return llvm::AArch64::parseArchExtension(FeatureStr).has_value();
+ // CPU features might be separated by '+', extract them and check
+ llvm::SmallVector Features;
+ FeatureStr.split(Features, "+");
+ for (auto &Feature : Features)
+if (!llvm::AArch64::parseArchExtension(Feature.trim()).has_value())
+ return false;
+ return true;
}
bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
diff --git a/clang/lib/Basic/Targets/AArch64.h
b/clang/lib/Basic/Targets/AArch64.h
index 26ee7fa1978256..c1ba156860a122 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -165,7 +165,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public
TargetInfo {
DiagnosticsEngine &Diags) override;
ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
bool supportsTargetAttributeTune() const override { return true; }
-
+ bool supportsCpuSupports() const override { return true; }
bool checkArithmeticFenceSupported() const override { return true; }
bool hasBFloat16Type() const override;
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index d454ccc1dd8613..b2af45719d00ec 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -10638,6 +10638,9 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned
BuiltinID,
BuiltinID <= clang::AArch64::LastSMEBuiltin)
return EmitAArch64SMEBuiltinExpr(BuiltinID, E);
+ if (BuiltinID == Builtin::BI__builtin_cpu_supports)
+return EmitAArch64CpuSupports(E);
+
unsigned HintID = static_cast(-1);
switch (BuiltinID) {
default: break;
@@ -14025,6 +14028,19 @@ Value *CodeGenFunction::EmitX86CpuInit() {
return Builder.CreateCall(Func);
}
+Value *CodeGenFunction::EmitAArch64CpuSupports(const CallExpr *E) {
+ const Expr *ArgExpr = E->getArg(0)->IgnoreParenCasts();
+ StringRef ArgStr = cast(ArgExpr)->getString();
+ llvm::SmallVector Features;
+ ArgStr.split(Features, "+");
+ for (auto &Feature : Features) {
+Feature = Feature.trim();
+if (Feature != "default")
+ Features.push_back(Feature);
+ }
+ return EmitAArch64CpuSupports(Features);
+}
+
llvm::Value *
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
uint64_t FeaturesMask = llvm::AArch64::getCpuSupportsMask(FeaturesStrs);
diff --g
[clang] [compiler-rt] [AArch64] Implement __builtin_cpu_supports, compiler-rt tests. (PR #82378)
https://github.com/ilinpv updated
https://github.com/llvm/llvm-project/pull/82378
>From 7ada935c9000e915acc9433341e8d4317ff158d6 Mon Sep 17 00:00:00 2001
From: Pavel Iliin
Date: Tue, 20 Feb 2024 02:01:04 +
Subject: [PATCH] [AArch64] Implement __builtin_cpu_supports, compiler-rt
tests.
The patch complements https://github.com/llvm/llvm-project/pull/68919
and adds AArch64 support for builtin
__builtin_cpu_supports("feature1+...+featureN")
which return true if all specified CPU features in argument are
detected. Also compiler-rt aarch64 native run tests for features
detection mechanism were added and 'cpu_model' check was fixed after its
refactor merged https://github.com/llvm/llvm-project/pull/75635
Original RFC was https://reviews.llvm.org/D153153
---
clang/lib/Basic/Targets/AArch64.cpp | 8 ++-
clang/lib/Basic/Targets/AArch64.h | 2 +-
clang/lib/CodeGen/CGBuiltin.cpp | 16 ++
clang/lib/CodeGen/CodeGenFunction.h | 2 +-
.../CodeGen/aarch64-cpu-supports-target.c | 52 ++
clang/test/CodeGen/aarch64-cpu-supports.c | 54 +++
clang/test/Preprocessor/has_builtin_cpuid.c | 7 +--
clang/test/Sema/aarch64-cpu-supports.c| 26 +
clang/test/Sema/builtin-cpu-supports.c| 2 +-
.../builtins/Unit/aarch64_cpu_features_test.c | 17 ++
.../test/builtins/Unit/cpu_model_test.c | 2 +-
11 files changed, 177 insertions(+), 11 deletions(-)
create mode 100644 clang/test/CodeGen/aarch64-cpu-supports-target.c
create mode 100644 clang/test/CodeGen/aarch64-cpu-supports.c
create mode 100644 clang/test/Sema/aarch64-cpu-supports.c
create mode 100644 compiler-rt/test/builtins/Unit/aarch64_cpu_features_test.c
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 68032961451d90..5abb060073c517 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -667,7 +667,13 @@ StringRef
AArch64TargetInfo::getFeatureDependencies(StringRef Name) const {
}
bool AArch64TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
- return llvm::AArch64::parseArchExtension(FeatureStr).has_value();
+ // CPU features might be separated by '+', extract them and check
+ llvm::SmallVector Features;
+ FeatureStr.split(Features, "+");
+ for (auto &Feature : Features)
+if (!llvm::AArch64::parseArchExtension(Feature.trim()).has_value())
+ return false;
+ return true;
}
bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
diff --git a/clang/lib/Basic/Targets/AArch64.h
b/clang/lib/Basic/Targets/AArch64.h
index 26ee7fa1978256..c1ba156860a122 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -165,7 +165,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public
TargetInfo {
DiagnosticsEngine &Diags) override;
ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
bool supportsTargetAttributeTune() const override { return true; }
-
+ bool supportsCpuSupports() const override { return true; }
bool checkArithmeticFenceSupported() const override { return true; }
bool hasBFloat16Type() const override;
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index d454ccc1dd8613..b2af45719d00ec 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -10638,6 +10638,9 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned
BuiltinID,
BuiltinID <= clang::AArch64::LastSMEBuiltin)
return EmitAArch64SMEBuiltinExpr(BuiltinID, E);
+ if (BuiltinID == Builtin::BI__builtin_cpu_supports)
+return EmitAArch64CpuSupports(E);
+
unsigned HintID = static_cast(-1);
switch (BuiltinID) {
default: break;
@@ -14025,6 +14028,19 @@ Value *CodeGenFunction::EmitX86CpuInit() {
return Builder.CreateCall(Func);
}
+Value *CodeGenFunction::EmitAArch64CpuSupports(const CallExpr *E) {
+ const Expr *ArgExpr = E->getArg(0)->IgnoreParenCasts();
+ StringRef ArgStr = cast(ArgExpr)->getString();
+ llvm::SmallVector Features;
+ ArgStr.split(Features, "+");
+ for (auto &Feature : Features) {
+Feature = Feature.trim();
+if (Feature != "default")
+ Features.push_back(Feature);
+ }
+ return EmitAArch64CpuSupports(Features);
+}
+
llvm::Value *
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
uint64_t FeaturesMask = llvm::AArch64::getCpuSupportsMask(FeaturesStrs);
diff --git a/clang/lib/CodeGen/CodeGenFunction.h
b/clang/lib/CodeGen/CodeGenFunction.h
index caa6a327550baa..92ce0edeaf9e9c 100644
--- a/clang/lib/CodeGen/CodeGenFunction.h
+++ b/clang/lib/CodeGen/CodeGenFunction.h
@@ -5013,10 +5013,10 @@ class CodeGenFunction : public CodeGenTypeCache {
llvm::Value *EmitAArch64CpuInit();
llvm::Value *
FormAArch64ResolverCondition(const MultiVersionResolverOption &RO);
+ llvm::Value *EmitAArch64CpuSupports(const CallExpr *E);
llvm::Val
[clang] [compiler-rt] [AArch64] Implement __builtin_cpu_supports, compiler-rt tests. (PR #82378)
https://github.com/ilinpv updated
https://github.com/llvm/llvm-project/pull/82378
>From 7ada935c9000e915acc9433341e8d4317ff158d6 Mon Sep 17 00:00:00 2001
From: Pavel Iliin
Date: Tue, 20 Feb 2024 02:01:04 +
Subject: [PATCH 1/2] [AArch64] Implement __builtin_cpu_supports, compiler-rt
tests.
The patch complements https://github.com/llvm/llvm-project/pull/68919
and adds AArch64 support for builtin
__builtin_cpu_supports("feature1+...+featureN")
which return true if all specified CPU features in argument are
detected. Also compiler-rt aarch64 native run tests for features
detection mechanism were added and 'cpu_model' check was fixed after its
refactor merged https://github.com/llvm/llvm-project/pull/75635
Original RFC was https://reviews.llvm.org/D153153
---
clang/lib/Basic/Targets/AArch64.cpp | 8 ++-
clang/lib/Basic/Targets/AArch64.h | 2 +-
clang/lib/CodeGen/CGBuiltin.cpp | 16 ++
clang/lib/CodeGen/CodeGenFunction.h | 2 +-
.../CodeGen/aarch64-cpu-supports-target.c | 52 ++
clang/test/CodeGen/aarch64-cpu-supports.c | 54 +++
clang/test/Preprocessor/has_builtin_cpuid.c | 7 +--
clang/test/Sema/aarch64-cpu-supports.c| 26 +
clang/test/Sema/builtin-cpu-supports.c| 2 +-
.../builtins/Unit/aarch64_cpu_features_test.c | 17 ++
.../test/builtins/Unit/cpu_model_test.c | 2 +-
11 files changed, 177 insertions(+), 11 deletions(-)
create mode 100644 clang/test/CodeGen/aarch64-cpu-supports-target.c
create mode 100644 clang/test/CodeGen/aarch64-cpu-supports.c
create mode 100644 clang/test/Sema/aarch64-cpu-supports.c
create mode 100644 compiler-rt/test/builtins/Unit/aarch64_cpu_features_test.c
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 68032961451d90..5abb060073c517 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -667,7 +667,13 @@ StringRef
AArch64TargetInfo::getFeatureDependencies(StringRef Name) const {
}
bool AArch64TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
- return llvm::AArch64::parseArchExtension(FeatureStr).has_value();
+ // CPU features might be separated by '+', extract them and check
+ llvm::SmallVector Features;
+ FeatureStr.split(Features, "+");
+ for (auto &Feature : Features)
+if (!llvm::AArch64::parseArchExtension(Feature.trim()).has_value())
+ return false;
+ return true;
}
bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
diff --git a/clang/lib/Basic/Targets/AArch64.h
b/clang/lib/Basic/Targets/AArch64.h
index 26ee7fa1978256..c1ba156860a122 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -165,7 +165,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public
TargetInfo {
DiagnosticsEngine &Diags) override;
ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
bool supportsTargetAttributeTune() const override { return true; }
-
+ bool supportsCpuSupports() const override { return true; }
bool checkArithmeticFenceSupported() const override { return true; }
bool hasBFloat16Type() const override;
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index d454ccc1dd8613..b2af45719d00ec 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -10638,6 +10638,9 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned
BuiltinID,
BuiltinID <= clang::AArch64::LastSMEBuiltin)
return EmitAArch64SMEBuiltinExpr(BuiltinID, E);
+ if (BuiltinID == Builtin::BI__builtin_cpu_supports)
+return EmitAArch64CpuSupports(E);
+
unsigned HintID = static_cast(-1);
switch (BuiltinID) {
default: break;
@@ -14025,6 +14028,19 @@ Value *CodeGenFunction::EmitX86CpuInit() {
return Builder.CreateCall(Func);
}
+Value *CodeGenFunction::EmitAArch64CpuSupports(const CallExpr *E) {
+ const Expr *ArgExpr = E->getArg(0)->IgnoreParenCasts();
+ StringRef ArgStr = cast(ArgExpr)->getString();
+ llvm::SmallVector Features;
+ ArgStr.split(Features, "+");
+ for (auto &Feature : Features) {
+Feature = Feature.trim();
+if (Feature != "default")
+ Features.push_back(Feature);
+ }
+ return EmitAArch64CpuSupports(Features);
+}
+
llvm::Value *
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
uint64_t FeaturesMask = llvm::AArch64::getCpuSupportsMask(FeaturesStrs);
diff --git a/clang/lib/CodeGen/CodeGenFunction.h
b/clang/lib/CodeGen/CodeGenFunction.h
index caa6a327550baa..92ce0edeaf9e9c 100644
--- a/clang/lib/CodeGen/CodeGenFunction.h
+++ b/clang/lib/CodeGen/CodeGenFunction.h
@@ -5013,10 +5013,10 @@ class CodeGenFunction : public CodeGenTypeCache {
llvm::Value *EmitAArch64CpuInit();
llvm::Value *
FormAArch64ResolverCondition(const MultiVersionResolverOption &RO);
+ llvm::Value *EmitAArch64CpuSupports(const CallExpr *E);
llvm:
[clang] [compiler-rt] [AArch64] Implement __builtin_cpu_supports, compiler-rt tests. (PR #82378)
https://github.com/ilinpv updated
https://github.com/llvm/llvm-project/pull/82378
>From 7283a6f34de8ca26aa36fcf83356f71f6f59a82f Mon Sep 17 00:00:00 2001
From: Pavel Iliin
Date: Tue, 20 Feb 2024 02:01:04 +
Subject: [PATCH 1/2] [AArch64] Implement __builtin_cpu_supports, compiler-rt
tests.
The patch complements https://github.com/llvm/llvm-project/pull/68919
and adds AArch64 support for builtin
__builtin_cpu_supports("feature1+...+featureN")
which return true if all specified CPU features in argument are
detected. Also compiler-rt aarch64 native run tests for features
detection mechanism were added and 'cpu_model' check was fixed after its
refactor merged https://github.com/llvm/llvm-project/pull/75635
Original RFC was https://reviews.llvm.org/D153153
---
clang/lib/Basic/Targets/AArch64.cpp | 8 ++-
clang/lib/Basic/Targets/AArch64.h | 2 +-
clang/lib/CodeGen/CGBuiltin.cpp | 16 ++
clang/lib/CodeGen/CodeGenFunction.h | 2 +-
.../CodeGen/aarch64-cpu-supports-target.c | 52 ++
clang/test/CodeGen/aarch64-cpu-supports.c | 54 +++
clang/test/Preprocessor/has_builtin_cpuid.c | 7 +--
clang/test/Sema/aarch64-cpu-supports.c| 26 +
clang/test/Sema/builtin-cpu-supports.c| 2 +-
.../builtins/Unit/aarch64_cpu_features_test.c | 17 ++
.../test/builtins/Unit/cpu_model_test.c | 2 +-
11 files changed, 177 insertions(+), 11 deletions(-)
create mode 100644 clang/test/CodeGen/aarch64-cpu-supports-target.c
create mode 100644 clang/test/CodeGen/aarch64-cpu-supports.c
create mode 100644 clang/test/Sema/aarch64-cpu-supports.c
create mode 100644 compiler-rt/test/builtins/Unit/aarch64_cpu_features_test.c
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 68032961451d90..5abb060073c517 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -667,7 +667,13 @@ StringRef
AArch64TargetInfo::getFeatureDependencies(StringRef Name) const {
}
bool AArch64TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
- return llvm::AArch64::parseArchExtension(FeatureStr).has_value();
+ // CPU features might be separated by '+', extract them and check
+ llvm::SmallVector Features;
+ FeatureStr.split(Features, "+");
+ for (auto &Feature : Features)
+if (!llvm::AArch64::parseArchExtension(Feature.trim()).has_value())
+ return false;
+ return true;
}
bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
diff --git a/clang/lib/Basic/Targets/AArch64.h
b/clang/lib/Basic/Targets/AArch64.h
index 26ee7fa1978256..c1ba156860a122 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -165,7 +165,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public
TargetInfo {
DiagnosticsEngine &Diags) override;
ParsedTargetAttr parseTargetAttr(StringRef Str) const override;
bool supportsTargetAttributeTune() const override { return true; }
-
+ bool supportsCpuSupports() const override { return true; }
bool checkArithmeticFenceSupported() const override { return true; }
bool hasBFloat16Type() const override;
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index d8b2115f1e5e3c..734eb5a035ca49 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -10638,6 +10638,9 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned
BuiltinID,
BuiltinID <= clang::AArch64::LastSMEBuiltin)
return EmitAArch64SMEBuiltinExpr(BuiltinID, E);
+ if (BuiltinID == Builtin::BI__builtin_cpu_supports)
+return EmitAArch64CpuSupports(E);
+
unsigned HintID = static_cast(-1);
switch (BuiltinID) {
default: break;
@@ -14025,6 +14028,19 @@ Value *CodeGenFunction::EmitX86CpuInit() {
return Builder.CreateCall(Func);
}
+Value *CodeGenFunction::EmitAArch64CpuSupports(const CallExpr *E) {
+ const Expr *ArgExpr = E->getArg(0)->IgnoreParenCasts();
+ StringRef ArgStr = cast(ArgExpr)->getString();
+ llvm::SmallVector Features;
+ ArgStr.split(Features, "+");
+ for (auto &Feature : Features) {
+Feature = Feature.trim();
+if (Feature != "default")
+ Features.push_back(Feature);
+ }
+ return EmitAArch64CpuSupports(Features);
+}
+
llvm::Value *
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
uint64_t FeaturesMask = llvm::AArch64::getCpuSupportsMask(FeaturesStrs);
diff --git a/clang/lib/CodeGen/CodeGenFunction.h
b/clang/lib/CodeGen/CodeGenFunction.h
index caa6a327550baa..92ce0edeaf9e9c 100644
--- a/clang/lib/CodeGen/CodeGenFunction.h
+++ b/clang/lib/CodeGen/CodeGenFunction.h
@@ -5013,10 +5013,10 @@ class CodeGenFunction : public CodeGenTypeCache {
llvm::Value *EmitAArch64CpuInit();
llvm::Value *
FormAArch64ResolverCondition(const MultiVersionResolverOption &RO);
+ llvm::Value *EmitAArch64CpuSupports(const CallExpr *E);
llvm:
[clang] [compiler-rt] [AArch64] Implement __builtin_cpu_supports, compiler-rt tests. (PR #82378)
https://github.com/ilinpv closed https://github.com/llvm/llvm-project/pull/82378 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][FMV] Do not omit explicit default target_version attribute. (PR #96628)
https://github.com/ilinpv approved this pull request. Look good, thanks for refactoring and removing obsolete checks after FMV changes related to ordering and default version. https://github.com/llvm/llvm-project/pull/96628 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] ff210b9 - [FMV][NFC] Add test for bti and mte check in resolver.
Author: Pavel Iliin
Date: 2024-05-03T00:58:17+01:00
New Revision: ff210b94d449de8ebe1f32cf0d7763ba63b27b39
URL:
https://github.com/llvm/llvm-project/commit/ff210b94d449de8ebe1f32cf0d7763ba63b27b39
DIFF:
https://github.com/llvm/llvm-project/commit/ff210b94d449de8ebe1f32cf0d7763ba63b27b39.diff
LOG: [FMV][NFC] Add test for bti and mte check in resolver.
Added:
Modified:
clang/test/CodeGen/attr-target-clones-aarch64.c
Removed:
diff --git a/clang/test/CodeGen/attr-target-clones-aarch64.c
b/clang/test/CodeGen/attr-target-clones-aarch64.c
index 8c8b951e9118d7..f75d8a69ebf02f 100644
--- a/clang/test/CodeGen/attr-target-clones-aarch64.c
+++ b/clang/test/CodeGen/attr-target-clones-aarch64.c
@@ -1,13 +1,15 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --check-attributes --check-globals --include-generated-funcs
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -S -emit-llvm -o - %s |
FileCheck %s
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fmv -S
-emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK-NOFMV
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +mte
-target-feature +bti -S -emit-llvm -o - %s | FileCheck %s
-check-prefix=CHECK-MTE-BTI
int __attribute__((target_clones("lse+aes", "sve2"))) ftc(void) { return 0; }
int __attribute__((target_clones("sha2", "sha2+memtag2", " default ")))
ftc_def(void) { return 1; }
int __attribute__((target_clones("sha2", "default"))) ftc_dup1(void) { return
2; }
int __attribute__((target_clones("fp", "crc+dotprod"))) ftc_dup2(void) {
return 3; }
+int __attribute__((target_clones("memtag2", "bti"))) ftc_dup3(void) { return
4; }
int foo() {
- return ftc() + ftc_def() + ftc_dup1() + ftc_dup2();
+ return ftc() + ftc_def() + ftc_dup1() + ftc_dup2() + ftc_dup3();
}
inline int __attribute__((target_clones("rng+simd", "rcpc+predres",
"sve2-aes+wfxt"))) ftc_inline1(void) { return 1; }
@@ -29,6 +31,7 @@ inline int __attribute__((target_clones("fp16",
"sve2-bitperm+fcma", "default"))
// CHECK: @ftc_def.ifunc = weak_odr alias i32 (), ptr @ftc_def
// CHECK: @ftc_dup1.ifunc = weak_odr alias i32 (), ptr @ftc_dup1
// CHECK: @ftc_dup2.ifunc = weak_odr alias i32 (), ptr @ftc_dup2
+// CHECK: @ftc_dup3.ifunc = weak_odr alias i32 (), ptr @ftc_dup3
// CHECK: @ftc_inline2.ifunc = weak_odr alias i32 (), ptr @ftc_inline2
// CHECK: @ftc_inline1.ifunc = weak_odr alias i32 (), ptr @ftc_inline1
// CHECK: @ftc_inline3.ifunc = weak_odr alias i32 (), ptr @ftc_inline3
@@ -36,10 +39,29 @@ inline int __attribute__((target_clones("fp16",
"sve2-bitperm+fcma", "default"))
// CHECK: @ftc_def = weak_odr ifunc i32 (), ptr @ftc_def.resolver
// CHECK: @ftc_dup1 = weak_odr ifunc i32 (), ptr @ftc_dup1.resolver
// CHECK: @ftc_dup2 = weak_odr ifunc i32 (), ptr @ftc_dup2.resolver
+// CHECK: @ftc_dup3 = weak_odr ifunc i32 (), ptr @ftc_dup3.resolver
// CHECK: @ftc_inline1 = weak_odr ifunc i32 (), ptr @ftc_inline1.resolver
// CHECK: @ftc_inline2 = weak_odr ifunc i32 (), ptr @ftc_inline2.resolver
// CHECK: @ftc_inline3 = weak_odr ifunc i32 (), ptr @ftc_inline3.resolver
//.
+// CHECK-MTE-BTI: @__aarch64_cpu_features = external dso_local global { i64 }
+// CHECK-MTE-BTI: @ftc.ifunc = weak_odr alias i32 (), ptr @ftc
+// CHECK-MTE-BTI: @ftc_def.ifunc = weak_odr alias i32 (), ptr @ftc_def
+// CHECK-MTE-BTI: @ftc_dup1.ifunc = weak_odr alias i32 (), ptr @ftc_dup1
+// CHECK-MTE-BTI: @ftc_dup2.ifunc = weak_odr alias i32 (), ptr @ftc_dup2
+// CHECK-MTE-BTI: @ftc_dup3.ifunc = weak_odr alias i32 (), ptr @ftc_dup3
+// CHECK-MTE-BTI: @ftc_inline2.ifunc = weak_odr alias i32 (), ptr @ftc_inline2
+// CHECK-MTE-BTI: @ftc_inline1.ifunc = weak_odr alias i32 (), ptr @ftc_inline1
+// CHECK-MTE-BTI: @ftc_inline3.ifunc = weak_odr alias i32 (), ptr @ftc_inline3
+// CHECK-MTE-BTI: @ftc = weak_odr ifunc i32 (), ptr @ftc.resolver
+// CHECK-MTE-BTI: @ftc_def = weak_odr ifunc i32 (), ptr @ftc_def.resolver
+// CHECK-MTE-BTI: @ftc_dup1 = weak_odr ifunc i32 (), ptr @ftc_dup1.resolver
+// CHECK-MTE-BTI: @ftc_dup2 = weak_odr ifunc i32 (), ptr @ftc_dup2.resolver
+// CHECK-MTE-BTI: @ftc_dup3 = weak_odr ifunc i32 (), ptr @ftc_dup3.resolver
+// CHECK-MTE-BTI: @ftc_inline1 = weak_odr ifunc i32 (), ptr
@ftc_inline1.resolver
+// CHECK-MTE-BTI: @ftc_inline2 = weak_odr ifunc i32 (), ptr
@ftc_inline2.resolver
+// CHECK-MTE-BTI: @ftc_inline3 = weak_odr ifunc i32 (), ptr
@ftc_inline3.resolver
+//.
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: @ftc._MaesMlse(
// CHECK-NEXT: entry:
@@ -155,6 +177,40 @@ inline int __attribute__((target_clones("fp16",
"sve2-bitperm+fcma", "default"))
//
//
// CHECK: Function Attrs: noinline nounwind optnone
+// CHECK-LABEL: @ftc_dup3._Mmemtag2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:ret i32 4
+//
+//
+// CHECK: Function Attrs: noinline nounwind optnone
+// CHECK-LABEL: @ftc_dup3.
[clang] [FMV][AArch64] Don't optimize backward compatible features in resolver. (PR #90928)
https://github.com/ilinpv created
https://github.com/llvm/llvm-project/pull/90928
For arch64 features, such as Branch Target Identification or MTE (Memory
Tagging Extension), compatible with targets that lack their support we may
encounter scenarios where a binary compiled with MTE for example is executed on
both MTE and non-MTE hardware and we still need to detect at runtime whether
the MTE feature is available to choose the appropriate function version.
So, we cannot optimize the function multi versioning resolver by removing
checks for these features enabled for the target during compilation.
>From 36a72bf75ce1897ab58d422954c54dc40270f942 Mon Sep 17 00:00:00 2001
From: Pavel Iliin
Date: Wed, 1 May 2024 18:43:47 +0100
Subject: [PATCH] [FMV][AArch64] Don't optimize backward compatible features in
resolver.
For arch64 features, such as Branch Target Identification or MTE (Memory
Tagging Extension), compatible with targets that lack their support we
may encounter scenarios where a binary compiled with MTE for example is
executed on both MTE and non-MTE hardware and we still need to detect at
runtime whether the MTE feature is available to choose the appropriate
function version.
So, we cannot optimize the function multi versioning resolver by removing
checks for these features enabled for the target during compilation.
---
clang/lib/CodeGen/CodeGenFunction.cpp | 10 +--
.../test/CodeGen/attr-target-clones-aarch64.c | 29 +--
2 files changed, 35 insertions(+), 4 deletions(-)
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp
b/clang/lib/CodeGen/CodeGenFunction.cpp
index 87766a758311d5..39943ed2a415e8 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -2759,8 +2759,14 @@ llvm::Value
*CodeGenFunction::FormAArch64ResolverCondition(
const MultiVersionResolverOption &RO) {
llvm::SmallVector CondFeatures;
for (const StringRef &Feature : RO.Conditions.Features) {
-// Form condition for features which are not yet enabled in target
-if (!getContext().getTargetInfo().hasFeature(Feature))
+// Optimize the Function Multi Versioning resolver by creating conditions
+// only for features that are not enabled in the target. The exception is
+// for features whose extension instructions are executed as NOP on targets
+// without extension support.
+if (!getContext().getTargetInfo().hasFeature(Feature) ||
+Feature.equals("bti") || Feature.equals("memtag") ||
+Feature.equals("memtag2") || Feature.equals("memtag3") ||
+Feature.equals("dgh"))
CondFeatures.push_back(Feature);
}
if (!CondFeatures.empty()) {
diff --git a/clang/test/CodeGen/attr-target-clones-aarch64.c
b/clang/test/CodeGen/attr-target-clones-aarch64.c
index f75d8a69ebf02f..603d067864b45a 100644
--- a/clang/test/CodeGen/attr-target-clones-aarch64.c
+++ b/clang/test/CodeGen/attr-target-clones-aarch64.c
@@ -526,8 +526,8 @@ inline int __attribute__((target_clones("fp16",
"sve2-bitperm+fcma", "default"))
// CHECK-MTE-BTI-NEXT: resolver_entry:
// CHECK-MTE-BTI-NEXT:call void @__init_cpu_features_resolver()
// CHECK-MTE-BTI-NEXT:[[TMP0:%.*]] = load i64, ptr
@__aarch64_cpu_features, align 8
-// CHECK-MTE-BTI-NEXT:[[TMP1:%.*]] = and i64 [[TMP0]], 4096
-// CHECK-MTE-BTI-NEXT:[[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4096
+// CHECK-MTE-BTI-NEXT:[[TMP1:%.*]] = and i64 [[TMP0]], 17592186048512
+// CHECK-MTE-BTI-NEXT:[[TMP2:%.*]] = icmp eq i64 [[TMP1]], 17592186048512
// CHECK-MTE-BTI-NEXT:[[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-MTE-BTI-NEXT:br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label
[[RESOLVER_ELSE:%.*]]
// CHECK-MTE-BTI: resolver_return:
@@ -604,7 +604,24 @@ inline int __attribute__((target_clones("fp16",
"sve2-bitperm+fcma", "default"))
//
// CHECK-MTE-BTI-LABEL: @ftc_dup3.resolver(
// CHECK-MTE-BTI-NEXT: resolver_entry:
+// CHECK-MTE-BTI-NEXT:call void @__init_cpu_features_resolver()
+// CHECK-MTE-BTI-NEXT:[[TMP0:%.*]] = load i64, ptr
@__aarch64_cpu_features, align 8
+// CHECK-MTE-BTI-NEXT:[[TMP1:%.*]] = and i64 [[TMP0]], 1125899906842624
+// CHECK-MTE-BTI-NEXT:[[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1125899906842624
+// CHECK-MTE-BTI-NEXT:[[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-MTE-BTI-NEXT:br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label
[[RESOLVER_ELSE:%.*]]
+// CHECK-MTE-BTI: resolver_return:
// CHECK-MTE-BTI-NEXT:ret ptr @ftc_dup3._Mbti
+// CHECK-MTE-BTI: resolver_else:
+// CHECK-MTE-BTI-NEXT:[[TMP4:%.*]] = load i64, ptr
@__aarch64_cpu_features, align 8
+// CHECK-MTE-BTI-NEXT:[[TMP5:%.*]] = and i64 [[TMP4]], 17592186044416
+// CHECK-MTE-BTI-NEXT:[[TMP6:%.*]] = icmp eq i64 [[TMP5]], 17592186044416
+// CHECK-MTE-BTI-NEXT:[[TMP7:%.*]] = and i1 true, [[TMP6]]
+// CHECK-MTE-BTI-NEXT:br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]],
label [[RESOLVER_ELSE2:%.*]]
+// CHECK-MTE-BTI:
[clang] [FMV][AArch64] Don't optimize backward compatible features in resolver. (PR #90928)
https://github.com/ilinpv closed https://github.com/llvm/llvm-project/pull/90928 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [FMV][AArch64] Don't optimize backward compatible features in resolver. (PR #90928)
ilinpv wrote: Apologies for quick merge and , thanks for comments. I agree with all of them. I would prefer to keep the patch and provide fixes on top of it. Let me know if you want it reverted. https://github.com/llvm/llvm-project/pull/90928 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [AArch64] add some more tests for FMV (PR #91490)
https://github.com/ilinpv approved this pull request. Thanks for additional FMV tests! https://github.com/llvm/llvm-project/pull/91490 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [FMV][AArch64] Remove features which expose non exploitable runtime behavior. (PR #114387)
https://github.com/ilinpv edited https://github.com/llvm/llvm-project/pull/114387 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [FMV][AArch64] Remove features which expose non exploitable runtime behavior. (PR #114387)
https://github.com/ilinpv approved this pull request. I wonder if we can get any cases of using asm msr in function version for features in question? Anyway LGTM to be aligned with specification. https://github.com/llvm/llvm-project/pull/114387 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [FMV][AArch64] Remove features which expose non exploitable runtime behavior. (PR #114387)
@@ -45,8 +45,6 @@ static void __init_cpu_features_constructor(unsigned long hwcap, setCPUFeature(FEAT_SSBS2); if (hwcap2 & HWCAP2_MTE) setCPUFeature(FEAT_MEMTAG2); - if (hwcap2 & HWCAP2_MTE3) ilinpv wrote: Do we need to remove runtime detection for these features for other targets as well? https://github.com/llvm/llvm-project/pull/114387 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [NFC] Remove invalid features from test and autogenerate checks. (PR #124130)
https://github.com/ilinpv approved this pull request. Thanks for updating `__builtin_cpu_supports `tests accordingly. https://github.com/llvm/llvm-project/pull/124130 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
